Series comparison

-[PULL 00/40] riscv-to-apply queue
+[PULL v2 00/45] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:
-The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
+  Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400)
   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +0000)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911
-for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
+for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a:
-  docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)
+  target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000)
 ----------------------------------------------------------------
-Fourth RISC-V PR for QEMU 7.0
+First RISC-V PR for 8.2
- * Remove old Ibex PLIC header file
+ * Remove 'host' CPU from TCG
- * Allow writing 8 bytes with generic loader
+ * riscv_htif Fixup printing on big endian hosts
- * Fixes for RV128
+ * Add zmmul isa string
- * Refactor RISC-V CPU configs
+ * Add smepmp isa string
- * Initial support for XVentanaCondOps custom extension
+ * Fix page_check_range use in fault-only-first
- * Fix for vill field in vtype
+ * Use existing lookup tables for MixColumns
- * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
+ * Add RISC-V vector cryptographic instruction set support
- * RISC-V AIA support for virt machine
+ * Implement WARL behaviour for mcountinhibit/mcounteren
- * Support for svnapot, svinval and svpbmt extensions
+ * Add Zihintntl extension ISA string to DTS
  * Fix zfa fleq.d and fltq.d
  * Fix upper/lower mtime write calculation
  * Make rtc variable names consistent
  * Use abi type for linux-user target_ucontext
  * Add RISC-V KVM AIA Support
  * Fix riscv,pmu DT node path in the virt machine
  * Update CSR bits name for svadu extension
  * Mark zicond non-experimental
  * Fix satp_mode_finalize() when satp_mode.supported = 0
  * Fix non-KVM --enable-debug build
  * Add new extensions to hwprobe
  * Use accelerated helper for AES64KS1I
  * Allocate itrigger timers only once
  * Respect mseccfg.RLB for pmpaddrX changes
  * Align the AIA model to v1.0 ratified spec
  * Don't read the CSR in riscv_csrrw_do64
 ----------------------------------------------------------------
-Anup Patel (23):
+Akihiko Odaki (1):
-      target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
+      target/riscv: Allocate itrigger timers only once
       target/riscv: Implement SGEIP bit in hip and hie CSRs
       target/riscv: Implement hgeie and hgeip CSRs
       target/riscv: Improve delivery of guest external interrupts
       target/riscv: Allow setting CPU feature from machine/device emulation
       target/riscv: Add AIA cpu feature
       target/riscv: Add defines for AIA CSRs
       target/riscv: Allow AIA device emulation to set ireg rmw callback
       target/riscv: Implement AIA local interrupt priorities
       target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
       target/riscv: Implement AIA hvictl and hviprioX CSRs
       target/riscv: Implement AIA interrupt filtering CSRs
       target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
       target/riscv: Implement AIA xiselect and xireg CSRs
       target/riscv: Implement AIA IMSIC interface CSRs
       hw/riscv: virt: Use AIA INTC compatible string when available
       target/riscv: Allow users to force enable AIA CSRs in HART
       hw/intc: Add RISC-V AIA APLIC device emulation
       hw/riscv: virt: Add optional AIA APLIC support to virt machine
       hw/intc: Add RISC-V AIA IMSIC device emulation
       hw/riscv: virt: Add optional AIA IMSIC support to virt machine
       docs/system: riscv: Document AIA options for virt machine
       hw/riscv: virt: Increase maximum number of allowed CPUs
-Frédéric Pétrot (1):
+Ard Biesheuvel (2):
-      target/riscv: correct "code should not be reached" for x-rv128
+      target/riscv: Use existing lookup tables for MixColumns
       target/riscv: Use accelerated helper for AES64KS1I
-Guo Ren (1):
+Conor Dooley (1):
-      target/riscv: Ignore reserved bits in PTE for RV64
+      hw/riscv: virt: Fix riscv,pmu DT node path
-LIU Zhiwei (1):
+Daniel Henrique Barboza (6):
-      target/riscv: Fix vill field write in vtype
+      target/riscv/cpu.c: do not run 'host' CPU with TCG
       target/riscv/cpu.c: add zmmul isa string
       target/riscv/cpu.c: add smepmp isa string
       target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
       hw/riscv/virt.c: fix non-KVM --enable-debug build
       hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
-Petr Tesarik (1):
+Dickon Hood (2):
-      Allow setting up to 8 bytes with the generic loader
+      target/riscv: Refactor translation of vector-widening instruction
       target/riscv: Add Zvbb ISA extension support
-Philipp Tomsich (7):
+Jason Chien (3):
-      target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
+      target/riscv: Add Zihintntl extension ISA string to DTS
-      target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
+      hw/intc: Fix upper/lower mtime write calculation
-      target/riscv: access configuration through cfg_ptr in DisasContext
+      hw/intc: Make rtc variable names consistent
       target/riscv: access cfg structure through DisasContext
       target/riscv: iterate over a table of decoders
       target/riscv: Add XVentanaCondOps custom extension
       target/riscv: add a MAINTAINERS entry for XVentanaCondOps
-Weiwei Li (4):
+Kiran Ostrolenk (4):
-      target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
+      target/riscv: Refactor some of the generic vector functionality
-      target/riscv: add support for svnapot extension
+      target/riscv: Refactor vector-vector translation macro
-      target/riscv: add support for svinval extension
+      target/riscv: Refactor some of the generic vector functionality
-      target/riscv: add support for svpbmt extension
+      target/riscv: Add Zvknh ISA extension support
-Wilfred Mallawa (1):
+LIU Zhiwei (3):
-      include: hw: remove ibex_plic.h
+      target/riscv: Fix page_check_range use in fault-only-first
       target/riscv: Fix zfa fleq.d and fltq.d
       linux-user/riscv: Use abi type for target_ucontext
-Yu Li (1):
+Lawrence Hunter (2):
-      docs/system: riscv: Update description of CPU
+      target/riscv: Add Zvbc ISA extension support
       target/riscv: Add Zvksh ISA extension support
- docs/system/riscv/virt.rst                         |   22 +-
+Leon Schuermann (1):
- include/hw/intc/ibex_plic.h                        |   67 -
+      target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
  include/hw/intc/riscv_aplic.h                      |   79 ++
  include/hw/intc/riscv_imsic.h                      |   68 ++
  include/hw/riscv/virt.h                            |   41 +-
  target/riscv/cpu.h                                 |  169 ++-
  target/riscv/cpu_bits.h                            |  129 ++
  target/riscv/XVentanaCondOps.decode                |   25 +
  target/riscv/insn32.decode                         |    7 +
  hw/core/generic-loader.c                           |    2 +-
  hw/intc/riscv_aplic.c                              |  978 +++++++++++++++
  hw/intc/riscv_imsic.c                              |  448 +++++++
  hw/riscv/virt.c                                    |  712 +++++++++--
  target/riscv/cpu.c                                 |  113 +-
  target/riscv/cpu_helper.c                          |  377 +++++-
  target/riscv/csr.c                                 | 1282 ++++++++++++++++++--
  target/riscv/gdbstub.c                             |    3 +
  target/riscv/machine.c                             |   24 +-
  target/riscv/translate.c                           |   61 +-
  target/riscv/vector_helper.c                       |    1 +
  target/riscv/insn_trans/trans_rvb.c.inc            |    8 +-
  target/riscv/insn_trans/trans_rvi.c.inc            |    2 +-
  target/riscv/insn_trans/trans_rvv.c.inc            |  146 ++-
  target/riscv/insn_trans/trans_rvzfh.c.inc          |    4 +-
  target/riscv/insn_trans/trans_svinval.c.inc        |   75 ++
  .../riscv/insn_trans/trans_xventanacondops.c.inc   |   39 +
  MAINTAINERS                                        |    7 +
  hw/intc/Kconfig                                    |    6 +
  hw/intc/meson.build                                |    2 +
  hw/riscv/Kconfig                                   |    2 +
  target/riscv/meson.build                           |    1 +
 files changed, 4409 insertions(+), 491 deletions(-)
  delete mode 100644 include/hw/intc/ibex_plic.h
  create mode 100644 include/hw/intc/riscv_aplic.h
  create mode 100644 include/hw/intc/riscv_imsic.h
  create mode 100644 target/riscv/XVentanaCondOps.decode
  create mode 100644 hw/intc/riscv_aplic.c
  create mode 100644 hw/intc/riscv_imsic.c
  create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
  create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc
+Max Chou (3):
+      crypto: Create sm4_subword
+      crypto: Add SM4 constant parameter CK
+      target/riscv: Add Zvksed ISA extension support
+Nazar Kazakov (4):
+      target/riscv: Remove redundant "cpu_vl == 0" checks
+      target/riscv: Move vector translation checks
+      target/riscv: Add Zvkned ISA extension support
+      target/riscv: Add Zvkg ISA extension support
+Nikita Shubin (1):
+      target/riscv: don't read CSR in riscv_csrrw_do64
+Rob Bradford (1):
+      target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
+Robbin Ehn (1):
+      linux-user/riscv: Add new extensions to hwprobe
+Thomas Huth (2):
+      hw/char/riscv_htif: Fix printing of console characters on big endian hosts
+      hw/char/riscv_htif: Fix the console syscall on big endian hosts
+Tommy Wu (1):
+      target/riscv: Align the AIA model to v1.0 ratified spec
+Vineet Gupta (1):
+      riscv: zicond: make non-experimental
+Weiwei Li (1):
+      target/riscv: Update CSR bits name for svadu extension
+Yong-Xuan Wang (5):
+      target/riscv: support the AIA device emulation with KVM enabled
+      target/riscv: check the in-kernel irqchip support
+      target/riscv: Create an KVM AIA irqchip
+      target/riscv: update APLIC and IMSIC to support KVM AIA
+      target/riscv: select KVM AIA in riscv virt machine
+ include/crypto/aes.h                      |   7 +
+ include/crypto/sm4.h                      |   9 +
+ target/riscv/cpu_bits.h                   |   8 +-
+ target/riscv/cpu_cfg.h                    |   9 +
+ target/riscv/debug.h                      |   3 +-
+ target/riscv/helper.h                     |  98 +++
+ target/riscv/kvm_riscv.h                  |   5 +
+ target/riscv/vector_internals.h           | 228 +++++++
+ target/riscv/insn32.decode                |  58 ++
+ crypto/aes.c                              |   4 +-
+ crypto/sm4.c                              |  10 +
+ hw/char/riscv_htif.c                      |  12 +-
+ hw/intc/riscv_aclint.c                    |  11 +-
+ hw/intc/riscv_aplic.c                     |  52 +-
+ hw/intc/riscv_imsic.c                     |  25 +-
+ hw/riscv/virt.c                           | 374 ++++++------
+ linux-user/riscv/signal.c                 |   4 +-
+ linux-user/syscall.c                      |  14 +-
+ target/arm/tcg/crypto_helper.c            |  10 +-
+ target/riscv/cpu.c                        |  83 ++-
+ target/riscv/cpu_helper.c                 |   6 +-
+ target/riscv/crypto_helper.c              |  51 +-
+ target/riscv/csr.c                        |  54 +-
+ target/riscv/debug.c                      |  15 +-
+ target/riscv/kvm.c                        | 201 ++++++-
+ target/riscv/pmp.c                        |   4 +
+ target/riscv/translate.c                  |   1 +
+ target/riscv/vcrypto_helper.c             | 970 ++++++++++++++++++++++++++++++
+ target/riscv/vector_helper.c              | 245 +-------
+ target/riscv/vector_internals.c           |  81 +++
+ target/riscv/insn_trans/trans_rvv.c.inc   | 171 +++---
+ target/riscv/insn_trans/trans_rvvk.c.inc  | 606 +++++++++++++++++++
+ target/riscv/insn_trans/trans_rvzfa.c.inc |   4 +-
+ target/riscv/meson.build                  |   4 +-
+files changed, 2785 insertions(+), 652 deletions(-)
+ create mode 100644 target/riscv/vector_internals.h
+ create mode 100644 target/riscv/vcrypto_helper.c
+ create mode 100644 target/riscv/vector_internals.c
+ create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc

-[PULL 40/40] docs/system: riscv: Update description of CPU
+[PULL v2 01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG
-From: Yu Li <liyu.yukiteru@bytedance.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Since the hypervisor extension been non experimental and enabled for
+The 'host' CPU is available in a CONFIG_KVM build and it's currently
-default CPU, the previous command is no longer available and the
+available for all accels, but is a KVM only CPU. This means that in a
-option `x-h=true` or `h=true` is also no longer required.
+RISC-V KVM capable host we can do things like this:
-Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
+$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
 qemu-system-riscv64: H extension requires priv spec 1.12.0
 This CPU does not have a priv spec because we don't filter its extensions
 via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
 with the 'host' CPU.
 We don't have a way to filter the 'host' CPU out of the available CPU
 options (-cpu help) if the build includes both KVM and TCG. What we can
 do is to error out during riscv_cpu_realize_tcg() if the user chooses
 the 'host' CPU with accel=tcg:
 $ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
 qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/virt.rst | 6 +++---
+ target/riscv/cpu.c | 5 +++++
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 5 insertions(+)
-diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/virt.rst
+--- a/target/riscv/cpu.c
-+++ b/docs/system/riscv/virt.rst
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ The ``virt`` machine supports the following devices:
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
- * 1 generic PCIe host bridge
+     CPURISCVState *env = &cpu->env;
- * The fw_cfg device that allows a guest to obtain data from QEMU
+     Error *local_err = NULL;
--Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
++    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
--can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
++        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
--enables the hypervisor extension for RV64.
++        return;
-+The hypervisor extension has been enabled for the default CPU, so virtual
++    }
-+machines with hypervisor extension can simply be used without explicitly
++
-+declaring.
+     riscv_cpu_validate_misa_mxl(cpu, &local_err);
+     if (local_err != NULL) {
- Hardware configuration information
+         error_propagate(errp, local_err);
  ----------------------------------
 --
-.34.1
+.41.0

-[PULL 17/40] target/riscv: Add AIA cpu feature
+[PULL v2 02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts
-From: Anup Patel <anup.patel@wdc.com>
+From: Thomas Huth <thuth@redhat.com>
-We define a CPU feature for AIA CSR support in RISC-V CPUs which
+The character that should be printed is stored in the 64 bit "payload"
-can be set by machine/device emulation. The RISC-V CSR emulation
+variable. The code currently tries to print it by taking the address
-will also check this feature for emulating AIA CSRs.
+of the variable and passing this pointer to qemu_chr_fe_write(). However,
 this only works on little endian hosts where the least significant bits
 are stored on the lowest address. To do this in a portable way, we have
 to store the value in an uint8_t variable instead.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Fixes: 5033606780 ("RISC-V HTIF Console")
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Signed-off-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Bin Meng <bmeng@tinylab.org>
-Message-id: 20220204174700.534953-7-anup@brainfault.org
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-Id: <20230721094720.902454-2-thuth@redhat.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 3 ++-
+ hw/char/riscv_htif.c | 3 ++-
 file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/hw/char/riscv_htif.c
-+++ b/target/riscv/cpu.h
++++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
-     RISCV_FEATURE_MMU,
+             s->tohost = 0; /* clear to indicate we read */
-     RISCV_FEATURE_PMP,
+             return;
-     RISCV_FEATURE_EPMP,
+         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
--    RISCV_FEATURE_MISA
+-            qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
-+    RISCV_FEATURE_MISA,
++            uint8_t ch = (uint8_t)payload;
-+    RISCV_FEATURE_AIA
++            qemu_chr_fe_write(&s->chr, &ch, 1);
- };
+             resp = 0x100 | (uint8_t)payload;
+         } else {
- #define PRIV_VERSION_1_10_0 0x00011000
+             qemu_log("HTIF device %d: unknown command\n", device);
 --
-.34.1
+.41.0

-New patch
+[PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts
+From: Thomas Huth <thuth@redhat.com>
+Values that have been read via cpu_physical_memory_read() from the
+guest's memory have to be swapped in case the host endianess differs
+from the guest.
+Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
+Signed-off-by: Thomas Huth <thuth@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-Id: <20230721094720.902454-3-thuth@redhat.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/char/riscv_htif.c | 9 +++++----
+file changed, 5 insertions(+), 4 deletions(-)
+diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/char/riscv_htif.c
++++ b/hw/char/riscv_htif.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/timer.h"
+ #include "qemu/error-report.h"
+ #include "exec/address-spaces.h"
++#include "exec/tswap.h"
+ #include "sysemu/dma.h"
+ #define RISCV_DEBUG_HTIF 0
+@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
+             } else {
+                 uint64_t syscall[8];
+                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
+-                if (syscall[0] == PK_SYS_WRITE &&
+-                    syscall[1] == HTIF_DEV_CONSOLE &&
+-                    syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
++                if (tswap64(syscall[0]) == PK_SYS_WRITE &&
++                    tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
++                    tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
+                     uint8_t ch;
+-                    cpu_physical_memory_read(syscall[2], &ch, 1);
++                    cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
+                     qemu_chr_fe_write(&s->chr, &ch, 1);
+                     resp = 0x100 | (uint8_t)payload;
+                 } else {
+--
+.41.0

-New patch
+[PULL v2 04/45] target/riscv/cpu.c: add zmmul isa string
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
+Add a riscv,isa string for it.
+Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties")
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
+     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
+     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
++    ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
+     ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
+     ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
+     ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
+--
+.41.0

-New patch
+[PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The cpu->cfg.epmp extension is still experimental, but it already has a
+'smepmp' riscv,isa string. Add it.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
+     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
++    ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
+     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
+     ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
+     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
+--
+.41.0

-[PULL 11/40] target/riscv: Fix vill field write in vtype
+[PULL v2 06/45] target/riscv: Fix page_check_range use in fault-only-first
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-The guest should be able to set the vill bit as part of vsetvl.
+Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
 integer return value to bool type. However, it wrongly converted the use
 of the API in riscv fault-only-first, where page_check_range < = 0, should
 be converted to !page_check_range.
-Currently we may set env->vill to 1 in the vsetvl helper, but there
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 is nowhere that we set it to 0, so once it transitions to 1 it's stuck
 there until the system is reset.
 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
 Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_helper.c | 1 +
+ target/riscv/vector_helper.c | 2 +-
-file changed, 1 insertion(+)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
+@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
-     env->vl = vl;
+                                          cpu_mmu_index(env, false));
-     env->vtype = s2;
+                 if (host) {
-     env->vstart = 0;
+ #ifdef CONFIG_USER_ONLY
-+    env->vill = 0;
+-                    if (page_check_range(addr, offset, PAGE_READ)) {
-     return vl;
++                    if (!page_check_range(addr, offset, PAGE_READ)) {
- }
+                         vl = i;
+                         goto ProbeSuccess;
                      }
 --
-.34.1
+.41.0

-[PULL 18/40] target/riscv: Add defines for AIA CSRs
+[PULL v2 07/45] target/riscv: Use existing lookup tables for MixColumns
-From: Anup Patel <anup.patel@wdc.com>
+From: Ard Biesheuvel <ardb@kernel.org>
-The RISC-V AIA specification extends RISC-V local interrupts and
+The AES MixColumns and InvMixColumns operations are relatively
-introduces new CSRs. This patch adds defines for the new AIA CSRs.
+expensive 4x4 matrix multiplications in GF(2^8), which is why C
 implementations usually rely on precomputed lookup tables rather than
 performing the calculations on demand.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Given that we already carry those tables in QEMU, we can just grab the
-Signed-off-by: Anup Patel <anup@brainfault.org>
+right value in the implementation of the RISC-V AES32 instructions. Note
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+that the tables in question are permuted according to the respective
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Sbox, so we can omit the Sbox lookup as well in this case.
-Message-id: 20220204174700.534953-8-anup@brainfault.org
 Cc: Richard Henderson <richard.henderson@linaro.org>
 Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
 Cc: Zewen Ye <lustrew@foxmail.com>
 Cc: Weiwei Li <liweiwei@iscas.ac.cn>
 Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
 Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h | 119 ++++++++++++++++++++++++++++++++++++++++
+ include/crypto/aes.h         |  7 +++++++
-file changed, 119 insertions(+)
+ crypto/aes.c                 |  4 ++--
  target/riscv/crypto_helper.c | 34 ++++------------------------------
 files changed, 13 insertions(+), 32 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/include/crypto/aes.h b/include/crypto/aes.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/include/crypto/aes.h
-+++ b/target/riscv/cpu_bits.h
++++ b/include/crypto/aes.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void AES_decrypt(const unsigned char *in, unsigned char *out,
- #define CSR_MTVAL           0x343
+ extern const uint8_t AES_sbox[256];
- #define CSR_MIP             0x344
+ extern const uint8_t AES_isbox[256];
-+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
++/*
-+#define CSR_MISELECT        0x350
++AES_Te0[x] = S [x].[02, 01, 01, 03];
-+#define CSR_MIREG           0x351
++AES_Td0[x] = Si[x].[0e, 09, 0d, 0b];
 +*/
 +
-+/* Machine-Level Interrupts (AIA) */
++extern const uint32_t AES_Te0[256], AES_Td0[256];
 +#define CSR_MTOPI           0xfb0
 +
 +/* Machine-Level IMSIC Interface (AIA) */
 +#define CSR_MSETEIPNUM      0x358
 +#define CSR_MCLREIPNUM      0x359
 +#define CSR_MSETEIENUM      0x35a
 +#define CSR_MCLREIENUM      0x35b
 +#define CSR_MTOPEI          0x35c
 +
 +/* Virtual Interrupts for Supervisor Level (AIA) */
 +#define CSR_MVIEN           0x308
 +#define CSR_MVIP            0x309
 +
 +/* Machine-Level High-Half CSRs (AIA) */
 +#define CSR_MIDELEGH        0x313
 +#define CSR_MIEH            0x314
 +#define CSR_MVIENH          0x318
 +#define CSR_MVIPH           0x319
 +#define CSR_MIPH            0x354
 +
  /* Supervisor Trap Setup */
  #define CSR_SSTATUS         0x100
  #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
  #define CSR_SPTBR           0x180
  #define CSR_SATP            0x180
 +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 +#define CSR_SISELECT        0x150
 +#define CSR_SIREG           0x151
 +
 +/* Supervisor-Level Interrupts (AIA) */
 +#define CSR_STOPI           0xdb0
 +
 +/* Supervisor-Level IMSIC Interface (AIA) */
 +#define CSR_SSETEIPNUM      0x158
 +#define CSR_SCLREIPNUM      0x159
 +#define CSR_SSETEIENUM      0x15a
 +#define CSR_SCLREIENUM      0x15b
 +#define CSR_STOPEI          0x15c
 +
 +/* Supervisor-Level High-Half CSRs (AIA) */
 +#define CSR_SIEH            0x114
 +#define CSR_SIPH            0x154
 +
  /* Hpervisor CSRs */
  #define CSR_HSTATUS         0x600
  #define CSR_HEDELEG         0x602
@@ -XXX,XX +XXX,XX @@
  #define CSR_MTINST          0x34a
  #define CSR_MTVAL2          0x34b
 +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
 +#define CSR_HVIEN           0x608
 +#define CSR_HVICTL          0x609
 +#define CSR_HVIPRIO1        0x646
 +#define CSR_HVIPRIO2        0x647
 +
 +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
 +#define CSR_VSISELECT       0x250
 +#define CSR_VSIREG          0x251
 +
 +/* VS-Level Interrupts (H-extension with AIA) */
 +#define CSR_VSTOPI          0xeb0
 +
 +/* VS-Level IMSIC Interface (H-extension with AIA) */
 +#define CSR_VSSETEIPNUM     0x258
 +#define CSR_VSCLREIPNUM     0x259
 +#define CSR_VSSETEIENUM     0x25a
 +#define CSR_VSCLREIENUM     0x25b
 +#define CSR_VSTOPEI         0x25c
 +
 +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
 +#define CSR_HIDELEGH        0x613
 +#define CSR_HVIENH          0x618
 +#define CSR_HVIPH           0x655
 +#define CSR_HVIPRIO1H       0x656
 +#define CSR_HVIPRIO2H       0x657
 +#define CSR_VSIEH           0x214
 +#define CSR_VSIPH           0x254
 +
  /* Enhanced Physical Memory Protection (ePMP) */
  #define CSR_MSECCFG         0x747
  #define CSR_MSECCFGH        0x757
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
  #define UMTE_U_PM_INSN      U_PM_INSN
  #define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
 +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
 +#define ISELECT_IPRIO0                     0x30
 +#define ISELECT_IPRIO15                    0x3f
 +#define ISELECT_IMSIC_EIDELIVERY           0x70
 +#define ISELECT_IMSIC_EITHRESHOLD          0x72
 +#define ISELECT_IMSIC_EIP0                 0x80
 +#define ISELECT_IMSIC_EIP63                0xbf
 +#define ISELECT_IMSIC_EIE0                 0xc0
 +#define ISELECT_IMSIC_EIE63                0xff
 +#define ISELECT_IMSIC_FIRST                ISELECT_IMSIC_EIDELIVERY
 +#define ISELECT_IMSIC_LAST                 ISELECT_IMSIC_EIE63
 +#define ISELECT_MASK                       0x1ff
 +
 +/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
 +#define ISELECT_IMSIC_TOPEI                (ISELECT_MASK + 1)
 +
 +/* IMSIC bits (AIA) */
 +#define IMSIC_TOPEI_IID_SHIFT              16
 +#define IMSIC_TOPEI_IID_MASK               0x7ff
 +#define IMSIC_TOPEI_IPRIO_MASK             0x7ff
 +#define IMSIC_EIPx_BITS                    32
 +#define IMSIC_EIEx_BITS                    32
 +
 +/* MTOPI and STOPI bits (AIA) */
 +#define TOPI_IID_SHIFT                     16
 +#define TOPI_IID_MASK                      0xfff
 +#define TOPI_IPRIO_MASK                    0xff
 +
 +/* Interrupt priority bits (AIA) */
 +#define IPRIO_IRQ_BITS                     8
 +#define IPRIO_MMAXIPRIO                    255
 +#define IPRIO_DEFAULT_UPPER                4
 +#define IPRIO_DEFAULT_MIDDLE               (IPRIO_DEFAULT_UPPER + 24)
 +#define IPRIO_DEFAULT_M                    IPRIO_DEFAULT_MIDDLE
 +#define IPRIO_DEFAULT_S                    (IPRIO_DEFAULT_M + 3)
 +#define IPRIO_DEFAULT_SGEXT                (IPRIO_DEFAULT_S + 3)
 +#define IPRIO_DEFAULT_VS                   (IPRIO_DEFAULT_SGEXT + 1)
 +#define IPRIO_DEFAULT_LOWER                (IPRIO_DEFAULT_VS + 3)
 +
 +/* HVICTL bits (AIA) */
 +#define HVICTL_VTI                         0x40000000
 +#define HVICTL_IID                         0x0fff0000
 +#define HVICTL_IPRIOM                      0x00000100
 +#define HVICTL_IPRIO                       0x000000ff
 +#define HVICTL_VALID_MASK                  \
 +    (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
 +
  #endif
+diff --git a/crypto/aes.c b/crypto/aes.c
+index XXXXXXX..XXXXXXX 100644
+--- a/crypto/aes.c
++++ b/crypto/aes.c
+@@ -XXX,XX +XXX,XX @@ AES_Td3[x] = Si[x].[09, 0d, 0b, 0e];
+ AES_Td4[x] = Si[x].[01, 01, 01, 01];
+ */
+-static const uint32_t AES_Te0[256] = {
++const uint32_t AES_Te0[256] = {
+xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
+xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
+x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
+@@ -XXX,XX +XXX,XX @@ static const uint32_t AES_Te4[256] = {
+xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
+ };
+-static const uint32_t AES_Td0[256] = {
++const uint32_t AES_Td0[256] = {
+x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
+x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
+x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
+diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/crypto_helper.c
++++ b/target/riscv/crypto_helper.c
+@@ -XXX,XX +XXX,XX @@
+ #include "crypto/aes-round.h"
+ #include "crypto/sm4.h"
+-#define AES_XTIME(a) \
+-    ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+-
+-#define AES_GFMUL(a, b) (( \
+-    (((b) & 0x1) ? (a) : 0) ^ \
+-    (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+-    (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+-    (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+-
+-static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+-{
+-    uint32_t u;
+-
+-    if (fwd) {
+-        u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
+-            (AES_GFMUL(x, 2) << 0);
+-    } else {
+-        u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
+-            (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
+-    }
+-    return u;
+-}
+-
+ #define sext32_xlen(x) (target_ulong)(int32_t)(x)
+ static inline target_ulong aes32_operation(target_ulong shamt,
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong aes32_operation(target_ulong shamt,
+                                            bool enc, bool mix)
+ {
+     uint8_t si = rs2 >> shamt;
+-    uint8_t so;
+     uint32_t mixed;
+     target_ulong res;
+     if (enc) {
+-        so = AES_sbox[si];
+         if (mix) {
+-            mixed = aes_mixcolumn_byte(so, true);
++            mixed = be32_to_cpu(AES_Te0[si]);
+         } else {
+-            mixed = so;
++            mixed = AES_sbox[si];
+         }
+     } else {
+-        so = AES_isbox[si];
+         if (mix) {
+-            mixed = aes_mixcolumn_byte(so, false);
++            mixed = be32_to_cpu(AES_Td0[si]);
+         } else {
+-            mixed = so;
++            mixed = AES_isbox[si];
+         }
+     }
+     mixed = rol32(mixed, shamt);
 --
-.34.1
+.41.0

-[PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation
+[PULL v2 08/45] target/riscv: Refactor some of the generic vector functionality
-From: Anup Patel <anup.patel@wdc.com>
+From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
-The RISC-V AIA (Advanced Interrupt Architecture) defines a new
+Take some functions/macros out of `vector_helper` and put them in a new
-interrupt controller for wired interrupts called APLIC (Advanced
+module called `vector_internals`. This ensures they can be used by both
-Platform Level Interrupt Controller). The APLIC is capabable of
+vector and vector-crypto helpers (latter implemented in proceeding
-forwarding wired interupts to RISC-V HARTs directly or as MSIs
+commits).
 (Message Signaled Interupts).
-This patch adds device emulation for RISC-V AIA APLIC.
+Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-ID: <20230711165917.2629866-2-max.chou@sifive.com>
 Message-id: 20220204174700.534953-19-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/intc/riscv_aplic.h |  79 +++
+ target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++
- hw/intc/riscv_aplic.c         | 978 ++++++++++++++++++++++++++++++++++
+ target/riscv/vector_helper.c    | 201 +-------------------------------
- hw/intc/Kconfig               |   3 +
+ target/riscv/vector_internals.c |  81 +++++++++++++
- hw/intc/meson.build           |   1 +
+ target/riscv/meson.build        |   1 +
-files changed, 1061 insertions(+)
+files changed, 265 insertions(+), 200 deletions(-)
- create mode 100644 include/hw/intc/riscv_aplic.h
+ create mode 100644 target/riscv/vector_internals.h
- create mode 100644 hw/intc/riscv_aplic.c
+ create mode 100644 target/riscv/vector_internals.c
-diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
+diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/intc/riscv_aplic.h
++++ b/target/riscv/vector_internals.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
++ * RISC-V Vector Extension Internals
 + *
-+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
++ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#ifndef HW_RISCV_APLIC_H
++#ifndef TARGET_RISCV_VECTOR_INTERNALS_H
-+#define HW_RISCV_APLIC_H
++#define TARGET_RISCV_VECTOR_INTERNALS_H
 +
-+#include "hw/sysbus.h"
++#include "qemu/osdep.h"
-+#include "qom/object.h"
++#include "qemu/bitops.h"
-+
++#include "cpu.h"
-+#define TYPE_RISCV_APLIC "riscv.aplic"
++#include "tcg/tcg-gvec-desc.h"
-+
++#include "internals.h"
-+typedef struct RISCVAPLICState RISCVAPLICState;
++
-+DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
++static inline uint32_t vext_nf(uint32_t desc)
-+
++{
-+#define APLIC_MIN_SIZE            0x4000
++    return FIELD_EX32(simd_data(desc), VDATA, NF);
-+#define APLIC_SIZE_ALIGN(__x)     (((__x) + (APLIC_MIN_SIZE - 1)) & \
++}
-+                                   ~(APLIC_MIN_SIZE - 1))
++
-+#define APLIC_SIZE(__num_harts)   (APLIC_MIN_SIZE + \
++/*
-+                                   APLIC_SIZE_ALIGN(32 * (__num_harts)))
++ * Note that vector data is stored in host-endian 64-bit chunks,
-+
++ * so addressing units smaller than that needs a host-endian fixup.
-+struct RISCVAPLICState {
++ */
-+    /*< private >*/
++#if HOST_BIG_ENDIAN
-+    SysBusDevice parent_obj;
++#define H1(x)   ((x) ^ 7)
-+    qemu_irq *external_irqs;
++#define H1_2(x) ((x) ^ 6)
-+
++#define H1_4(x) ((x) ^ 4)
-+    /*< public >*/
++#define H2(x)   ((x) ^ 3)
-+    MemoryRegion mmio;
++#define H4(x)   ((x) ^ 1)
-+    uint32_t bitfield_words;
++#define H8(x)   ((x))
-+    uint32_t domaincfg;
++#else
-+    uint32_t mmsicfgaddr;
++#define H1(x)   (x)
-+    uint32_t mmsicfgaddrH;
++#define H1_2(x) (x)
-+    uint32_t smsicfgaddr;
++#define H1_4(x) (x)
-+    uint32_t smsicfgaddrH;
++#define H2(x)   (x)
-+    uint32_t genmsi;
++#define H4(x)   (x)
-+    uint32_t *sourcecfg;
++#define H8(x)   (x)
 +    uint32_t *state;
 +    uint32_t *target;
 +    uint32_t *idelivery;
 +    uint32_t *iforce;
 +    uint32_t *ithreshold;
 +
 +    /* topology */
 +#define QEMU_APLIC_MAX_CHILDREN        16
 +    struct RISCVAPLICState *parent;
 +    struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
 +    uint16_t num_children;
 +
 +    /* config */
 +    uint32_t aperture_size;
 +    uint32_t hartid_base;
 +    uint32_t num_harts;
 +    uint32_t iprio_mask;
 +    uint32_t num_irqs;
 +    bool msimode;
 +    bool mmode;
 +};
 +
 +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
 +
 +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
 +    uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
 +    uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
 +
 +#endif
-diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
++
 +/*
 + * Encode LMUL to lmul as following:
 + *     LMUL    vlmul    lmul
 + *      1       000       0
 + *      2       001       1
 + *      4       010       2
 + *      8       011       3
 + *      -       100       -
 + *     1/8      101      -3
 + *     1/4      110      -2
 + *     1/2      111      -1
 + */
 +static inline int32_t vext_lmul(uint32_t desc)
 +{
 +    return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
 +}
 +
 +static inline uint32_t vext_vm(uint32_t desc)
 +{
 +    return FIELD_EX32(simd_data(desc), VDATA, VM);
 +}
 +
 +static inline uint32_t vext_vma(uint32_t desc)
 +{
 +    return FIELD_EX32(simd_data(desc), VDATA, VMA);
 +}
 +
 +static inline uint32_t vext_vta(uint32_t desc)
 +{
 +    return FIELD_EX32(simd_data(desc), VDATA, VTA);
 +}
 +
 +static inline uint32_t vext_vta_all_1s(uint32_t desc)
 +{
 +    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
 +}
 +
 +/*
 + * Earlier designs (pre-0.9) had a varying number of bits
 + * per mask value (MLEN). In the 0.9 design, MLEN=1.
 + * (Section 4.5)
 + */
 +static inline int vext_elem_mask(void *v0, int index)
 +{
 +    int idx = index / 64;
 +    int pos = index  % 64;
 +    return (((uint64_t *)v0)[idx] >> pos) & 1;
 +}
 +
 +/*
 + * Get number of total elements, including prestart, body and tail elements.
 + * Note that when LMUL < 1, the tail includes the elements past VLMAX that
 + * are held in the same vector register.
 + */
 +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
 +                                            uint32_t esz)
 +{
 +    uint32_t vlenb = simd_maxsz(desc);
 +    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
 +    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
 +                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
 +    return (vlenb << emul) / esz;
 +}
 +
 +/* set agnostic elements to 1s */
 +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
 +                       uint32_t tot);
 +
 +/* expand macro args before macro */
 +#define RVVCALL(macro, ...)  macro(__VA_ARGS__)
 +
 +/* (TD, T1, T2, TX1, TX2) */
 +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
 +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
 +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
 +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
 +
 +/* operation of two vector elements */
 +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
 +
 +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)    \
 +static void do_##NAME(void *vd, void *vs1, void *vs2, int i)    \
 +{                                                               \
 +    TX1 s1 = *((T1 *)vs1 + HS1(i));                             \
 +    TX2 s2 = *((T2 *)vs2 + HS2(i));                             \
 +    *((TD *)vd + HD(i)) = OP(s2, s1);                           \
 +}
 +
 +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
 +                CPURISCVState *env, uint32_t desc,
 +                opivv2_fn *fn, uint32_t esz);
 +
 +/* generate the helpers for OPIVV */
 +#define GEN_VEXT_VV(NAME, ESZ)                            \
 +void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
 +                  void *vs2, CPURISCVState *env,          \
 +                  uint32_t desc)                          \
 +{                                                         \
 +    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
 +               do_##NAME, ESZ);                           \
 +}
 +
 +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
 +
 +/*
 + * (T1)s1 gives the real operator type.
 + * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
 + */
 +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
 +static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
 +{                                                                   \
 +    TX2 s2 = *((T2 *)vs2 + HS2(i));                                 \
 +    *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1);                      \
 +}
 +
 +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
 +                CPURISCVState *env, uint32_t desc,
 +                opivx2_fn fn, uint32_t esz);
 +
 +/* generate the helpers for OPIVX */
 +#define GEN_VEXT_VX(NAME, ESZ)                            \
 +void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
 +                  void *vs2, CPURISCVState *env,          \
 +                  uint32_t desc)                          \
 +{                                                         \
 +    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
 +               do_##NAME, ESZ);                           \
 +}
 +
 +#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "fpu/softfloat.h"
  #include "tcg/tcg-gvec-desc.h"
  #include "internals.h"
 +#include "vector_internals.h"
  #include <math.h>
  target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
      return vl;
  }
 -/*
 - * Note that vector data is stored in host-endian 64-bit chunks,
 - * so addressing units smaller than that needs a host-endian fixup.
 - */
 -#if HOST_BIG_ENDIAN
 -#define H1(x)   ((x) ^ 7)
 -#define H1_2(x) ((x) ^ 6)
 -#define H1_4(x) ((x) ^ 4)
 -#define H2(x)   ((x) ^ 3)
 -#define H4(x)   ((x) ^ 1)
 -#define H8(x)   ((x))
 -#else
 -#define H1(x)   (x)
 -#define H1_2(x) (x)
 -#define H1_4(x) (x)
 -#define H2(x)   (x)
 -#define H4(x)   (x)
 -#define H8(x)   (x)
 -#endif
 -
 -static inline uint32_t vext_nf(uint32_t desc)
 -{
 -    return FIELD_EX32(simd_data(desc), VDATA, NF);
 -}
 -
 -static inline uint32_t vext_vm(uint32_t desc)
 -{
 -    return FIELD_EX32(simd_data(desc), VDATA, VM);
 -}
 -
 -/*
 - * Encode LMUL to lmul as following:
 - *     LMUL    vlmul    lmul
 - *      1       000       0
 - *      2       001       1
 - *      4       010       2
 - *      8       011       3
 - *      -       100       -
 - *     1/8      101      -3
 - *     1/4      110      -2
 - *     1/2      111      -1
 - */
 -static inline int32_t vext_lmul(uint32_t desc)
 -{
 -    return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
 -}
 -
 -static inline uint32_t vext_vta(uint32_t desc)
 -{
 -    return FIELD_EX32(simd_data(desc), VDATA, VTA);
 -}
 -
 -static inline uint32_t vext_vma(uint32_t desc)
 -{
 -    return FIELD_EX32(simd_data(desc), VDATA, VMA);
 -}
 -
 -static inline uint32_t vext_vta_all_1s(uint32_t desc)
 -{
 -    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
 -}
 -
  /*
   * Get the maximum number of elements can be operated.
   *
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
      return scale < 0 ? vlenb >> -scale : vlenb << scale;
  }
 -/*
 - * Get number of total elements, including prestart, body and tail elements.
 - * Note that when LMUL < 1, the tail includes the elements past VLMAX that
 - * are held in the same vector register.
 - */
 -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
 -                                            uint32_t esz)
 -{
 -    uint32_t vlenb = simd_maxsz(desc);
 -    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
 -    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
 -                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
 -    return (vlenb << emul) / esz;
 -}
 -
  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
  {
      return (addr & ~env->cur_pmmask) | env->cur_pmbase;
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
      }
  }
 -/* set agnostic elements to 1s */
 -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
 -                              uint32_t tot)
 -{
 -    if (is_agnostic == 0) {
 -        /* policy undisturbed */
 -        return;
 -    }
 -    if (tot - cnt == 0) {
 -        return;
 -    }
 -    memset(base + cnt, -1, tot - cnt);
 -}
 -
  static inline void vext_set_elem_mask(void *v0, int index,
                                        uint8_t value)
  {
@@ -XXX,XX +XXX,XX @@ static inline void vext_set_elem_mask(void *v0, int index,
      ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
  }
 -/*
 - * Earlier designs (pre-0.9) had a varying number of bits
 - * per mask value (MLEN). In the 0.9 design, MLEN=1.
 - * (Section 4.5)
 - */
 -static inline int vext_elem_mask(void *v0, int index)
 -{
 -    int idx = index / 64;
 -    int pos = index  % 64;
 -    return (((uint64_t *)v0)[idx] >> pos) & 1;
 -}
 -
  /* elements operations for load and store */
  typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr,
                                 uint32_t idx, void *vd, uintptr_t retaddr);
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
   * Vector Integer Arithmetic Instructions
   */
 -/* expand macro args before macro */
 -#define RVVCALL(macro, ...)  macro(__VA_ARGS__)
 -
  /* (TD, T1, T2, TX1, TX2) */
  #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
  #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
  #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
  #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
 -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
 -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
 -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
 -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
  #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
  #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
  #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
  #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
  #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
 -/* operation of two vector elements */
 -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
 -
 -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)    \
 -static void do_##NAME(void *vd, void *vs1, void *vs2, int i)    \
 -{                                                               \
 -    TX1 s1 = *((T1 *)vs1 + HS1(i));                             \
 -    TX2 s2 = *((T2 *)vs2 + HS2(i));                             \
 -    *((TD *)vd + HD(i)) = OP(s2, s1);                           \
 -}
  #define DO_SUB(N, M) (N - M)
  #define DO_RSUB(N, M) (M - N)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
  RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
  RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
 -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
 -                       CPURISCVState *env, uint32_t desc,
 -                       opivv2_fn *fn, uint32_t esz)
 -{
 -    uint32_t vm = vext_vm(desc);
 -    uint32_t vl = env->vl;
 -    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 -    uint32_t vta = vext_vta(desc);
 -    uint32_t vma = vext_vma(desc);
 -    uint32_t i;
 -
 -    for (i = env->vstart; i < vl; i++) {
 -        if (!vm && !vext_elem_mask(v0, i)) {
 -            /* set masked-off elements to 1s */
 -            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
 -            continue;
 -        }
 -        fn(vd, vs1, vs2, i);
 -    }
 -    env->vstart = 0;
 -    /* set tail elements to 1s */
 -    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 -}
 -
 -/* generate the helpers for OPIVV */
 -#define GEN_VEXT_VV(NAME, ESZ)                            \
 -void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
 -                  void *vs2, CPURISCVState *env,          \
 -                  uint32_t desc)                          \
 -{                                                         \
 -    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
 -               do_##NAME, ESZ);                           \
 -}
 -
  GEN_VEXT_VV(vadd_vv_b, 1)
  GEN_VEXT_VV(vadd_vv_h, 2)
  GEN_VEXT_VV(vadd_vv_w, 4)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VV(vsub_vv_h, 2)
  GEN_VEXT_VV(vsub_vv_w, 4)
  GEN_VEXT_VV(vsub_vv_d, 8)
 -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
 -
 -/*
 - * (T1)s1 gives the real operator type.
 - * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
 - */
 -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
 -static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
 -{                                                                   \
 -    TX2 s2 = *((T2 *)vs2 + HS2(i));                                 \
 -    *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1);                      \
 -}
  RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
  RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
  RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
  RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
 -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
 -                       CPURISCVState *env, uint32_t desc,
 -                       opivx2_fn fn, uint32_t esz)
 -{
 -    uint32_t vm = vext_vm(desc);
 -    uint32_t vl = env->vl;
 -    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 -    uint32_t vta = vext_vta(desc);
 -    uint32_t vma = vext_vma(desc);
 -    uint32_t i;
 -
 -    for (i = env->vstart; i < vl; i++) {
 -        if (!vm && !vext_elem_mask(v0, i)) {
 -            /* set masked-off elements to 1s */
 -            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
 -            continue;
 -        }
 -        fn(vd, s1, vs2, i);
 -    }
 -    env->vstart = 0;
 -    /* set tail elements to 1s */
 -    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 -}
 -
 -/* generate the helpers for OPIVX */
 -#define GEN_VEXT_VX(NAME, ESZ)                            \
 -void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
 -                  void *vs2, CPURISCVState *env,          \
 -                  uint32_t desc)                          \
 -{                                                         \
 -    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
 -               do_##NAME, ESZ);                           \
 -}
 -
  GEN_VEXT_VX(vadd_vx_b, 1)
  GEN_VEXT_VX(vadd_vx_h, 2)
  GEN_VEXT_VX(vadd_vx_w, 4)
 diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/intc/riscv_aplic.c
++++ b/target/riscv/vector_internals.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
++ * RISC-V Vector Extension Internals
 + *
-+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
++ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#include "qemu/osdep.h"
++#include "vector_internals.h"
-+#include "qapi/error.h"
++
-+#include "qemu/log.h"
++/* set agnostic elements to 1s */
-+#include "qemu/module.h"
++void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-+#include "qemu/error-report.h"
++                       uint32_t tot)
-+#include "qemu/bswap.h"
++{
-+#include "exec/address-spaces.h"
++    if (is_agnostic == 0) {
-+#include "hw/sysbus.h"
++        /* policy undisturbed */
-+#include "hw/pci/msi.h"
++        return;
-+#include "hw/boards.h"
++    }
-+#include "hw/qdev-properties.h"
++    if (tot - cnt == 0) {
-+#include "hw/intc/riscv_aplic.h"
++        return ;
-+#include "hw/irq.h"
++    }
-+#include "target/riscv/cpu.h"
++    memset(base + cnt, -1, tot - cnt);
-+#include "sysemu/sysemu.h"
++}
-+#include "migration/vmstate.h"
++
-+
++void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
-+#define APLIC_MAX_IDC                  (1UL << 14)
++                CPURISCVState *env, uint32_t desc,
-+#define APLIC_MAX_SOURCE               1024
++                opivv2_fn *fn, uint32_t esz)
-+#define APLIC_MIN_IPRIO_BITS           1
++{
-+#define APLIC_MAX_IPRIO_BITS           8
++    uint32_t vm = vext_vm(desc);
-+#define APLIC_MAX_CHILDREN             1024
++    uint32_t vl = env->vl;
-+
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-+#define APLIC_DOMAINCFG                0x0000
++    uint32_t vta = vext_vta(desc);
-+#define APLIC_DOMAINCFG_RDONLY         0x80000000
++    uint32_t vma = vext_vma(desc);
-+#define APLIC_DOMAINCFG_IE             (1 << 8)
++    uint32_t i;
-+#define APLIC_DOMAINCFG_DM             (1 << 2)
++
-+#define APLIC_DOMAINCFG_BE             (1 << 0)
++    for (i = env->vstart; i < vl; i++) {
-+
++        if (!vm && !vext_elem_mask(v0, i)) {
-+#define APLIC_SOURCECFG_BASE           0x0004
++            /* set masked-off elements to 1s */
-+#define APLIC_SOURCECFG_D              (1 << 10)
++            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
 +#define APLIC_SOURCECFG_CHILDIDX_MASK  0x000003ff
 +#define APLIC_SOURCECFG_SM_MASK        0x00000007
 +#define APLIC_SOURCECFG_SM_INACTIVE    0x0
 +#define APLIC_SOURCECFG_SM_DETACH      0x1
 +#define APLIC_SOURCECFG_SM_EDGE_RISE   0x4
 +#define APLIC_SOURCECFG_SM_EDGE_FALL   0x5
 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH  0x6
 +#define APLIC_SOURCECFG_SM_LEVEL_LOW   0x7
 +
 +#define APLIC_MMSICFGADDR              0x1bc0
 +#define APLIC_MMSICFGADDRH             0x1bc4
 +#define APLIC_SMSICFGADDR              0x1bc8
 +#define APLIC_SMSICFGADDRH             0x1bcc
 +
 +#define APLIC_xMSICFGADDRH_L           (1UL << 31)
 +#define APLIC_xMSICFGADDRH_HHXS_MASK   0x1f
 +#define APLIC_xMSICFGADDRH_HHXS_SHIFT  24
 +#define APLIC_xMSICFGADDRH_LHXS_MASK   0x7
 +#define APLIC_xMSICFGADDRH_LHXS_SHIFT  20
 +#define APLIC_xMSICFGADDRH_HHXW_MASK   0x7
 +#define APLIC_xMSICFGADDRH_HHXW_SHIFT  16
 +#define APLIC_xMSICFGADDRH_LHXW_MASK   0xf
 +#define APLIC_xMSICFGADDRH_LHXW_SHIFT  12
 +#define APLIC_xMSICFGADDRH_BAPPN_MASK  0xfff
 +
 +#define APLIC_xMSICFGADDR_PPN_SHIFT    12
 +
 +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
 +    ((1UL << (__lhxs)) - 1)
 +
 +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
 +    ((1UL << (__lhxw)) - 1)
 +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
 +    ((__lhxs))
 +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
 +    (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
 +     APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
 +
 +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
 +    ((1UL << (__hhxw)) - 1)
 +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
 +    ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
 +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
 +    (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
 +     APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
 +
 +#define APLIC_xMSICFGADDRH_VALID_MASK   \
 +    (APLIC_xMSICFGADDRH_L | \
 +     (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \
 +     (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \
 +     (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \
 +     (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \
 +     APLIC_xMSICFGADDRH_BAPPN_MASK)
 +
 +#define APLIC_SETIP_BASE               0x1c00
 +#define APLIC_SETIPNUM                 0x1cdc
 +
 +#define APLIC_CLRIP_BASE               0x1d00
 +#define APLIC_CLRIPNUM                 0x1ddc
 +
 +#define APLIC_SETIE_BASE               0x1e00
 +#define APLIC_SETIENUM                 0x1edc
 +
 +#define APLIC_CLRIE_BASE               0x1f00
 +#define APLIC_CLRIENUM                 0x1fdc
 +
 +#define APLIC_SETIPNUM_LE              0x2000
 +#define APLIC_SETIPNUM_BE              0x2004
 +
 +#define APLIC_ISTATE_PENDING           (1U << 0)
 +#define APLIC_ISTATE_ENABLED           (1U << 1)
 +#define APLIC_ISTATE_ENPEND            (APLIC_ISTATE_ENABLED | \
 +                                        APLIC_ISTATE_PENDING)
 +#define APLIC_ISTATE_INPUT             (1U << 8)
 +
 +#define APLIC_GENMSI                   0x3000
 +
 +#define APLIC_TARGET_BASE              0x3004
 +#define APLIC_TARGET_HART_IDX_SHIFT    18
 +#define APLIC_TARGET_HART_IDX_MASK     0x3fff
 +#define APLIC_TARGET_GUEST_IDX_SHIFT   12
 +#define APLIC_TARGET_GUEST_IDX_MASK    0x3f
 +#define APLIC_TARGET_IPRIO_MASK        0xff
 +#define APLIC_TARGET_EIID_MASK         0x7ff
 +
 +#define APLIC_IDC_BASE                 0x4000
 +#define APLIC_IDC_SIZE                 32
 +
 +#define APLIC_IDC_IDELIVERY            0x00
 +
 +#define APLIC_IDC_IFORCE               0x04
 +
 +#define APLIC_IDC_ITHRESHOLD           0x08
 +
 +#define APLIC_IDC_TOPI                 0x18
 +#define APLIC_IDC_TOPI_ID_SHIFT        16
 +#define APLIC_IDC_TOPI_ID_MASK         0x3ff
 +#define APLIC_IDC_TOPI_PRIO_MASK       0xff
 +
 +#define APLIC_IDC_CLAIMI               0x1c
 +
 +static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
 +                                            uint32_t word)
 +{
 +    uint32_t i, irq, ret = 0;
 +
 +    for (i = 0; i < 32; i++) {
 +        irq = word * 32 + i;
 +        if (!irq || aplic->num_irqs <= irq) {
 +            continue;
 +        }
-+
++        fn(vd, vs1, vs2, i);
 +        ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
 +    }
-+
++    env->vstart = 0;
-+    return ret;
++    /* set tail elements to 1s */
-+}
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
-+
++}
-+static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic,
++
-+                                              uint32_t word)
++void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
-+{
++                CPURISCVState *env, uint32_t desc,
-+    uint32_t i, irq, ret = 0;
++                opivx2_fn fn, uint32_t esz)
-+
++{
-+    for (i = 0; i < 32; i++) {
++    uint32_t vm = vext_vm(desc);
-+        irq = word * 32 + i;
++    uint32_t vl = env->vl;
-+        if (!irq || aplic->num_irqs <= irq) {
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +    uint32_t vta = vext_vta(desc);
 +    uint32_t vma = vext_vma(desc);
 +    uint32_t i;
 +
 +    for (i = env->vstart; i < vl; i++) {
 +        if (!vm && !vext_elem_mask(v0, i)) {
 +            /* set masked-off elements to 1s */
 +            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
 +            continue;
 +        }
-+
++        fn(vd, s1, vs2, i);
 +        ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i;
 +    }
-+
++    env->vstart = 0;
-+    return ret;
++    /* set tail elements to 1s */
-+}
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
-+
++}
-+static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic,
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 +                                        uint32_t irq, bool pending)
 +{
 +    if (pending) {
 +        aplic->state[irq] |= APLIC_ISTATE_PENDING;
 +    } else {
 +        aplic->state[irq] &= ~APLIC_ISTATE_PENDING;
 +    }
 +}
 +
 +static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
 +                                    uint32_t irq, bool pending)
 +{
 +    uint32_t sourcecfg, sm;
 +
 +    if ((irq <= 0) || (aplic->num_irqs <= irq)) {
 +        return;
 +    }
 +
 +    sourcecfg = aplic->sourcecfg[irq];
 +    if (sourcecfg & APLIC_SOURCECFG_D) {
 +        return;
 +    }
 +
 +    sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
 +    if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
 +        ((!aplic->msimode || (aplic->msimode && !pending)) &&
 +         ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
 +          (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
 +        return;
 +    }
 +
 +    riscv_aplic_set_pending_raw(aplic, irq, pending);
 +}
 +
 +static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic,
 +                                         uint32_t word, uint32_t value,
 +                                         bool pending)
 +{
 +    uint32_t i, irq;
 +
 +    for (i = 0; i < 32; i++) {
 +        irq = word * 32 + i;
 +        if (!irq || aplic->num_irqs <= irq) {
 +            continue;
 +        }
 +
 +        if (value & (1U << i)) {
 +            riscv_aplic_set_pending(aplic, irq, pending);
 +        }
 +    }
 +}
 +
 +static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic,
 +                                              int word)
 +{
 +    uint32_t i, irq, ret = 0;
 +
 +    for (i = 0; i < 32; i++) {
 +        irq = word * 32 + i;
 +        if (!irq || aplic->num_irqs <= irq) {
 +            continue;
 +        }
 +
 +        ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i;
 +    }
 +
 +    return ret;
 +}
 +
 +static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic,
 +                                        uint32_t irq, bool enabled)
 +{
 +    if (enabled) {
 +        aplic->state[irq] |= APLIC_ISTATE_ENABLED;
 +    } else {
 +        aplic->state[irq] &= ~APLIC_ISTATE_ENABLED;
 +    }
 +}
 +
 +static void riscv_aplic_set_enabled(RISCVAPLICState *aplic,
 +                                    uint32_t irq, bool enabled)
 +{
 +    uint32_t sourcecfg, sm;
 +
 +    if ((irq <= 0) || (aplic->num_irqs <= irq)) {
 +        return;
 +    }
 +
 +    sourcecfg = aplic->sourcecfg[irq];
 +    if (sourcecfg & APLIC_SOURCECFG_D) {
 +        return;
 +    }
 +
 +    sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
 +    if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
 +        return;
 +    }
 +
 +    riscv_aplic_set_enabled_raw(aplic, irq, enabled);
 +}
 +
 +static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic,
 +                                         uint32_t word, uint32_t value,
 +                                         bool enabled)
 +{
 +    uint32_t i, irq;
 +
 +    for (i = 0; i < 32; i++) {
 +        irq = word * 32 + i;
 +        if (!irq || aplic->num_irqs <= irq) {
 +            continue;
 +        }
 +
 +        if (value & (1U << i)) {
 +            riscv_aplic_set_enabled(aplic, irq, enabled);
 +        }
 +    }
 +}
 +
 +static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
 +                                 uint32_t hart_idx, uint32_t guest_idx,
 +                                 uint32_t eiid)
 +{
 +    uint64_t addr;
 +    MemTxResult result;
 +    RISCVAPLICState *aplic_m;
 +    uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
 +
 +    aplic_m = aplic;
 +    while (aplic_m && !aplic_m->mmode) {
 +        aplic_m = aplic_m->parent;
 +    }
 +    if (!aplic_m) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
 +                      __func__);
 +        return;
 +    }
 +
 +    if (aplic->mmode) {
 +        msicfgaddr = aplic_m->mmsicfgaddr;
 +        msicfgaddrH = aplic_m->mmsicfgaddrH;
 +    } else {
 +        msicfgaddr = aplic_m->smsicfgaddr;
 +        msicfgaddrH = aplic_m->smsicfgaddrH;
 +    }
 +
 +    lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
 +            APLIC_xMSICFGADDRH_LHXS_MASK;
 +    lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) &
 +            APLIC_xMSICFGADDRH_LHXW_MASK;
 +    hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) &
 +            APLIC_xMSICFGADDRH_HHXS_MASK;
 +    hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) &
 +            APLIC_xMSICFGADDRH_HHXW_MASK;
 +
 +    group_idx = hart_idx >> lhxw;
 +    hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
 +
 +    addr = msicfgaddr;
 +    addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
 +    addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) <<
 +             APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs);
 +    addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) <<
 +             APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs);
 +    addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
 +    addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
 +
 +    address_space_stl_le(&address_space_memory, addr,
 +                         eiid, MEMTXATTRS_UNSPECIFIED, &result);
 +    if (result != MEMTX_OK) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
 +                      "hart_index=%d guest_index=%d eiid=%d\n",
 +                      __func__, hart_idx, guest_idx, eiid);
 +    }
 +}
 +
 +static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq)
 +{
 +    uint32_t hart_idx, guest_idx, eiid;
 +
 +    if (!aplic->msimode || (aplic->num_irqs <= irq) ||
 +        !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) {
 +        return;
 +    }
 +
 +    if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) {
 +        return;
 +    }
 +
 +    riscv_aplic_set_pending_raw(aplic, irq, false);
 +
 +    hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
 +    hart_idx &= APLIC_TARGET_HART_IDX_MASK;
 +    if (aplic->mmode) {
 +        /* M-level APLIC ignores guest_index */
 +        guest_idx = 0;
 +    } else {
 +        guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT;
 +        guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
 +    }
 +    eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK;
 +    riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid);
 +}
 +
 +static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc)
 +{
 +    uint32_t best_irq, best_iprio;
 +    uint32_t irq, iprio, ihartidx, ithres;
 +
 +    if (aplic->num_harts <= idc) {
 +        return 0;
 +    }
 +
 +    ithres = aplic->ithreshold[idc];
 +    best_irq = best_iprio = UINT32_MAX;
 +    for (irq = 1; irq < aplic->num_irqs; irq++) {
 +        if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=
 +            APLIC_ISTATE_ENPEND) {
 +            continue;
 +        }
 +
 +        ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
 +        ihartidx &= APLIC_TARGET_HART_IDX_MASK;
 +        if (ihartidx != idc) {
 +            continue;
 +        }
 +
 +        iprio = aplic->target[irq] & aplic->iprio_mask;
 +        if (ithres && iprio >= ithres) {
 +            continue;
 +        }
 +
 +        if (iprio < best_iprio) {
 +            best_irq = irq;
 +            best_iprio = iprio;
 +        }
 +    }
 +
 +    if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) {
 +        return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio;
 +    }
 +
 +    return 0;
 +}
 +
 +static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc)
 +{
 +    uint32_t topi;
 +
 +    if (aplic->msimode || aplic->num_harts <= idc) {
 +        return;
 +    }
 +
 +    topi = riscv_aplic_idc_topi(aplic, idc);
 +    if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) &&
 +        aplic->idelivery[idc] &&
 +        (aplic->iforce[idc] || topi)) {
 +        qemu_irq_raise(aplic->external_irqs[idc]);
 +    } else {
 +        qemu_irq_lower(aplic->external_irqs[idc]);
 +    }
 +}
 +
 +static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
 +{
 +    uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc);
 +
 +    if (!topi) {
 +        aplic->iforce[idc] = 0;
 +        return 0;
 +    }
 +
 +    irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;
 +    sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
 +    state = aplic->state[irq];
 +    riscv_aplic_set_pending_raw(aplic, irq, false);
 +    if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) &&
 +        (state & APLIC_ISTATE_INPUT)) {
 +        riscv_aplic_set_pending_raw(aplic, irq, true);
 +    } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) &&
 +               !(state & APLIC_ISTATE_INPUT)) {
 +        riscv_aplic_set_pending_raw(aplic, irq, true);
 +    }
 +    riscv_aplic_idc_update(aplic, idc);
 +
 +    return topi;
 +}
 +
 +static void riscv_aplic_request(void *opaque, int irq, int level)
 +{
 +    bool update = false;
 +    RISCVAPLICState *aplic = opaque;
 +    uint32_t sourcecfg, childidx, state, idc;
 +
 +    assert((0 < irq) && (irq < aplic->num_irqs));
 +
 +    sourcecfg = aplic->sourcecfg[irq];
 +    if (sourcecfg & APLIC_SOURCECFG_D) {
 +        childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK;
 +        if (childidx < aplic->num_children) {
 +            riscv_aplic_request(aplic->children[childidx], irq, level);
 +        }
 +        return;
 +    }
 +
 +    state = aplic->state[irq];
 +    switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) {
 +    case APLIC_SOURCECFG_SM_EDGE_RISE:
 +        if ((level > 0) && !(state & APLIC_ISTATE_INPUT) &&
 +            !(state & APLIC_ISTATE_PENDING)) {
 +            riscv_aplic_set_pending_raw(aplic, irq, true);
 +            update = true;
 +        }
 +        break;
 +    case APLIC_SOURCECFG_SM_EDGE_FALL:
 +        if ((level <= 0) && (state & APLIC_ISTATE_INPUT) &&
 +            !(state & APLIC_ISTATE_PENDING)) {
 +            riscv_aplic_set_pending_raw(aplic, irq, true);
 +            update = true;
 +        }
 +        break;
 +    case APLIC_SOURCECFG_SM_LEVEL_HIGH:
 +        if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) {
 +            riscv_aplic_set_pending_raw(aplic, irq, true);
 +            update = true;
 +        }
 +        break;
 +    case APLIC_SOURCECFG_SM_LEVEL_LOW:
 +        if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) {
 +            riscv_aplic_set_pending_raw(aplic, irq, true);
 +            update = true;
 +        }
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    if (level <= 0) {
 +        aplic->state[irq] &= ~APLIC_ISTATE_INPUT;
 +    } else {
 +        aplic->state[irq] |= APLIC_ISTATE_INPUT;
 +    }
 +
 +    if (update) {
 +        if (aplic->msimode) {
 +            riscv_aplic_msi_irq_update(aplic, irq);
 +        } else {
 +            idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
 +            idc &= APLIC_TARGET_HART_IDX_MASK;
 +            riscv_aplic_idc_update(aplic, idc);
 +        }
 +    }
 +}
 +
 +static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    uint32_t irq, word, idc;
 +    RISCVAPLICState *aplic = opaque;
 +
 +    /* Reads must be 4 byte words */
 +    if ((addr & 0x3) != 0) {
 +        goto err;
 +    }
 +
 +    if (addr == APLIC_DOMAINCFG) {
 +        return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg |
 +               (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);
 +    } else if ((APLIC_SOURCECFG_BASE <= addr) &&
 +            (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
 +        irq  = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
 +        return aplic->sourcecfg[irq];
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_MMSICFGADDR)) {
 +        return aplic->mmsicfgaddr;
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_MMSICFGADDRH)) {
 +        return aplic->mmsicfgaddrH;
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_SMSICFGADDR)) {
 +        /*
 +         * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
 +         * (a) the interrupt domain is at machine level
 +         * (b) the domain's harts implement supervisor mode
 +         * (c) the domain has one or more child supervisor-level domains
 +         *     that support MSI delivery mode (domaincfg.DM is not read-
 +         *     only zero in at least one of the supervisor-level child
 +         * domains).
 +         */
 +        return (aplic->num_children) ? aplic->smsicfgaddr : 0;
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_SMSICFGADDRH)) {
 +        return (aplic->num_children) ? aplic->smsicfgaddrH : 0;
 +    } else if ((APLIC_SETIP_BASE <= addr) &&
 +            (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_SETIP_BASE) >> 2;
 +        return riscv_aplic_read_pending_word(aplic, word);
 +    } else if (addr == APLIC_SETIPNUM) {
 +        return 0;
 +    } else if ((APLIC_CLRIP_BASE <= addr) &&
 +            (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_CLRIP_BASE) >> 2;
 +        return riscv_aplic_read_input_word(aplic, word);
 +    } else if (addr == APLIC_CLRIPNUM) {
 +        return 0;
 +    } else if ((APLIC_SETIE_BASE <= addr) &&
 +            (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_SETIE_BASE) >> 2;
 +        return riscv_aplic_read_enabled_word(aplic, word);
 +    } else if (addr == APLIC_SETIENUM) {
 +        return 0;
 +    } else if ((APLIC_CLRIE_BASE <= addr) &&
 +            (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
 +        return 0;
 +    } else if (addr == APLIC_CLRIENUM) {
 +        return 0;
 +    } else if (addr == APLIC_SETIPNUM_LE) {
 +        return 0;
 +    } else if (addr == APLIC_SETIPNUM_BE) {
 +        return 0;
 +    } else if (addr == APLIC_GENMSI) {
 +        return (aplic->msimode) ? aplic->genmsi : 0;
 +    } else if ((APLIC_TARGET_BASE <= addr) &&
 +            (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
 +        irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
 +        return aplic->target[irq];
 +    } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
 +            (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
 +        idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
 +        switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
 +        case APLIC_IDC_IDELIVERY:
 +            return aplic->idelivery[idc];
 +        case APLIC_IDC_IFORCE:
 +            return aplic->iforce[idc];
 +        case APLIC_IDC_ITHRESHOLD:
 +            return aplic->ithreshold[idc];
 +        case APLIC_IDC_TOPI:
 +            return riscv_aplic_idc_topi(aplic, idc);
 +        case APLIC_IDC_CLAIMI:
 +            return riscv_aplic_idc_claimi(aplic, idc);
 +        default:
 +            goto err;
 +        };
 +    }
 +
 +err:
 +    qemu_log_mask(LOG_GUEST_ERROR,
 +                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 +                  __func__, addr);
 +    return 0;
 +}
 +
 +static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
 +        unsigned size)
 +{
 +    RISCVAPLICState *aplic = opaque;
 +    uint32_t irq, word, idc = UINT32_MAX;
 +
 +    /* Writes must be 4 byte words */
 +    if ((addr & 0x3) != 0) {
 +        goto err;
 +    }
 +
 +    if (addr == APLIC_DOMAINCFG) {
 +        /* Only IE bit writeable at the moment */
 +        value &= APLIC_DOMAINCFG_IE;
 +        aplic->domaincfg = value;
 +    } else if ((APLIC_SOURCECFG_BASE <= addr) &&
 +            (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
 +        irq  = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
 +        if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) {
 +            value = 0;
 +        }
 +        if (value & APLIC_SOURCECFG_D) {
 +            value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK);
 +        } else {
 +            value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK);
 +        }
 +        aplic->sourcecfg[irq] = value;
 +        if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) ||
 +            (aplic->sourcecfg[irq] == 0)) {
 +            riscv_aplic_set_pending_raw(aplic, irq, false);
 +            riscv_aplic_set_enabled_raw(aplic, irq, false);
 +        }
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_MMSICFGADDR)) {
 +        if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
 +            aplic->mmsicfgaddr = value;
 +        }
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_MMSICFGADDRH)) {
 +        if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
 +            aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
 +        }
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_SMSICFGADDR)) {
 +        /*
 +         * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
 +         * (a) the interrupt domain is at machine level
 +         * (b) the domain's harts implement supervisor mode
 +         * (c) the domain has one or more child supervisor-level domains
 +         *     that support MSI delivery mode (domaincfg.DM is not read-
 +         *     only zero in at least one of the supervisor-level child
 +         * domains).
 +         */
 +        if (aplic->num_children &&
 +            !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
 +            aplic->smsicfgaddr = value;
 +        }
 +    } else if (aplic->mmode && aplic->msimode &&
 +               (addr == APLIC_SMSICFGADDRH)) {
 +        if (aplic->num_children &&
 +            !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
 +            aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
 +        }
 +    } else if ((APLIC_SETIP_BASE <= addr) &&
 +            (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_SETIP_BASE) >> 2;
 +        riscv_aplic_set_pending_word(aplic, word, value, true);
 +    } else if (addr == APLIC_SETIPNUM) {
 +        riscv_aplic_set_pending(aplic, value, true);
 +    } else if ((APLIC_CLRIP_BASE <= addr) &&
 +            (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_CLRIP_BASE) >> 2;
 +        riscv_aplic_set_pending_word(aplic, word, value, false);
 +    } else if (addr == APLIC_CLRIPNUM) {
 +        riscv_aplic_set_pending(aplic, value, false);
 +    } else if ((APLIC_SETIE_BASE <= addr) &&
 +            (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_SETIE_BASE) >> 2;
 +        riscv_aplic_set_enabled_word(aplic, word, value, true);
 +    } else if (addr == APLIC_SETIENUM) {
 +        riscv_aplic_set_enabled(aplic, value, true);
 +    } else if ((APLIC_CLRIE_BASE <= addr) &&
 +            (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
 +        word = (addr - APLIC_CLRIE_BASE) >> 2;
 +        riscv_aplic_set_enabled_word(aplic, word, value, false);
 +    } else if (addr == APLIC_CLRIENUM) {
 +        riscv_aplic_set_enabled(aplic, value, false);
 +    } else if (addr == APLIC_SETIPNUM_LE) {
 +        riscv_aplic_set_pending(aplic, value, true);
 +    } else if (addr == APLIC_SETIPNUM_BE) {
 +        riscv_aplic_set_pending(aplic, bswap32(value), true);
 +    } else if (addr == APLIC_GENMSI) {
 +        if (aplic->msimode) {
 +            aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK <<
 +                                      APLIC_TARGET_GUEST_IDX_SHIFT);
 +            riscv_aplic_msi_send(aplic,
 +                                 value >> APLIC_TARGET_HART_IDX_SHIFT,
 +                                 0,
 +                                 value & APLIC_TARGET_EIID_MASK);
 +        }
 +    } else if ((APLIC_TARGET_BASE <= addr) &&
 +            (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
 +        irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
 +        if (aplic->msimode) {
 +            aplic->target[irq] = value;
 +        } else {
 +            aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) |
 +                                 ((value & aplic->iprio_mask) ?
 +                                  (value & aplic->iprio_mask) : 1);
 +        }
 +    } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
 +            (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
 +        idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
 +        switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
 +        case APLIC_IDC_IDELIVERY:
 +            aplic->idelivery[idc] = value & 0x1;
 +            break;
 +        case APLIC_IDC_IFORCE:
 +            aplic->iforce[idc] = value & 0x1;
 +            break;
 +        case APLIC_IDC_ITHRESHOLD:
 +            aplic->ithreshold[idc] = value & aplic->iprio_mask;
 +            break;
 +        default:
 +            goto err;
 +        };
 +    } else {
 +        goto err;
 +    }
 +
 +    if (aplic->msimode) {
 +        for (irq = 1; irq < aplic->num_irqs; irq++) {
 +            riscv_aplic_msi_irq_update(aplic, irq);
 +        }
 +    } else {
 +        if (idc == UINT32_MAX) {
 +            for (idc = 0; idc < aplic->num_harts; idc++) {
 +                riscv_aplic_idc_update(aplic, idc);
 +            }
 +        } else {
 +            riscv_aplic_idc_update(aplic, idc);
 +        }
 +    }
 +
 +    return;
 +
 +err:
 +    qemu_log_mask(LOG_GUEST_ERROR,
 +                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 +                  __func__, addr);
 +}
 +
 +static const MemoryRegionOps riscv_aplic_ops = {
 +    .read = riscv_aplic_read,
 +    .write = riscv_aplic_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4
 +    }
 +};
 +
 +static void riscv_aplic_realize(DeviceState *dev, Error **errp)
 +{
 +    uint32_t i;
 +    RISCVAPLICState *aplic = RISCV_APLIC(dev);
 +
 +    aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
 +    aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
 +    aplic->state = g_new(uint32_t, aplic->num_irqs);
 +    aplic->target = g_new0(uint32_t, aplic->num_irqs);
 +    if (!aplic->msimode) {
 +        for (i = 0; i < aplic->num_irqs; i++) {
 +            aplic->target[i] = 1;
 +        }
 +    }
 +    aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
 +    aplic->iforce = g_new0(uint32_t, aplic->num_harts);
 +    aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
 +
 +    memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
 +                          TYPE_RISCV_APLIC, aplic->aperture_size);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
 +
 +    /*
 +     * Only root APLICs have hardware IRQ lines. All non-root APLICs
 +     * have IRQ lines delegated by their parent APLIC.
 +     */
 +    if (!aplic->parent) {
 +        qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
 +    }
 +
 +    /* Create output IRQ lines for non-MSI mode */
 +    if (!aplic->msimode) {
 +        aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
 +        qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
 +
 +        /* Claim the CPU interrupt to be triggered by this APLIC */
 +        for (i = 0; i < aplic->num_harts; i++) {
 +            RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
 +            if (riscv_cpu_claim_interrupts(cpu,
 +                (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
 +                error_report("%s already claimed",
 +                             (aplic->mmode) ? "MEIP" : "SEIP");
 +                exit(1);
 +            }
 +        }
 +    }
 +
 +    msi_nonbroken = true;
 +}
 +
 +static Property riscv_aplic_properties[] = {
 +    DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0),
 +    DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
 +    DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
 +    DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0),
 +    DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0),
 +    DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0),
 +    DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static const VMStateDescription vmstate_riscv_aplic = {
 +    .name = "riscv_aplic",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +            VMSTATE_UINT32(domaincfg, RISCVAPLICState),
 +            VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
 +            VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState),
 +            VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
 +            VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
 +            VMSTATE_UINT32(genmsi, RISCVAPLICState),
 +            VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
 +                                  num_irqs, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_VARRAY_UINT32(state, RISCVAPLICState,
 +                                  num_irqs, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_VARRAY_UINT32(target, RISCVAPLICState,
 +                                  num_irqs, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState,
 +                                  num_harts, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState,
 +                                  num_harts, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState,
 +                                  num_harts, 0,
 +                                  vmstate_info_uint32, uint32_t),
 +            VMSTATE_END_OF_LIST()
 +        }
 +};
 +
 +static void riscv_aplic_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    device_class_set_props(dc, riscv_aplic_properties);
 +    dc->realize = riscv_aplic_realize;
 +    dc->vmsd = &vmstate_riscv_aplic;
 +}
 +
 +static const TypeInfo riscv_aplic_info = {
 +    .name          = TYPE_RISCV_APLIC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(RISCVAPLICState),
 +    .class_init    = riscv_aplic_class_init,
 +};
 +
 +static void riscv_aplic_register_types(void)
 +{
 +    type_register_static(&riscv_aplic_info);
 +}
 +
 +type_init(riscv_aplic_register_types)
 +
 +/*
 + * Add a APLIC device to another APLIC device as child for
 + * interrupt delegation.
 + */
 +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
 +{
 +    RISCVAPLICState *caplic, *paplic;
 +
 +    assert(parent && child);
 +    caplic = RISCV_APLIC(child);
 +    paplic = RISCV_APLIC(parent);
 +
 +    assert(paplic->num_irqs == caplic->num_irqs);
 +    assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
 +
 +    caplic->parent = paplic;
 +    paplic->children[paplic->num_children] = caplic;
 +    paplic->num_children++;
 +}
 +
 +/*
 + * Create APLIC device.
 + */
 +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
 +    uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
 +    uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
 +{
 +    DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
 +    uint32_t i;
 +
 +    assert(num_harts < APLIC_MAX_IDC);
 +    assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
 +    assert(num_sources < APLIC_MAX_SOURCE);
 +    assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
 +    assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
 +
 +    qdev_prop_set_uint32(dev, "aperture-size", size);
 +    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
 +    qdev_prop_set_uint32(dev, "num-harts", num_harts);
 +    qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
 +    qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
 +    qdev_prop_set_bit(dev, "msimode", msimode);
 +    qdev_prop_set_bit(dev, "mmode", mmode);
 +
 +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 +
 +    if (parent) {
 +        riscv_aplic_add_child(parent, dev);
 +    }
 +
 +    if (!msimode) {
 +        for (i = 0; i < num_harts; i++) {
 +            CPUState *cpu = qemu_get_cpu(hartid_base + i);
 +
 +            qdev_connect_gpio_out_named(dev, NULL, i,
 +                                        qdev_get_gpio_in(DEVICE(cpu),
 +                                            (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
 +        }
 +    }
 +
 +    return dev;
 +}
 diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/Kconfig
+--- a/target/riscv/meson.build
-+++ b/hw/intc/Kconfig
++++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
- config RISCV_ACLINT
+   'gdbstub.c',
-     bool
+   'op_helper.c',
+   'vector_helper.c',
-+config RISCV_APLIC
++  'vector_internals.c',
-+    bool
+   'bitmanip_helper.c',
-+
+   'translate.c',
- config SIFIVE_PLIC
+   'm128_helper.c',
      bool
 diff --git a/hw/intc/meson.build b/hw/intc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/meson.build
 +++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
  specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
  specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
 +specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
  specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
  specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
 --
-.34.1
+.41.0

-[PULL 08/40] target/riscv: iterate over a table of decoders
+[PULL v2 09/45] target/riscv: Refactor vector-vector translation macro
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
-To split up the decoder into multiple functions (both to support
+Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
-vendor-specific opcodes in separate files and to simplify maintenance
+function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
-of orthogonal extensions), this changes decode_op to iterate over a
+used in proceeding vector-crypto commits.
 table of decoders predicated on guard functions.
-This commit only adds the new structure and the table, allowing for
+Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 the easy addition of additional decoders in the future.
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220202005249.3566542-6-philipp.tomsich@vrull.eu>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 32 +++++++++++++++++++++++++++-----
+ target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
-file changed, 27 insertions(+), 5 deletions(-)
+file changed, 32 insertions(+), 30 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
-     return ctx->misa_ext & ext;
+ GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
- }
+ GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
-+static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
++static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
 +                        gen_helper_gvec_4_ptr *fn, DisasContext *s)
 +{
++    uint32_t data = 0;
++    TCGLabel *over = gen_new_label();
++    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
++    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
++
++    data = FIELD_DP32(data, VDATA, VM, vm);
++    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
++    data = FIELD_DP32(data, VDATA, VTA, s->vta);
++    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
++    data = FIELD_DP32(data, VDATA, VMA, s->vma);
++    tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
++                       vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
++                       s->cfg_ptr->vlen / 8, data, fn);
++    mark_vs_dirty(s);
++    gen_set_label(over);
 +    return true;
 +}
 +
- #ifdef TARGET_RISCV32
+ /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
- #define get_xl(ctx)    MXL_RV32
+ /* OPIVV without GVEC IR */
- #elif defined(CONFIG_USER_ONLY)
+-#define GEN_OPIVV_TRANS(NAME, CHECK)                               \
-@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+-static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
+-{                                                                  \
- static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+-    if (CHECK(s, a)) {                                             \
- {
+-        uint32_t data = 0;                                         \
--    /* check for compressed insn */
+-        static gen_helper_gvec_4_ptr * const fns[4] = {            \
-+    /*
+-            gen_helper_##NAME##_b, gen_helper_##NAME##_h,          \
-+     * A table with predicate (i.e., guard) functions and decoder functions
+-            gen_helper_##NAME##_w, gen_helper_##NAME##_d,          \
-+     * that are tested in-order until a decoder matches onto the opcode.
+-        };                                                         \
-+     */
+-        TCGLabel *over = gen_new_label();                          \
-+    static const struct {
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-+        bool (*guard_func)(DisasContext *);
+-        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-+        bool (*decode_func)(DisasContext *, uint32_t);
+-                                                                   \
-+    } decoders[] = {
+-        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-+        { always_true_p,  decode_insn32 },
+-        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-+    };
+-        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
-+
+-        data =                                                     \
-+    /* Check for compressed insn */
+-            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
-     if (extract16(opcode, 0, 2) != 3) {
+-        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
-         if (!has_ext(ctx, RVC)) {
+-        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-             gen_exception_illegal(ctx);
+-                           vreg_ofs(s, a->rs1),                    \
-         } else {
+-                           vreg_ofs(s, a->rs2), cpu_env,           \
-             ctx->opcode = opcode;
+-                           s->cfg_ptr->vlen / 8,                   \
-             ctx->pc_succ_insn = ctx->base.pc_next + 2;
+-                           s->cfg_ptr->vlen / 8, data,             \
--            if (!decode_insn16(ctx, opcode)) {
+-                           fns[s->sew]);                           \
--                gen_exception_illegal(ctx);
+-        mark_vs_dirty(s);                                          \
-+            if (decode_insn16(ctx, opcode)) {
+-        gen_set_label(over);                                       \
-+                return;
+-        return true;                                               \
-             }
+-    }                                                              \
-         }
+-    return false;                                                  \
-     } else {
++#define GEN_OPIVV_TRANS(NAME, CHECK)                                     \
-@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
++static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
-                                              ctx->base.pc_next + 2));
++{                                                                        \
-         ctx->opcode = opcode32;
++    if (CHECK(s, a)) {                                                   \
-         ctx->pc_succ_insn = ctx->base.pc_next + 4;
++        static gen_helper_gvec_4_ptr * const fns[4] = {                  \
--        if (!decode_insn32(ctx, opcode32)) {
++            gen_helper_##NAME##_b, gen_helper_##NAME##_h,                \
--            gen_exception_illegal(ctx);
++            gen_helper_##NAME##_w, gen_helper_##NAME##_d,                \
-+
++        };                                                               \
-+        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
++        return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
-+            if (decoders[i].guard_func(ctx) &&
++    }                                                                    \
-+                decoders[i].decode_func(ctx, opcode32)) {
++    return false;                                                        \
 +                return;
 +            }
          }
      }
 +
 +    gen_exception_illegal(ctx);
  }
- static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+ /*
 --
-.34.1
+.41.0

-[PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext
+[PULL v2 10/45] target/riscv: Remove redundant "cpu_vl == 0" checks
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
+Remove the redundant "vl == 0" check which is already included within the  vstart >= vl check, when vl == 0.
 copies (in DisasContext) of some of the elements available in the
 RISCVCPUConfig structure.  This commit redirects accesses to use the
 cfg_ptr copied into DisasContext and removes the shallow copies.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
+Message-ID: <20230711165917.2629866-4-max.chou@sifive.com>
 [ Changes by AF:
  - Fixup checkpatch failures
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                  |  14 ---
+ target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------
- target/riscv/insn_trans/trans_rvi.c.inc   |   2 +-
+file changed, 1 insertion(+), 30 deletions(-)
  target/riscv/insn_trans/trans_rvv.c.inc   | 146 ++++++++++++++--------
  target/riscv/insn_trans/trans_rvzfh.c.inc |   4 +-
 files changed, 97 insertions(+), 69 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     RISCVMXL ol;
-     bool virt_enabled;
-     const RISCVCPUConfig *cfg_ptr;
--    bool ext_ifencei;
--    bool ext_zfh;
--    bool ext_zfhmin;
--    bool ext_zve32f;
--    bool ext_zve64f;
-     bool hlsx;
-     /* vector extension */
-     bool vill;
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-      */
-     int8_t lmul;
-     uint8_t sew;
--    uint16_t vlen;
--    uint16_t elen;
-     target_ulong vstart;
-     bool vl_eq_vlmax;
-     uint8_t ntemp;
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->misa_ext = env->misa_ext;
-     ctx->frm = -1;  /* unknown rounding mode */
-     ctx->cfg_ptr = &(cpu->cfg);
--    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
--    ctx->ext_zfh = cpu->cfg.ext_zfh;
--    ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
--    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
--    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
--    ctx->vlen = cpu->cfg.vlen;
--    ctx->elen = cpu->cfg.elen;
-     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-     ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
-     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
- static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
- {
--    if (!ctx->ext_ifencei) {
-+    if (!ctx->cfg_ptr->ext_ifencei) {
-         return false;
-     }
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool require_zve32f(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
-     }
+     TCGv_i32 desc;
-     /* Zve32f doesn't support FP64. (Section 18.2) */
+     TCGLabel *over = gen_new_label();
--    return s->ext_zve32f ? s->sew <= MO_32 : true;
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-+    return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
- }
+     dest = tcg_temp_new_ptr();
- static bool require_scale_zve32f(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
-@@ -XXX,XX +XXX,XX @@ static bool require_scale_zve32f(DisasContext *s)
+     TCGv_i32 desc;
-     }
+     TCGLabel *over = gen_new_label();
-     /* Zve32f doesn't support FP64. (Section 18.2) */
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
--    return s->ext_zve64f ? s->sew <= MO_16 : true;
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
- }
+     dest = tcg_temp_new_ptr();
+@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- static bool require_zve64f(DisasContext *s)
+     TCGv_i32 desc;
-@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
-     }
+     TCGLabel *over = gen_new_label();
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     /* Zve64f doesn't support FP64. (Section 18.2) */
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
--    return s->ext_zve64f ? s->sew <= MO_32 : true;
-+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
+     dest = tcg_temp_new_ptr();
- }
+@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+     TCGv_i32 desc;
- static bool require_scale_zve64f(DisasContext *s)
-@@ -XXX,XX +XXX,XX @@ static bool require_scale_zve64f(DisasContext *s)
+     TCGLabel *over = gen_new_label();
-     }
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-     /* Zve64f doesn't support FP64. (Section 18.2) */
--    return s->ext_zve64f ? s->sew <= MO_16 : true;
+     dest = tcg_temp_new_ptr();
-+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
+@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
  }
  /* Destination vector register group cannot overlap source mask register. */
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
      TCGv s1, dst;
      if (!require_rvv(s) ||
 -        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
 +        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
 +          s->cfg_ptr->ext_zve64f)) {
          return false;
      }
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     TCGv dst;
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-     if (!require_rvv(s) ||
+     if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
--        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
-+        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
+     uint32_t data = 0;
-+          s->cfg_ptr->ext_zve64f)) {
-         return false;
+     TCGLabel *over = gen_new_label();
-     }
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
- /* vector register offset from env */
+     dest = tcg_temp_new_ptr();
- static uint32_t vreg_ofs(DisasContext *s, int reg)
+@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
      uint32_t data = 0;
      TCGLabel *over = gen_new_label();
 -    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
      if (checkfn(s, a)) {
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
 -        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
      if (opiwv_widen_check(s, a)) {
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
 -        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
  {
--    return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
+     uint32_t data = 0;
-+    return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
+     TCGLabel *over = gen_new_label();
- }
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
  /* check functions */
@@ -XXX,XX +XXX,XX @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
       * when XLEN=32. (Section 18.2)
       */
      if (get_xl(s) == MXL_RV32) {
 -        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
 +        ret &= (!has_ext(s, RVV) &&
 +                s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
      }
      return ret;
@@ -XXX,XX +XXX,XX @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm)
  {
      return (s->lmul <= 2) &&
             (s->sew < MO_64) &&
 -           ((s->sew + 1) <= (s->elen >> 4)) &&
 +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
             require_align(vd, s->lmul + 1) &&
             require_vm(vm, vd);
  }
@@ -XXX,XX +XXX,XX @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
  {
      return (s->lmul <= 2) &&
             (s->sew < MO_64) &&
 -           ((s->sew + 1) <= (s->elen >> 4)) &&
 +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
             require_align(vs2, s->lmul + 1) &&
             require_align(vd, s->lmul) &&
             require_vm(vm, vd);
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
       * The first part is vlen in bytes, encoded in maxsz of simd_desc.
       * The second part is lmul, encoded in data of simd_desc.
       */
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      mask = tcg_temp_new_ptr();
      base = get_gpr(s, rs1, EXT_NONE);
      stride = get_gpr(s, rs2, EXT_NONE);
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      mask = tcg_temp_new_ptr();
      index = tcg_temp_new_ptr();
      base = get_gpr(s, rs1, EXT_NONE);
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      base = get_gpr(s, rs1, EXT_NONE);
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
      uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
      dest = tcg_temp_new_ptr();
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      base = get_gpr(s, rs1, EXT_NONE);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
  static inline uint32_t MAXSZ(DisasContext *s)
  {
      int scale = s->lmul - 3;
 -    return scale < 0 ? s->vlen >> -scale : s->vlen << scale;
 +    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
  }
  static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
 -                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
 +                           cpu_env, s->cfg_ptr->vlen / 8,
 +                           s->cfg_ptr->vlen / 8, data, fn);
      }
      mark_vs_dirty(s);
      gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      data = FIELD_DP32(data, VDATA, VM, vm);
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
-+                                      s->cfg_ptr->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
-     data = FIELD_DP32(data, VDATA, VM, vm);
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
-+                                      s->cfg_ptr->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1),
-                            vreg_ofs(s, a->rs2),
--                           cpu_env, s->vlen / 8, s->vlen / 8,
-+                           cpu_env, s->cfg_ptr->vlen / 8,
-+                           s->cfg_ptr->vlen / 8,
-                            data, fn);
-         mark_vs_dirty(s);
-         gen_set_label(over);
-@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1),
-                            vreg_ofs(s, a->rs2),
--                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
-+                           cpu_env, s->cfg_ptr->vlen / 8,
-+                           s->cfg_ptr->vlen / 8, data, fn);
-         mark_vs_dirty(s);
-         gen_set_label(over);
-         return true;
 @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
+             gen_helper_##NAME##_w,                                 \
-                            vreg_ofs(s, a->rs1),                    \
+         };                                                         \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
+         TCGLabel *over = gen_new_label();                          \
--                           s->vlen / 8, s->vlen / 8, data,         \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-+                           s->cfg_ptr->vlen / 8,                   \
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-+                           s->cfg_ptr->vlen / 8, data,             \
+                                                                    \
-                            fns[s->sew]);                           \
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         mark_vs_dirty(s);                                          \
+@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
-         gen_set_label(over);                                       \
+                 gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
              };
              TCGLabel *over = gen_new_label();
 -            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
              tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
              tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          vext_check_ss(s, a->rd, 0, 1)) {
          TCGv s1;
          TCGLabel *over = gen_new_label();
 -        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          s1 = get_gpr(s, a->rs1, EXT_SIGN);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
                  gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
              };
              TCGLabel *over = gen_new_label();
 -            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
              tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
              s1 = tcg_constant_i64(simm);
 @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
+         };                                                         \
-                            vreg_ofs(s, a->rs1),                    \
+         TCGLabel *over = gen_new_label();                          \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
+         gen_set_rm(s, RISCV_FRM_DYN);                              \
--                           s->vlen / 8, s->vlen / 8, data,         \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-+                           s->cfg_ptr->vlen / 8,                   \
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-+                           s->cfg_ptr->vlen / 8, data,             \
+                                                                    \
-                            fns[s->sew]);                           \
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         mark_vs_dirty(s);                                          \
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-         gen_set_label(over);                                       \
+     TCGv_i64 t1;
-@@ -XXX,XX +XXX,XX @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
-      * are not included for EEW=64 in Zve64*. (Section 18.2)
+     TCGLabel *over = gen_new_label();
-      */
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     return opivv_check(s, a) &&
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
--           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
-+           (!has_ext(s, RVV) &&
+     dest = tcg_temp_new_ptr();
-+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
- }
+         };                                                       \
+         TCGLabel *over = gen_new_label();                        \
- static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+         gen_set_rm(s, RISCV_FRM_DYN);                            \
-@@ -XXX,XX +XXX,XX @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
-      * are not included for EEW=64 in Zve64*. (Section 18.2)
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
-      */
+                                                                  \
-     return opivx_check(s, a) &&
+         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
--           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-+           (!has_ext(s, RVV) &&
+         };                                                         \
-+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+         TCGLabel *over = gen_new_label();                          \
- }
+         gen_set_rm(s, RISCV_FRM_DYN);                              \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
- GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+                                                                    \
-             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
+@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
-             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+         uint32_t data = 0;
--                               cpu_env, s->vlen / 8, s->vlen / 8, data,
+         TCGLabel *over = gen_new_label();
-+                               cpu_env, s->cfg_ptr->vlen / 8,
+         gen_set_rm_chkfrm(s, rm);
-+                               s->cfg_ptr->vlen / 8, data,
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-                                fns[s->sew]);
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-             gen_set_label(over);
-         }
+         data = FIELD_DP32(data, VDATA, VM, a->vm);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                  gen_helper_vmv_v_x_d,
              };
+             TCGLabel *over = gen_new_label();
-             tcg_gen_ext_tl_i64(s1_i64, s1);
+-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
--            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+             tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-+            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
-+                                              s->cfg_ptr->vlen / 8, data));
+             t1 = tcg_temp_new_i64();
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-             fns[s->sew](dest, s1_i64, cpu_env, desc);
+         };                                                         \
+         TCGLabel *over = gen_new_label();                          \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
+         gen_set_rm_chkfrm(s, FRM);                                 \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-             s1 = tcg_constant_i64(simm);
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-             dest = tcg_temp_new_ptr();
+                                                                    \
--            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-+            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-+                                              s->cfg_ptr->vlen / 8, data));
+         };                                                         \
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+         TCGLabel *over = gen_new_label();                          \
-             fns[s->sew](dest, s1, cpu_env, desc);
+         gen_set_rm(s, RISCV_FRM_DYN);                              \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-@@ -XXX,XX +XXX,XX @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-      * for EEW=64 in Zve64*. (Section 18.2)
+                                                                    \
-      */
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-     return opivv_check(s, a) &&
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
--           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+         };                                                         \
-+           (!has_ext(s, RVV) &&
+         TCGLabel *over = gen_new_label();                          \
-+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+         gen_set_rm_chkfrm(s, FRM);                                 \
- }
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
- static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
+                                                                    \
-@@ -XXX,XX +XXX,XX @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-      * for EEW=64 in Zve64*. (Section 18.2)
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-      */
+         };                                                         \
-     return opivx_check(s, a) &&
+         TCGLabel *over = gen_new_label();                          \
--           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+         gen_set_rm_chkfrm(s, FRM);                                 \
-+           (!has_ext(s, RVV) &&
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
- }
+                                                                    \
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
- GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
+         uint32_t data = 0;                                         \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
+         gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
-                            vreg_ofs(s, a->rs1),                    \
+         TCGLabel *over = gen_new_label();                          \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
--                           s->vlen / 8, s->vlen / 8, data,         \
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-+                           s->cfg_ptr->vlen / 8,                   \
+                                                                    \
 +                           s->cfg_ptr->vlen / 8, data,             \
                             fns[s->sew - 1]);                       \
          mark_vs_dirty(s);                                          \
          gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      src2 = tcg_temp_new_ptr();
 -    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                      s->cfg_ptr->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                             vreg_ofs(s, a->rs1),                  \
                             vreg_ofs(s, a->rs2), cpu_env,         \
 -                           s->vlen / 8, s->vlen / 8, data,       \
 +                           s->cfg_ptr->vlen / 8,                 \
 +                           s->cfg_ptr->vlen / 8, data,           \
                             fns[s->sew - 1]);                     \
          mark_vs_dirty(s);                                        \
          gen_set_label(over);                                     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs1),                    \
                             vreg_ofs(s, a->rs2), cpu_env,           \
 -                           s->vlen / 8, s->vlen / 8, data,         \
 +                           s->cfg_ptr->vlen / 8,                   \
 +                           s->cfg_ptr->vlen / 8, data,             \
                             fns[s->sew - 1]);                       \
          mark_vs_dirty(s);                                          \
          gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs2), cpu_env,
 -                           s->vlen / 8, s->vlen / 8, data, fn);
 +                           s->cfg_ptr->vlen / 8,
 +                           s->cfg_ptr->vlen / 8, data, fn);
          mark_vs_dirty(s);
          gen_set_label(over);
          return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
              do_nanbox(s, t1, cpu_fpr[a->rs1]);
              dest = tcg_temp_new_ptr();
 -            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
 +                                              s->cfg_ptr->vlen / 8, data));
              tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
              fns[s->sew - 1](dest, t1, cpu_env, desc);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
--                           s->vlen / 8, s->vlen / 8, data,         \
-+                           s->cfg_ptr->vlen / 8,                   \
-+                           s->cfg_ptr->vlen / 8, data,             \
-                            fns[s->sew - 1]);                       \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
--                           s->vlen / 8, s->vlen / 8, data,         \
-+                           s->cfg_ptr->vlen / 8,                   \
-+                           s->cfg_ptr->vlen / 8, data,             \
-                            fns[s->sew]);                           \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
--                           s->vlen / 8, s->vlen / 8, data,         \
-+                           s->cfg_ptr->vlen / 8,                   \
-+                           s->cfg_ptr->vlen / 8, data,             \
-                            fns[s->sew - 1]);                       \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
--                           s->vlen / 8, s->vlen / 8, data,         \
-+                           s->cfg_ptr->vlen / 8,                   \
-+                           s->cfg_ptr->vlen / 8, data,             \
-                            fns[s->sew]);                           \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-@@ -XXX,XX +XXX,XX @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
- static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
- {
-     return reduction_check(s, a) && (s->sew < MO_64) &&
--           ((s->sew + 1) <= (s->elen >> 4));
-+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
- }
- GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
-                            vreg_ofs(s, a->rs2), cpu_env,           \
--                           s->vlen / 8, s->vlen / 8, data, fn);    \
-+                           s->cfg_ptr->vlen / 8,                   \
-+                           s->cfg_ptr->vlen / 8, data, fn);        \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-         return true;                                               \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = dest_gpr(s, a->rd);
--        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
-+                                          s->cfg_ptr->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = dest_gpr(s, a->rd);
--        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
-+                                          s->cfg_ptr->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
-                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
--                           cpu_env, s->vlen / 8, s->vlen / 8,      \
-+                           cpu_env, s->cfg_ptr->vlen / 8,          \
-+                           s->cfg_ptr->vlen / 8,                   \
-                            data, fn);                              \
-         mark_vs_dirty(s);                                          \
-         gen_set_label(over);                                       \
-@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
-         };
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs2), cpu_env,
--                           s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
-+                           s->cfg_ptr->vlen / 8,
-+                           s->cfg_ptr->vlen / 8, data, fns[s->sew]);
-         mark_vs_dirty(s);
-         gen_set_label(over);
-         return true;
 @@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
-             gen_helper_vid_v_w, gen_helper_vid_v_d,
+         require_vm(a->vm, a->rd)) {
-         };
+         uint32_t data = 0;
-         tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+         TCGLabel *over = gen_new_label();
--                           cpu_env, s->vlen / 8, s->vlen / 8,
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-+                           cpu_env, s->cfg_ptr->vlen / 8,
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-+                           s->cfg_ptr->vlen / 8,
-                            data, fns[s->sew]);
+         data = FIELD_DP32(data, VDATA, VM, a->vm);
-         mark_vs_dirty(s);
+@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
-         gen_set_label(over);
+         TCGv s1;
-@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
+         TCGLabel *over = gen_new_label();
-     if (a->vm && s->vl_eq_vlmax) {
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-         int scale = s->lmul - (s->sew + 3);
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
--        int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
-+        int vlmax = scale < 0 ?
+         t1 = tcg_temp_new_i64();
-+                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
-         TCGv_i64 dest = tcg_temp_new_i64();
+         TCGv_i64 t1;
+         TCGLabel *over = gen_new_label();
-         if (a->rs1 == 0) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
+-        /* if vl == 0 or vstart >= vl, skip vector register write back */
+-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     if (a->vm && s->vl_eq_vlmax) {
++        /* if vstart >= vl, skip vector register write back */
-         int scale = s->lmul - (s->sew + 3);
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
--        int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
-+        int vlmax = scale < 0 ?
+         /* NaN-box f[rs1] */
 +                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
          if (a->rs1 >= vlmax) {
              tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
                                   MAXSZ(s), MAXSZ(s), 0);
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
 -                           cpu_env, s->vlen / 8, s->vlen / 8, data,
 +                           cpu_env, s->cfg_ptr->vlen / 8,
 +                           s->cfg_ptr->vlen / 8, data,
                             fns[s->sew]);
          mark_vs_dirty(s);
          gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
      if (require_rvv(s) &&                                               \
          QEMU_IS_ALIGNED(a->rd, LEN) &&                                  \
          QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
 -        uint32_t maxsz = (s->vlen >> 3) * LEN;                          \
 +        uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
          if (s->vstart == 0) {                                           \
              /* EEW = 8 */                                               \
              tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),                  \
 @@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
+     uint32_t data = 0;
-     tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+     gen_helper_gvec_3_ptr *fn;
-                        vreg_ofs(s, a->rs2), cpu_env,
+     TCGLabel *over = gen_new_label();
--                       s->vlen / 8, s->vlen / 8, data, fn);
+-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-+                       s->cfg_ptr->vlen / 8,
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-+                       s->cfg_ptr->vlen / 8, data, fn);
+     static gen_helper_gvec_3_ptr * const fns[6][4] = {
      mark_vs_dirty(s);
      gen_set_label(over);
 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -XXX,XX +XXX,XX @@
   */
  #define REQUIRE_ZFH(ctx) do { \
 -    if (!ctx->ext_zfh) {      \
 +    if (!ctx->cfg_ptr->ext_zfh) {      \
          return false;         \
      }                         \
  } while (0)
  #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do {       \
 -    if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \
 +    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
          return false;                         \
      }                                         \
  } while (0)
 --
-.34.1
+.41.0

-[PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation
+[PULL v2 11/45] target/riscv: Add Zvbc ISA extension support
-From: Anup Patel <anup.patel@wdc.com>
+From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
-The RISC-V AIA (Advanced Interrupt Architecture) defines a new
+This commit adds support for the Zvbc vector-crypto extension, which
-interrupt controller for MSIs (message signal interrupts) called
+consists of the following instructions:
-IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
-is per-HART device and also suppport virtualizaiton of MSIs using
+* vclmulh.[vx,vv]
-dedicated VS-level guest interrupt files.
+* vclmul.[vx,vv]
-This patch adds device emulation for RISC-V AIA IMSIC which
+Translation functions are defined in
-supports M-level, S-level, and VS-level MSIs.
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
+`target/riscv/vcrypto_helper.c`.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Co-authored-by: Max Chou <max.chou@sifive.com>
-Message-id: 20220204174700.534953-21-anup@brainfault.org
+Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 [max.chou@sifive.com: Exposed x-zvbc property]
 Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/intc/riscv_imsic.h |  68 ++++++
+ target/riscv/cpu_cfg.h                   |  1 +
- hw/intc/riscv_imsic.c         | 448 ++++++++++++++++++++++++++++++++++
+ target/riscv/helper.h                    |  6 +++
- hw/intc/Kconfig               |   3 +
+ target/riscv/insn32.decode               |  6 +++
- hw/intc/meson.build           |   1 +
+ target/riscv/cpu.c                       |  9 ++++
-files changed, 520 insertions(+)
+ target/riscv/translate.c                 |  1 +
- create mode 100644 include/hw/intc/riscv_imsic.h
+ target/riscv/vcrypto_helper.c            | 59 ++++++++++++++++++++++
- create mode 100644 hw/intc/riscv_imsic.c
+ target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++
+ target/riscv/meson.build                 |  3 +-
-diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h
+files changed, 146 insertions(+), 1 deletion(-)
  create mode 100644 target/riscv/vcrypto_helper.c
  create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_cfg.h
 +++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
      bool ext_zve32f;
      bool ext_zve64f;
      bool ext_zve64d;
 +    bool ext_zvbc;
      bool ext_zmmul;
      bool ext_zvfbfmin;
      bool ext_zvfbfwma;
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
  DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32)
  DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32)
 +
 +/* Vector crypto functions */
 +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vfwcvtbf16_f_f_v  010010 . ..... 01101 001 ..... 1010111 @r2_vm
  # *** Zvfbfwma Standard Extension ***
  vfwmaccbf16_vv    111011 . ..... ..... 001 ..... 1010111 @r_vm
  vfwmaccbf16_vf    111011 . ..... ..... 101 ..... 1010111 @r_vm
 +
 +# *** Zvbc vector crypto extension ***
 +vclmul_vv   001100 . ..... ..... 010 ..... 1010111 @r_vm
 +vclmul_vx   001100 . ..... ..... 110 ..... 1010111 @r_vm
 +vclmulh_vv  001101 . ..... ..... 010 ..... 1010111 @r_vm
 +vclmulh_vx  001101 . ..... ..... 110 ..... 1010111 @r_vm
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
      ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
      ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
 +    ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
      ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 +    if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
 +        error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
 +        return;
 +    }
 +
      if (cpu->cfg.ext_zk) {
          cpu->cfg.ext_zkn = true;
          cpu->cfg.ext_zkr = true;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
      DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
 +    /* Vector cryptography extensions */
 +    DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
 +
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  #include "insn_trans/trans_rvzfa.c.inc"
  #include "insn_trans/trans_rvzfh.c.inc"
  #include "insn_trans/trans_rvk.c.inc"
 +#include "insn_trans/trans_rvvk.c.inc"
  #include "insn_trans/trans_privileged.c.inc"
  #include "insn_trans/trans_svinval.c.inc"
  #include "insn_trans/trans_rvbf16.c.inc"
 diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/intc/riscv_imsic.h
++++ b/target/riscv/vcrypto_helper.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
++ * RISC-V Vector Crypto Extension Helpers for QEMU.
 + *
-+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
++ * Copyright (C) 2023 SiFive, Inc.
 + * Written by Codethink Ltd and SiFive.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#ifndef HW_RISCV_IMSIC_H
++#include "qemu/osdep.h"
-+#define HW_RISCV_IMSIC_H
++#include "qemu/host-utils.h"
-+
++#include "qemu/bitops.h"
-+#include "hw/sysbus.h"
++#include "cpu.h"
-+#include "qom/object.h"
++#include "exec/memop.h"
-+
++#include "exec/exec-all.h"
-+#define TYPE_RISCV_IMSIC "riscv.imsic"
++#include "exec/helper-proto.h"
-+
++#include "internals.h"
-+typedef struct RISCVIMSICState RISCVIMSICState;
++#include "vector_internals.h"
-+DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
++
-+
++static uint64_t clmul64(uint64_t y, uint64_t x)
-+#define IMSIC_MMIO_PAGE_SHIFT          12
++{
-+#define IMSIC_MMIO_PAGE_SZ             (1UL << IMSIC_MMIO_PAGE_SHIFT)
++    uint64_t result = 0;
-+#define IMSIC_MMIO_SIZE(__num_pages)   ((__num_pages) * IMSIC_MMIO_PAGE_SZ)
++    for (int j = 63; j >= 0; j--) {
-+
++        if ((y >> j) & 1) {
-+#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
++            result ^= (x << j);
-+#define IMSIC_MMIO_GROUP_MIN_SHIFT     24
++        }
-+
++    }
-+#define IMSIC_HART_NUM_GUESTS(__guest_bits)           \
++    return result;
-+    (1U << (__guest_bits))
++}
-+#define IMSIC_HART_SIZE(__guest_bits)                 \
++
-+    (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
++static uint64_t clmulh64(uint64_t y, uint64_t x)
-+#define IMSIC_GROUP_NUM_HARTS(__hart_bits)            \
++{
-+    (1U << (__hart_bits))
++    uint64_t result = 0;
-+#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits)   \
++    for (int j = 63; j >= 1; j--) {
-+    (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
++        if ((y >> j) & 1) {
-+
++            result ^= (x >> (64 - j));
-+struct RISCVIMSICState {
++        }
-+    /*< private >*/
++    }
-+    SysBusDevice parent_obj;
++    return result;
-+    qemu_irq *external_irqs;
++}
 +
-+    /*< public >*/
++RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64)
-+    MemoryRegion mmio;
++GEN_VEXT_VV(vclmul_vv, 8)
-+    uint32_t num_eistate;
++RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64)
-+    uint32_t *eidelivery;
++GEN_VEXT_VX(vclmul_vx, 8)
-+    uint32_t *eithreshold;
++RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
-+    uint32_t *eistate;
++GEN_VEXT_VV(vclmulh_vv, 8)
-+
++RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
-+    /* config */
++GEN_VEXT_VX(vclmulh_vx, 8)
-+    bool mmode;
+diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
 +    uint32_t hartid;
 +    uint32_t num_pages;
 +    uint32_t num_irqs;
 +};
 +
 +DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
 +                                uint32_t num_pages, uint32_t num_ids);
 +
 +#endif
 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/intc/riscv_imsic.c
++++ b/target/riscv/insn_trans/trans_rvvk.c.inc
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V IMSIC (Incoming Message Signaled Interrupt Controller)
++ * RISC-V translation routines for the vector crypto extension.
 + *
-+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
++ * Copyright (C) 2023 SiFive, Inc.
 + * Written by Codethink Ltd and SiFive.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#include "qemu/osdep.h"
-+#include "qapi/error.h"
-+#include "qemu/log.h"
-+#include "qemu/module.h"
-+#include "qemu/error-report.h"
-+#include "qemu/bswap.h"
-+#include "exec/address-spaces.h"
-+#include "hw/sysbus.h"
-+#include "hw/pci/msi.h"
-+#include "hw/boards.h"
-+#include "hw/qdev-properties.h"
-+#include "hw/intc/riscv_imsic.h"
-+#include "hw/irq.h"
-+#include "target/riscv/cpu.h"
-+#include "target/riscv/cpu_bits.h"
-+#include "sysemu/sysemu.h"
-+#include "migration/vmstate.h"
-+
-+#define IMSIC_MMIO_PAGE_LE             0x00
-+#define IMSIC_MMIO_PAGE_BE             0x04
-+
-+#define IMSIC_MIN_ID                   ((IMSIC_EIPx_BITS * 2) - 1)
-+#define IMSIC_MAX_ID                   (IMSIC_TOPEI_IID_MASK)
-+
-+#define IMSIC_EISTATE_PENDING          (1U << 0)
-+#define IMSIC_EISTATE_ENABLED          (1U << 1)
-+#define IMSIC_EISTATE_ENPEND           (IMSIC_EISTATE_ENABLED | \
-+                                        IMSIC_EISTATE_PENDING)
-+
-+static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
-+{
-+    uint32_t i, max_irq, base;
-+
-+    base = page * imsic->num_irqs;
-+    max_irq = (imsic->eithreshold[page] &&
-+               (imsic->eithreshold[page] <= imsic->num_irqs)) ?
-+               imsic->eithreshold[page] : imsic->num_irqs;
-+    for (i = 1; i < max_irq; i++) {
-+        if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
-+                IMSIC_EISTATE_ENPEND) {
-+            return (i << IMSIC_TOPEI_IID_SHIFT) | i;
-+        }
-+    }
-+
-+    return 0;
-+}
-+
-+static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
-+{
-+    if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
-+        qemu_irq_raise(imsic->external_irqs[page]);
-+    } else {
-+        qemu_irq_lower(imsic->external_irqs[page]);
-+    }
-+}
-+
-+static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
-+                                      target_ulong *val,
-+                                      target_ulong new_val,
-+                                      target_ulong wr_mask)
-+{
-+    target_ulong old_val = imsic->eidelivery[page];
-+
-+    if (val) {
-+        *val = old_val;
-+    }
-+
-+    wr_mask &= 0x1;
-+    imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
-+
-+    riscv_imsic_update(imsic, page);
-+    return 0;
-+}
-+
-+static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
-+                                      target_ulong *val,
-+                                      target_ulong new_val,
-+                                      target_ulong wr_mask)
-+{
-+    target_ulong old_val = imsic->eithreshold[page];
-+
-+    if (val) {
-+        *val = old_val;
-+    }
-+
-+    wr_mask &= IMSIC_MAX_ID;
-+    imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
-+
-+    riscv_imsic_update(imsic, page);
-+    return 0;
-+}
-+
-+static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
-+                                 target_ulong *val, target_ulong new_val,
-+                                 target_ulong wr_mask)
-+{
-+    uint32_t base, topei = riscv_imsic_topei(imsic, page);
-+
-+    /* Read pending and enabled interrupt with highest priority */
-+    if (val) {
-+        *val = topei;
-+    }
-+
-+    /* Writes ignore value and clear top pending interrupt */
-+    if (topei && wr_mask) {
-+        topei >>= IMSIC_TOPEI_IID_SHIFT;
-+        base = page * imsic->num_irqs;
-+        if (topei) {
-+            imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;
-+        }
-+
-+        riscv_imsic_update(imsic, page);
-+    }
-+
-+    return 0;
-+}
-+
-+static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
-+                               uint32_t xlen, uint32_t page,
-+                               uint32_t num, bool pend, target_ulong *val,
-+                               target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint32_t i, base;
-+    target_ulong mask;
-+    uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
-+
-+    if (xlen != 32) {
-+        if (num & 0x1) {
-+            return -EINVAL;
-+        }
-+        num >>= 1;
-+    }
-+    if (num >= (imsic->num_irqs / xlen)) {
-+        return -EINVAL;
-+    }
-+
-+    base = (page * imsic->num_irqs) + (num * xlen);
-+
-+    if (val) {
-+        *val = 0;
-+        for (i = 0; i < xlen; i++) {
-+            mask = (target_ulong)1 << i;
-+            *val |= (imsic->eistate[base + i] & state) ? mask : 0;
-+        }
-+    }
-+
-+    for (i = 0; i < xlen; i++) {
-+        /* Bit0 of eip0 and eie0 are read-only zero */
-+        if (!num && !i) {
-+            continue;
-+        }
-+
-+        mask = (target_ulong)1 << i;
-+        if (wr_mask & mask) {
-+            if (new_val & mask) {
-+                imsic->eistate[base + i] |= state;
-+            } else {
-+                imsic->eistate[base + i] &= ~state;
-+            }
-+        }
-+    }
-+
-+    riscv_imsic_update(imsic, page);
-+    return 0;
-+}
-+
-+static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val,
-+                           target_ulong new_val, target_ulong wr_mask)
-+{
-+    RISCVIMSICState *imsic = arg;
-+    uint32_t isel, priv, virt, vgein, xlen, page;
-+
-+    priv = AIA_IREG_PRIV(reg);
-+    virt = AIA_IREG_VIRT(reg);
-+    isel = AIA_IREG_ISEL(reg);
-+    vgein = AIA_IREG_VGEIN(reg);
-+    xlen = AIA_IREG_XLEN(reg);
-+
-+    if (imsic->mmode) {
-+        if (priv == PRV_M && !virt) {
-+            page = 0;
-+        } else {
-+            goto err;
-+        }
-+    } else {
-+        if (priv == PRV_S) {
-+            if (virt) {
-+                if (vgein && vgein < imsic->num_pages) {
-+                    page = vgein;
-+                } else {
-+                    goto err;
-+                }
-+            } else {
-+                page = 0;
-+            }
-+        } else {
-+            goto err;
-+        }
-+    }
-+
-+    switch (isel) {
-+    case ISELECT_IMSIC_EIDELIVERY:
-+        return riscv_imsic_eidelivery_rmw(imsic, page, val,
-+                                          new_val, wr_mask);
-+    case ISELECT_IMSIC_EITHRESHOLD:
-+        return riscv_imsic_eithreshold_rmw(imsic, page, val,
-+                                           new_val, wr_mask);
-+    case ISELECT_IMSIC_TOPEI:
-+        return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask);
-+    case ISELECT_IMSIC_EIP0 ... ISELECT_IMSIC_EIP63:
-+        return riscv_imsic_eix_rmw(imsic, xlen, page,
-+                                   isel - ISELECT_IMSIC_EIP0,
-+                                   true, val, new_val, wr_mask);
-+    case ISELECT_IMSIC_EIE0 ... ISELECT_IMSIC_EIE63:
-+        return riscv_imsic_eix_rmw(imsic, xlen, page,
-+                                   isel - ISELECT_IMSIC_EIE0,
-+                                   false, val, new_val, wr_mask);
-+    default:
-+        break;
-+    };
-+
-+err:
-+    qemu_log_mask(LOG_GUEST_ERROR,
-+                  "%s: Invalid register priv=%d virt=%d isel=%d vgein=%d\n",
-+                  __func__, priv, virt, isel, vgein);
-+    return -EINVAL;
-+}
-+
-+static uint64_t riscv_imsic_read(void *opaque, hwaddr addr, unsigned size)
-+{
-+    RISCVIMSICState *imsic = opaque;
-+
-+    /* Reads must be 4 byte words */
-+    if ((addr & 0x3) != 0) {
-+        goto err;
-+    }
-+
-+    /* Reads cannot be out of range */
-+    if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
-+        goto err;
-+    }
-+
-+    return 0;
-+
-+err:
-+    qemu_log_mask(LOG_GUEST_ERROR,
-+                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
-+                  __func__, addr);
-+    return 0;
-+}
-+
-+static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
-+        unsigned size)
-+{
-+    RISCVIMSICState *imsic = opaque;
-+    uint32_t page;
-+
-+    /* Writes must be 4 byte words */
-+    if ((addr & 0x3) != 0) {
-+        goto err;
-+    }
-+
-+    /* Writes cannot be out of range */
-+    if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
-+        goto err;
-+    }
-+
-+    /* Writes only supported for MSI little-endian registers */
-+    page = addr >> IMSIC_MMIO_PAGE_SHIFT;
-+    if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
-+        if (value && (value < imsic->num_irqs)) {
-+            imsic->eistate[(page * imsic->num_irqs) + value] |=
-+                                                    IMSIC_EISTATE_PENDING;
-+        }
-+    }
-+
-+    /* Update CPU external interrupt status */
-+    riscv_imsic_update(imsic, page);
-+
-+    return;
-+
-+err:
-+    qemu_log_mask(LOG_GUEST_ERROR,
-+                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
-+                  __func__, addr);
-+}
-+
-+static const MemoryRegionOps riscv_imsic_ops = {
-+    .read = riscv_imsic_read,
-+    .write = riscv_imsic_write,
-+    .endianness = DEVICE_LITTLE_ENDIAN,
-+    .valid = {
-+        .min_access_size = 4,
-+        .max_access_size = 4
-+    }
-+};
-+
-+static void riscv_imsic_realize(DeviceState *dev, Error **errp)
-+{
-+    RISCVIMSICState *imsic = RISCV_IMSIC(dev);
-+    RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
-+    CPUState *cpu = qemu_get_cpu(imsic->hartid);
-+    CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
-+
-+    imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
-+    imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
-+    imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
-+    imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
-+
-+    memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
-+                          imsic, TYPE_RISCV_IMSIC,
-+                          IMSIC_MMIO_SIZE(imsic->num_pages));
-+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
-+
-+    /* Claim the CPU interrupt to be triggered by this IMSIC */
-+    if (riscv_cpu_claim_interrupts(rcpu,
-+            (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
-+        error_setg(errp, "%s already claimed",
-+                   (imsic->mmode) ? "MEIP" : "SEIP");
-+        return;
-+    }
-+
-+    /* Create output IRQ lines */
-+    imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
-+    qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
-+
-+    /* Force select AIA feature and setup CSR read-modify-write callback */
-+    if (env) {
-+        riscv_set_feature(env, RISCV_FEATURE_AIA);
-+        if (!imsic->mmode) {
-+            riscv_cpu_set_geilen(env, imsic->num_pages - 1);
-+        }
-+        riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
-+                                      riscv_imsic_rmw, imsic);
-+    }
-+
-+    msi_nonbroken = true;
-+}
-+
-+static Property riscv_imsic_properties[] = {
-+    DEFINE_PROP_BOOL("mmode", RISCVIMSICState, mmode, 0),
-+    DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0),
-+    DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0),
-+    DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0),
-+    DEFINE_PROP_END_OF_LIST(),
-+};
-+
-+static const VMStateDescription vmstate_riscv_imsic = {
-+    .name = "riscv_imsic",
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-+    .fields = (VMStateField[]) {
-+            VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState,
-+                                  num_pages, 0,
-+                                  vmstate_info_uint32, uint32_t),
-+            VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState,
-+                                  num_pages, 0,
-+                                  vmstate_info_uint32, uint32_t),
-+            VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState,
-+                                  num_eistate, 0,
-+                                  vmstate_info_uint32, uint32_t),
-+            VMSTATE_END_OF_LIST()
-+        }
-+};
-+
-+static void riscv_imsic_class_init(ObjectClass *klass, void *data)
-+{
-+    DeviceClass *dc = DEVICE_CLASS(klass);
-+
-+    device_class_set_props(dc, riscv_imsic_properties);
-+    dc->realize = riscv_imsic_realize;
-+    dc->vmsd = &vmstate_riscv_imsic;
-+}
-+
-+static const TypeInfo riscv_imsic_info = {
-+    .name          = TYPE_RISCV_IMSIC,
-+    .parent        = TYPE_SYS_BUS_DEVICE,
-+    .instance_size = sizeof(RISCVIMSICState),
-+    .class_init    = riscv_imsic_class_init,
-+};
-+
-+static void riscv_imsic_register_types(void)
-+{
-+    type_register_static(&riscv_imsic_info);
-+}
-+
-+type_init(riscv_imsic_register_types)
-+
 +/*
-+ * Create IMSIC device.
++ * Zvbc
 + */
-+DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
++
-+                                uint32_t num_pages, uint32_t num_ids)
++#define GEN_VV_MASKED_TRANS(NAME, CHECK)                     \
-+{
++    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)   \
-+    DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
++    {                                                        \
-+    CPUState *cpu = qemu_get_cpu(hartid);
++        if (CHECK(s, a)) {                                   \
-+    uint32_t i;
++            return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
-+
++                               gen_helper_##NAME, s);        \
-+    assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
++        }                                                    \
-+    if (mmode) {
++        return false;                                        \
-+        assert(num_pages == 1);
++    }
-+    } else {
++
-+        assert(num_pages >= 1 && num_pages <= (IRQ_LOCAL_GUEST_MAX + 1));
++static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
-+    }
++{
-+    assert(IMSIC_MIN_ID <= num_ids);
++    return opivv_check(s, a) &&
-+    assert(num_ids <= IMSIC_MAX_ID);
++           s->cfg_ptr->ext_zvbc == true &&
-+    assert((num_ids & IMSIC_MIN_ID) == IMSIC_MIN_ID);
++           s->sew == MO_64;
-+
++}
-+    qdev_prop_set_bit(dev, "mmode", mmode);
++
-+    qdev_prop_set_uint32(dev, "hartid", hartid);
++GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check)
-+    qdev_prop_set_uint32(dev, "num-pages", num_pages);
++GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check)
-+    qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1);
++
-+
++#define GEN_VX_MASKED_TRANS(NAME, CHECK)                     \
-+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)   \
-+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
++    {                                                        \
-+
++        if (CHECK(s, a)) {                                   \
-+    for (i = 0; i < num_pages; i++) {
++            return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
-+        if (!i) {
++                               gen_helper_##NAME, s);        \
-+            qdev_connect_gpio_out_named(dev, NULL, i,
++        }                                                    \
-+                                        qdev_get_gpio_in(DEVICE(cpu),
++        return false;                                        \
-+                                            (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
++    }
-+        } else {
++
-+            qdev_connect_gpio_out_named(dev, NULL, i,
++static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
-+                                        qdev_get_gpio_in(DEVICE(cpu),
++{
-+                                            IRQ_LOCAL_MAX + i - 1));
++    return opivx_check(s, a) &&
-+        }
++           s->cfg_ptr->ext_zvbc == true &&
-+    }
++           s->sew == MO_64;
-+
++}
-+    return dev;
++
-+}
++GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
-diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
++GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
---- a/hw/intc/Kconfig
+index XXXXXXX..XXXXXXX 100644
-+++ b/hw/intc/Kconfig
+--- a/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ config RISCV_ACLINT
++++ b/target/riscv/meson.build
- config RISCV_APLIC
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
-     bool
+   'translate.c',
+   'm128_helper.c',
-+config RISCV_IMSIC
+   'crypto_helper.c',
-+    bool
+-  'zce_helper.c'
-+
++  'zce_helper.c',
- config SIFIVE_PLIC
++  'vcrypto_helper.c'
-     bool
+ ))
+ riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
-diff --git a/hw/intc/meson.build b/hw/intc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/meson.build
 +++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
  specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
  specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
  specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
 +specific_ss.add(when: 'CONFIG_RISCV_IMSIC', if_true: files('riscv_imsic.c'))
  specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
  specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
 --
-.34.1
+.41.0

-[PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
+[PULL v2 12/45] target/riscv: Move vector translation checks
-From: Anup Patel <anup.patel@wdc.com>
+From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-The AIA specification adds new CSRs for RV32 so that RISC-V hart can
+Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
-support 64 local interrupts on both RV32 and RV64.
+and into the corresponding macros. This enables the functions to be
 reused in proceeding commits without check duplication.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Message-id: 20220204174700.534953-11-anup@brainfault.org
+Message-ID: <20230711165917.2629866-6-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  14 +-
+ target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++--------------
- target/riscv/cpu_helper.c |  10 +-
+file changed, 12 insertions(+), 16 deletions(-)
  target/riscv/csr.c        | 560 +++++++++++++++++++++++++++++++-------
  target/riscv/machine.c    |  10 +-
 files changed, 474 insertions(+), 120 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
-      */
+               gen_helper_gvec_4_ptr *fn)
-     uint64_t mstatus;
+ {
+     TCGLabel *over = gen_new_label();
--    target_ulong mip;
+-    if (!opivv_check(s, a)) {
-+    uint64_t mip;
+-        return false;
+-    }
--    uint32_t miclaim;
-+    uint64_t miclaim;
+     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
--    target_ulong mie;
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
--    target_ulong mideleg;
+         gen_helper_##NAME##_b, gen_helper_##NAME##_h,              \
-+    uint64_t mie;
+         gen_helper_##NAME##_w, gen_helper_##NAME##_d,              \
-+    uint64_t mideleg;
+     };                                                             \
++    if (!opivv_check(s, a)) {                                      \
-     target_ulong satp;   /* since: priv-1.10.0 */
++        return false;                                              \
-     target_ulong stval;
++    }                                                              \
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);   \
      /* Hypervisor CSRs */
      target_ulong hstatus;
      target_ulong hedeleg;
 -    target_ulong hideleg;
 +    uint64_t hideleg;
      target_ulong hcounteren;
      target_ulong htval;
      target_ulong htinst;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_list(void);
  #ifndef CONFIG_USER_ONLY
  bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
  void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
  #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
  void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
                               uint32_t arg);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_two_stage_lookup(int mmu_idx)
      return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
  }
--int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+@@ -XXX,XX +XXX,XX @@ static inline bool
-+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
+ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
                gen_helper_opivx *fn)
  {
-     CPURISCVState *env = &cpu->env;
+-    if (!opivx_check(s, a)) {
-     if (env->miclaim & interrupts) {
+-        return false;
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+-    }
-     }
+-
      if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
          TCGv_i64 src1 = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          gen_helper_##NAME##_b, gen_helper_##NAME##_h,              \
          gen_helper_##NAME##_w, gen_helper_##NAME##_d,              \
      };                                                             \
 +    if (!opivx_check(s, a)) {                                      \
 +        return false;                                              \
 +    }                                                              \
      return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);   \
  }
--uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+@@ -XXX,XX +XXX,XX @@ static inline bool
-+uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
+ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
                gen_helper_opivx *fn, imm_mode_t imm_mode)
  {
-     CPURISCVState *env = &cpu->env;
+-    if (!opivx_check(s, a)) {
-     CPUState *cs = CPU(cpu);
+-        return false;
--    uint32_t gein, vsgein = 0, old = env->mip;
+-    }
-+    uint64_t gein, vsgein = 0, old = env->mip;
+-
-     bool locked = false;
+     if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
+         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
-     if (riscv_cpu_virt_enabled(env)) {
+                 extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-      */
+         gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h,            \
-     bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
+         gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d,            \
-     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
+     };                                                             \
--    target_ulong deleg = async ? env->mideleg : env->medeleg;
++    if (!opivx_check(s, a)) {                                      \
-+    uint64_t deleg = async ? env->mideleg : env->medeleg;
++        return false;                                              \
-     target_ulong tval = 0;
++    }                                                              \
-     target_ulong htval = 0;
+     return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF,                 \
-     target_ulong mtval2 = 0;
+                          fns[s->sew], IMM_MODE);                   \
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
              cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
          /* handle the trap in S-mode */
          if (riscv_has_ext(env, RVH)) {
 -            target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 +            uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
                  /* Trap to VS mode */
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException any32(CPURISCVState *env, int csrno)
  }
+@@ -XXX,XX +XXX,XX @@ static inline bool
-+static int aia_any32(CPURISCVState *env, int csrno)
+ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
-+{
+                     gen_helper_opivx *fn)
 +    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    return any32(env, csrno);
 +}
 +
  static RISCVException smode(CPURISCVState *env, int csrno)
  {
-     if (riscv_has_ext(env, RVS)) {
+-    if (!opivx_check(s, a)) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException smode(CPURISCVState *env, int csrno)
+-        return false;
-     return RISCV_EXCP_ILLEGAL_INST;
+-    }
 -
      if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
          TCGv_i32 src1 = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
          gen_helper_##NAME##_b, gen_helper_##NAME##_h,                     \
          gen_helper_##NAME##_w, gen_helper_##NAME##_d,                     \
      };                                                                    \
 -                                                                          \
 +    if (!opivx_check(s, a)) {                                             \
 +        return false;                                                     \
 +    }                                                                     \
      return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);    \
  }
-+static int smode32(CPURISCVState *env, int csrno)
-+{
-+    if (riscv_cpu_mxl(env) != MXL_RV32) {
-+        return RISCV_EXCP_ILLEGAL_INST;
-+    }
-+
-+    return smode(env, csrno);
-+}
-+
-+static int aia_smode32(CPURISCVState *env, int csrno)
-+{
-+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
-+        return RISCV_EXCP_ILLEGAL_INST;
-+    }
-+
-+    return smode32(env, csrno);
-+}
-+
- static RISCVException hmode(CPURISCVState *env, int csrno)
- {
-     if (riscv_has_ext(env, RVS) &&
-@@ -XXX,XX +XXX,XX @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
-     return RISCV_EXCP_ILLEGAL_INST;
- }
-+static int aia_hmode32(CPURISCVState *env, int csrno)
-+{
-+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
-+        return RISCV_EXCP_ILLEGAL_INST;
-+    }
-+
-+    return hmode32(env, csrno);
-+}
-+
- static RISCVException pmp(CPURISCVState *env, int csrno)
- {
-     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
- /* Machine constants */
--#define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
--#define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
--#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
--#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
-+#define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
-+#define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
-+#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
-+#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
--static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
-+static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
-                                            VS_MODE_INTERRUPTS;
--static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
--static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
-+static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
-+static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
-                                      HS_MODE_INTERRUPTS;
- #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
-                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_medeleg(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
--static RISCVException read_mideleg(CPURISCVState *env, int csrno,
--                                   target_ulong *val)
-+static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
-+                                    uint64_t *ret_val,
-+                                    uint64_t new_val, uint64_t wr_mask)
- {
--    *val = env->mideleg;
--    return RISCV_EXCP_NONE;
--}
-+    uint64_t mask = wr_mask & delegable_ints;
-+
-+    if (ret_val) {
-+        *ret_val = env->mideleg;
-+    }
-+
-+    env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
--static RISCVException write_mideleg(CPURISCVState *env, int csrno,
--                                    target_ulong val)
--{
--    env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
-     if (riscv_has_ext(env, RVH)) {
-         env->mideleg |= HS_MODE_INTERRUPTS;
-     }
-+
-     return RISCV_EXCP_NONE;
- }
--static RISCVException read_mie(CPURISCVState *env, int csrno,
--                               target_ulong *val)
-+static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
-+                                  target_ulong *ret_val,
-+                                  target_ulong new_val, target_ulong wr_mask)
- {
--    *val = env->mie;
--    return RISCV_EXCP_NONE;
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
- }
--static RISCVException write_mie(CPURISCVState *env, int csrno,
--                                target_ulong val)
-+static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
-+                                   target_ulong *ret_val,
-+                                   target_ulong new_val,
-+                                   target_ulong wr_mask)
- {
--    env->mie = (env->mie & ~all_ints) | (val & all_ints);
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mideleg64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
-+                                uint64_t *ret_val,
-+                                uint64_t new_val, uint64_t wr_mask)
-+{
-+    uint64_t mask = wr_mask & all_ints;
-+
-+    if (ret_val) {
-+        *ret_val = env->mie;
-+    }
-+
-+    env->mie = (env->mie & ~mask) | (new_val & mask);
-+
-     if (!riscv_has_ext(env, RVH)) {
--        env->mie &= ~MIP_SGEIP;
-+        env->mie &= ~((uint64_t)MIP_SGEIP);
-     }
-+
-     return RISCV_EXCP_NONE;
- }
-+static RISCVException rmw_mie(CPURISCVState *env, int csrno,
-+                              target_ulong *ret_val,
-+                              target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mie64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
-+}
-+
- static RISCVException read_mtvec(CPURISCVState *env, int csrno,
-                                  target_ulong *val)
- {
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
--static RISCVException rmw_mip(CPURISCVState *env, int csrno,
--                              target_ulong *ret_value,
--                              target_ulong new_value, target_ulong write_mask)
-+static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
-+                                uint64_t *ret_val,
-+                                uint64_t new_val, uint64_t wr_mask)
- {
-     RISCVCPU *cpu = env_archcpu(env);
-     /* Allow software control of delegable interrupts not claimed by hardware */
--    target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
--    uint32_t gin, old_mip;
-+    uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
-+    uint32_t gin;
-     if (mask) {
--        old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
-+        old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
-     } else {
-         old_mip = env->mip;
-     }
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
-         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
-     }
--    if (ret_value) {
--        *ret_value = old_mip;
-+    if (ret_val) {
-+        *ret_val = old_mip;
-     }
-     return RISCV_EXCP_NONE;
- }
-+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
-+                              target_ulong *ret_val,
-+                              target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_miph(CPURISCVState *env, int csrno,
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_mip64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
-+}
-+
- /* Supervisor Trap Setup */
- static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
-                                         Int128 *val)
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
-     return write_mstatus(env, CSR_MSTATUS, newval);
- }
--static RISCVException read_vsie(CPURISCVState *env, int csrno,
--                                target_ulong *val)
-+static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
-+                                 uint64_t *ret_val,
-+                                 uint64_t new_val, uint64_t wr_mask)
- {
--    /* Shift the VS bits to their S bit location in vsie */
--    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
--    return RISCV_EXCP_NONE;
-+    RISCVException ret;
-+    uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
-+
-+    /* Bring VS-level bits to correct position */
-+    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
-+    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
-+    new_val |= vsbits << 1;
-+    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
-+    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
-+    wr_mask |= vsbits << 1;
-+
-+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
-+    if (ret_val) {
-+        rval &= mask;
-+        vsbits = rval & VS_MODE_INTERRUPTS;
-+        rval &= ~VS_MODE_INTERRUPTS;
-+        *ret_val = rval | (vsbits >> 1);
-+    }
-+
-+    return ret;
- }
--static RISCVException read_sie(CPURISCVState *env, int csrno,
--                               target_ulong *val)
-+static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
- {
--    if (riscv_cpu_virt_enabled(env)) {
--        read_vsie(env, CSR_VSIE, val);
--    } else {
--        *val = env->mie & env->mideleg;
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-     }
--    return RISCV_EXCP_NONE;
-+
-+    return ret;
- }
--static RISCVException write_vsie(CPURISCVState *env, int csrno,
--                                 target_ulong val)
-+static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
-+                                target_ulong *ret_val,
-+                                target_ulong new_val, target_ulong wr_mask)
- {
--    /* Shift the S bits to their VS bit location in mie */
--    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
--                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
--    return write_mie(env, CSR_MIE, newval);
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_vsie64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
- }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
-+static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
-+                                uint64_t *ret_val,
-+                                uint64_t new_val, uint64_t wr_mask)
- {
-+    RISCVException ret;
-+    uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
-+
-     if (riscv_cpu_virt_enabled(env)) {
--        write_vsie(env, CSR_VSIE, val);
-+        ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
-     } else {
--        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
--                              (val & S_MODE_INTERRUPTS);
--        write_mie(env, CSR_MIE, newval);
-+        ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
-     }
--    return RISCV_EXCP_NONE;
-+    if (ret_val) {
-+        *ret_val &= mask;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_sie(CPURISCVState *env, int csrno,
-+                              target_ulong *ret_val,
-+                              target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_sie64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
- }
- static RISCVException read_stvec(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_stval(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
-+static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
-+                                 uint64_t *ret_val,
-+                                 uint64_t new_val, uint64_t wr_mask)
-+{
-+    RISCVException ret;
-+    uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
-+
-+    /* Bring VS-level bits to correct position */
-+    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
-+    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
-+    new_val |= vsbits << 1;
-+    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
-+    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
-+    wr_mask |= vsbits << 1;
-+
-+    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
-+    if (ret_val) {
-+        rval &= mask;
-+        vsbits = rval & VS_MODE_INTERRUPTS;
-+        rval &= ~VS_MODE_INTERRUPTS;
-+        *ret_val = rval | (vsbits >> 1);
-+    }
-+
-+    return ret;
-+}
-+
- static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
--                               target_ulong *ret_value,
--                               target_ulong new_value, target_ulong write_mask)
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
- {
--    /* Shift the S bits to their VS bit location in mip */
--    int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
--                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
-+    uint64_t rval;
-+    RISCVException ret;
--    if (ret_value) {
--        *ret_value &= VS_MODE_INTERRUPTS;
--        /* Shift the VS bits to their S bit location in vsip */
--        *ret_value >>= 1;
-+    ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-     }
-+
-     return ret;
- }
--static RISCVException rmw_sip(CPURISCVState *env, int csrno,
--                              target_ulong *ret_value,
--                              target_ulong new_value, target_ulong write_mask)
-+static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
-+                                target_ulong *ret_val,
-+                                target_ulong new_val, target_ulong wr_mask)
- {
--    int ret;
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_vsip64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
-+                                uint64_t *ret_val,
-+                                uint64_t new_val, uint64_t wr_mask)
-+{
-+    RISCVException ret;
-+    uint64_t mask = env->mideleg & sip_writable_mask;
-     if (riscv_cpu_virt_enabled(env)) {
--        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
-+        ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
-     } else {
--        ret = rmw_mip(env, csrno, ret_value, new_value,
--                      write_mask & env->mideleg & sip_writable_mask);
-+        ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
-     }
--    if (ret_value) {
--        *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
-+    if (ret_val) {
-+        *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
-+                              target_ulong *ret_val,
-+                              target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-     }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_siph(CPURISCVState *env, int csrno,
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_sip64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-     return ret;
- }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
--static RISCVException read_hideleg(CPURISCVState *env, int csrno,
--                                   target_ulong *val)
-+static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
-+                                    uint64_t *ret_val,
-+                                    uint64_t new_val, uint64_t wr_mask)
- {
--    *val = env->hideleg;
-+    uint64_t mask = wr_mask & vs_delegable_ints;
-+
-+    if (ret_val) {
-+        *ret_val = env->hideleg & vs_delegable_ints;
-+    }
-+
-+    env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
-     return RISCV_EXCP_NONE;
- }
--static RISCVException write_hideleg(CPURISCVState *env, int csrno,
--                                    target_ulong val)
-+static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
-+                                  target_ulong *ret_val,
-+                                  target_ulong new_val, target_ulong wr_mask)
- {
--    env->hideleg = val & vs_delegable_ints;
--    return RISCV_EXCP_NONE;
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
-+                                   target_ulong *ret_val,
-+                                   target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_hideleg64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
-+                                 uint64_t *ret_val,
-+                                 uint64_t new_val, uint64_t wr_mask)
-+{
-+    RISCVException ret;
-+
-+    ret = rmw_mip64(env, csrno, ret_val, new_val,
-+                    wr_mask & hvip_writable_mask);
-+    if (ret_val) {
-+        *ret_val &= VS_MODE_INTERRUPTS;
-+    }
-+
-+    return ret;
- }
- static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
--                               target_ulong *ret_value,
--                               target_ulong new_value, target_ulong write_mask)
-+                               target_ulong *ret_val,
-+                               target_ulong new_val, target_ulong wr_mask)
- {
--    int ret = rmw_mip(env, csrno, ret_value, new_value,
--                      write_mask & hvip_writable_mask);
-+    uint64_t rval;
-+    RISCVException ret;
--    if (ret_value) {
--        *ret_value &= VS_MODE_INTERRUPTS;
-+    ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
-+    if (ret_val) {
-+        *ret_val = rval;
-+    }
-+
-+    return ret;
-+}
-+
-+static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
-+                                target_ulong *ret_val,
-+                                target_ulong new_val, target_ulong wr_mask)
-+{
-+    uint64_t rval;
-+    RISCVException ret;
-+
-+    ret = rmw_hvip64(env, csrno, &rval,
-+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
-+    if (ret_val) {
-+        *ret_val = rval >> 32;
-     }
-+
-     return ret;
- }
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
-     return ret;
- }
--static RISCVException read_hie(CPURISCVState *env, int csrno,
--                               target_ulong *val)
-+static RISCVException rmw_hie(CPURISCVState *env, int csrno,
-+                              target_ulong *ret_val,
-+                              target_ulong new_val, target_ulong wr_mask)
- {
--    *val = env->mie & HS_MODE_INTERRUPTS;
--    return RISCV_EXCP_NONE;
--}
-+    uint64_t rval;
-+    RISCVException ret;
--static RISCVException write_hie(CPURISCVState *env, int csrno,
--                                target_ulong val)
--{
--    target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
--    return write_mie(env, CSR_MIE, newval);
-+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
-+    if (ret_val) {
-+        *ret_val = rval & HS_MODE_INTERRUPTS;
-+    }
-+
-+    return ret;
- }
- static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-                                                read_mstatus_i128                   },
-     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
-                                                read_misa_i128                      },
--    [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
-+    [CSR_MIDELEG]     = { "mideleg",    any,   NULL,    NULL,    rmw_mideleg       },
-     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
--    [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
-+    [CSR_MIE]         = { "mie",        any,   NULL,    NULL,    rmw_mie           },
-     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
-     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
-     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
-+    /* Machine-Level High-Half CSRs (AIA) */
-+    [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
-+    [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
-+    [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
-+
-     /* Supervisor Trap Setup */
-     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
-                                               read_sstatus_i128                 },
--    [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
-+    [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie          },
-     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
-     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     /* Supervisor Protection and Translation */
-     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
-+    /* Supervisor-Level High-Half CSRs (AIA) */
-+    [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
-+    [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
-+
-     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
-     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
--    [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
-+    [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL,     rmw_hideleg       },
-     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
-     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
--    [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
-+    [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL,     rmw_hie           },
-     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
-     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
-     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
-     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
--    [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
-+    [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL,    rmw_vsie          },
-     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
-     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
-     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
-     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
-+    /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
-+    [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
-+    [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
-+    [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
-+    [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
-+
-     /* Physical Memory Protection */
-     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
-     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
-diff --git a/target/riscv/machine.c b/target/riscv/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/machine.c
-+++ b/target/riscv/machine.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
-     .fields = (VMStateField[]) {
-         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
-         VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
--        VMSTATE_UINTTL(env.hideleg, RISCVCPU),
-+        VMSTATE_UINT64(env.hideleg, RISCVCPU),
-         VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
-         VMSTATE_UINTTL(env.htval, RISCVCPU),
-         VMSTATE_UINTTL(env.htinst, RISCVCPU),
-@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
-         VMSTATE_UINTTL(env.resetvec, RISCVCPU),
-         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
-         VMSTATE_UINT64(env.mstatus, RISCVCPU),
--        VMSTATE_UINTTL(env.mip, RISCVCPU),
--        VMSTATE_UINT32(env.miclaim, RISCVCPU),
--        VMSTATE_UINTTL(env.mie, RISCVCPU),
--        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
-+        VMSTATE_UINT64(env.mip, RISCVCPU),
-+        VMSTATE_UINT64(env.miclaim, RISCVCPU),
-+        VMSTATE_UINT64(env.mie, RISCVCPU),
-+        VMSTATE_UINT64(env.mideleg, RISCVCPU),
-         VMSTATE_UINTTL(env.satp, RISCVCPU),
-         VMSTATE_UINTTL(env.stval, RISCVCPU),
-         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
 --
-.34.1
+.41.0

-New patch
+[PULL v2 13/45] target/riscv: Refactor translation of vector-widening instruction
+From: Dickon Hood <dickon.hood@codethink.co.uk>
+Zvbb (implemented in later commit) has a widening instruction, which
+requires an extra check on the enabled extensions.  Refactor
+GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
+it.
+Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20230711165917.2629866-7-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++--------------
+file changed, 23 insertions(+), 29 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
+ }
+-static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
+-                           gen_helper_opivx *fn)
+-{
+-    if (opivx_widen_check(s, a)) {
+-        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+-    }
+-    return false;
+-}
+-
+-#define GEN_OPIVX_WIDEN_TRANS(NAME) \
+-static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
+-{                                                            \
+-    static gen_helper_opivx * const fns[3] = {               \
+-        gen_helper_##NAME##_b,                               \
+-        gen_helper_##NAME##_h,                               \
+-        gen_helper_##NAME##_w                                \
+-    };                                                       \
+-    return do_opivx_widen(s, a, fns[s->sew]);                \
++#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
++static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
++{                                                                         \
++    if (CHECK(s, a)) {                                                    \
++        static gen_helper_opivx * const fns[3] = {                        \
++            gen_helper_##NAME##_b,                                        \
++            gen_helper_##NAME##_h,                                        \
++            gen_helper_##NAME##_w                                         \
++        };                                                                \
++        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \
++    }                                                                     \
++    return false;                                                         \
+ }
+-GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
++GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check)
+ /* WIDEN OPIVV with WIDEN */
+ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
+-GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
++GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check)
+ /* Vector Single-Width Integer Multiply-Add Instructions */
+ GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
+ GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
+-GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
+-GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
++GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
++GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
+ /* Vector Integer Merge and Move Instructions */
+ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+--
+.41.0

-New patch
+[PULL v2 14/45] target/riscv: Refactor some of the generic vector functionality
+From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
+Move some macros out of `vector_helper` and into `vector_internals`.
+This ensures they can be used by both vector and vector-crypto helpers
+(latter implemented in proceeding commits).
+Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20230711165917.2629866-8-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++
+ target/riscv/vector_helper.c    | 42 ------------------------------
+files changed, 46 insertions(+), 42 deletions(-)
+diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_internals.h
++++ b/target/riscv/vector_internals.h
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+ /* expand macro args before macro */
+ #define RVVCALL(macro, ...)  macro(__VA_ARGS__)
++/* (TD, T2, TX2) */
++#define OP_UU_B uint8_t, uint8_t, uint8_t
++#define OP_UU_H uint16_t, uint16_t, uint16_t
++#define OP_UU_W uint32_t, uint32_t, uint32_t
++#define OP_UU_D uint64_t, uint64_t, uint64_t
++
+ /* (TD, T1, T2, TX1, TX2) */
+ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
+ #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
+ #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
+ #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
++#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
++static void do_##NAME(void *vd, void *vs2, int i)      \
++{                                                      \
++    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
++    *((TD *)vd + HD(i)) = OP(s2);                      \
++}
++
++#define GEN_VEXT_V(NAME, ESZ)                          \
++void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
++                  CPURISCVState *env, uint32_t desc)   \
++{                                                      \
++    uint32_t vm = vext_vm(desc);                       \
++    uint32_t vl = env->vl;                             \
++    uint32_t total_elems =                             \
++        vext_get_total_elems(env, desc, ESZ);          \
++    uint32_t vta = vext_vta(desc);                     \
++    uint32_t vma = vext_vma(desc);                     \
++    uint32_t i;                                        \
++                                                       \
++    for (i = env->vstart; i < vl; i++) {               \
++        if (!vm && !vext_elem_mask(v0, i)) {           \
++            /* set masked-off elements to 1s */        \
++            vext_set_elems_1s(vd, vma, i * ESZ,        \
++                              (i + 1) * ESZ);          \
++            continue;                                  \
++        }                                              \
++        do_##NAME(vd, vs2, i);                         \
++    }                                                  \
++    env->vstart = 0;                                   \
++    /* set tail elements to 1s */                      \
++    vext_set_elems_1s(vd, vta, vl * ESZ,               \
++                      total_elems * ESZ);              \
++}
++
+ /* operation of two vector elements */
+ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
+                do_##NAME, ESZ);                           \
+ }
++/* Three of the widening shortening macros: */
++/* (TD, T1, T2, TX1, TX2) */
++#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
++#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
++#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
++
+ #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
+ #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
+ #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
+ #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
+-#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
+-#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
+-#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
+ #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
+ #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
+ #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4)
+ GEN_VEXT_VF(vfwnmsac_vf_w, 8)
+ /* Vector Floating-Point Square-Root Instruction */
+-/* (TD, T2, TX2) */
+-#define OP_UU_H uint16_t, uint16_t, uint16_t
+-#define OP_UU_W uint32_t, uint32_t, uint32_t
+-#define OP_UU_D uint64_t, uint64_t, uint64_t
+-
+ #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
+ static void do_##NAME(void *vd, void *vs2, int i,      \
+                       CPURISCVState *env)              \
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
+ GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
+ /* Vector Floating-Point Classify Instruction */
+-#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
+-static void do_##NAME(void *vd, void *vs2, int i)      \
+-{                                                      \
+-    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
+-    *((TD *)vd + HD(i)) = OP(s2);                      \
+-}
+-
+-#define GEN_VEXT_V(NAME, ESZ)                          \
+-void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+-                  CPURISCVState *env, uint32_t desc)   \
+-{                                                      \
+-    uint32_t vm = vext_vm(desc);                       \
+-    uint32_t vl = env->vl;                             \
+-    uint32_t total_elems =                             \
+-        vext_get_total_elems(env, desc, ESZ);          \
+-    uint32_t vta = vext_vta(desc);                     \
+-    uint32_t vma = vext_vma(desc);                     \
+-    uint32_t i;                                        \
+-                                                       \
+-    for (i = env->vstart; i < vl; i++) {               \
+-        if (!vm && !vext_elem_mask(v0, i)) {           \
+-            /* set masked-off elements to 1s */        \
+-            vext_set_elems_1s(vd, vma, i * ESZ,        \
+-                              (i + 1) * ESZ);          \
+-            continue;                                  \
+-        }                                              \
+-        do_##NAME(vd, vs2, i);                         \
+-    }                                                  \
+-    env->vstart = 0;                                   \
+-    /* set tail elements to 1s */                      \
+-    vext_set_elems_1s(vd, vta, vl * ESZ,               \
+-                      total_elems * ESZ);              \
+-}
+-
+ target_ulong fclass_h(uint64_t frs1)
+ {
+     float16 f = frs1;
+--
+.41.0

-[PULL 09/40] target/riscv: Add XVentanaCondOps custom extension
+[PULL v2 15/45] target/riscv: Add Zvbb ISA extension support
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Dickon Hood <dickon.hood@codethink.co.uk>
-This adds the decoder and translation for the XVentanaCondOps custom
+This commit adds support for the Zvbb vector-crypto extension, which
-extension (vendor-defined by Ventana Micro Systems), which is
+consists of the following instructions:
 documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
-This commit then also adds a guard-function (has_XVentanaCondOps_p)
+* vrol.[vv,vx]
-and the decoder function to the table of decoders, enabling the
+* vror.[vv,vx,vi]
-support for the XVentanaCondOps extension.
+* vbrev8.v
 * vrev8.v
 * vandn.[vv,vx]
 * vbrev.v
 * vclz.v
 * vctz.v
 * vcpop.v
 * vwsll.[vv,vx,vi]
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Translation functions are defined in
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+`target/riscv/vcrypto_helper.c`.
-Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
 Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
 Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 [max.chou@sifive.com: Fix imm mode of vror.vi]
 Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
 Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 [max.chou@sifive.com: Exposed x-zvbb property]
 Message-ID: <20230711165917.2629866-9-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                            |  3 ++
+ target/riscv/cpu_cfg.h                   |   1 +
- target/riscv/XVentanaCondOps.decode           | 25 ++++++++++++
+ target/riscv/helper.h                    |  62 +++++++++
- target/riscv/cpu.c                            |  3 ++
+ target/riscv/insn32.decode               |  20 +++
- target/riscv/translate.c                      | 12 ++++++
+ target/riscv/cpu.c                       |  12 ++
- .../insn_trans/trans_xventanacondops.c.inc    | 39 +++++++++++++++++++
+ target/riscv/vcrypto_helper.c            | 138 +++++++++++++++++++
- target/riscv/meson.build                      |  1 +
+ target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++
-files changed, 83 insertions(+)
+files changed, 397 insertions(+)
  create mode 100644 target/riscv/XVentanaCondOps.decode
  create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
 @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
      bool ext_zve32f;
      bool ext_zve64f;
+     bool ext_zve64d;
-+    /* Vendor-specific custom extensions */
++    bool ext_zvbb;
-+    bool ext_XVentanaCondOps;
+     bool ext_zvbc;
-+
+     bool ext_zmmul;
-     char *priv_spec;
+     bool ext_zvfbfmin;
-     char *user_spec;
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-     char *bext_spec;
+index XXXXXXX..XXXXXXX 100644
-diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode
+--- a/target/riscv/helper.h
-new file mode 100644
++++ b/target/riscv/helper.h
-index XXXXXXX..XXXXXXX
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
---- /dev/null
+ DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
-+++ b/target/riscv/XVentanaCondOps.decode
+ DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
  DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
 +
 +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
 +
 +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32)
 +
 +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
 +
 +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32)
 +
 +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32)
 +
 +DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32)
 +
 +DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 +
 +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
 @@ -XXX,XX +XXX,XX @@
-+#
+ %imm_u    12:s20                 !function=ex_shift_12
-+# RISC-V translation routines for the XVentanaCondOps extension
+ %imm_bs   30:2                   !function=ex_shift_3
-+#
+ %imm_rnum 20:4
-+# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
++%imm_z6   26:1 15:5
-+#
-+# SPDX-License-Identifier: LGPL-2.1-or-later
+ # Argument sets:
-+#
+ &empty
-+# Reference: VTx-family custom instructions
+@@ -XXX,XX +XXX,XX @@
-+#            Custom ISA extensions for Ventana Micro Systems RISC-V cores
+ @r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
-+#            (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
+ @r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
-+
+ @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
-+# Fields
++@r2_zimm6  ..... . vm:1 ..... ..... ... ..... .......  &rmrr %rs2 rs1=%imm_z6 %rd
-+%rs2  20:5
+ @r2_zimm11 . zimm:11  ..... ... ..... ....... %rs1 %rd
-+%rs1  15:5
+ @r2_zimm10 .. zimm:10  ..... ... ..... ....... %rs1 %rd
-+%rd    7:5
+ @r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
-+
+@@ -XXX,XX +XXX,XX @@ vclmul_vv   001100 . ..... ..... 010 ..... 1010111 @r_vm
-+# Argument sets
+ vclmul_vx   001100 . ..... ..... 110 ..... 1010111 @r_vm
-+&r    rd rs1 rs2  !extern
+ vclmulh_vv  001101 . ..... ..... 010 ..... 1010111 @r_vm
-+
+ vclmulh_vx  001101 . ..... ..... 110 ..... 1010111 @r_vm
-+# Formats
++
-+@r         .......  ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
++# *** Zvbb vector crypto extension ***
-+
++vrol_vv     010101 . ..... ..... 000 ..... 1010111 @r_vm
-+# *** RV64 Custom-3 Extension ***
++vrol_vx     010101 . ..... ..... 100 ..... 1010111 @r_vm
-+vt_maskc   0000000  ..... ..... 110 ..... 1111011 @r
++vror_vv     010100 . ..... ..... 000 ..... 1010111 @r_vm
-+vt_maskcn  0000000  ..... ..... 111 ..... 1111011 @r
++vror_vx     010100 . ..... ..... 100 ..... 1010111 @r_vm
 +vror_vi     01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
 +vbrev8_v    010010 . ..... 01000 010 ..... 1010111 @r2_vm
 +vrev8_v     010010 . ..... 01001 010 ..... 1010111 @r2_vm
 +vandn_vv    000001 . ..... ..... 000 ..... 1010111 @r_vm
 +vandn_vx    000001 . ..... ..... 100 ..... 1010111 @r_vm
 +vbrev_v     010010 . ..... 01010 010 ..... 1010111 @r2_vm
 +vclz_v      010010 . ..... 01100 010 ..... 1010111 @r2_vm
 +vctz_v      010010 . ..... 01101 010 ..... 1010111 @r2_vm
 +vcpop_v     010010 . ..... 01110 010 ..... 1010111 @r2_vm
 +vwsll_vv    110101 . ..... ..... 000 ..... 1010111 @r_vm
 +vwsll_vx    110101 . ..... ..... 100 ..... 1010111 @r_vm
 +vwsll_vi    110101 . ..... ..... 011 ..... 1010111 @r_vm
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
-     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
+     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
-+    /* Vendor-specific custom extensions */
++    ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
-+    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
-+
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
-     /* These are experimental so mark with 'x-' */
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     /* ePMP 0.9.3 */
+         return;
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+     }
 +    /*
 +     * In principle Zve*x would also suffice here, were they supported
 +     * in qemu
 +     */
 +    if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
 +        error_setg(errp,
 +                   "Vector crypto extensions require V or Zve* extensions");
 +        return;
 +    }
 +
      if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
          error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
          return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
      /* Vector cryptography extensions */
 +    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
      DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
      DEFINE_PROP_END_OF_LIST(),
 diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/vcrypto_helper.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/vcrypto_helper.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
      return true;
  }
 +#define MATERIALISE_EXT_PREDICATE(ext)  \
 +    static bool has_ ## ext ## _p(DisasContext *ctx)    \
 +    { \
 +        return ctx->cfg_ptr->ext_ ## ext ; \
 +    }
 +
 +MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
 +
  #ifdef TARGET_RISCV32
  #define get_xl(ctx)    MXL_RV32
  #elif defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  #include "insn_trans/trans_rvb.c.inc"
  #include "insn_trans/trans_rvzfh.c.inc"
  #include "insn_trans/trans_privileged.c.inc"
 +#include "insn_trans/trans_xventanacondops.c.inc"
  /* Include the auto-generated decoder for 16 bit insn */
  #include "decode-insn16.c.inc"
 +/* Include decoders for factored-out extensions */
 +#include "decode-XVentanaCondOps.c.inc"
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          bool (*decode_func)(DisasContext *, uint32_t);
      } decoders[] = {
          { always_true_p,  decode_insn32 },
 +        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
      };
      /* Check for compressed insn */
 diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
 @@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qemu/host-utils.h"
+ #include "qemu/bitops.h"
++#include "qemu/bswap.h"
+ #include "cpu.h"
+ #include "exec/memop.h"
+ #include "exec/exec-all.h"
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
+ GEN_VEXT_VV(vclmulh_vv, 8)
+ RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
+ GEN_VEXT_VX(vclmulh_vx, 8)
++
++RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8)
++RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16)
++RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32)
++RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64)
++GEN_VEXT_VV(vror_vv_b, 1)
++GEN_VEXT_VV(vror_vv_h, 2)
++GEN_VEXT_VV(vror_vv_w, 4)
++GEN_VEXT_VV(vror_vv_d, 8)
++
++RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8)
++RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16)
++RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32)
++RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64)
++GEN_VEXT_VX(vror_vx_b, 1)
++GEN_VEXT_VX(vror_vx_h, 2)
++GEN_VEXT_VX(vror_vx_w, 4)
++GEN_VEXT_VX(vror_vx_d, 8)
++
++RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8)
++RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16)
++RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32)
++RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64)
++GEN_VEXT_VV(vrol_vv_b, 1)
++GEN_VEXT_VV(vrol_vv_h, 2)
++GEN_VEXT_VV(vrol_vv_w, 4)
++GEN_VEXT_VV(vrol_vv_d, 8)
++
++RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8)
++RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16)
++RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32)
++RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64)
++GEN_VEXT_VX(vrol_vx_b, 1)
++GEN_VEXT_VX(vrol_vx_h, 2)
++GEN_VEXT_VX(vrol_vx_w, 4)
++GEN_VEXT_VX(vrol_vx_d, 8)
++
++static uint64_t brev8(uint64_t val)
++{
++    val = ((val & 0x5555555555555555ull) << 1) |
++          ((val & 0xAAAAAAAAAAAAAAAAull) >> 1);
++    val = ((val & 0x3333333333333333ull) << 2) |
++          ((val & 0xCCCCCCCCCCCCCCCCull) >> 2);
++    val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4) |
++          ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4);
++
++    return val;
++}
++
++RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8)
++RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8)
++RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8)
++RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8)
++GEN_VEXT_V(vbrev8_v_b, 1)
++GEN_VEXT_V(vbrev8_v_h, 2)
++GEN_VEXT_V(vbrev8_v_w, 4)
++GEN_VEXT_V(vbrev8_v_d, 8)
++
++#define DO_IDENTITY(a) (a)
++RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY)
++RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16)
++RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32)
++RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64)
++GEN_VEXT_V(vrev8_v_b, 1)
++GEN_VEXT_V(vrev8_v_h, 2)
++GEN_VEXT_V(vrev8_v_w, 4)
++GEN_VEXT_V(vrev8_v_d, 8)
++
++#define DO_ANDN(a, b) ((a) & ~(b))
++RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN)
++RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN)
++RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN)
++RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN)
++GEN_VEXT_VV(vandn_vv_b, 1)
++GEN_VEXT_VV(vandn_vv_h, 2)
++GEN_VEXT_VV(vandn_vv_w, 4)
++GEN_VEXT_VV(vandn_vv_d, 8)
++
++RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN)
++RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN)
++RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN)
++RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN)
++GEN_VEXT_VX(vandn_vx_b, 1)
++GEN_VEXT_VX(vandn_vx_h, 2)
++GEN_VEXT_VX(vandn_vx_w, 4)
++GEN_VEXT_VX(vandn_vx_d, 8)
++
++RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8)
++RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16)
++RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32)
++RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64)
++GEN_VEXT_V(vbrev_v_b, 1)
++GEN_VEXT_V(vbrev_v_h, 2)
++GEN_VEXT_V(vbrev_v_w, 4)
++GEN_VEXT_V(vbrev_v_d, 8)
++
++RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8)
++RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16)
++RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32)
++RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64)
++GEN_VEXT_V(vclz_v_b, 1)
++GEN_VEXT_V(vclz_v_h, 2)
++GEN_VEXT_V(vclz_v_w, 4)
++GEN_VEXT_V(vclz_v_d, 8)
++
++RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8)
++RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16)
++RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32)
++RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64)
++GEN_VEXT_V(vctz_v_b, 1)
++GEN_VEXT_V(vctz_v_h, 2)
++GEN_VEXT_V(vctz_v_w, 4)
++GEN_VEXT_V(vctz_v_d, 8)
++
++RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8)
++RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16)
++RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32)
++RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64)
++GEN_VEXT_V(vcpop_v_b, 1)
++GEN_VEXT_V(vcpop_v_h, 2)
++GEN_VEXT_V(vcpop_v_w, 4)
++GEN_VEXT_V(vcpop_v_d, 8)
++
++#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1)))
++RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL)
++RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL)
++RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL)
++GEN_VEXT_VV(vwsll_vv_b, 2)
++GEN_VEXT_VV(vwsll_vv_h, 4)
++GEN_VEXT_VV(vwsll_vv_w, 8)
++
++RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL)
++RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL)
++RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
++GEN_VEXT_VX(vwsll_vx_b, 2)
++GEN_VEXT_VX(vwsll_vx_h, 4)
++GEN_VEXT_VX(vwsll_vx_w, 8)
+diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvvk.c.inc
++++ b/target/riscv/insn_trans/trans_rvvk.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
+ GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
+ GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
++
 +/*
-+ * RISC-V translation routines for the XVentanaCondOps extension.
++ * Zvbb
 + *
 + * Copyright (c) 2021-2022 VRULL GmbH.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
++#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK)   \
 +    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)              \
 +    {                                                                   \
 +        if (CHECK(s, a)) {                                              \
 +            static gen_helper_opivx *const fns[4] = {                   \
 +                gen_helper_##OPIVX##_b,                                 \
 +                gen_helper_##OPIVX##_h,                                 \
 +                gen_helper_##OPIVX##_w,                                 \
 +                gen_helper_##OPIVX##_d,                                 \
 +            };                                                          \
 +            return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \
 +                                 IMM_MODE);                             \
 +        }                                                               \
 +        return false;                                                   \
 +    }
 +
 +#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK)                     \
 +    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)               \
 +    {                                                                    \
 +        if (CHECK(s, a)) {                                               \
 +            static gen_helper_gvec_4_ptr *const fns[4] = {               \
 +                gen_helper_##NAME##_b,                                   \
 +                gen_helper_##NAME##_h,                                   \
 +                gen_helper_##NAME##_w,                                   \
 +                gen_helper_##NAME##_d,                                   \
 +            };                                                           \
 +            return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
 +        }                                                                \
 +        return false;                                                    \
 +    }
 +
 +#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK)       \
 +    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
 +    {                                                            \
 +        if (CHECK(s, a)) {                                       \
 +            static gen_helper_opivx *const fns[4] = {            \
 +                gen_helper_##NAME##_b,                           \
 +                gen_helper_##NAME##_h,                           \
 +                gen_helper_##NAME##_w,                           \
 +                gen_helper_##NAME##_d,                           \
 +            };                                                   \
 +            return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \
 +                                       fns[s->sew]);             \
 +        }                                                        \
 +        return false;                                            \
 +    }
 +
 +static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
 +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 +
 +    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
 +
 +    gen_set_gpr(ctx, a->rd, dest);
 +    return true;
 +}
 +
-+static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
++static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
 +{
-+    return gen_vt_condmask(ctx, a, TCG_COND_NE);
++    return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
 +}
 +
-+static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
++/* vrol.v[vx] */
 +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
 +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
 +
 +/* vror.v[vxi] */
 +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
 +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
 +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
 +
 +#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK)                     \
 +    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)               \
 +    {                                                                    \
 +        if (CHECK(s, a)) {                                               \
 +            static gen_helper_opivx *const fns[4] = {                    \
 +                gen_helper_##NAME##_b,                                   \
 +                gen_helper_##NAME##_h,                                   \
 +                gen_helper_##NAME##_w,                                   \
 +                gen_helper_##NAME##_d,                                   \
 +            };                                                           \
 +            return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
 +        }                                                                \
 +        return false;                                                    \
 +    }
 +
 +/* vandn.v[vx] */
 +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
 +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
 +
 +#define GEN_OPIV_TRANS(NAME, CHECK)                                        \
 +    static bool trans_##NAME(DisasContext *s, arg_rmr *a)                  \
 +    {                                                                      \
 +        if (CHECK(s, a)) {                                                 \
 +            uint32_t data = 0;                                             \
 +            static gen_helper_gvec_3_ptr *const fns[4] = {                 \
 +                gen_helper_##NAME##_b,                                     \
 +                gen_helper_##NAME##_h,                                     \
 +                gen_helper_##NAME##_w,                                     \
 +                gen_helper_##NAME##_d,                                     \
 +            };                                                             \
 +            TCGLabel *over = gen_new_label();                              \
 +            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);     \
 +                                                                           \
 +            data = FIELD_DP32(data, VDATA, VM, a->vm);                     \
 +            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                 \
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);                   \
 +            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
 +            data = FIELD_DP32(data, VDATA, VMA, s->vma);                   \
 +            tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),         \
 +                               vreg_ofs(s, a->rs2), cpu_env,               \
 +                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
 +                               data, fns[s->sew]);                         \
 +            mark_vs_dirty(s);                                              \
 +            gen_set_label(over);                                           \
 +            return true;                                                   \
 +        }                                                                  \
 +        return false;                                                      \
 +    }
 +
 +static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
 +{
-+    return gen_vt_condmask(ctx, a, TCG_COND_EQ);
++    return s->cfg_ptr->ext_zvbb == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           vext_check_ss(s, a->rd, a->rs2, a->vm);
 +}
-diff --git a/target/riscv/meson.build b/target/riscv/meson.build
++
-index XXXXXXX..XXXXXXX 100644
++GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
---- a/target/riscv/meson.build
++GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
-+++ b/target/riscv/meson.build
++GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
-@@ -XXX,XX +XXX,XX @@ dir = meson.current_source_dir()
++GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
- gen = [
++GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
-   decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
++GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check)
-   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
++
-+  decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
++static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a)
- ]
++{
++    return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a);
- riscv_ss = ss.source_set()
++}
 +
 +static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
 +{
 +    return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a);
 +}
 +
 +/* OPIVI without GVEC IR */
 +#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK)                  \
 +    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
 +    {                                                                        \
 +        if (CHECK(s, a)) {                                                   \
 +            static gen_helper_opivx *const fns[3] = {                        \
 +                gen_helper_##OPIVX##_b,                                      \
 +                gen_helper_##OPIVX##_h,                                      \
 +                gen_helper_##OPIVX##_w,                                      \
 +            };                                                               \
 +            return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
 +                               IMM_MODE);                                    \
 +        }                                                                    \
 +        return false;                                                        \
 +    }
 +
 +GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
 +GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
 +GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
 --
-.34.1
+.41.0

-[PULL 39/40] target/riscv: add support for svpbmt extension
+[PULL v2 16/45] target/riscv: Add Zvkned ISA extension support
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
+This commit adds support for the Zvkned vector-crypto extension, which
-- add PTE_PBMT bit check for inner PTE
+consists of the following instructions:
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+* vaesef.[vv,vs]
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+* vaesdf.[vv,vs]
-Reviewed-by: Anup Patel <anup@brainfault.org>
+* vaesdm.[vv,vs]
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+* vaesz.vs
-Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
+* vaesem.[vv,vs]
 * vaeskf1.vi
 * vaeskf2.vi
 Translation functions are defined in
 `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
 `target/riscv/vcrypto_helper.c`.
 Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
 [max.chou@sifive.com: Replaced vstart checking by TCG op]
 Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
 Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
 property]
 [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
 egs checking by helper function]
 [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
 Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h   | 2 ++
+ target/riscv/cpu_cfg.h                   |   1 +
- target/riscv/cpu.c        | 1 +
+ target/riscv/helper.h                    |  14 ++
- target/riscv/cpu_helper.c | 4 +++-
+ target/riscv/insn32.decode               |  14 ++
-files changed, 6 insertions(+), 1 deletion(-)
+ target/riscv/cpu.c                       |   4 +-
  target/riscv/vcrypto_helper.c            | 202 +++++++++++++++++++++++
  target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++
 files changed, 381 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- #define PTE_A               0x040 /* Accessed */
+     bool ext_zve64d;
- #define PTE_D               0x080 /* Dirty */
+     bool ext_zvbb;
- #define PTE_SOFT            0x300 /* Reserved for Software */
+     bool ext_zvbc;
-+#define PTE_PBMT            0x6000000000000000ULL /* Page-based memory types */
++    bool ext_zvkned;
- #define PTE_N               0x8000000000000000ULL /* NAPOT translation */
+     bool ext_zmmul;
-+#define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */
+     bool ext_zvfbfmin;
+     bool ext_zvfbfwma;
- /* Page table PPN shift amount */
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
- #define PTE_PPN_SHIFT       10
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
 +
 +DEF_HELPER_2(egs_check, void, i32, env)
 +
 +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
 +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
 +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
 +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
  @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  @r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
 +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
  @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
  @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -XXX,XX +XXX,XX @@ vcpop_v     010010 . ..... 01110 010 ..... 1010111 @r2_vm
  vwsll_vv    110101 . ..... ..... 000 ..... 1010111 @r_vm
  vwsll_vx    110101 . ..... ..... 100 ..... 1010111 @r_vm
  vwsll_vi    110101 . ..... ..... 011 ..... 1010111 @r_vm
 +
 +# *** Zvkned vector crypto extension ***
 +vaesef_vv   101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
 +vaesef_vs   101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
 +vaesdf_vv   101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
 +vaesdf_vs   101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
 +vaesem_vv   101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
 +vaesem_vs   101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
 +vaesdm_vv   101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
 +vaesdm_vs   101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
 +vaesz_vs    101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
 +vaeskf1_vi  100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +vaeskf2_vi  101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
-     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
-+    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
++    ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
+     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
-     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
-     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
+     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
       * In principle Zve*x would also suffice here, were they supported
       * in qemu
       */
 -    if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
 +    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      /* Vector cryptography extensions */
      DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
      DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
 +    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/vcrypto_helper.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/vcrypto_helper.c
-@@ -XXX,XX +XXX,XX @@ restart:
+@@ -XXX,XX +XXX,XX @@
-         if (!(pte & PTE_V)) {
+ #include "qemu/bitops.h"
-             /* Invalid PTE */
+ #include "qemu/bswap.h"
-             return TRANSLATE_FAIL;
+ #include "cpu.h"
-+        } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
++#include "crypto/aes.h"
-+            return TRANSLATE_FAIL;
++#include "crypto/aes-round.h"
-         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
+ #include "exec/memop.h"
-             /* Inner PTE, continue walking */
+ #include "exec/exec-all.h"
--            if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+ #include "exec/helper-proto.h"
-+            if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
-                 return TRANSLATE_FAIL;
+ GEN_VEXT_VX(vwsll_vx_b, 2)
-             }
+ GEN_VEXT_VX(vwsll_vx_h, 4)
-             base = ppn << PGSHIFT;
+ GEN_VEXT_VX(vwsll_vx_w, 8)
 +
 +void HELPER(egs_check)(uint32_t egs, CPURISCVState *env)
 +{
 +    uint32_t vl = env->vl;
 +    uint32_t vstart = env->vstart;
 +
 +    if (vl % egs != 0 || vstart % egs != 0) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
 +static inline void xor_round_key(AESState *round_state, AESState *round_key)
 +{
 +    round_state->v = round_state->v ^ round_key->v;
 +}
 +
 +#define GEN_ZVKNED_HELPER_VV(NAME, ...)                                   \
 +    void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env,            \
 +                      uint32_t desc)                                      \
 +    {                                                                     \
 +        uint32_t vl = env->vl;                                            \
 +        uint32_t total_elems = vext_get_total_elems(env, desc, 4);        \
 +        uint32_t vta = vext_vta(desc);                                    \
 +                                                                          \
 +        for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {        \
 +            AESState round_key;                                           \
 +            round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0));          \
 +            round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1));          \
 +            AESState round_state;                                         \
 +            round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0));         \
 +            round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1));         \
 +            __VA_ARGS__;                                                  \
 +            *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0];         \
 +            *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1];         \
 +        }                                                                 \
 +        env->vstart = 0;                                                  \
 +        /* set tail elements to 1s */                                     \
 +        vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);              \
 +    }
 +
 +#define GEN_ZVKNED_HELPER_VS(NAME, ...)                                   \
 +    void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env,            \
 +                      uint32_t desc)                                      \
 +    {                                                                     \
 +        uint32_t vl = env->vl;                                            \
 +        uint32_t total_elems = vext_get_total_elems(env, desc, 4);        \
 +        uint32_t vta = vext_vta(desc);                                    \
 +                                                                          \
 +        for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {        \
 +            AESState round_key;                                           \
 +            round_key.d[0] = *((uint64_t *)vs2 + H8(0));                  \
 +            round_key.d[1] = *((uint64_t *)vs2 + H8(1));                  \
 +            AESState round_state;                                         \
 +            round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0));         \
 +            round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1));         \
 +            __VA_ARGS__;                                                  \
 +            *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0];         \
 +            *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1];         \
 +        }                                                                 \
 +        env->vstart = 0;                                                  \
 +        /* set tail elements to 1s */                                     \
 +        vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);              \
 +    }
 +
 +GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state,
 +                                                &round_state,
 +                                                &round_key,
 +                                                false);)
 +GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state,
 +                                                &round_state,
 +                                                &round_key,
 +                                                false);)
 +GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state,
 +                                                  &round_state,
 +                                                  &round_key,
 +                                                  false);)
 +GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state,
 +                                                  &round_state,
 +                                                  &round_key,
 +                                                  false);)
 +GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state,
 +                                                   &round_state,
 +                                                   &round_key,
 +                                                   false);)
 +GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state,
 +                                                   &round_state,
 +                                                   &round_key,
 +                                                   false);)
 +GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state,
 +                                                      &round_state,
 +                                                      &round_key,
 +                                                      false);)
 +GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state,
 +                                                      &round_state,
 +                                                      &round_key,
 +                                                      false);)
 +GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);)
 +
 +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
 +                        CPURISCVState *env, uint32_t desc)
 +{
 +    uint32_t *vd = vd_vptr;
 +    uint32_t *vs2 = vs2_vptr;
 +    uint32_t vl = env->vl;
 +    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
 +    uint32_t vta = vext_vta(desc);
 +
 +    uimm &= 0b1111;
 +    if (uimm > 10 || uimm == 0) {
 +        uimm ^= 0b1000;
 +    }
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        uint32_t rk[8], tmp;
 +        static const uint32_t rcon[] = {
 +            0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
 +            0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
 +        };
 +
 +        rk[0] = vs2[i * 4 + H4(0)];
 +        rk[1] = vs2[i * 4 + H4(1)];
 +        rk[2] = vs2[i * 4 + H4(2)];
 +        rk[3] = vs2[i * 4 + H4(3)];
 +        tmp = ror32(rk[3], 8);
 +
 +        rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
 +                         ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
 +                         ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
 +                         ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
 +                      ^ rcon[uimm - 1];
 +        rk[5] = rk[1] ^ rk[4];
 +        rk[6] = rk[2] ^ rk[5];
 +        rk[7] = rk[3] ^ rk[6];
 +
 +        vd[i * 4 + H4(0)] = rk[4];
 +        vd[i * 4 + H4(1)] = rk[5];
 +        vd[i * 4 + H4(2)] = rk[6];
 +        vd[i * 4 + H4(3)] = rk[7];
 +    }
 +    env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
 +}
 +
 +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
 +                        CPURISCVState *env, uint32_t desc)
 +{
 +    uint32_t *vd = vd_vptr;
 +    uint32_t *vs2 = vs2_vptr;
 +    uint32_t vl = env->vl;
 +    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
 +    uint32_t vta = vext_vta(desc);
 +
 +    uimm &= 0b1111;
 +    if (uimm > 14 || uimm < 2) {
 +        uimm ^= 0b1000;
 +    }
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        uint32_t rk[12], tmp;
 +        static const uint32_t rcon[] = {
 +            0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
 +            0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
 +        };
 +
 +        rk[0] = vd[i * 4 + H4(0)];
 +        rk[1] = vd[i * 4 + H4(1)];
 +        rk[2] = vd[i * 4 + H4(2)];
 +        rk[3] = vd[i * 4 + H4(3)];
 +        rk[4] = vs2[i * 4 + H4(0)];
 +        rk[5] = vs2[i * 4 + H4(1)];
 +        rk[6] = vs2[i * 4 + H4(2)];
 +        rk[7] = vs2[i * 4 + H4(3)];
 +
 +        if (uimm % 2 == 0) {
 +            tmp = ror32(rk[7], 8);
 +            rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
 +                             ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
 +                             ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
 +                             ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
 +                          ^ rcon[(uimm - 1) / 2];
 +        } else {
 +            rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) |
 +                             ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) |
 +                             ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) |
 +                             ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0));
 +        }
 +        rk[9] = rk[1] ^ rk[8];
 +        rk[10] = rk[2] ^ rk[9];
 +        rk[11] = rk[3] ^ rk[10];
 +
 +        vd[i * 4 + H4(0)] = rk[8];
 +        vd[i * 4 + H4(1)] = rk[9];
 +        vd[i * 4 + H4(2)] = rk[10];
 +        vd[i * 4 + H4(3)] = rk[11];
 +    }
 +    env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
 +}
 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
  GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
  GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
  GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
 +
 +/*
 + * Zvkned
 + */
 +
 +#define ZVKNED_EGS 4
 +
 +#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS)                                \
 +    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)                  \
 +    {                                                                         \
 +        if (CHECK(s, a)) {                                                    \
 +            TCGv_ptr rd_v, rs2_v;                                             \
 +            TCGv_i32 desc, egs;                                               \
 +            uint32_t data = 0;                                                \
 +            TCGLabel *over = gen_new_label();                                 \
 +                                                                              \
 +            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
 +                /* save opcode for unwinding in case we throw an exception */ \
 +                decode_save_opc(s);                                           \
 +                egs = tcg_constant_i32(EGS);                                  \
 +                gen_helper_egs_check(egs, cpu_env);                           \
 +                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
 +            }                                                                 \
 +                                                                              \
 +            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
 +            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
 +            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
 +            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
 +            rd_v = tcg_temp_new_ptr();                                        \
 +            rs2_v = tcg_temp_new_ptr();                                       \
 +            desc = tcg_constant_i32(                                          \
 +                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
 +            tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd));              \
 +            tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2));            \
 +            gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc);                    \
 +            mark_vs_dirty(s);                                                 \
 +            gen_set_label(over);                                              \
 +            return true;                                                      \
 +        }                                                                     \
 +        return false;                                                         \
 +    }
 +
 +static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
 +{
 +    int egw_bytes = ZVKNED_EGS << s->sew;
 +    return s->cfg_ptr->ext_zvkned == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           require_align(a->rd, s->lmul) &&
 +           require_align(a->rs2, s->lmul) &&
 +           s->sew == MO_32;
 +}
 +
 +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
 +{
 +    int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
 +    return !is_overlapped(vd, op_size, vs2, 1);
 +}
 +
 +static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
 +{
 +    int egw_bytes = ZVKNED_EGS << s->sew;
 +    return vaes_check_overlap(s, a->rd, a->rs2) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           s->cfg_ptr->ext_zvkned == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           require_align(a->rd, s->lmul) &&
 +           s->sew == MO_32;
 +}
 +
 +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS)
 +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
 +
 +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS)                               \
 +    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)                  \
 +    {                                                                         \
 +        if (CHECK(s, a)) {                                                    \
 +            TCGv_ptr rd_v, rs2_v;                                             \
 +            TCGv_i32 uimm_v, desc, egs;                                       \
 +            uint32_t data = 0;                                                \
 +            TCGLabel *over = gen_new_label();                                 \
 +                                                                              \
 +            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
 +                /* save opcode for unwinding in case we throw an exception */ \
 +                decode_save_opc(s);                                           \
 +                egs = tcg_constant_i32(EGS);                                  \
 +                gen_helper_egs_check(egs, cpu_env);                           \
 +                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
 +            }                                                                 \
 +                                                                              \
 +            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
 +            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
 +            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
 +            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
 +                                                                              \
 +            rd_v = tcg_temp_new_ptr();                                        \
 +            rs2_v = tcg_temp_new_ptr();                                       \
 +            uimm_v = tcg_constant_i32(a->rs1);                                \
 +            desc = tcg_constant_i32(                                          \
 +                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
 +            tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd));              \
 +            tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2));            \
 +            gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc);            \
 +            mark_vs_dirty(s);                                                 \
 +            gen_set_label(over);                                              \
 +            return true;                                                      \
 +        }                                                                     \
 +        return false;                                                         \
 +    }
 +
 +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
 +{
 +    int egw_bytes = ZVKNED_EGS << s->sew;
 +    return s->cfg_ptr->ext_zvkned == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           s->sew == MO_32 &&
 +           require_align(a->rd, s->lmul) &&
 +           require_align(a->rs2, s->lmul);
 +}
 +
 +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
 +{
 +    int egw_bytes = ZVKNED_EGS << s->sew;
 +    return s->cfg_ptr->ext_zvkned == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           s->sew == MO_32 &&
 +           require_align(a->rd, s->lmul) &&
 +           require_align(a->rs2, s->lmul);
 +}
 +
 +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
 +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
 --
-.34.1
+.41.0

-[PULL 38/40] target/riscv: add support for svinval extension
+[PULL v2 17/45] target/riscv: Add Zvknh ISA extension support
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
-- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
+This commit adds support for the Zvknh vector-crypto extension, which
-- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
+consists of the following instructions:
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+* vsha2ms.vv
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+* vsha2c[hl].vv
-Reviewed-by: Anup Patel <anup@brainfault.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Translation functions are defined in
-Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
 `target/riscv/vcrypto_helper.c`.
 Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 [max.chou@sifive.com: Replaced vstart checking by TCG op]
 Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
 [max.chou@sifive.com: Replaced SEW selection to happened during
 translation]
 Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                          |  1 +
+ target/riscv/cpu_cfg.h                   |   2 +
- target/riscv/insn32.decode                  |  7 ++
+ target/riscv/helper.h                    |   6 +
- target/riscv/cpu.c                          |  1 +
+ target/riscv/insn32.decode               |   5 +
- target/riscv/translate.c                    |  1 +
+ target/riscv/cpu.c                       |  13 +-
- target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
+ target/riscv/vcrypto_helper.c            | 238 +++++++++++++++++++++++
-files changed, 85 insertions(+)
+ target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++
- create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
+files changed, 390 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
 @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     bool ext_counters;
+     bool ext_zvbb;
-     bool ext_ifencei;
+     bool ext_zvbc;
-     bool ext_icsr;
+     bool ext_zvkned;
-+    bool ext_svinval;
++    bool ext_zvknha;
-     bool ext_svnapot;
++    bool ext_zvknhb;
-     bool ext_svpbmt;
+     bool ext_zmmul;
-     bool ext_zfh;
+     bool ext_zvfbfmin;
      bool ext_zvfbfwma;
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
  DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
  DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
  DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
 +
 +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
+@@ -XXX,XX +XXX,XX @@ vaesdm_vs   101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
- fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
+ vaesz_vs    101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
- fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
+ vaeskf1_vi  100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
- fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm
+ vaeskf2_vi  101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +
-+# *** Svinval Standard Extension ***
++# *** Zvknh vector crypto extension ***
-+sinval_vma        0001011 ..... ..... 000 00000 1110011 @sfence_vma
++vsha2ms_vv  101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
-+sfence_w_inval    0001100 00000 00000 000 00000 1110011
++vsha2ch_vv  101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
-+sfence_inval_ir   0001100 00001 00000 000 00000 1110011
++vsha2cl_vv  101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
 +hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
-+    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
++    ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
-     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
++    ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
+     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
-     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
       * In principle Zve*x would also suffice here, were they supported
       * in qemu
       */
 -    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
 +    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
 +        !cpu->cfg.ext_zve32f) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
      }
 -    if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
 -        error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +        error_setg(
 +            errp,
 +            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
          return;
      }
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
      DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
      DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
 +    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
 +    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/vcrypto_helper.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/vcrypto_helper.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+@@ -XXX,XX +XXX,XX @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
- #include "insn_trans/trans_rvb.c.inc"
+     /* set tail elements to 1s */
- #include "insn_trans/trans_rvzfh.c.inc"
+     vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
- #include "insn_trans/trans_privileged.c.inc"
+ }
-+#include "insn_trans/trans_svinval.c.inc"
++
- #include "insn_trans/trans_xventanacondops.c.inc"
++static inline uint32_t sig0_sha256(uint32_t x)
++{
- /* Include the auto-generated decoder for 16 bit insn */
++    return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3);
-diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
++}
-new file mode 100644
++
-index XXXXXXX..XXXXXXX
++static inline uint32_t sig1_sha256(uint32_t x)
---- /dev/null
++{
-+++ b/target/riscv/insn_trans/trans_svinval.c.inc
++    return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
-@@ -XXX,XX +XXX,XX @@
++}
 +
 +static inline uint64_t sig0_sha512(uint64_t x)
 +{
 +    return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7);
 +}
 +
 +static inline uint64_t sig1_sha512(uint64_t x)
 +{
 +    return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
 +}
 +
 +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2)
 +{
 +    uint32_t res[4];
 +    res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) +
 +             vd[H4(0)];
 +    res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) +
 +             vd[H4(1)];
 +    res[2] =
 +        sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(2)];
 +    res[3] =
 +        sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)];
 +    vd[H4(3)] = res[3];
 +    vd[H4(2)] = res[2];
 +    vd[H4(1)] = res[1];
 +    vd[H4(0)] = res[0];
 +}
 +
 +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2)
 +{
 +    uint64_t res[4];
 +    res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0];
 +    res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1];
 +    res[2] = sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2];
 +    res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3];
 +    vd[3] = res[3];
 +    vd[2] = res[2];
 +    vd[1] = res[1];
 +    vd[0] = res[0];
 +}
 +
 +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
 +                        uint32_t desc)
 +{
 +    uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
 +    uint32_t esz = sew == MO_32 ? 4 : 8;
 +    uint32_t total_elems;
 +    uint32_t vta = vext_vta(desc);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        if (sew == MO_32) {
 +            vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4,
 +                        ((uint32_t *)vs2) + i * 4);
 +        } else {
 +            /* If not 32 then SEW should be 64 */
 +            vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4,
 +                        ((uint64_t *)vs2) + i * 4);
 +        }
 +    }
 +    /* set tail elements to 1s */
 +    total_elems = vext_get_total_elems(env, desc, esz);
 +    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 +
 +static inline uint64_t sum0_64(uint64_t x)
 +{
 +    return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39);
 +}
 +
 +static inline uint32_t sum0_32(uint32_t x)
 +{
 +    return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22);
 +}
 +
 +static inline uint64_t sum1_64(uint64_t x)
 +{
 +    return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41);
 +}
 +
 +static inline uint32_t sum1_32(uint32_t x)
 +{
 +    return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25);
 +}
 +
 +#define ch(x, y, z) ((x & y) ^ ((~x) & z))
 +
 +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
 +
 +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1)
 +{
 +    uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0];
 +    uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0];
 +    uint64_t W0 = vs1[0], W1 = vs1[1];
 +    uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0;
 +    uint64_t T2 = sum0_64(a) + maj(a, b, c);
 +
 +    h = g;
 +    g = f;
 +    f = e;
 +    e = d + T1;
 +    d = c;
 +    c = b;
 +    b = a;
 +    a = T1 + T2;
 +
 +    T1 = h + sum1_64(e) + ch(e, f, g) + W1;
 +    T2 = sum0_64(a) + maj(a, b, c);
 +    h = g;
 +    g = f;
 +    f = e;
 +    e = d + T1;
 +    d = c;
 +    c = b;
 +    b = a;
 +    a = T1 + T2;
 +
 +    vd[0] = f;
 +    vd[1] = e;
 +    vd[2] = b;
 +    vd[3] = a;
 +}
 +
 +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1)
 +{
 +    uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)];
 +    uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)];
 +    uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)];
 +    uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0;
 +    uint32_t T2 = sum0_32(a) + maj(a, b, c);
 +
 +    h = g;
 +    g = f;
 +    f = e;
 +    e = d + T1;
 +    d = c;
 +    c = b;
 +    b = a;
 +    a = T1 + T2;
 +
 +    T1 = h + sum1_32(e) + ch(e, f, g) + W1;
 +    T2 = sum0_32(a) + maj(a, b, c);
 +    h = g;
 +    g = f;
 +    f = e;
 +    e = d + T1;
 +    d = c;
 +    c = b;
 +    b = a;
 +    a = T1 + T2;
 +
 +    vd[H4(0)] = f;
 +    vd[H4(1)] = e;
 +    vd[H4(2)] = b;
 +    vd[H4(3)] = a;
 +}
 +
 +void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
 +                          uint32_t desc)
 +{
 +    const uint32_t esz = 4;
 +    uint32_t total_elems;
 +    uint32_t vta = vext_vta(desc);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
 +                  ((uint32_t *)vs1) + 4 * i + 2);
 +    }
 +
 +    /* set tail elements to 1s */
 +    total_elems = vext_get_total_elems(env, desc, esz);
 +    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 +
 +void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
 +                          uint32_t desc)
 +{
 +    const uint32_t esz = 8;
 +    uint32_t total_elems;
 +    uint32_t vta = vext_vta(desc);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
 +                  ((uint64_t *)vs1) + 4 * i + 2);
 +    }
 +
 +    /* set tail elements to 1s */
 +    total_elems = vext_get_total_elems(env, desc, esz);
 +    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 +
 +void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
 +                          uint32_t desc)
 +{
 +    const uint32_t esz = 4;
 +    uint32_t total_elems;
 +    uint32_t vta = vext_vta(desc);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
 +                  (((uint32_t *)vs1) + 4 * i));
 +    }
 +
 +    /* set tail elements to 1s */
 +    total_elems = vext_get_total_elems(env, desc, esz);
 +    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 +
 +void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
 +                          uint32_t desc)
 +{
 +    uint32_t esz = 8;
 +    uint32_t total_elems;
 +    uint32_t vta = vext_vta(desc);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
 +                  (((uint64_t *)vs1) + 4 * i));
 +    }
 +
 +    /* set tail elements to 1s */
 +    total_elems = vext_get_total_elems(env, desc, esz);
 +    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
  GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
  GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
 +
 +/*
-+ * RISC-V translation routines for the Svinval Standard Instruction Set.
++ * Zvknh
 + *
 + * Copyright (c) 2020-2022 PLCT lab
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#define REQUIRE_SVINVAL(ctx) do {          \
++#define ZVKNH_EGS 4
-+    if (!ctx->cfg_ptr->ext_svinval) {      \
++
-+        return false;                      \
++#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS)                               \
-+    }                                      \
++    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
-+} while (0)
++    {                                                                         \
-+
++        if (CHECK(s, a)) {                                                    \
-+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
++            uint32_t data = 0;                                                \
-+{
++            TCGLabel *over = gen_new_label();                                 \
-+    REQUIRE_SVINVAL(ctx);
++            TCGv_i32 egs;                                                     \
-+    /* Do the same as sfence.vma currently */
++                                                                              \
-+    REQUIRE_EXT(ctx, RVS);
++            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
-+#ifndef CONFIG_USER_ONLY
++                /* save opcode for unwinding in case we throw an exception */ \
-+    gen_helper_tlb_flush(cpu_env);
++                decode_save_opc(s);                                           \
-+    return true;
++                egs = tcg_constant_i32(EGS);                                  \
-+#endif
++                gen_helper_egs_check(egs, cpu_env);                           \
 +                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
 +            }                                                                 \
 +                                                                              \
 +            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
 +            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
 +            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
 +            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
 +                                                                              \
 +            tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),       \
 +                               vreg_ofs(s, a->rs2), cpu_env,                  \
 +                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,    \
 +                               data, gen_helper_##NAME);                      \
 +                                                                              \
 +            mark_vs_dirty(s);                                                 \
 +            gen_set_label(over);                                              \
 +            return true;                                                      \
 +        }                                                                     \
 +        return false;                                                         \
 +    }
 +
 +static bool vsha_check_sew(DisasContext *s)
 +{
 +    return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) ||
 +           (s->cfg_ptr->ext_zvknhb == true &&
 +            (s->sew == MO_32 || s->sew == MO_64));
 +}
 +
 +static bool vsha_check(DisasContext *s, arg_rmrr *a)
 +{
 +    int egw_bytes = ZVKNH_EGS << s->sew;
 +    int mult = 1 << MAX(s->lmul, 0);
 +    return opivv_check(s, a) &&
 +           vsha_check_sew(s) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           !is_overlapped(a->rd, mult, a->rs1, mult) &&
 +           !is_overlapped(a->rd, mult, a->rs2, mult) &&
 +           s->lmul >= 0;
 +}
 +
 +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)
 +
 +static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
 +{
 +    if (vsha_check(s, a)) {
 +        uint32_t data = 0;
 +        TCGLabel *over = gen_new_label();
 +        TCGv_i32 egs;
 +
 +        if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
 +            /* save opcode for unwinding in case we throw an exception */
 +            decode_save_opc(s);
 +            egs = tcg_constant_i32(ZVKNH_EGS);
 +            gen_helper_egs_check(egs, cpu_env);
 +            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 +        }
 +
 +        data = FIELD_DP32(data, VDATA, VM, a->vm);
 +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
 +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
 +        data = FIELD_DP32(data, VDATA, VMA, s->vma);
 +
 +        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
 +            vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
 +            s->cfg_ptr->vlen / 8, data,
 +            s->sew == MO_32 ?
 +                gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
 +
 +        mark_vs_dirty(s);
 +        gen_set_label(over);
 +        return true;
 +    }
 +    return false;
 +}
 +
-+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
++static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
 +{
-+    REQUIRE_SVINVAL(ctx);
++    if (vsha_check(s, a)) {
-+    REQUIRE_EXT(ctx, RVS);
++        uint32_t data = 0;
-+    /* Do nothing currently */
++        TCGLabel *over = gen_new_label();
-+    return true;
++        TCGv_i32 egs;
-+}
++
-+
++        if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
-+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
++            /* save opcode for unwinding in case we throw an exception */
-+{
++            decode_save_opc(s);
-+    REQUIRE_SVINVAL(ctx);
++            egs = tcg_constant_i32(ZVKNH_EGS);
-+    REQUIRE_EXT(ctx, RVS);
++            gen_helper_egs_check(egs, cpu_env);
-+    /* Do nothing currently */
++            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-+    return true;
++        }
-+}
++
-+
++        data = FIELD_DP32(data, VDATA, VM, a->vm);
-+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
++        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-+{
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);
-+    REQUIRE_SVINVAL(ctx);
++        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
-+    /* Do the same as hfence.vvma currently */
++        data = FIELD_DP32(data, VDATA, VMA, s->vma);
-+    REQUIRE_EXT(ctx, RVH);
++
-+#ifndef CONFIG_USER_ONLY
++        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
-+    gen_helper_hyp_tlb_flush(cpu_env);
++            vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
-+    return true;
++            s->cfg_ptr->vlen / 8, data,
-+#endif
++            s->sew == MO_32 ?
 +                gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
 +
 +        mark_vs_dirty(s);
 +        gen_set_label(over);
 +        return true;
 +    }
 +    return false;
 +}
-+
-+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
-+{
-+    REQUIRE_SVINVAL(ctx);
-+    /* Do the same as hfence.gvma currently */
-+    REQUIRE_EXT(ctx, RVH);
-+#ifndef CONFIG_USER_ONLY
-+    gen_helper_hyp_gvma_tlb_flush(cpu_env);
-+    return true;
-+#endif
-+    return false;
-+}
 --
-.34.1
+.41.0

-[PULL 37/40] target/riscv: add support for svnapot extension
+[PULL v2 18/45] target/riscv: Add Zvksh ISA extension support
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
-- add PTE_N bit
+This commit adds support for the Zvksh vector-crypto extension, which
-- add PTE_N bit check for inner PTE
+consists of the following instructions:
-- update address translation to support 64KiB continuous region (napot_bits = 4)
+* vsm3me.vv
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+* vsm3c.vi
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
-Reviewed-by: Anup Patel <anup@brainfault.org>
+Translation functions are defined in
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
-Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
+`target/riscv/vcrypto_helper.c`.
 Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 [max.chou@sifive.com: Replaced vstart checking by TCG op]
 Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
 Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 [max.chou@sifive.com: Exposed x-zvksh property]
 Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h   |  1 +
+ target/riscv/cpu_cfg.h                   |   1 +
- target/riscv/cpu.c        |  2 ++
+ target/riscv/helper.h                    |   3 +
- target/riscv/cpu_helper.c | 18 +++++++++++++++---
+ target/riscv/insn32.decode               |   4 +
-files changed, 18 insertions(+), 3 deletions(-)
+ target/riscv/cpu.c                       |   6 +-
+ target/riscv/vcrypto_helper.c            | 134 +++++++++++++++++++++++
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+ target/riscv/insn_trans/trans_rvvk.c.inc |  31 ++++++
-index XXXXXXX..XXXXXXX 100644
+files changed, 177 insertions(+), 2 deletions(-)
---- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+index XXXXXXX..XXXXXXX 100644
- #define PTE_A               0x040 /* Accessed */
+--- a/target/riscv/cpu_cfg.h
- #define PTE_D               0x080 /* Dirty */
++++ b/target/riscv/cpu_cfg.h
- #define PTE_SOFT            0x300 /* Reserved for Software */
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-+#define PTE_N               0x8000000000000000ULL /* NAPOT translation */
+     bool ext_zvkned;
+     bool ext_zvknha;
- /* Page table PPN shift amount */
+     bool ext_zvknhb;
- #define PTE_PPN_SHIFT       10
++    bool ext_zvksh;
      bool ext_zmmul;
      bool ext_zvfbfmin;
      bool ext_zvfbfwma;
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
  DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
  DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
  DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
 +
 +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
 +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vaeskf2_vi  101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
  vsha2ms_vv  101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
  vsha2ch_vv  101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
  vsha2cl_vv  101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +
 +# *** Zvksh vector crypto extension ***
 +vsm3me_vv   100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +vsm3c_vi    101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
+     ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
-+    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
++    ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
-+
+     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
-     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
-     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
+     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
-     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+      * In principle Zve*x would also suffice here, were they supported
-index XXXXXXX..XXXXXXX 100644
+      * in qemu
---- a/target/riscv/cpu_helper.c
+      */
-+++ b/target/riscv/cpu_helper.c
+-    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+-        !cpu->cfg.ext_zve32f) {
-     bool use_background = false;
++    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
-     hwaddr ppn;
++         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
-     RISCVCPU *cpu = env_archcpu(env);
+         error_setg(errp,
-+    int napot_bits = 0;
+                    "Vector crypto extensions require V or Zve* extensions");
-+    target_ulong napot_mask;
+         return;
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     /*
+     DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
-      * Check if we should use the background registers for the two
+     DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
-@@ -XXX,XX +XXX,XX @@ restart:
+     DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
-             return TRANSLATE_FAIL;
++    DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
-         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
-             /* Inner PTE, continue walking */
+     DEFINE_PROP_END_OF_LIST(),
--            if (pte & (PTE_D | PTE_A | PTE_U)) {
+ };
-+            if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
-                 return TRANSLATE_FAIL;
+index XXXXXXX..XXXXXXX 100644
-             }
+--- a/target/riscv/vcrypto_helper.c
-             base = ppn << PGSHIFT;
++++ b/target/riscv/vcrypto_helper.c
-@@ -XXX,XX +XXX,XX @@ restart:
+@@ -XXX,XX +XXX,XX @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
-             /* for superpage mappings, make a fake leaf PTE for the TLB's
+     vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
-                benefit. */
+     env->vstart = 0;
-             target_ulong vpn = addr >> PGSHIFT;
+ }
--            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
++
--                        (addr & ~TARGET_PAGE_MASK);
++static inline uint32_t p1(uint32_t x)
-+
++{
-+            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
++    return x ^ rol32(x, 15) ^ rol32(x, 23);
-+                napot_bits = ctzl(ppn) + 1;
++}
-+                if ((i != (levels - 1)) || (napot_bits != 4)) {
++
-+                    return TRANSLATE_FAIL;
++static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3,
-+                }
++                               uint32_t m13, uint32_t m6)
-+            }
++{
-+
++    return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6;
-+            napot_mask = (1 << napot_bits) - 1;
++}
-+            *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
++
-+                          (vpn & (((target_ulong)1 << ptshift) - 1))
++void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
-+                         ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
++                       CPURISCVState *env, uint32_t desc)
++{
-             /* set permissions on the TLB entry */
++    uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
-             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +    uint32_t vta = vext_vta(desc);
 +    uint32_t *vd = vd_vptr;
 +    uint32_t *vs1 = vs1_vptr;
 +    uint32_t *vs2 = vs2_vptr;
 +
 +    for (int i = env->vstart / 8; i < env->vl / 8; i++) {
 +        uint32_t w[24];
 +        for (int j = 0; j < 8; j++) {
 +            w[j] = bswap32(vs1[H4((i * 8) + j)]);
 +            w[j + 8] = bswap32(vs2[H4((i * 8) + j)]);
 +        }
 +        for (int j = 0; j < 8; j++) {
 +            w[j + 16] =
 +                zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]);
 +        }
 +        for (int j = 0; j < 8; j++) {
 +            vd[(i * 8) + j] = bswap32(w[H4(j + 16)]);
 +        }
 +    }
 +    vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 +
 +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z)
 +{
 +    return x ^ y ^ z;
 +}
 +
 +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z)
 +{
 +    return (x & y) | (x & z) | (y & z);
 +}
 +
 +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
 +{
 +    return (j <= 15) ? ff1(x, y, z) : ff2(x, y, z);
 +}
 +
 +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z)
 +{
 +    return x ^ y ^ z;
 +}
 +
 +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z)
 +{
 +    return (x & y) | (~x & z);
 +}
 +
 +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
 +{
 +    return (j <= 15) ? gg1(x, y, z) : gg2(x, y, z);
 +}
 +
 +static inline uint32_t t_j(uint32_t j)
 +{
 +    return (j <= 15) ? 0x79cc4519 : 0x7a879d8a;
 +}
 +
 +static inline uint32_t p_0(uint32_t x)
 +{
 +    return x ^ rol32(x, 9) ^ rol32(x, 17);
 +}
 +
 +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm)
 +{
 +    uint32_t x0, x1;
 +    uint32_t j;
 +    uint32_t ss1, ss2, tt1, tt2;
 +    x0 = vs2[0] ^ vs2[4];
 +    x1 = vs2[1] ^ vs2[5];
 +    j = 2 * uimm;
 +    ss1 = rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7);
 +    ss2 = ss1 ^ rol32(vs1[0], 12);
 +    tt1 = ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0;
 +    tt2 = gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0];
 +    vs1[3] = vs1[2];
 +    vd[3] = rol32(vs1[1], 9);
 +    vs1[1] = vs1[0];
 +    vd[1] = tt1;
 +    vs1[7] = vs1[6];
 +    vd[7] = rol32(vs1[5], 19);
 +    vs1[5] = vs1[4];
 +    vd[5] = p_0(tt2);
 +    j = 2 * uimm + 1;
 +    ss1 = rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7);
 +    ss2 = ss1 ^ rol32(vd[1], 12);
 +    tt1 = ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1;
 +    tt2 = gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1];
 +    vd[2] = rol32(vs1[1], 9);
 +    vd[0] = tt1;
 +    vd[6] = rol32(vs1[5], 19);
 +    vd[4] = p_0(tt2);
 +}
 +
 +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
 +                      CPURISCVState *env, uint32_t desc)
 +{
 +    uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +    uint32_t vta = vext_vta(desc);
 +    uint32_t *vd = vd_vptr;
 +    uint32_t *vs2 = vs2_vptr;
 +    uint32_t v1[8], v2[8], v3[8];
 +
 +    for (int i = env->vstart / 8; i < env->vl / 8; i++) {
 +        for (int k = 0; k < 8; k++) {
 +            v2[k] = bswap32(vd[H4(i * 8 + k)]);
 +            v3[k] = bswap32(vs2[H4(i * 8 + k)]);
 +        }
 +        sm3c(v1, v2, v3, uimm);
 +        for (int k = 0; k < 8; k++) {
 +            vd[i * 8 + k] = bswap32(v1[H4(k)]);
 +        }
 +    }
 +    vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
 +    env->vstart = 0;
 +}
 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
      }
      return false;
  }
 +
 +/*
 + * Zvksh
 + */
 +
 +#define ZVKSH_EGS 8
 +
 +static inline bool vsm3_check(DisasContext *s, arg_rmrr *a)
 +{
 +    int egw_bytes = ZVKSH_EGS << s->sew;
 +    int mult = 1 << MAX(s->lmul, 0);
 +    return s->cfg_ptr->ext_zvksh == true &&
 +           require_rvv(s) &&
 +           vext_check_isa_ill(s) &&
 +           !is_overlapped(a->rd, mult, a->rs2, mult) &&
 +           MAXSZ(s) >= egw_bytes &&
 +           s->sew == MO_32;
 +}
 +
 +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a)
 +{
 +    return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
 +}
 +
 +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
 +{
 +    return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm);
 +}
 +
 +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS)
 +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS)
 --
-.34.1
+.41.0

-[PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs
+[PULL v2 19/45] target/riscv: Add Zvkg ISA extension support
-From: Anup Patel <anup.patel@wdc.com>
+From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
-The hgeie and hgeip CSRs are required for emulating an external
+This commit adds support for the Zvkg vector-crypto extension, which
-interrupt controller capable of injecting virtual external interrupt
+consists of the following instructions:
-to Guest/VM running at VS-level.
+* vgmul.vv
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+* vghsh.vv
-Signed-off-by: Anup Patel <anup@brainfault.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Translation functions are defined in
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
-Message-id: 20220204174700.534953-4-anup@brainfault.org
+`target/riscv/vcrypto_helper.c`.
 Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 [max.chou@sifive.com: Replaced vstart checking by TCG op]
 Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
 Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 [max.chou@sifive.com: Exposed x-zvkg property]
 [max.chou@sifive.com: Replaced uint by int for cross win32 build]
 Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  5 +++
+ target/riscv/cpu_cfg.h                   |  1 +
- target/riscv/cpu_bits.h   |  1 +
+ target/riscv/helper.h                    |  3 +
- target/riscv/cpu.c        | 67 +++++++++++++++++++++++++++------------
+ target/riscv/insn32.decode               |  4 ++
- target/riscv/cpu_helper.c | 37 +++++++++++++++++++--
+ target/riscv/cpu.c                       |  6 +-
- target/riscv/csr.c        | 43 +++++++++++++++++--------
+ target/riscv/vcrypto_helper.c            | 72 ++++++++++++++++++++++++
- target/riscv/machine.c    |  6 ++--
+ target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++
-files changed, 121 insertions(+), 38 deletions(-)
+files changed, 114 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     target_ulong priv;
+     bool ext_zve64d;
-     /* This contains QEMU specific information about the virt state. */
+     bool ext_zvbb;
-     target_ulong virt;
+     bool ext_zvbc;
-+    target_ulong geilen;
++    bool ext_zvkg;
-     target_ulong resetvec;
+     bool ext_zvkned;
+     bool ext_zvknha;
-     target_ulong mhartid;
+     bool ext_zvknhb;
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-     target_ulong htval;
+index XXXXXXX..XXXXXXX 100644
-     target_ulong htinst;
+--- a/target/riscv/helper.h
-     target_ulong hgatp;
++++ b/target/riscv/helper.h
-+    target_ulong hgeie;
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
-+    target_ulong hgeip;
-     uint64_t htimedelta;
+ DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
+ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
-     /* Upper 64-bits of 128-bit CSRs */
++
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
++DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32)
- int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
++DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32)
- int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- bool riscv_cpu_fp_enabled(CPURISCVState *env);
+index XXXXXXX..XXXXXXX 100644
-+target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
+--- a/target/riscv/insn32.decode
-+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
++++ b/target/riscv/insn32.decode
- bool riscv_cpu_vector_enabled(CPURISCVState *env);
+@@ -XXX,XX +XXX,XX @@ vsha2cl_vv  101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
- bool riscv_cpu_virt_enabled(CPURISCVState *env);
+ # *** Zvksh vector crypto extension ***
- void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
+ vsm3me_vv   100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+ vsm3c_vi    101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
-index XXXXXXX..XXXXXXX 100644
++
---- a/target/riscv/cpu_bits.h
++# *** Zvkg vector crypto extension ***
-+++ b/target/riscv/cpu_bits.h
++vghsh_vv    101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
-@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
++vgmul_vv    101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
  #define IRQ_M_EXT                          11
  #define IRQ_S_GEXT                         12
  #define IRQ_LOCAL_MAX                      16
 +#define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
  /* mip masks */
  #define MIP_USIP                           (1 << IRQ_U_SOFT)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
- static void riscv_cpu_set_irq(void *opaque, int irq, int level)
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
- {
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-     RISCVCPU *cpu = RISCV_CPU(opaque);
+     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
-+    CPURISCVState *env = &cpu->env;
++    ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
+     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
--    switch (irq) {
+     ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
--    case IRQ_U_SOFT:
+     ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
--    case IRQ_S_SOFT:
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
--    case IRQ_VS_SOFT:
+      * In principle Zve*x would also suffice here, were they supported
--    case IRQ_M_SOFT:
+      * in qemu
--    case IRQ_U_TIMER:
+      */
--    case IRQ_S_TIMER:
+-    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
--    case IRQ_VS_TIMER:
+-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
--    case IRQ_M_TIMER:
++    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
--    case IRQ_U_EXT:
++         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
--    case IRQ_S_EXT:
+         error_setg(errp,
--    case IRQ_VS_EXT:
+                    "Vector crypto extensions require V or Zve* extensions");
--    case IRQ_M_EXT:
+         return;
--        if (kvm_enabled()) {
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
--            kvm_riscv_set_irq(cpu, irq, level);
+     /* Vector cryptography extensions */
--        } else {
+     DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
--            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+     DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
-+    if (irq < IRQ_LOCAL_MAX) {
++    DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
-+        switch (irq) {
+     DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
-+        case IRQ_U_SOFT:
+     DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
-+        case IRQ_S_SOFT:
+     DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
-+        case IRQ_VS_SOFT:
+diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
-+        case IRQ_M_SOFT:
+index XXXXXXX..XXXXXXX 100644
-+        case IRQ_U_TIMER:
+--- a/target/riscv/vcrypto_helper.c
-+        case IRQ_S_TIMER:
++++ b/target/riscv/vcrypto_helper.c
-+        case IRQ_VS_TIMER:
+@@ -XXX,XX +XXX,XX @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
-+        case IRQ_M_TIMER:
+     vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
-+        case IRQ_U_EXT:
+     env->vstart = 0;
-+        case IRQ_S_EXT:
+ }
-+        case IRQ_VS_EXT:
++
-+        case IRQ_M_EXT:
++void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
-+             if (kvm_enabled()) {
++                      CPURISCVState *env, uint32_t desc)
-+                kvm_riscv_set_irq(cpu, irq, level);
++{
-+             } else {
++    uint64_t *vd = vd_vptr;
-+                riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
++    uint64_t *vs1 = vs1_vptr;
-+             }
++    uint64_t *vs2 = vs2_vptr;
-+             break;
++    uint32_t vta = vext_vta(desc);
-+        default:
++    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
-+            g_assert_not_reached();
++
-         }
++    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
--        break;
++        uint64_t Y[2] = {vd[i * 2 + 0], vd[i * 2 + 1]};
--    default:
++        uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])};
-+    } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
++        uint64_t X[2] = {vs1[i * 2 + 0], vs1[i * 2 + 1]};
-+        /* Require H-extension for handling guest local interrupts */
++        uint64_t Z[2] = {0, 0};
-+        if (!riscv_has_ext(env, RVH)) {
++
-+            g_assert_not_reached();
++        uint64_t S[2] = {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])};
 +
 +        for (int j = 0; j < 128; j++) {
 +            if ((S[j / 64] >> (j % 64)) & 1) {
 +                Z[0] ^= H[0];
 +                Z[1] ^= H[1];
 +            }
 +            bool reduce = ((H[1] >> 63) & 1);
 +            H[1] = H[1] << 1 | H[0] >> 63;
 +            H[0] = H[0] << 1;
 +            if (reduce) {
 +                H[0] ^= 0x87;
 +            }
 +        }
 +
-+        /* Compute bit position in HGEIP CSR */
++        vd[i * 2 + 0] = brev8(Z[0]);
-+        irq = irq - IRQ_LOCAL_MAX + 1;
++        vd[i * 2 + 1] = brev8(Z[1]);
-+        if (env->geilen < irq) {
++    }
-+            g_assert_not_reached();
++    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
 +    env->vstart = 0;
 +}
 +
 +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env,
 +                      uint32_t desc)
 +{
 +    uint64_t *vd = vd_vptr;
 +    uint64_t *vs2 = vs2_vptr;
 +    uint32_t vta = vext_vta(desc);
 +    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
 +
 +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
 +        uint64_t Y[2] = {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])};
 +        uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])};
 +        uint64_t Z[2] = {0, 0};
 +
 +        for (int j = 0; j < 128; j++) {
 +            if ((Y[j / 64] >> (j % 64)) & 1) {
 +                Z[0] ^= H[0];
 +                Z[1] ^= H[1];
 +            }
 +            bool reduce = ((H[1] >> 63) & 1);
 +            H[1] = H[1] << 1 | H[0] >> 63;
 +            H[0] = H[0] << 1;
 +            if (reduce) {
 +                H[0] ^= 0x87;
 +            }
 +        }
 +
-+        /* Update HGEIP CSR */
++        vd[i * 2 + 0] = brev8(Z[0]);
-+        env->hgeip &= ~((target_ulong)1 << irq);
++        vd[i * 2 + 1] = brev8(Z[1]);
 +        if (level) {
 +            env->hgeip |= (target_ulong)1 << irq;
 +        }
 +
 +        /* Update mip.SGEIP bit */
 +        riscv_cpu_update_mip(cpu, MIP_SGEIP,
 +                             BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
 +    } else {
          g_assert_not_reached();
      }
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
      cpu_set_cpustate_pointers(cpu);
  #ifndef CONFIG_USER_ONLY
 -    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
 +    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
 +                      IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
  #endif /* CONFIG_USER_ONLY */
  }
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
      target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
      target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
 -    target_ulong pending = env->mip & env->mie;
 +    target_ulong vsgemask =
 +                (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
 +    target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
 +
 +    target_ulong pending = (env->mip | vsgein) & env->mie;
      target_ulong mie    = env->priv < PRV_M ||
                            (env->priv == PRV_M && mstatus_mie);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
      }
  }
 +target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
 +{
 +    if (!riscv_has_ext(env, RVH)) {
 +        return 0;
 +    }
-+
++    /* set tail elements to 1s */
-+    return env->geilen;
++    vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
-+}
++    env->vstart = 0;
-+
++}
-+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
+diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
-+{
+index XXXXXXX..XXXXXXX 100644
-+    if (!riscv_has_ext(env, RVH)) {
+--- a/target/riscv/insn_trans/trans_rvvk.c.inc
-+        return;
++++ b/target/riscv/insn_trans/trans_rvvk.c.inc
-+    }
+@@ -XXX,XX +XXX,XX @@ static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
-+
-+    if (geilen > (TARGET_LONG_BITS - 1)) {
+ GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS)
-+        return;
+ GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS)
-+    }
++
-+
++/*
-+    env->geilen = geilen;
++ * Zvkg
-+}
++ */
 +
- bool riscv_cpu_virt_enabled(CPURISCVState *env)
++#define ZVKG_EGS 4
- {
++
-     if (!riscv_has_ext(env, RVH)) {
++static bool vgmul_check(DisasContext *s, arg_rmr *a)
-@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
++{
- {
++    int egw_bytes = ZVKG_EGS << s->sew;
-     CPURISCVState *env = &cpu->env;
++    return s->cfg_ptr->ext_zvkg == true &&
-     CPUState *cs = CPU(cpu);
++           vext_check_isa_ill(s) &&
--    uint32_t old = env->mip;
++           require_rvv(s) &&
-+    uint32_t gein, vsgein = 0, old = env->mip;
++           MAXSZ(s) >= egw_bytes &&
-     bool locked = false;
++           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           s->sew == MO_32;
-+    if (riscv_cpu_virt_enabled(env)) {
++}
-+        gein = get_field(env->hstatus, HSTATUS_VGEIN);
++
-+        vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
++GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS)
-+    }
++
-+
++static bool vghsh_check(DisasContext *s, arg_rmrr *a)
-     if (!qemu_mutex_iothread_locked()) {
++{
-         locked = true;
++    int egw_bytes = ZVKG_EGS << s->sew;
-         qemu_mutex_lock_iothread();
++    return s->cfg_ptr->ext_zvkg == true &&
-@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
++           opivv_check(s, a) &&
++           MAXSZ(s) >= egw_bytes &&
-     env->mip = (env->mip & ~mask) | (value & mask);
++           s->sew == MO_32;
++}
--    if (env->mip) {
++
-+    if (env->mip | vsgein) {
++GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS)
          cpu_interrupt(cs, CPU_INTERRUPT_HARD);
      } else {
          cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
      RISCVCPU *cpu = env_archcpu(env);
      /* Allow software control of delegable interrupts not claimed by hardware */
      target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 -    uint32_t old_mip;
 +    uint32_t gin, old_mip;
      if (mask) {
          old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
          old_mip = env->mip;
      }
 +    if (csrno != CSR_HVIP) {
 +        gin = get_field(env->hstatus, HSTATUS_VGEIN);
 +        old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
 +    }
 +
      if (ret_value) {
          *ret_value = old_mip;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
                                 target_ulong new_value, target_ulong write_mask)
  {
      /* Shift the S bits to their VS bit location in mip */
 -    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +    int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
                        (write_mask << 1) & vsip_writable_mask & env->hideleg);
      if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
      if (riscv_cpu_virt_enabled(env)) {
          ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
      } else {
 -        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 +        ret = rmw_mip(env, csrno, ret_value, new_value,
                        write_mask & env->mideleg & sip_writable_mask);
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
                                 target_ulong *ret_value,
                                 target_ulong new_value, target_ulong write_mask)
  {
 -    int ret = rmw_mip(env, 0, ret_value, new_value,
 +    int ret = rmw_mip(env, csrno, ret_value, new_value,
                        write_mask & hvip_writable_mask);
      if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
                                target_ulong *ret_value,
                                target_ulong new_value, target_ulong write_mask)
  {
 -    int ret = rmw_mip(env, 0, ret_value, new_value,
 +    int ret = rmw_mip(env, csrno, ret_value, new_value,
                        write_mask & hip_writable_mask);
      if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 -static RISCVException write_hgeie(CPURISCVState *env, int csrno,
 -                                  target_ulong val)
 +static RISCVException read_hgeie(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      if (val) {
 -        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 +        *val = env->hgeie;
      }
      return RISCV_EXCP_NONE;
  }
 +static RISCVException write_hgeie(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
 +{
 +    /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
 +    val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
 +    env->hgeie = val;
 +    /* Update mip.SGEIP bit */
 +    riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
 +                         BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
 +    return RISCV_EXCP_NONE;
 +}
 +
  static RISCVException read_htval(CPURISCVState *env, int csrno,
                                   target_ulong *val)
  {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 -static RISCVException write_hgeip(CPURISCVState *env, int csrno,
 -                                  target_ulong val)
 +static RISCVException read_hgeip(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      if (val) {
 -        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 +        *val = env->hgeip;
      }
      return RISCV_EXCP_NONE;
  }
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
      [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
      [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
 -    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
 +    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
      [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
      [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
 -    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
 +    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       NULL              },
      [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
      [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
      [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
  static const VMStateDescription vmstate_hyper = {
      .name = "cpu/hyper",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .needed = hyper_needed,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL(env.hstatus, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
          VMSTATE_UINTTL(env.htval, RISCVCPU),
          VMSTATE_UINTTL(env.htinst, RISCVCPU),
          VMSTATE_UINTTL(env.hgatp, RISCVCPU),
 +        VMSTATE_UINTTL(env.hgeie, RISCVCPU),
 +        VMSTATE_UINTTL(env.hgeip, RISCVCPU),
          VMSTATE_UINT64(env.htimedelta, RISCVCPU),
          VMSTATE_UINT64(env.vsstatus, RISCVCPU),
 --
-.34.1
+.41.0

-[PULL 02/40] Allow setting up to 8 bytes with the generic loader
+[PULL v2 20/45] crypto: Create sm4_subword
-From: Petr Tesarik <ptesarik@suse.com>
+From: Max Chou <max.chou@sifive.com>
-The documentation for the generic loader says that "the maximum size of
+Allows sharing of sm4_subword between different targets.
 the data is 8 bytes". However, attempts to set data-len=8 trigger the
 following assertion failure:
-../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len < sizeof(s->data)' failed.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-assert should use <= instead of <.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20230711165917.2629866-14-max.chou@sifive.com>
 Fixes: e481a1f63c93 ("generic-loader: Add a generic loader")
 Signed-off-by: Petr Tesarik <ptesarik@suse.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20220120092715.7805-1-ptesarik@suse.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/core/generic-loader.c | 2 +-
+ include/crypto/sm4.h           |  8 ++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/tcg/crypto_helper.c | 10 ++--------
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
+diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/generic-loader.c
+--- a/include/crypto/sm4.h
-+++ b/hw/core/generic-loader.c
++++ b/include/crypto/sm4.h
-@@ -XXX,XX +XXX,XX @@ static void generic_loader_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@
-     }
+ extern const uint8_t sm4_sbox[256];
-     if (s->data_len) {
--        assert(s->data_len < sizeof(s->data));
++static inline uint32_t sm4_subword(uint32_t word)
-+        assert(s->data_len <= sizeof(s->data));
++{
-         dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len,
++    return sm4_sbox[word & 0xff] |
-                          MEMTXATTRS_UNSPECIFIED);
++           sm4_sbox[(word >> 8) & 0xff] << 8 |
 +           sm4_sbox[(word >> 16) & 0xff] << 16 |
 +           sm4_sbox[(word >> 24) & 0xff] << 24;
 +}
 +
  #endif
 diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/crypto_helper.c
 +++ b/target/arm/tcg/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
              CR_ST_WORD(d, (i + 3) % 4) ^
              CR_ST_WORD(n, i);
 -        t = sm4_sbox[t & 0xff] |
 -            sm4_sbox[(t >> 8) & 0xff] << 8 |
 -            sm4_sbox[(t >> 16) & 0xff] << 16 |
 -            sm4_sbox[(t >> 24) & 0xff] << 24;
 +        t = sm4_subword(t);
          CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^
                              rol32(t, 24);
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
              CR_ST_WORD(d, (i + 3) % 4) ^
              CR_ST_WORD(m, i);
 -        t = sm4_sbox[t & 0xff] |
 -            sm4_sbox[(t >> 8) & 0xff] << 8 |
 -            sm4_sbox[(t >> 16) & 0xff] << 16 |
 -            sm4_sbox[(t >> 24) & 0xff] << 24;
 +        t = sm4_subword(t);
          CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23);
      }
 --
-.34.1
+.41.0

-[PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
+[PULL v2 21/45] crypto: Add SM4 constant parameter CK
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Max Chou <max.chou@sifive.com>
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Adds sm4_ck constant for use in sm4 cryptography across different targets.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
+Signed-off-by: Max Chou <max.chou@sifive.com>
 Message-ID: <20230711165917.2629866-15-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 78 ++++++++++++++++++++++++----------------------
+ include/crypto/sm4.h |  1 +
-file changed, 41 insertions(+), 37 deletions(-)
+ crypto/sm4.c         | 10 ++++++++++
 files changed, 11 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/include/crypto/sm4.h
-+++ b/target/riscv/cpu.h
++++ b/include/crypto/sm4.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUClass {
+@@ -XXX,XX +XXX,XX @@
-     DeviceReset parent_reset;
+ #define QEMU_SM4_H
  extern const uint8_t sm4_sbox[256];
 +extern const uint32_t sm4_ck[32];
  static inline uint32_t sm4_subword(uint32_t word)
  {
 diff --git a/crypto/sm4.c b/crypto/sm4.c
 index XXXXXXX..XXXXXXX 100644
 --- a/crypto/sm4.c
 +++ b/crypto/sm4.c
@@ -XXX,XX +XXX,XX @@ uint8_t const sm4_sbox[] = {
 x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
  };
-+struct RISCVCPUConfig {
++uint32_t const sm4_ck[] = {
-+    bool ext_i;
++    0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
-+    bool ext_e;
++    0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
-+    bool ext_g;
++    0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
-+    bool ext_m;
++    0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
-+    bool ext_a;
++    0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
-+    bool ext_f;
++    0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
-+    bool ext_d;
++    0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
-+    bool ext_c;
++    0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
 +    bool ext_s;
 +    bool ext_u;
 +    bool ext_h;
 +    bool ext_j;
 +    bool ext_v;
 +    bool ext_zba;
 +    bool ext_zbb;
 +    bool ext_zbc;
 +    bool ext_zbs;
 +    bool ext_counters;
 +    bool ext_ifencei;
 +    bool ext_icsr;
 +    bool ext_zfh;
 +    bool ext_zfhmin;
 +    bool ext_zve32f;
 +    bool ext_zve64f;
 +
 +    char *priv_spec;
 +    char *user_spec;
 +    char *bext_spec;
 +    char *vext_spec;
 +    uint16_t vlen;
 +    uint16_t elen;
 +    bool mmu;
 +    bool pmp;
 +    bool epmp;
 +    uint64_t resetvec;
 +};
-+
-+typedef struct RISCVCPUConfig RISCVCPUConfig;
-+
- /**
-  * RISCVCPU:
-  * @env: #CPURISCVState
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
-     char *dyn_vreg_xml;
-     /* Configuration Settings */
--    struct {
--        bool ext_i;
--        bool ext_e;
--        bool ext_g;
--        bool ext_m;
--        bool ext_a;
--        bool ext_f;
--        bool ext_d;
--        bool ext_c;
--        bool ext_s;
--        bool ext_u;
--        bool ext_h;
--        bool ext_j;
--        bool ext_v;
--        bool ext_zba;
--        bool ext_zbb;
--        bool ext_zbc;
--        bool ext_zbs;
--        bool ext_counters;
--        bool ext_ifencei;
--        bool ext_icsr;
--        bool ext_zfh;
--        bool ext_zfhmin;
--        bool ext_zve32f;
--        bool ext_zve64f;
--
--        char *priv_spec;
--        char *user_spec;
--        char *bext_spec;
--        char *vext_spec;
--        uint16_t vlen;
--        uint16_t elen;
--        bool mmu;
--        bool pmp;
--        bool epmp;
--        uint64_t resetvec;
--    } cfg;
-+    RISCVCPUConfig cfg;
- };
- static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 --
-.34.1
+.41.0

-[PULL 20/40] target/riscv: Implement AIA local interrupt priorities
+[PULL v2 22/45] target/riscv: Add Zvksed ISA extension support
-From: Anup Patel <anup.patel@wdc.com>
+From: Max Chou <max.chou@sifive.com>
-The AIA spec defines programmable 8-bit priority for each local interrupt
+This commit adds support for the Zvksed vector-crypto extension, which
-at M-level, S-level and VS-level so we extend local interrupt processing
+consists of the following instructions:
-to consider AIA interrupt priorities. The AIA CSRs which help software
-configure local interrupt priorities will be added by subsequent patches.
+* vsm4k.vi
+* vsm4r.[vv,vs]
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Translation functions are defined in
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
-Message-id: 20220204174700.534953-10-anup@brainfault.org
+`target/riscv/vcrypto_helper.c`.
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 [lawrence.hunter@codethink.co.uk: Moved SM4 functions from
 crypto_helper.c to vcrypto_helper.c]
 [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
 use macros, and minor style changes]
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  12 ++
+ target/riscv/cpu_cfg.h                   |   1 +
- target/riscv/cpu.c        |  19 +++
+ target/riscv/helper.h                    |   4 +
- target/riscv/cpu_helper.c | 281 +++++++++++++++++++++++++++++++++++---
+ target/riscv/insn32.decode               |   5 +
- target/riscv/machine.c    |   3 +
+ target/riscv/cpu.c                       |   5 +-
-files changed, 294 insertions(+), 21 deletions(-)
+ target/riscv/vcrypto_helper.c            | 127 +++++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvvk.c.inc |  43 ++++++++
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+files changed, 184 insertions(+), 1 deletion(-)
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+--- a/target/riscv/cpu_cfg.h
-     target_ulong mcause;
++++ b/target/riscv/cpu_cfg.h
-     target_ulong mtval;  /* since: priv-1.10.0 */
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zvkned;
-+    /* Machine and Supervisor interrupt priorities */
+     bool ext_zvknha;
-+    uint8_t miprio[64];
+     bool ext_zvknhb;
-+    uint8_t siprio[64];
++    bool ext_zvksed;
-+
+     bool ext_zvksh;
-     /* Hypervisor CSRs */
+     bool ext_zmmul;
-     target_ulong hstatus;
+     bool ext_zvfbfmin;
-     target_ulong hedeleg;
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+index XXXXXXX..XXXXXXX 100644
-     target_ulong hgeip;
+--- a/target/riscv/helper.h
-     uint64_t htimedelta;
++++ b/target/riscv/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
-+    /* Hypervisor controlled virtual interrupt priorities */
-+    uint8_t hviprio[64];
+ DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32)
-+
+ DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32)
-     /* Upper 64-bits of 128-bit CSRs */
++
-     uint64_t mscratchh;
++DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32)
-     uint64_t sscratchh;
++DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32)
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
++DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)
-                                int cpuid, void *opaque);
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
+index XXXXXXX..XXXXXXX 100644
- int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+--- a/target/riscv/insn32.decode
-+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
++++ b/target/riscv/insn32.decode
-+uint8_t riscv_cpu_default_priority(int irq);
+@@ -XXX,XX +XXX,XX @@ vsm3c_vi    101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
-+int riscv_cpu_mirq_pending(CPURISCVState *env);
+ # *** Zvkg vector crypto extension ***
-+int riscv_cpu_sirq_pending(CPURISCVState *env);
+ vghsh_vv    101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
-+int riscv_cpu_vsirq_pending(CPURISCVState *env);
+ vgmul_vv    101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
- bool riscv_cpu_fp_enabled(CPURISCVState *env);
++
- target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
++# *** Zvksed vector crypto extension ***
- void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
++vsm4k_vi    100001 1 ..... ..... 010 ..... 1110111 @r_vm_1
 +vsm4r_vv    101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1
 +vsm4r_vs    101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
- static void riscv_cpu_reset(DeviceState *dev)
+     ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
- {
+     ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
-+#ifndef CONFIG_USER_ONLY
++    ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
-+    uint8_t iprio;
+     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
-+    int i, irq, rdzero;
+     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
-+#endif
+     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
-     CPUState *cs = CPU(dev);
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     RISCVCPU *cpu = RISCV_CPU(cs);
+      * in qemu
-     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+      */
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
-     env->miclaim = MIP_SGEIP;
+-         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
-     env->pc = env->resetvec;
++         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
-     env->two_stage_lookup = false;
++        !cpu->cfg.ext_zve32f) {
-+
+         error_setg(errp,
-+    /* Initialized default priorities of local interrupts. */
+                    "Vector crypto extensions require V or Zve* extensions");
-+    for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
+         return;
-+        iprio = riscv_cpu_default_priority(i);
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-+        env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
+     DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
-+        env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
+     DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
-+        env->hviprio[i] = 0;
+     DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
-+    }
++    DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
-+    i = 0;
+     DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
-+    while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
-+        if (!rdzero) {
+     DEFINE_PROP_END_OF_LIST(),
-+            env->hviprio[irq] = env->miprio[irq];
+diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
-+        }
+index XXXXXXX..XXXXXXX 100644
-+        i++;
+--- a/target/riscv/vcrypto_helper.c
-+    }
++++ b/target/riscv/vcrypto_helper.c
-     /* mmte is supposed to have pm.current hardwired to 1 */
+@@ -XXX,XX +XXX,XX @@
-     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
+ #include "cpu.h"
- #endif
+ #include "crypto/aes.h"
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+ #include "crypto/aes-round.h"
-index XXXXXXX..XXXXXXX 100644
++#include "crypto/sm4.h"
---- a/target/riscv/cpu_helper.c
+ #include "exec/memop.h"
-+++ b/target/riscv/cpu_helper.c
+ #include "exec/exec-all.h"
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_update_mask(CPURISCVState *env)
+ #include "exec/helper-proto.h"
@@ -XXX,XX +XXX,XX @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env,
      vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
      env->vstart = 0;
  }
++
- #ifndef CONFIG_USER_ONLY
++void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *env,
--static int riscv_cpu_local_irq_pending(CPURISCVState *env)
++                      uint32_t desc)
 +{
 +    const uint32_t egs = 4;
 +    uint32_t rnd = uimm5 & 0x7;
 +    uint32_t group_start = env->vstart / egs;
 +    uint32_t group_end = env->vl / egs;
 +    uint32_t esz = sizeof(uint32_t);
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +
 +    for (uint32_t i = group_start; i < group_end; ++i) {
 +        uint32_t vstart = i * egs;
 +        uint32_t vend = (i + 1) * egs;
 +        uint32_t rk[4] = {0};
 +        uint32_t tmp[8] = {0};
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            rk[j - vstart] = *((uint32_t *)vs2 + H4(j));
 +        }
 +
 +        for (uint32_t j = 0; j < egs; ++j) {
 +            tmp[j] = rk[j];
 +        }
 +
 +        for (uint32_t j = 0; j < egs; ++j) {
 +            uint32_t b, s;
 +            b = tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + j];
 +
 +            s = sm4_subword(b);
 +
 +            tmp[j + 4] = tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23));
 +        }
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
 +        }
 +    }
 +
 +    env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
 +}
 +
 +static void do_sm4_round(uint32_t *rk, uint32_t *buf)
 +{
 +    const uint32_t egs = 4;
 +    uint32_t s, b;
 +
 +    for (uint32_t j = egs; j < egs * 2; ++j) {
 +        b = buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4];
 +
 +        s = sm4_subword(b);
 +
 +        buf[j] = buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s, 18) ^
 +                               rol32(s, 24));
 +    }
 +}
 +
 +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
 +{
 +    const uint32_t egs = 4;
 +    uint32_t group_start = env->vstart / egs;
 +    uint32_t group_end = env->vl / egs;
 +    uint32_t esz = sizeof(uint32_t);
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +
 +    for (uint32_t i = group_start; i < group_end; ++i) {
 +        uint32_t vstart = i * egs;
 +        uint32_t vend = (i + 1) * egs;
 +        uint32_t rk[4] = {0};
 +        uint32_t tmp[8] = {0};
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            rk[j - vstart] = *((uint32_t *)vs2 + H4(j));
 +        }
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            tmp[j - vstart] = *((uint32_t *)vd + H4(j));
 +        }
 +
 +        do_sm4_round(rk, tmp);
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
 +        }
 +    }
 +
 +    env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
 +}
 +
 +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
 +{
 +    const uint32_t egs = 4;
 +    uint32_t group_start = env->vstart / egs;
 +    uint32_t group_end = env->vl / egs;
 +    uint32_t esz = sizeof(uint32_t);
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +
 +    for (uint32_t i = group_start; i < group_end; ++i) {
 +        uint32_t vstart = i * egs;
 +        uint32_t vend = (i + 1) * egs;
 +        uint32_t rk[4] = {0};
 +        uint32_t tmp[8] = {0};
 +
 +        for (uint32_t j = 0; j < egs; ++j) {
 +            rk[j] = *((uint32_t *)vs2 + H4(j));
 +        }
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            tmp[j - vstart] = *((uint32_t *)vd + H4(j));
 +        }
 +
 +        do_sm4_round(rk, tmp);
 +
 +        for (uint32_t j = vstart; j < vend; ++j) {
 +            *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
 +        }
 +    }
 +
 +    env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
 +}
 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a)
  }
  GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS)
 +
 +/*
-+ * The HS-mode is allowed to configure priority only for the
++ * Zvksed
 + * following VS-mode local interrupts:
 + *
 + * 0  (Reserved interrupt, reads as zero)
 + * 1  Supervisor software interrupt
 + * 4  (Reserved interrupt, reads as zero)
 + * 5  Supervisor timer interrupt
 + * 8  (Reserved interrupt, reads as zero)
 + * 13 (Reserved interrupt)
 + * 14 "
 + * 15 "
 + * 16 "
 + * 18 Debug/trace interrupt
 + * 20 (Reserved interrupt)
 + * 22 "
 + * 24 "
 + * 26 "
 + * 28 "
 + * 30 (Reserved for standard reporting of bus or system errors)
 + */
 +
-+static const int hviprio_index2irq[] = {
++#define ZVKSED_EGS 4
-+    0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
++
-+static const int hviprio_index2rdzero[] = {
++static bool zvksed_check(DisasContext *s)
-+    1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
++{
-+
++    int egw_bytes = ZVKSED_EGS << s->sew;
-+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
++    return s->cfg_ptr->ext_zvksed == true &&
-+{
++           require_rvv(s) &&
-+    if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
++           vext_check_isa_ill(s) &&
-+        return -EINVAL;
++           MAXSZ(s) >= egw_bytes &&
-+    }
++           s->sew == MO_32;
-+
++}
-+    if (out_irq) {
++
-+        *out_irq = hviprio_index2irq[index];
++static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a)
-+    }
++{
-+
++    return zvksed_check(s) &&
-+    if (out_rdzero) {
++           require_align(a->rd, s->lmul) &&
-+        *out_rdzero = hviprio_index2rdzero[index];
++           require_align(a->rs2, s->lmul);
-+    }
++}
 +
-+    return 0;
++GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS)
-+}
++
-+
++static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a)
-+/*
++{
-+ * Default priorities of local interrupts are defined in the
++    return zvksed_check(s) &&
-+ * RISC-V Advanced Interrupt Architecture specification.
++           require_align(a->rd, s->lmul) &&
-+ *
++           require_align(a->rs2, s->lmul);
-+ * ----------------------------------------------------------------
++}
-+ *  Default  |
++
-+ *  Priority | Major Interrupt Numbers
++GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check, ZVKSED_EGS)
-+ * ----------------------------------------------------------------
++
-+ *  Highest  | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c),
++static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a)
-+ *           | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38),
++{
-+ *           | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34),
++    return zvksed_check(s) &&
-+ *           | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30)
++           !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
-+ *           |
++           require_align(a->rd, s->lmul);
-+ *           | 11 (0b),  3 (03),  7 (07)
++}
-+ *           |  9 (09),  1 (01),  5 (05)
++
-+ *           | 12 (0c)
++GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check, ZVKSED_EGS)
 + *           | 10 (0a),  2 (02),  6 (06)
 + *           |
 + *           | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c),
 + *           | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28),
 + *           | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24),
 + *  Lowest   | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20)
 + * ----------------------------------------------------------------
 + */
 +static const uint8_t default_iprio[64] = {
 + [63] = IPRIO_DEFAULT_UPPER,
 + [62] = IPRIO_DEFAULT_UPPER + 1,
 + [31] = IPRIO_DEFAULT_UPPER + 2,
 + [30] = IPRIO_DEFAULT_UPPER + 3,
 + [61] = IPRIO_DEFAULT_UPPER + 4,
 + [60] = IPRIO_DEFAULT_UPPER + 5,
 +
 + [59] = IPRIO_DEFAULT_UPPER + 6,
 + [58] = IPRIO_DEFAULT_UPPER + 7,
 + [29] = IPRIO_DEFAULT_UPPER + 8,
 + [28] = IPRIO_DEFAULT_UPPER + 9,
 + [57] = IPRIO_DEFAULT_UPPER + 10,
 + [56] = IPRIO_DEFAULT_UPPER + 11,
 +
 + [55] = IPRIO_DEFAULT_UPPER + 12,
 + [54] = IPRIO_DEFAULT_UPPER + 13,
 + [27] = IPRIO_DEFAULT_UPPER + 14,
 + [26] = IPRIO_DEFAULT_UPPER + 15,
 + [53] = IPRIO_DEFAULT_UPPER + 16,
 + [52] = IPRIO_DEFAULT_UPPER + 17,
 +
 + [51] = IPRIO_DEFAULT_UPPER + 18,
 + [50] = IPRIO_DEFAULT_UPPER + 19,
 + [25] = IPRIO_DEFAULT_UPPER + 20,
 + [24] = IPRIO_DEFAULT_UPPER + 21,
 + [49] = IPRIO_DEFAULT_UPPER + 22,
 + [48] = IPRIO_DEFAULT_UPPER + 23,
 +
 + [11] = IPRIO_DEFAULT_M,
 + [3]  = IPRIO_DEFAULT_M + 1,
 + [7]  = IPRIO_DEFAULT_M + 2,
 +
 + [9]  = IPRIO_DEFAULT_S,
 + [1]  = IPRIO_DEFAULT_S + 1,
 + [5]  = IPRIO_DEFAULT_S + 2,
 +
 + [12] = IPRIO_DEFAULT_SGEXT,
 +
 + [10] = IPRIO_DEFAULT_VS,
 + [2]  = IPRIO_DEFAULT_VS + 1,
 + [6]  = IPRIO_DEFAULT_VS + 2,
 +
 + [47] = IPRIO_DEFAULT_LOWER,
 + [46] = IPRIO_DEFAULT_LOWER + 1,
 + [23] = IPRIO_DEFAULT_LOWER + 2,
 + [22] = IPRIO_DEFAULT_LOWER + 3,
 + [45] = IPRIO_DEFAULT_LOWER + 4,
 + [44] = IPRIO_DEFAULT_LOWER + 5,
 +
 + [43] = IPRIO_DEFAULT_LOWER + 6,
 + [42] = IPRIO_DEFAULT_LOWER + 7,
 + [21] = IPRIO_DEFAULT_LOWER + 8,
 + [20] = IPRIO_DEFAULT_LOWER + 9,
 + [41] = IPRIO_DEFAULT_LOWER + 10,
 + [40] = IPRIO_DEFAULT_LOWER + 11,
 +
 + [39] = IPRIO_DEFAULT_LOWER + 12,
 + [38] = IPRIO_DEFAULT_LOWER + 13,
 + [19] = IPRIO_DEFAULT_LOWER + 14,
 + [18] = IPRIO_DEFAULT_LOWER + 15,
 + [37] = IPRIO_DEFAULT_LOWER + 16,
 + [36] = IPRIO_DEFAULT_LOWER + 17,
 +
 + [35] = IPRIO_DEFAULT_LOWER + 18,
 + [34] = IPRIO_DEFAULT_LOWER + 19,
 + [17] = IPRIO_DEFAULT_LOWER + 20,
 + [16] = IPRIO_DEFAULT_LOWER + 21,
 + [33] = IPRIO_DEFAULT_LOWER + 22,
 + [32] = IPRIO_DEFAULT_LOWER + 23,
 +};
 +
 +uint8_t riscv_cpu_default_priority(int irq)
  {
 -    target_ulong virt_enabled = riscv_cpu_virt_enabled(env);
 +    if (irq < 0 || irq > 63) {
 +        return IPRIO_MMAXIPRIO;
 +    }
 +
 +    return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
 +};
 -    target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
 -    target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
 +static int riscv_cpu_pending_to_irq(CPURISCVState *env,
 +                                    int extirq, unsigned int extirq_def_prio,
 +                                    uint64_t pending, uint8_t *iprio)
 +{
 +    int irq, best_irq = RISCV_EXCP_NONE;
 +    unsigned int prio, best_prio = UINT_MAX;
 -    target_ulong vsgemask =
 -                (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
 -    target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
 +    if (!pending) {
 +        return RISCV_EXCP_NONE;
 +    }
 -    target_ulong pending = (env->mip | vsgein) & env->mie;
 +    irq = ctz64(pending);
 +    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 +        return irq;
 +    }
 -    target_ulong mie    = env->priv < PRV_M ||
 -                          (env->priv == PRV_M && mstatus_mie);
 -    target_ulong sie    = env->priv < PRV_S ||
 -                          (env->priv == PRV_S && mstatus_sie);
 -    target_ulong hsie   = virt_enabled || sie;
 -    target_ulong vsie   = virt_enabled && sie;
 +    pending = pending >> irq;
 +    while (pending) {
 +        prio = iprio[irq];
 +        if (!prio) {
 +            if (irq == extirq) {
 +                prio = extirq_def_prio;
 +            } else {
 +                prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
 +                       1 : IPRIO_MMAXIPRIO;
 +            }
 +        }
 +        if ((pending & 0x1) && (prio <= best_prio)) {
 +            best_irq = irq;
 +            best_prio = prio;
 +        }
 +        irq++;
 +        pending = pending >> 1;
 +    }
 -    target_ulong irqs =
 -            (pending & ~env->mideleg & -mie) |
 -            (pending &  env->mideleg & ~env->hideleg & -hsie) |
 -            (pending &  env->mideleg &  env->hideleg & -vsie);
 +    return best_irq;
 +}
 -    if (irqs) {
 -        return ctz64(irqs); /* since non-zero */
 +static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
 +{
 +    uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
 +    uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
 +
 +    return (env->mip | vsgein) & env->mie;
 +}
 +
 +int riscv_cpu_mirq_pending(CPURISCVState *env)
 +{
 +    uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
 +                    ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
 +
 +    return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
 +                                    irqs, env->miprio);
 +}
 +
 +int riscv_cpu_sirq_pending(CPURISCVState *env)
 +{
 +    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
 +                    ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
 +
 +    return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
 +                                    irqs, env->siprio);
 +}
 +
 +int riscv_cpu_vsirq_pending(CPURISCVState *env)
 +{
 +    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
 +                    (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
 +
 +    return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
 +                                    irqs >> 1, env->hviprio);
 +}
 +
 +static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 +{
 +    int virq;
 +    uint64_t irqs, pending, mie, hsie, vsie;
 +
 +    /* Determine interrupt enable state of all privilege modes */
 +    if (riscv_cpu_virt_enabled(env)) {
 +        mie = 1;
 +        hsie = 1;
 +        vsie = (env->priv < PRV_S) ||
 +               (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
      } else {
 -        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
 +        mie = (env->priv < PRV_M) ||
 +              (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
 +        hsie = (env->priv < PRV_S) ||
 +               (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
 +        vsie = 0;
 +    }
 +
 +    /* Determine all pending interrupts */
 +    pending = riscv_cpu_all_pending(env);
 +
 +    /* Check M-mode interrupts */
 +    irqs = pending & ~env->mideleg & -mie;
 +    if (irqs) {
 +        return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
 +                                        irqs, env->miprio);
      }
 +
 +    /* Check HS-mode interrupts */
 +    irqs = pending & env->mideleg & ~env->hideleg & -hsie;
 +    if (irqs) {
 +        return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
 +                                        irqs, env->siprio);
 +    }
 +
 +    /* Check VS-mode interrupts */
 +    irqs = pending & env->mideleg & env->hideleg & -vsie;
 +    if (irqs) {
 +        virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
 +                                        irqs >> 1, env->hviprio);
 +        return (virq <= 0) ? virq : virq + 1;
 +    }
 +
 +    /* Indicate no pending interrupt */
 +    return RISCV_EXCP_NONE;
  }
  bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
          VMSTATE_UINTTL(env.hgeie, RISCVCPU),
          VMSTATE_UINTTL(env.hgeip, RISCVCPU),
          VMSTATE_UINT64(env.htimedelta, RISCVCPU),
 +        VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
          VMSTATE_UINT64(env.vsstatus, RISCVCPU),
          VMSTATE_UINTTL(env.vstvec, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
 +        VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
 +        VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
          VMSTATE_UINTTL(env.pc, RISCVCPU),
          VMSTATE_UINTTL(env.load_res, RISCVCPU),
          VMSTATE_UINTTL(env.load_val, RISCVCPU),
 --
-.34.1
+.41.0

-[PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs
+[PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
-From: Anup Patel <anup.patel@wdc.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-The AIA specification defines IMSIC interface CSRs for easy access
+These are WARL fields - zero out the bits for unavailable counters and
-to the per-HART IMSIC registers without using indirect xiselect and
+special case the TM bit in mcountinhibit which is hardwired to zero.
-xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
+This patch achieves this by modifying the value written so that any use
 of the field will see the correctly masked bits.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Tested by modifying OpenSBI to write max value to these CSRs and upon
-Signed-off-by: Anup Patel <anup@brainfault.org>
+subsequent read the appropriate number of bits for number of PMUs is
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+enabled and the TM bit is zero in mcountinhibit.
-Message-id: 20220204174700.534953-16-anup@brainfault.org
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Atish Patra <atishp@rivosinc.com>
 Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 203 +++++++++++++++++++++++++++++++++++++++++++++
+ target/riscv/csr.c | 11 +++++++++--
-file changed, 203 insertions(+)
+file changed, 9 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
-         return CSR_VSISELECT;
+ {
-     case CSR_SIREG:
+     int cidx;
-         return CSR_VSIREG;
+     PMUCTRState *counter;
-+    case CSR_SSETEIPNUM:
++    RISCVCPU *cpu = env_archcpu(env);
-+        return CSR_VSSETEIPNUM;
-+    case CSR_SCLREIPNUM:
+-    env->mcountinhibit = val;
-+        return CSR_VSCLREIPNUM;
++    /* WARL register - disable unavailable counters; TM bit is always 0 */
-+    case CSR_SSETEIENUM:
++    env->mcountinhibit =
-+        return CSR_VSSETEIENUM;
++        val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR);
-+    case CSR_SCLREIENUM:
-+        return CSR_VSCLREIENUM;
+     /* Check if any other counter is also monitoring cycles/instructions */
-+    case CSR_STOPEI:
+     for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
-+        return CSR_VSTOPEI;
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
-     default:
+ static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
-         return csrno;
+                                        target_ulong val)
-     };
+ {
-@@ -XXX,XX +XXX,XX @@ done:
+-    env->mcounteren = val;
 +    RISCVCPU *cpu = env_archcpu(env);
 +
 +    /* WARL register - disable unavailable counters */
 +    env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
 +                             COUNTEREN_IR);
      return RISCV_EXCP_NONE;
  }
-+static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
-+                            target_ulong new_val, target_ulong wr_mask)
-+{
-+    int ret = -EINVAL;
-+    bool set, pend, virt;
-+    target_ulong priv, isel, vgein, xlen, nval, wmask;
-+
-+    /* Translate CSR number for VS-mode */
-+    csrno = aia_xlate_vs_csrno(env, csrno);
-+
-+    /* Decode register details from CSR number */
-+    virt = set = pend = false;
-+    switch (csrno) {
-+    case CSR_MSETEIPNUM:
-+        priv = PRV_M;
-+        set = true;
-+        pend = true;
-+        break;
-+    case CSR_MCLREIPNUM:
-+        priv = PRV_M;
-+        pend = true;
-+        break;
-+    case CSR_MSETEIENUM:
-+        priv = PRV_M;
-+        set = true;
-+        break;
-+    case CSR_MCLREIENUM:
-+        priv = PRV_M;
-+        break;
-+    case CSR_SSETEIPNUM:
-+        priv = PRV_S;
-+        set = true;
-+        pend = true;
-+        break;
-+    case CSR_SCLREIPNUM:
-+        priv = PRV_S;
-+        pend = true;
-+        break;
-+    case CSR_SSETEIENUM:
-+        priv = PRV_S;
-+        set = true;
-+        break;
-+    case CSR_SCLREIENUM:
-+        priv = PRV_S;
-+        break;
-+    case CSR_VSSETEIPNUM:
-+        priv = PRV_S;
-+        virt = true;
-+        set = true;
-+        pend = true;
-+        break;
-+    case CSR_VSCLREIPNUM:
-+        priv = PRV_S;
-+        virt = true;
-+        pend = true;
-+        break;
-+    case CSR_VSSETEIENUM:
-+        priv = PRV_S;
-+        virt = true;
-+        set = true;
-+        break;
-+    case CSR_VSCLREIENUM:
-+        priv = PRV_S;
-+        virt = true;
-+        break;
-+    default:
-+         goto done;
-+    };
-+
-+    /* IMSIC CSRs only available when machine implements IMSIC. */
-+    if (!env->aia_ireg_rmw_fn[priv]) {
-+        goto done;
-+    }
-+
-+    /* Find the selected guest interrupt file */
-+    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
-+
-+    /* Selected guest interrupt file should be valid */
-+    if (virt && (!vgein || env->geilen < vgein)) {
-+        goto done;
-+    }
-+
-+    /* Set/Clear CSRs always read zero */
-+    if (val) {
-+        *val = 0;
-+    }
-+
-+    if (wr_mask) {
-+        /* Get interrupt number */
-+        new_val &= wr_mask;
-+
-+        /* Find target interrupt pending/enable register */
-+        xlen = riscv_cpu_mxl_bits(env);
-+        isel = (new_val / xlen);
-+        isel *= (xlen / IMSIC_EIPx_BITS);
-+        isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
-+
-+        /* Find the interrupt bit to be set/clear */
-+        wmask = ((target_ulong)1) << (new_val % xlen);
-+        nval = (set) ? wmask : 0;
-+
-+        /* Call machine specific IMSIC register emulation */
-+        ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
-+                                         AIA_MAKE_IREG(isel, priv, virt,
-+                                                       vgein, xlen),
-+                                         NULL, nval, wmask);
-+    } else {
-+        ret = 0;
-+    }
-+
-+done:
-+    if (ret) {
-+        return (riscv_cpu_virt_enabled(env) && virt) ?
-+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
-+    }
-+    return RISCV_EXCP_NONE;
-+}
-+
-+static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
-+                      target_ulong new_val, target_ulong wr_mask)
-+{
-+    bool virt;
-+    int ret = -EINVAL;
-+    target_ulong priv, vgein;
-+
-+    /* Translate CSR number for VS-mode */
-+    csrno = aia_xlate_vs_csrno(env, csrno);
-+
-+    /* Decode register details from CSR number */
-+    virt = false;
-+    switch (csrno) {
-+    case CSR_MTOPEI:
-+        priv = PRV_M;
-+        break;
-+    case CSR_STOPEI:
-+        priv = PRV_S;
-+        break;
-+    case CSR_VSTOPEI:
-+        priv = PRV_S;
-+        virt = true;
-+        break;
-+    default:
-+        goto done;
-+    };
-+
-+    /* IMSIC CSRs only available when machine implements IMSIC. */
-+    if (!env->aia_ireg_rmw_fn[priv]) {
-+        goto done;
-+    }
-+
-+    /* Find the selected guest interrupt file */
-+    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
-+
-+    /* Selected guest interrupt file should be valid */
-+    if (virt && (!vgein || env->geilen < vgein)) {
-+        goto done;
-+    }
-+
-+    /* Call machine specific IMSIC register emulation for TOPEI */
-+    ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
-+                    AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
-+                                  riscv_cpu_mxl_bits(env)),
-+                    val, new_val, wr_mask);
-+
-+done:
-+    if (ret) {
-+        return (riscv_cpu_virt_enabled(env) && virt) ?
-+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
-+    }
-+    return RISCV_EXCP_NONE;
-+}
-+
- static RISCVException read_mtvec(CPURISCVState *env, int csrno,
-                                  target_ulong *val)
- {
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     /* Machine-Level Interrupts (AIA) */
-     [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
-+    /* Machine-Level IMSIC Interface (AIA) */
-+    [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_MTOPEI]     = { "mtopei",     aia_any, NULL, NULL, rmw_xtopei },
-+
-     /* Virtual Interrupts for Supervisor Level (AIA) */
-     [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
-     [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     /* Supervisor-Level Interrupts (AIA) */
-     [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
-+    /* Supervisor-Level IMSIC Interface (AIA) */
-+    [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_STOPEI]     = { "stopei",     aia_smode, NULL, NULL, rmw_xtopei },
-+
-     /* Supervisor-Level High-Half CSRs (AIA) */
-     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
-     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     /* VS-Level Interrupts (H-extension with AIA) */
-     [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
-+    /* VS-Level IMSIC Interface (H-extension with AIA) */
-+    [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
-+    [CSR_VSTOPEI]     = { "vstopei",     aia_hmode, NULL, NULL, rmw_xtopei },
-+
-     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
-     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
-     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
 --
-.34.1
+.41.0

-[PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation
+[PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS
-From: Anup Patel <anup.patel@wdc.com>
+From: Jason Chien <jason.chien@sifive.com>
-The machine or device emulation should be able to force set certain
+RVA23 Profiles states:
-CPU features because:
+The RVA23 profiles are intended to be used for 64-bit application
-) We can have certain CPU features which are in-general optional
+processors that will run rich OS stacks from standard binary OS
-   but implemented by RISC-V CPUs on the machine.
+distributions and with a substantial number of third-party binary user
-) We can have devices which require a certain CPU feature. For example,
+applications that will be supported over a considerable length of time
-   AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
+in the field.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+The chapter 4 of the unprivileged spec introduces the Zihintntl extension
-Signed-off-by: Anup Patel <anup@brainfault.org>
+and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+purpose is to enable application and operating system portability across
 different implementations. Thus the DTS should contain the Zihintntl ISA
 string in order to pass to software.
 The unprivileged spec states:
 Like any HINTs, these instructions may be freely ignored. Hence, although
 they are described in terms of cache-based memory hierarchies, they do not
 mandate the provision of caches.
 These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2,
 which QEMU already supports, and QEMU does not emulate cache. Therefore
 these instructions can be considered as a no-op, and we only need to add
 a new property for the Zihintntl extension.
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Message-id: 20220204174700.534953-6-anup@brainfault.org
+Message-ID: <20230726074049.19505-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h |  5 +++++
+ target/riscv/cpu_cfg.h | 1 +
- target/riscv/cpu.c | 11 +++--------
+ target/riscv/cpu.c     | 2 ++
-files changed, 8 insertions(+), 8 deletions(-)
+files changed, 3 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     return env->features & (1ULL << feature);
+     bool ext_icbom;
- }
+     bool ext_icboz;
+     bool ext_zicond;
-+static inline void riscv_set_feature(CPURISCVState *env, int feature)
++    bool ext_zihintntl;
-+{
+     bool ext_zihintpause;
-+    env->features |= (1ULL << feature);
+     bool ext_smstateen;
-+}
+     bool ext_sstc;
 +
  #include "cpu_user.h"
  extern const char * const riscv_int_regnames[];
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     env->vext_ver = vext_ver;
+     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
- }
+     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
+     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
--static void set_feature(CPURISCVState *env, int feature)
++    ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
--{
+     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
--    env->features |= (1ULL << feature);
+     ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
--}
+     ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
--
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
- static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
+     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
- {
+     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
- #ifndef CONFIG_USER_ONLY
+     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
++    DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
-     }
+     DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
+     DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
-     if (cpu->cfg.mmu) {
+     DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
 -        set_feature(env, RISCV_FEATURE_MMU);
 +        riscv_set_feature(env, RISCV_FEATURE_MMU);
      }
      if (cpu->cfg.pmp) {
 -        set_feature(env, RISCV_FEATURE_PMP);
 +        riscv_set_feature(env, RISCV_FEATURE_PMP);
          /*
           * Enhanced PMP should only be available
           * on harts with PMP support
           */
          if (cpu->cfg.epmp) {
 -            set_feature(env, RISCV_FEATURE_EPMP);
 +            riscv_set_feature(env, RISCV_FEATURE_EPMP);
          }
      }
 --
-.34.1
+.41.0

-[PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
+[PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
+Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension.
 However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s
 helper function.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Fixes: a47842d ("riscv: Add support for the Zfa extension")
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
+Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 3 +++
+ target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
-file changed, 3 insertions(+)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/insn_trans/trans_rvzfa.c.inc
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/insn_trans/trans_rvzfa.c.inc
-@@ -XXX,XX +XXX,XX @@ restart:
+@@ -XXX,XX +XXX,XX @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
-             return TRANSLATE_FAIL;
+     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
-         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
+     TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
-             /* Inner PTE, continue walking */
-+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+-    gen_helper_fltq_s(dest, cpu_env, src1, src2);
-+                return TRANSLATE_FAIL;
++    gen_helper_fleq_d(dest, cpu_env, src1, src2);
-+            }
+     gen_set_gpr(ctx, a->rd, dest);
-             base = ppn << PGSHIFT;
+     return true;
-         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
+ }
-             /* Reserved leaf PTE flags: PTE_W */
+@@ -XXX,XX +XXX,XX @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
      TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
      TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
 -    gen_helper_fltq_s(dest, cpu_env, src1, src2);
 +    gen_helper_fltq_d(dest, cpu_env, src1, src2);
      gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
 --
-.34.1
+.41.0

-[PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
+[PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Jason Chien <jason.chien@sifive.com>
-The XVentanaCondOps extension is supported by VRULL on behalf of the
+When writing the upper mtime, we should keep the original lower mtime
-Ventana Micro.  Add myself as a point-of-contact.
+whose value is given by cpu_riscv_read_rtc() instead of
 cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220202005249.3566542-8-philipp.tomsich@vrull.eu>
+Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- MAINTAINERS | 7 +++++++
+ hw/intc/riscv_aclint.c | 5 +++--
-file changed, 7 insertions(+)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/intc/riscv_aclint.c
-+++ b/MAINTAINERS
++++ b/hw/intc/riscv_aclint.c
-@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/
+@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
- F: linux-user/host/riscv32/
+         return;
- F: linux-user/host/riscv64/
+     } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
+         uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
-+RISC-V XVentanaCondOps extension
++        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
-+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
-+L: qemu-riscv@nongnu.org
+         if (addr == mtimer->time_base) {
-+S: Supported
+             if (size == 4) {
-+F: target/riscv/XVentanaCondOps.decode
+                 /* time_lo for RV32/RV64 */
-+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+-                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
-+
++                mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
- RENESAS RX CPUs
+             } else {
- R: Yoshinori Sato <ysato@users.sourceforge.jp>
+                 /* time for RV64 */
- S: Orphan
+                 mtimer->time_delta = value - rtc_r;
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
          } else {
              if (size == 4) {
                  /* time_hi for RV32/RV64 */
 -                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
 +                mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
              } else {
                  qemu_log_mask(LOG_GUEST_ERROR,
                                "aclint-mtimer: invalid time_hi write: %08x",
 --
-.34.1
+.41.0

-[PULL 33/40] docs/system: riscv: Document AIA options for virt machine
+[PULL v2 27/45] hw/intc: Make rtc variable names consistent
-From: Anup Patel <anup.patel@wdc.com>
+From: Jason Chien <jason.chien@sifive.com>
-We have two new machine options "aia" and "aia-guests" available
+The variables whose values are given by cpu_riscv_read_rtc() should be named
-for the RISC-V virt machine so let's document these options.
+"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
 should be named "rtc_r".
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Signed-off-by: Anup Patel <anup@brainfault.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-ID: <20230728082502.26439-2-jason.chien@sifive.com>
 Message-id: 20220204174700.534953-23-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/virt.rst | 16 ++++++++++++++++
+ hw/intc/riscv_aclint.c | 6 +++---
-file changed, 16 insertions(+)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
+diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/virt.rst
+--- a/hw/intc/riscv_aclint.c
-+++ b/docs/system/riscv/virt.rst
++++ b/hw/intc/riscv_aclint.c
-@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
+@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
-   When this option is "on", ACLINT devices will be emulated instead of
+     uint64_t next;
-   SiFive CLINT. When not specified, this option is assumed to be "off".
+     uint64_t diff;
-+- aia=[none|aplic|aplic-imsic]
+-    uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
-+
++    uint64_t rtc = cpu_riscv_read_rtc(mtimer);
-+  This option allows selecting interrupt controller defined by the AIA
-+  (advanced interrupt architecture) specification. The "aia=aplic" selects
+     /* Compute the relative hartid w.r.t the socket */
-+  APLIC (advanced platform level interrupt controller) to handle wired
+     hartid = hartid - mtimer->hartid_base;
-+  interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
-+  message signaled interrupt controller) to handle both wired interrupts and
+     mtimer->timecmp[hartid] = value;
-+  MSIs. When not specified, this option is assumed to be "none" which selects
+-    if (mtimer->timecmp[hartid] <= rtc_r) {
-+  SiFive PLIC to handle wired interrupts.
++    if (mtimer->timecmp[hartid] <= rtc) {
-+
+         /*
-+- aia-guests=nnn
+          * If we're setting an MTIMECMP value in the "past",
-+
+          * immediately raise the timer interrupt
-+  The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
-+  having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
-+  the default number of per-HART VS-level AIA IMSIC pages is 0.
+     /* otherwise, set up the future timer interrupt */
-+
+     qemu_irq_lower(mtimer->timer_irqs[hartid]);
- Running Linux kernel
+-    diff = mtimer->timecmp[hartid] - rtc_r;
- --------------------
++    diff = mtimer->timecmp[hartid] - rtc;
      /* back to ns (note args switched in muldiv64) */
      uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
 --
-.34.1
+.41.0

-[PULL 07/40] target/riscv: access cfg structure through DisasContext
+[PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-The Zb[abcs] support code still uses the RISCV_CPU macros to access
+We should not use types dependend on host arch for target_ucontext.
-the configuration information (i.e., check whether an extension is
+This bug is found when run rv32 applications.
 available/enabled).  Now that we provide this information directly
 from DisasContext, we can access this directly via the cfg_ptr field.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
+ linux-user/riscv/signal.c | 4 ++--
-file changed, 4 insertions(+), 4 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/linux-user/riscv/signal.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/linux-user/riscv/signal.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct target_sigcontext {
-  */
+ }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */
- #define REQUIRE_ZBA(ctx) do {                    \
+ struct target_ucontext {
--    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
+-    unsigned long uc_flags;
-+    if (ctx->cfg_ptr->ext_zba) {                 \
+-    struct target_ucontext *uc_link;
-         return false;                            \
++    abi_ulong uc_flags;
-     }                                            \
++    abi_ptr uc_link;
- } while (0)
+     target_stack_t uc_stack;
+     target_sigset_t uc_sigmask;
- #define REQUIRE_ZBB(ctx) do {                    \
+     uint8_t   __unused[1024 / 8 - sizeof(target_sigset_t)];
 -    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
 +    if (ctx->cfg_ptr->ext_zbb) {                 \
          return false;                            \
      }                                            \
  } while (0)
  #define REQUIRE_ZBC(ctx) do {                    \
 -    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
 +    if (ctx->cfg_ptr->ext_zbc) {                 \
          return false;                            \
      }                                            \
  } while (0)
  #define REQUIRE_ZBS(ctx) do {                    \
 -    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
 +    if (ctx->cfg_ptr->ext_zbs) {                 \
          return false;                            \
      }                                            \
  } while (0)
 --
-.34.1
+.41.0

-[PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
+[PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled
-From: Anup Patel <anup.patel@wdc.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-We extend virt machine to emulate both AIA IMSIC and AIA APLIC
+In this patch, we create the APLIC and IMSIC FDT helper functions and
-devices only when "aia=aplic-imsic" parameter is passed along
+remove M mode AIA devices when using KVM acceleration.
 with machine name in the QEMU command-line. The AIA IMSIC is
 only a per-HART MSI controller so we use AIA APLIC in MSI-mode
 to forward all wired interrupts as MSIs to the AIA IMSIC.
-We also provide "aia-guests=<xyz>" parameter which can be used
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-to specify number of VS-level AIA IMSIC Guests MMIO pages for
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
-each HART.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com>
 Signed-off-by: Anup Patel <anup@brainfault.org>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20220204174700.534953-22-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  17 +-
+ hw/riscv/virt.c | 290 +++++++++++++++++++++++-------------------------
- hw/riscv/virt.c         | 440 ++++++++++++++++++++++++++++++++--------
+file changed, 137 insertions(+), 153 deletions(-)
  hw/riscv/Kconfig        |   1 +
 files changed, 374 insertions(+), 84 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/block/flash.h"
- #include "qom/object.h"
--#define VIRT_CPUS_MAX 32
--#define VIRT_SOCKETS_MAX 8
-+#define VIRT_CPUS_MAX_BITS             3
-+#define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
-+#define VIRT_SOCKETS_MAX_BITS          2
-+#define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
- #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
- typedef struct RISCVVirtState RISCVVirtState;
-@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
- typedef enum RISCVVirtAIAType {
-     VIRT_AIA_TYPE_NONE = 0,
-     VIRT_AIA_TYPE_APLIC,
-+    VIRT_AIA_TYPE_APLIC_IMSIC,
- } RISCVVirtAIAType;
- struct RISCVVirtState {
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
-     int fdt_size;
-     bool have_aclint;
-     RISCVVirtAIAType aia_type;
-+    int aia_guests;
- };
- enum {
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_UART0,
-     VIRT_VIRTIO,
-     VIRT_FW_CFG,
-+    VIRT_IMSIC_M,
-+    VIRT_IMSIC_S,
-     VIRT_FLASH,
-     VIRT_DRAM,
-     VIRT_PCIE_MMIO,
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
- };
--#define VIRT_IRQCHIP_NUM_SOURCES 127
-+#define VIRT_IRQCHIP_IPI_MSI 1
-+#define VIRT_IRQCHIP_NUM_MSIS 255
-+#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
- #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
-+#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
-+#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
- #define VIRT_PLIC_PRIORITY_BASE 0x04
- #define VIRT_PLIC_PENDING_BASE 0x1000
-@@ -XXX,XX +XXX,XX @@ enum {
- #define FDT_PCI_INT_CELLS     1
- #define FDT_PLIC_INT_CELLS    1
- #define FDT_APLIC_INT_CELLS   2
-+#define FDT_IMSIC_INT_CELLS   0
- #define FDT_MAX_INT_CELLS     2
- #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
-+ FDT_MAX_INT_CELLS)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint32_t imsic_num_bits(uint32_t count)
- #include "hw/riscv/numa.h"
+     return ret;
- #include "hw/intc/riscv_aclint.h"
+ }
- #include "hw/intc/riscv_aplic.h"
-+#include "hw/intc/riscv_imsic.h"
+-static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
- #include "hw/intc/sifive_plic.h"
+-                             uint32_t *phandle, uint32_t *intc_phandles,
- #include "hw/misc/sifive_test.h"
+-                             uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
- #include "chardev/char.h"
++static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
-@@ -XXX,XX +XXX,XX @@
++                                 uint32_t *intc_phandles, uint32_t msi_phandle,
- #include "hw/pci-host/gpex.h"
++                                 bool m_mode, uint32_t imsic_guest_bits)
  #include "hw/display/ramfb.h"
 +#define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
 +#if VIRT_IMSIC_GROUP_MAX_SIZE < \
 +    IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
 +#error "Can't accomodate single IMSIC group in address space"
 +#endif
 +
 +#define VIRT_IMSIC_MAX_SIZE            (VIRT_SOCKETS_MAX * \
 +                                        VIRT_IMSIC_GROUP_MAX_SIZE)
 +#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
 +#error "Can't accomodate all IMSIC groups in address space"
 +#endif
 +
  static const MemMapEntry virt_memmap[] = {
      [VIRT_DEBUG] =       {        0x0,         0x100 },
      [VIRT_MROM] =        {     0x1000,        0xf000 },
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
      [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
 +    [VIRT_IMSIC_M] =     { 0x24000000, VIRT_IMSIC_MAX_SIZE },
 +    [VIRT_IMSIC_S] =     { 0x28000000, VIRT_IMSIC_MAX_SIZE },
      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
      [VIRT_DRAM] =        { 0x80000000,           0x0 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
  {
-     int cpu;
+     int cpu, socket;
-     char *name;
+     char *imsic_name;
--    unsigned long addr;
+     MachineState *ms = MACHINE(s);
-+    unsigned long addr, size;
+     int socket_count = riscv_socket_count(ms);
-     uint32_t aclint_cells_size;
+-    uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
-     uint32_t *aclint_mswi_cells;
++    uint32_t imsic_max_hart_per_socket;
-     uint32_t *aclint_sswi_cells;
+     uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
-     }
+-    *msi_m_phandle = (*phandle)++;
-     aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
+-    *msi_s_phandle = (*phandle)++;
+     imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
--    addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+     imsic_regs = g_new0(uint32_t, socket_count * 4);
--    name = g_strdup_printf("/soc/mswi@%lx", addr);
--    qemu_fdt_add_subnode(mc->fdt, name);
+-    /* M-level IMSIC node */
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
+     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+         imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
--        0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+-        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
--    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
++        imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
--        aclint_mswi_cells, aclint_cells_size);
+     }
--    qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+-    imsic_max_hart_per_socket = 0;
--    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+-    for (socket = 0; socket < socket_count; socket++) {
--    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+-        imsic_addr = memmap[VIRT_IMSIC_M].base +
--    g_free(name);
+-                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
-+    if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+-        imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
-+        addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+-        imsic_regs[socket * 4 + 0] = 0;
-+        name = g_strdup_printf("/soc/mswi@%lx", addr);
+-        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
-+        qemu_fdt_add_subnode(mc->fdt, name);
+-        imsic_regs[socket * 4 + 2] = 0;
-+        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+-        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
-+            "riscv,aclint-mswi");
+-        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
-+        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+-            imsic_max_hart_per_socket = s->soc[socket].num_harts;
-+            0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+-        }
-+        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+-    }
-+            aclint_mswi_cells, aclint_cells_size);
+-    imsic_name = g_strdup_printf("/soc/imsics@%lx",
-+        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+-        (unsigned long)memmap[VIRT_IMSIC_M].base);
-+        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+-    qemu_fdt_add_subnode(ms->fdt, imsic_name);
-+        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+-    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
-+        g_free(name);
+-        "riscv,imsics");
-+    }
+-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
+-        FDT_IMSIC_INT_CELLS);
--    addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
--        (memmap[VIRT_CLINT].size * socket);
+-        NULL, 0);
-+    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
-+        addr = memmap[VIRT_CLINT].base +
+-        NULL, 0);
-+               (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
-+        size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
+-        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
-+    } else {
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
-+        addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
+-        socket_count * sizeof(uint32_t) * 4);
-+            (memmap[VIRT_CLINT].size * socket);
+-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
-+        size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
+-        VIRT_IRQCHIP_NUM_MSIS);
-+    }
+-    if (socket_count > 1) {
-     name = g_strdup_printf("/soc/mtimer@%lx", addr);
+-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
-     qemu_fdt_add_subnode(mc->fdt, name);
+-            imsic_num_bits(imsic_max_hart_per_socket));
-     qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
-         "riscv,aclint-mtimer");
+-            imsic_num_bits(socket_count));
-     qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
-x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
+-            IMSIC_MMIO_GROUP_MIN_SHIFT);
--        0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE -
+-    }
--             RISCV_ACLINT_DEFAULT_MTIME,
+-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
-+        0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
+-
-x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
+-    g_free(imsic_name);
-x0, RISCV_ACLINT_DEFAULT_MTIME);
-     qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+-    /* S-level IMSIC node */
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
+-    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
-     riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+-        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-     g_free(name);
+-        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+-    }
--    addr = memmap[VIRT_ACLINT_SSWI].base +
+-    imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
--        (memmap[VIRT_ACLINT_SSWI].size * socket);
+     imsic_max_hart_per_socket = 0;
--    name = g_strdup_printf("/soc/sswi@%lx", addr);
+     for (socket = 0; socket < socket_count; socket++) {
--    qemu_fdt_add_subnode(mc->fdt, name);
+-        imsic_addr = memmap[VIRT_IMSIC_S].base +
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
+-                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
++        imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
--        0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
+         imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
--    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+                      s->soc[socket].num_harts;
--        aclint_sswi_cells, aclint_cells_size);
+         imsic_regs[socket * 4 + 0] = 0;
--    qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
--    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+             imsic_max_hart_per_socket = s->soc[socket].num_harts;
--    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+         }
--    g_free(name);
+     }
-+    if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+-    imsic_name = g_strdup_printf("/soc/imsics@%lx",
-+        addr = memmap[VIRT_ACLINT_SSWI].base +
+-        (unsigned long)memmap[VIRT_IMSIC_S].base);
-+            (memmap[VIRT_ACLINT_SSWI].size * socket);
++
-+        name = g_strdup_printf("/soc/sswi@%lx", addr);
++    imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr);
-+        qemu_fdt_add_subnode(mc->fdt, name);
+     qemu_fdt_add_subnode(ms->fdt, imsic_name);
-+        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+-    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
-+            "riscv,aclint-sswi");
+-        "riscv,imsics");
-+        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
++    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics");
-+            0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
+     qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
-+        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+-        FDT_IMSIC_INT_CELLS);
-+            aclint_sswi_cells, aclint_cells_size);
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
-+        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+-        NULL, 0);
-+        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+-    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
-+        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+-        NULL, 0);
-+        g_free(name);
++                          FDT_IMSIC_INT_CELLS);
-+    }
++    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
++    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
-     g_free(aclint_mswi_cells);
+     qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
-     g_free(aclint_mtimer_cells);
+-        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
++                     imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
-     g_free(plic_cells);
+     qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
 -        socket_count * sizeof(uint32_t) * 4);
 +                     socket_count * sizeof(uint32_t) * 4);
      qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
 -        VIRT_IRQCHIP_NUM_MSIS);
 +                     VIRT_IRQCHIP_NUM_MSIS);
 +
      if (imsic_guest_bits) {
          qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
 -            imsic_guest_bits);
 +                              imsic_guest_bits);
      }
 +
      if (socket_count > 1) {
          qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
 -            imsic_num_bits(imsic_max_hart_per_socket));
 +                              imsic_num_bits(imsic_max_hart_per_socket));
          qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
 -            imsic_num_bits(socket_count));
 +                              imsic_num_bits(socket_count));
          qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
 -            IMSIC_MMIO_GROUP_MIN_SHIFT);
 +                              IMSIC_MMIO_GROUP_MIN_SHIFT);
      }
 -    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
 -    g_free(imsic_name);
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
 +    g_free(imsic_name);
      g_free(imsic_regs);
      g_free(imsic_cells);
  }
--static void create_fdt_socket_aia(RISCVVirtState *s,
+-static void create_fdt_socket_aplic(RISCVVirtState *s,
--                                  const MemMapEntry *memmap, int socket,
+-                                    const MemMapEntry *memmap, int socket,
--                                  uint32_t *phandle, uint32_t *intc_phandles,
+-                                    uint32_t msi_m_phandle,
--                                  uint32_t *aplic_phandles)
+-                                    uint32_t msi_s_phandle,
-+static uint32_t imsic_num_bits(uint32_t count)
+-                                    uint32_t *phandle,
-+{
+-                                    uint32_t *intc_phandles,
-+    uint32_t ret = 0;
+-                                    uint32_t *aplic_phandles)
 +
 +    while (BIT(ret) < count) {
 +        ret++;
 +    }
 +
 +    return ret;
 +}
 +
 +static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
 +                             uint32_t *phandle, uint32_t *intc_phandles,
 +                             uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
 +{
-+    int cpu, socket;
-+    char *imsic_name;
-+    MachineState *mc = MACHINE(s);
-+    uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
-+    uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
-+
 +    *msi_m_phandle = (*phandle)++;
 +    *msi_s_phandle = (*phandle)++;
-+    imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
++
-+    imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
++    if (!kvm_enabled()) {
-+
++        /* M-level IMSIC node */
-+    /* M-level IMSIC node */
++        create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles,
-+    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
++                             *msi_m_phandle, true, 0);
 +        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
 +    }
-+    imsic_max_hart_per_socket = 0;
++
-+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
++    /* S-level IMSIC node */
-+        imsic_addr = memmap[VIRT_IMSIC_M].base +
++    create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles,
-+                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
++                         *msi_s_phandle, false,
-+        imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
++                         imsic_num_bits(s->aia_guests + 1));
-+        imsic_regs[socket * 4 + 0] = 0;
++
-+        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
++}
-+        imsic_regs[socket * 4 + 2] = 0;
++
-+        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
++static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
-+        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
++                                 unsigned long aplic_addr, uint32_t aplic_size,
-+            imsic_max_hart_per_socket = s->soc[socket].num_harts;
++                                 uint32_t msi_phandle,
-+        }
++                                 uint32_t *intc_phandles,
 +                                 uint32_t aplic_phandle,
 +                                 uint32_t aplic_child_phandle,
 +                                 bool m_mode)
  {
      int cpu;
      char *aplic_name;
      uint32_t *aplic_cells;
 -    unsigned long aplic_addr;
      MachineState *ms = MACHINE(s);
 -    uint32_t aplic_m_phandle, aplic_s_phandle;
 -    aplic_m_phandle = (*phandle)++;
 -    aplic_s_phandle = (*phandle)++;
      aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
 -    /* M-level APLIC node */
      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
          aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 -        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
 +        aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
      }
 -    aplic_addr = memmap[VIRT_APLIC_M].base +
 -                 (memmap[VIRT_APLIC_M].size * socket);
 +
      aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
      qemu_fdt_add_subnode(ms->fdt, aplic_name);
      qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
      qemu_fdt_setprop_cell(ms->fdt, aplic_name,
 -        "#interrupt-cells", FDT_APLIC_INT_CELLS);
 +                          "#interrupt-cells", FDT_APLIC_INT_CELLS);
      qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
 +
      if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
          qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
 -            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
 +                         aplic_cells,
 +                         s->soc[socket].num_harts * sizeof(uint32_t) * 2);
      } else {
 -        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
 -            msi_m_phandle);
 +        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
      }
 +
      qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
 -        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
 +                           0x0, aplic_addr, 0x0, aplic_size);
      qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
 -        VIRT_IRQCHIP_NUM_SOURCES);
 -    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
 -        aplic_s_phandle);
 -    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
 -        aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
 +                          VIRT_IRQCHIP_NUM_SOURCES);
 +
 +    if (aplic_child_phandle) {
 +        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
 +                              aplic_child_phandle);
 +        qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
 +                               aplic_child_phandle, 0x1,
 +                               VIRT_IRQCHIP_NUM_SOURCES);
 +    }
-+    imsic_name = g_strdup_printf("/soc/imsics@%lx",
++
-+        memmap[VIRT_IMSIC_M].base);
+     riscv_socket_fdt_write_id(ms, aplic_name, socket);
-+    qemu_fdt_add_subnode(mc->fdt, imsic_name);
+-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
-+    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
++    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
-+        "riscv,imsics");
++
-+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+     g_free(aplic_name);
-+        FDT_IMSIC_INT_CELLS);
++    g_free(aplic_cells);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
 +        NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
 +        NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
 +        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
 +        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
 +    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
 +        VIRT_IRQCHIP_NUM_MSIS);
 +    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
 +        VIRT_IRQCHIP_IPI_MSI);
 +    if (riscv_socket_count(mc) > 1) {
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
 +            imsic_num_bits(imsic_max_hart_per_socket));
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
 +            imsic_num_bits(riscv_socket_count(mc)));
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
 +            IMSIC_MMIO_GROUP_MIN_SHIFT);
 +    }
 +    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
 +    g_free(imsic_name);
 +
 +    /* S-level IMSIC node */
 +    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
 +        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
 +    }
 +    imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
 +    imsic_max_hart_per_socket = 0;
 +    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
 +        imsic_addr = memmap[VIRT_IMSIC_S].base +
 +                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
 +        imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
 +                     s->soc[socket].num_harts;
 +        imsic_regs[socket * 4 + 0] = 0;
 +        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
 +        imsic_regs[socket * 4 + 2] = 0;
 +        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
 +        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
 +            imsic_max_hart_per_socket = s->soc[socket].num_harts;
 +        }
 +    }
 +    imsic_name = g_strdup_printf("/soc/imsics@%lx",
 +        memmap[VIRT_IMSIC_S].base);
 +    qemu_fdt_add_subnode(mc->fdt, imsic_name);
 +    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
 +        "riscv,imsics");
 +    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
 +        FDT_IMSIC_INT_CELLS);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
 +        NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
 +        NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
 +        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
 +        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
 +    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
 +        VIRT_IRQCHIP_NUM_MSIS);
 +    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
 +        VIRT_IRQCHIP_IPI_MSI);
 +    if (imsic_guest_bits) {
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
 +            imsic_guest_bits);
 +    }
 +    if (riscv_socket_count(mc) > 1) {
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
 +            imsic_num_bits(imsic_max_hart_per_socket));
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
 +            imsic_num_bits(riscv_socket_count(mc)));
 +        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
 +            IMSIC_MMIO_GROUP_MIN_SHIFT);
 +    }
 +    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
 +    g_free(imsic_name);
 +
 +    g_free(imsic_regs);
 +    g_free(imsic_cells);
 +}
-+
 -    /* S-level APLIC node */
 -    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
 -        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 -        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
 +static void create_fdt_socket_aplic(RISCVVirtState *s,
 +                                    const MemMapEntry *memmap, int socket,
 +                                    uint32_t msi_m_phandle,
 +                                    uint32_t msi_s_phandle,
 +                                    uint32_t *phandle,
 +                                    uint32_t *intc_phandles,
 +                                    uint32_t *aplic_phandles)
- {
++{
-     int cpu;
++    char *aplic_name;
-     char *aplic_name;
++    unsigned long aplic_addr;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aia(RISCVVirtState *s,
++    MachineState *ms = MACHINE(s);
-     qemu_fdt_setprop_cell(mc->fdt, aplic_name,
++    uint32_t aplic_m_phandle, aplic_s_phandle;
-         "#interrupt-cells", FDT_APLIC_INT_CELLS);
++
-     qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
++    aplic_m_phandle = (*phandle)++;
--    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
++    aplic_s_phandle = (*phandle)++;
--        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
++
-+    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
++    if (!kvm_enabled()) {
-+        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
++        /* M-level APLIC node */
-+            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
++        aplic_addr = memmap[VIRT_APLIC_M].base +
-+    } else {
++                     (memmap[VIRT_APLIC_M].size * socket);
-+        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
++        create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
-+            msi_m_phandle);
++                             msi_m_phandle, intc_phandles,
-+    }
++                             aplic_m_phandle, aplic_s_phandle,
-     qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
++                             true);
-x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
+     }
-     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
++
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aia(RISCVVirtState *s,
++    /* S-level APLIC node */
-     qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+     aplic_addr = memmap[VIRT_APLIC_S].base +
-         "#interrupt-cells", FDT_APLIC_INT_CELLS);
+                  (memmap[VIRT_APLIC_S].size * socket);
-     qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
++    create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
--    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
++                         msi_s_phandle, intc_phandles,
--        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
++                         aplic_s_phandle, 0,
-+    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
++                         false);
-+        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
++
-+            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
-+    } else {
+-    qemu_fdt_add_subnode(ms->fdt, aplic_name);
-+        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+-    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
-+            msi_s_phandle);
+-    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
-+    }
+-        "#interrupt-cells", FDT_APLIC_INT_CELLS);
-     qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+-    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
-x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
+-    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
-     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+-        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+-            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
-                                bool is_32_bit, uint32_t *phandle,
+-    } else {
-                                uint32_t *irq_mmio_phandle,
+-        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
-                                uint32_t *irq_pcie_phandle,
+-            msi_s_phandle);
--                               uint32_t *irq_virtio_phandle)
+-    }
-+                               uint32_t *irq_virtio_phandle,
+-    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
-+                               uint32_t *msi_pcie_phandle)
+-        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
- {
+-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
--    int socket;
+-        VIRT_IRQCHIP_NUM_SOURCES);
-     char *clust_name;
+-    riscv_socket_fdt_write_id(ms, aplic_name, socket);
--    uint32_t *intc_phandles;
+-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
-+    int socket, phandle_pos;
-     MachineState *mc = MACHINE(s);
+     if (!socket) {
--    uint32_t xplic_phandles[MAX_NODES];
+         platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
-+    uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
-+    uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
+     g_free(aplic_name);
-     qemu_fdt_add_subnode(mc->fdt, "/cpus");
-     qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
+-    g_free(aplic_cells);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+     aplic_phandles[socket] = aplic_s_phandle;
-     qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
+ }
-     qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
-+    intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+     int i;
-+
+     hwaddr addr;
-+    phandle_pos = mc->smp.cpus;
+     uint32_t guest_bits;
-     for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+-    DeviceState *aplic_m;
-+        phandle_pos -= s->soc[socket].num_harts;
+-    bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
-+
++    DeviceState *aplic_s = NULL;
-         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
++    DeviceState *aplic_m = NULL;
-         qemu_fdt_add_subnode(mc->fdt, clust_name);
++    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
--        intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
+     if (msimode) {
 -        /* Per-socket M-level IMSICs */
 -        addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
 -        for (i = 0; i < hart_count; i++) {
 -            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
 -                               base_hartid + i, true, 1,
 -                               VIRT_IRQCHIP_NUM_MSIS);
 +        if (!kvm_enabled()) {
 +            /* Per-socket M-level IMSICs */
 +            addr = memmap[VIRT_IMSIC_M].base +
 +                   socket * VIRT_IMSIC_GROUP_MAX_SIZE;
 +            for (i = 0; i < hart_count; i++) {
 +                riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
 +                                   base_hartid + i, true, 1,
 +                                   VIRT_IRQCHIP_NUM_MSIS);
 +            }
          }
          /* Per-socket S-level IMSICs */
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
          }
      }
 -    /* Per-socket M-level APLIC */
 -    aplic_m = riscv_aplic_create(
 -        memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
 -        memmap[VIRT_APLIC_M].size,
 -        (msimode) ? 0 : base_hartid,
 -        (msimode) ? 0 : hart_count,
 -        VIRT_IRQCHIP_NUM_SOURCES,
 -        VIRT_IRQCHIP_NUM_PRIO_BITS,
 -        msimode, true, NULL);
 -
-         create_fdt_socket_cpus(s, socket, clust_name, phandle,
+-    if (aplic_m) {
--            is_32_bit, intc_phandles);
+-        /* Per-socket S-level APLIC */
-+            is_32_bit, &intc_phandles[phandle_pos]);
+-        riscv_aplic_create(
+-            memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
-         create_fdt_socket_memory(s, memmap, socket);
+-            memmap[VIRT_APLIC_S].size,
+-            (msimode) ? 0 : base_hartid,
-+        g_free(clust_name);
+-            (msimode) ? 0 : hart_count,
-+
+-            VIRT_IRQCHIP_NUM_SOURCES,
-         if (!kvm_enabled()) {
+-            VIRT_IRQCHIP_NUM_PRIO_BITS,
-             if (s->have_aclint) {
+-            msimode, false, aplic_m);
--                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
++    if (!kvm_enabled()) {
-+                create_fdt_socket_aclint(s, memmap, socket,
++        /* Per-socket M-level APLIC */
-+                    &intc_phandles[phandle_pos]);
++        aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
-             } else {
++                                     socket * memmap[VIRT_APLIC_M].size,
--                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
++                                     memmap[VIRT_APLIC_M].size,
-+                create_fdt_socket_clint(s, memmap, socket,
++                                     (msimode) ? 0 : base_hartid,
-+                    &intc_phandles[phandle_pos]);
++                                     (msimode) ? 0 : hart_count,
-             }
++                                     VIRT_IRQCHIP_NUM_SOURCES,
-         }
++                                     VIRT_IRQCHIP_NUM_PRIO_BITS,
-+    }
++                                     msimode, true, NULL);
-+
+     }
-+    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
-+        create_fdt_imsic(s, memmap, phandle, intc_phandles,
+-    return aplic_m;
-+            &msi_m_phandle, &msi_s_phandle);
++    /* Per-socket S-level APLIC */
-+        *msi_pcie_phandle = msi_s_phandle;
++    aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
-+    }
++                                 socket * memmap[VIRT_APLIC_S].size,
-+
++                                 memmap[VIRT_APLIC_S].size,
-+    phandle_pos = mc->smp.cpus;
++                                 (msimode) ? 0 : base_hartid,
-+    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
++                                 (msimode) ? 0 : hart_count,
-+        phandle_pos -= s->soc[socket].num_harts;
++                                 VIRT_IRQCHIP_NUM_SOURCES,
++                                 VIRT_IRQCHIP_NUM_PRIO_BITS,
-         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
++                                 msimode, false, aplic_m);
-             create_fdt_socket_plic(s, memmap, socket, phandle,
++
--                intc_phandles, xplic_phandles);
++    return kvm_enabled() ? aplic_s : aplic_m;
 +                &intc_phandles[phandle_pos], xplic_phandles);
          } else {
 -            create_fdt_socket_aia(s, memmap, socket, phandle,
 -                intc_phandles, xplic_phandles);
 +            create_fdt_socket_aplic(s, memmap, socket,
 +                msi_m_phandle, msi_s_phandle, phandle,
 +                &intc_phandles[phandle_pos], xplic_phandles);
          }
 -
 -        g_free(intc_phandles);
 -        g_free(clust_name);
      }
 +    g_free(intc_phandles);
 +
      for (socket = 0; socket < riscv_socket_count(mc); socket++) {
          if (socket == 0) {
              *irq_mmio_phandle = xplic_phandles[socket];
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
  }
- static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
+ static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
 -                            uint32_t irq_pcie_phandle)
 +                            uint32_t irq_pcie_phandle,
 +                            uint32_t msi_pcie_phandle)
  {
      char *name;
      MachineState *mc = MACHINE(s);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
      qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
          memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
      qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
 +    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
 +        qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
 +    }
      qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
          memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
      qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
                         uint64_t mem_size, const char *cmdline, bool is_32_bit)
  {
      MachineState *mc = MACHINE(s);
 -    uint32_t phandle = 1, irq_mmio_phandle = 1;
 +    uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
      uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
      if (mc->dtb) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
      qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
      create_fdt_sockets(s, memmap, is_32_bit, &phandle,
 -        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
 +        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
 +        &msi_pcie_phandle);
      create_fdt_virtio(s, memmap, irq_virtio_phandle);
 -    create_fdt_pcie(s, memmap, irq_pcie_phandle);
 +    create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
      create_fdt_reset(s, memmap, &phandle);
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
      return ret;
  }
 -static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
 +static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
                                      const MemMapEntry *memmap, int socket,
                                      int base_hartid, int hart_count)
  {
 +    int i;
 +    hwaddr addr;
 +    uint32_t guest_bits;
      DeviceState *aplic_m;
 +    bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
 +
 +    if (msimode) {
 +        /* Per-socket M-level IMSICs */
 +        addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
 +        for (i = 0; i < hart_count; i++) {
 +            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
 +                               base_hartid + i, true, 1,
 +                               VIRT_IRQCHIP_NUM_MSIS);
 +        }
 +
 +        /* Per-socket S-level IMSICs */
 +        guest_bits = imsic_num_bits(aia_guests + 1);
 +        addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
 +        for (i = 0; i < hart_count; i++) {
 +            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
 +                               base_hartid + i, false, 1 + aia_guests,
 +                               VIRT_IRQCHIP_NUM_MSIS);
 +        }
 +    }
      /* Per-socket M-level APLIC */
      aplic_m = riscv_aplic_create(
          memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
          memmap[VIRT_APLIC_M].size,
 -        base_hartid, hart_count,
 +        (msimode) ? 0 : base_hartid,
 +        (msimode) ? 0 : hart_count,
          VIRT_IRQCHIP_NUM_SOURCES,
          VIRT_IRQCHIP_NUM_PRIO_BITS,
 -        false, true, NULL);
 +        msimode, true, NULL);
      if (aplic_m) {
          /* Per-socket S-level APLIC */
          riscv_aplic_create(
              memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
              memmap[VIRT_APLIC_S].size,
 -            base_hartid, hart_count,
 +            (msimode) ? 0 : base_hartid,
 +            (msimode) ? 0 : hart_count,
              VIRT_IRQCHIP_NUM_SOURCES,
              VIRT_IRQCHIP_NUM_PRIO_BITS,
 -            false, false, aplic_m);
 +            msimode, false, aplic_m);
      }
      return aplic_m;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
          if (!kvm_enabled()) {
 -            /* Per-socket CLINT */
 -            riscv_aclint_swi_create(
 -                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 -                base_hartid, hart_count, false);
 -            riscv_aclint_mtimer_create(
 -                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
 -                    RISCV_ACLINT_SWI_SIZE,
 -                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 -                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 -                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 -
 -            /* Per-socket ACLINT SSWI */
              if (s->have_aclint) {
 +                if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
 +                    /* Per-socket ACLINT MTIMER */
 +                    riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
 +                            i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
 +                        RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
 +                        base_hartid, hart_count,
 +                        RISCV_ACLINT_DEFAULT_MTIMECMP,
 +                        RISCV_ACLINT_DEFAULT_MTIME,
 +                        RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 +                } else {
 +                    /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
 +                    riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
 +                            i * memmap[VIRT_CLINT].size,
 +                        base_hartid, hart_count, false);
 +                    riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
 +                            i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
 +                        RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
 +                        base_hartid, hart_count,
 +                        RISCV_ACLINT_DEFAULT_MTIMECMP,
 +                        RISCV_ACLINT_DEFAULT_MTIME,
 +                        RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 +                    riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
 +                            i * memmap[VIRT_ACLINT_SSWI].size,
 +                        base_hartid, hart_count, true);
 +                }
 +            } else {
 +                /* Per-socket SiFive CLINT */
                  riscv_aclint_swi_create(
 -                    memmap[VIRT_ACLINT_SSWI].base +
 -                        i * memmap[VIRT_ACLINT_SSWI].size,
 -                    base_hartid, hart_count, true);
 +                    memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 +                    base_hartid, hart_count, false);
 +                riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
 +                        i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
 +                    RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
 +                    base_hartid, hart_count,
 +                    RISCV_ACLINT_DEFAULT_MTIMECMP,
 +                    RISCV_ACLINT_DEFAULT_MTIME,
 +                    RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
              }
          }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
              s->irqchip[i] = virt_create_plic(memmap, i,
                                               base_hartid, hart_count);
          } else {
 -            s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
 -                                            base_hartid, hart_count);
 +            s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
 +                                            memmap, i, base_hartid,
 +                                            hart_count);
          }
          /* Try to use different IRQCHIP instance based device type */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
  {
  }
 +static char *virt_get_aia_guests(Object *obj, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +    char val[32];
 +
 +    sprintf(val, "%d", s->aia_guests);
 +    return g_strdup(val);
 +}
 +
 +static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +
 +    s->aia_guests = atoi(val);
 +    if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
 +        error_setg(errp, "Invalid number of AIA IMSIC guests");
 +        error_append_hint(errp, "Valid values be between 0 and %d.\n",
 +                          VIRT_IRQCHIP_MAX_GUESTS);
 +    }
 +}
 +
  static char *virt_get_aia(Object *obj, Error **errp)
  {
      RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static char *virt_get_aia(Object *obj, Error **errp)
      case VIRT_AIA_TYPE_APLIC:
          val = "aplic";
          break;
 +    case VIRT_AIA_TYPE_APLIC_IMSIC:
 +        val = "aplic-imsic";
 +        break;
      default:
          val = "none";
          break;
@@ -XXX,XX +XXX,XX @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
          s->aia_type = VIRT_AIA_TYPE_NONE;
      } else if (!strcmp(val, "aplic")) {
          s->aia_type = VIRT_AIA_TYPE_APLIC;
 +    } else if (!strcmp(val, "aplic-imsic")) {
 +        s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
      } else {
          error_setg(errp, "Invalid AIA interrupt controller type");
 -        error_append_hint(errp, "Valid values are none, and aplic.\n");
 +        error_append_hint(errp, "Valid values are none, aplic, and "
 +                          "aplic-imsic.\n");
      }
  }
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
  static void virt_machine_class_init(ObjectClass *oc, void *data)
  {
 +    char str[128];
      MachineClass *mc = MACHINE_CLASS(oc);
      mc->desc = "RISC-V VirtIO board";
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      object_class_property_set_description(oc, "aia",
                                            "Set type of AIA interrupt "
                                            "conttoller. Valid values are "
 -                                          "none, and aplic.");
 +                                          "none, aplic, and aplic-imsic.");
 +
 +    object_class_property_add_str(oc, "aia-guests",
 +                                  virt_get_aia_guests,
 +                                  virt_set_aia_guests);
 +    sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
 +                 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
 +    object_class_property_set_description(oc, "aia-guests", str);
  }
  static const TypeInfo virt_machine_typeinfo = {
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select SERIAL
      select RISCV_ACLINT
      select RISCV_APLIC
 +    select RISCV_IMSIC
      select SIFIVE_PLIC
      select SIFIVE_TEST
      select VIRTIO_MMIO
 --
-.34.1
+.41.0

-[PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64
+[PULL v2 30/45] target/riscv: check the in-kernel irqchip support
-From: Guo Ren <ren_guo@c-sky.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
+We check the in-kernel irqchip support when using KVM acceleration.
 need to ignore them. They cannot be a part of ppn.
-: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-.4 Sv39: Page-Based 39-bit Virtual-Memory System
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
-.5 Sv48: Page-Based 48-bit Virtual-Memory System
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
+Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com>
 Signed-off-by: Guo Ren <ren_guo@c-sky.com>
 Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Cc: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 15 +++++++++++++++
+ target/riscv/kvm.c | 10 +++++++++-
- target/riscv/cpu_bits.h   |  3 +++
+file changed, 9 insertions(+), 1 deletion(-)
  target/riscv/cpu_helper.c | 13 ++++++++++++-
 files changed, 30 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/kvm.c
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
-     bool ext_counters;
-     bool ext_ifencei;
+ int kvm_arch_irqchip_create(KVMState *s)
-     bool ext_icsr;
+ {
-+    bool ext_svnapot;
+-    return 0;
-+    bool ext_svpbmt;
++    if (kvm_kernel_irqchip_split()) {
-     bool ext_zfh;
++        error_report("-machine kernel_irqchip=split is not supported on RISC-V.");
-     bool ext_zfhmin;
++        exit(1);
-     bool ext_zve32f;
++    }
-@@ -XXX,XX +XXX,XX @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
++
-     return 16 << env->xl;
++    /*
 +     * We can create the VAIA using the newer device control API.
 +     */
 +    return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
  }
-+#ifdef TARGET_RISCV32
+ int kvm_arch_process_async_events(CPUState *cs)
 +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 +#else
 +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 +{
 +#ifdef CONFIG_USER_ONLY
 +    return env->misa_mxl;
 +#else
 +    return get_field(env->mstatus, MSTATUS64_SXL);
 +#endif
 +}
 +#endif
 +
  /*
   * Encode LMUL to lmul as follows:
   *     LMUL    vlmul    lmul
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  /* Page table PPN shift amount */
  #define PTE_PPN_SHIFT       10
 +/* Page table PPN mask */
 +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
 +
  /* Leaf page shift amount */
  #define PGSHIFT             12
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
      int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
      bool use_background = false;
 +    hwaddr ppn;
 +    RISCVCPU *cpu = env_archcpu(env);
      /*
       * Check if we should use the background registers for the two
@@ -XXX,XX +XXX,XX @@ restart:
              return TRANSLATE_FAIL;
          }
 -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
 +        if (riscv_cpu_sxl(env) == MXL_RV32) {
 +            ppn = pte >> PTE_PPN_SHIFT;
 +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
 +            ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
 +        } else {
 +            ppn = pte >> PTE_PPN_SHIFT;
 +            if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
 +                return TRANSLATE_FAIL;
 +            }
 +        }
          if (!(pte & PTE_V)) {
              /* Invalid PTE */
 --
-.34.1
+.41.0

-[PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs
+[PULL v2 31/45] target/riscv: Create an KVM AIA irqchip
-From: Anup Patel <anup.patel@wdc.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
+We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
-which allow indirect access to interrupt priority arrays and per-HART
+the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
-IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
+We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
 parameter is passed along with --accel in QEMU command-line.
 ) "riscv-aia=emul": IMSIC is emulated by hypervisor
 ) "riscv-aia=hwaccel": use hardware guest IMSIC
 ) "riscv-aia=auto": use the hardware guest IMSICs whenever available
                      otherwise we fallback to software emulation.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20220204174700.534953-15-anup@brainfault.org
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h     |   7 ++
+ target/riscv/kvm_riscv.h |   4 +
- target/riscv/csr.c     | 177 +++++++++++++++++++++++++++++++++++++++++
+ target/riscv/kvm.c       | 186 +++++++++++++++++++++++++++++++++++++++
- target/riscv/machine.c |   3 +
+files changed, 190 insertions(+)
 files changed, 187 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@
-     uint8_t miprio[64];
+ void kvm_riscv_init_user_properties(Object *cpu_obj);
-     uint8_t siprio[64];
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
-+    /* AIA CSRs */
++void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-+    target_ulong miselect;
++                          uint64_t aia_irq_num, uint64_t aia_msi_num,
-+    target_ulong siselect;
++                          uint64_t aplic_base, uint64_t imsic_base,
-+
++                          uint64_t guest_num);
-     /* Hypervisor CSRs */
-     target_ulong hstatus;
+ #endif
-     target_ulong hedeleg;
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
      target_ulong vstval;
      target_ulong vsatp;
 +    /* AIA VS-mode CSRs */
 +    target_ulong vsiselect;
 +
      target_ulong mtval2;
      target_ulong mtinst;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/kvm.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@
-     return RISCV_EXCP_NONE;
+ #include "exec/address-spaces.h"
  #include "hw/boards.h"
  #include "hw/irq.h"
 +#include "hw/intc/riscv_imsic.h"
  #include "qemu/log.h"
  #include "hw/loader.h"
  #include "kvm_riscv.h"
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char-fe.h"
  #include "migration/migration.h"
  #include "sysemu/runstate.h"
 +#include "hw/riscv/numa.h"
  static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                   uint64_t idx)
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_cpu_check_are_resettable(void)
      return true;
  }
-+static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
++static int aia_mode;
-+{
++
-+    if (!riscv_cpu_virt_enabled(env)) {
++static const char *kvm_aia_mode_str(uint64_t mode)
-+        return csrno;
++{
-+    }
++    switch (mode) {
-+
++    case KVM_DEV_RISCV_AIA_MODE_EMUL:
-+    switch (csrno) {
++        return "emul";
-+    case CSR_SISELECT:
++    case KVM_DEV_RISCV_AIA_MODE_HWACCEL:
-+        return CSR_VSISELECT;
++        return "hwaccel";
-+    case CSR_SIREG:
++    case KVM_DEV_RISCV_AIA_MODE_AUTO:
 +        return CSR_VSIREG;
 +    default:
-+        return csrno;
++        return "auto";
 +    };
 +}
 +
-+static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
++static char *riscv_get_kvm_aia(Object *obj, Error **errp)
-+                        target_ulong new_val, target_ulong wr_mask)
++{
-+{
++    return g_strdup(kvm_aia_mode_str(aia_mode));
-+    target_ulong *iselect;
++}
 +
-+    /* Translate CSR number for VS-mode */
++static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp)
-+    csrno = aia_xlate_vs_csrno(env, csrno);
++{
-+
++    if (!strcmp(val, "emul")) {
-+    /* Find the iselect CSR based on CSR number */
++        aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL;
-+    switch (csrno) {
++    } else if (!strcmp(val, "hwaccel")) {
-+    case CSR_MISELECT:
++        aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL;
-+        iselect = &env->miselect;
++    } else if (!strcmp(val, "auto")) {
-+        break;
++        aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO;
-+    case CSR_SISELECT:
++    } else {
-+        iselect = &env->siselect;
++        error_setg(errp, "Invalid KVM AIA mode");
-+        break;
++        error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n");
-+    case CSR_VSISELECT:
++    }
-+        iselect = &env->vsiselect;
++}
-+        break;
++
-+    default:
+ void kvm_arch_accel_class_init(ObjectClass *oc)
-+         return RISCV_EXCP_ILLEGAL_INST;
+ {
-+    };
++    object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia,
-+
++                                  riscv_set_kvm_aia);
-+    if (val) {
++    object_class_property_set_description(oc, "riscv-aia",
-+        *val = *iselect;
++                                          "Set KVM AIA mode. Valid values are "
-+    }
++                                          "emul, hwaccel, and auto. Default "
-+
++                                          "is auto.");
-+    wr_mask &= ISELECT_MASK;
++    object_property_set_default_str(object_class_property_find(oc, "riscv-aia"),
-+    if (wr_mask) {
++                                    "auto");
-+        *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
++}
-+    }
++
-+
++void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-+    return RISCV_EXCP_NONE;
++                          uint64_t aia_irq_num, uint64_t aia_msi_num,
-+}
++                          uint64_t aplic_base, uint64_t imsic_base,
-+
++                          uint64_t guest_num)
-+static int rmw_iprio(target_ulong xlen,
++{
-+                     target_ulong iselect, uint8_t *iprio,
++    int ret, i;
-+                     target_ulong *val, target_ulong new_val,
++    int aia_fd = -1;
-+                     target_ulong wr_mask, int ext_irq_no)
++    uint64_t default_aia_mode;
-+{
++    uint64_t socket_count = riscv_socket_count(machine);
-+    int i, firq, nirqs;
++    uint64_t max_hart_per_socket = 0;
-+    target_ulong old_val;
++    uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr;
-+
++    uint64_t socket_bits, hart_bits, guest_bits;
-+    if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
++
-+        return -EINVAL;
++    aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false);
-+    }
++
-+    if (xlen != 32 && iselect & 0x1) {
++    if (aia_fd < 0) {
-+        return -EINVAL;
++        error_report("Unable to create in-kernel irqchip");
-+    }
++        exit(1);
-+
++    }
-+    nirqs = 4 * (xlen / 32);
++
-+    firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
++    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+
++                            KVM_DEV_RISCV_AIA_CONFIG_MODE,
-+    old_val = 0;
++                            &default_aia_mode, false, NULL);
-+    for (i = 0; i < nirqs; i++) {
++    if (ret < 0) {
-+        old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
++        error_report("KVM AIA: failed to get current KVM AIA mode");
-+    }
++        exit(1);
-+
++    }
-+    if (val) {
++    qemu_log("KVM AIA: default mode is %s\n",
-+        *val = old_val;
++             kvm_aia_mode_str(default_aia_mode));
-+    }
++
-+
++    if (default_aia_mode != aia_mode) {
-+    if (wr_mask) {
++        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+        new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
++                                KVM_DEV_RISCV_AIA_CONFIG_MODE,
-+        for (i = 0; i < nirqs; i++) {
++                                &aia_mode, true, NULL);
-+            /*
++        if (ret < 0)
-+             * M-level and S-level external IRQ priority always read-only
++            warn_report("KVM AIA: failed to set KVM AIA mode");
-+             * zero. This means default priority order is always preferred
++        else
-+             * for M-level and S-level external IRQs.
++            qemu_log("KVM AIA: set current mode to %s\n",
-+             */
++                     kvm_aia_mode_str(aia_mode));
-+            if ((firq + i) == ext_irq_no) {
++    }
-+                continue;
++
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
 +                            KVM_DEV_RISCV_AIA_CONFIG_SRCS,
 +                            &aia_irq_num, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set number of input irq lines");
 +        exit(1);
 +    }
 +
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
 +                            KVM_DEV_RISCV_AIA_CONFIG_IDS,
 +                            &aia_msi_num, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set number of msi");
 +        exit(1);
 +    }
 +
 +    socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1;
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
 +                            KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS,
 +                            &socket_bits, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set group_bits");
 +        exit(1);
 +    }
 +
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
 +                            KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT,
 +                            &group_shift, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set group_shift");
 +        exit(1);
 +    }
 +
 +    guest_bits = guest_num == 0 ? 0 :
 +                 find_last_bit(&guest_num, BITS_PER_LONG) + 1;
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
 +                            KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS,
 +                            &guest_bits, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set guest_bits");
 +        exit(1);
 +    }
 +
 +    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
 +                            KVM_DEV_RISCV_AIA_ADDR_APLIC,
 +                            &aplic_base, true, NULL);
 +    if (ret < 0) {
 +        error_report("KVM AIA: failed to set the base address of APLIC");
 +        exit(1);
 +    }
 +
 +    for (socket = 0; socket < socket_count; socket++) {
 +        socket_imsic_base = imsic_base + socket * (1U << group_shift);
 +        hart_count = riscv_socket_hart_count(machine, socket);
 +        base_hart = riscv_socket_first_hartid(machine, socket);
 +
 +        if (max_hart_per_socket < hart_count) {
 +            max_hart_per_socket = hart_count;
 +        }
 +
 +        for (i = 0; i < hart_count; i++) {
 +            imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits);
 +            ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
 +                                    KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart),
 +                                    &imsic_addr, true, NULL);
 +            if (ret < 0) {
 +                error_report("KVM AIA: failed to set the IMSIC address for hart %d", i);
 +                exit(1);
 +            }
-+            iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
 +        }
 +    }
 +
-+    return 0;
++    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+}
++    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+
++                            KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-+static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
++                            &hart_bits, true, NULL);
-+                     target_ulong new_val, target_ulong wr_mask)
++    if (ret < 0) {
-+{
++        error_report("KVM AIA: failed to set hart_bits");
-+    bool virt;
++        exit(1);
-+    uint8_t *iprio;
++    }
-+    int ret = -EINVAL;
++
-+    target_ulong priv, isel, vgein;
++    if (kvm_has_gsi_routing()) {
-+
++        for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) {
-+    /* Translate CSR number for VS-mode */
++            /* KVM AIA only has one APLIC instance */
-+    csrno = aia_xlate_vs_csrno(env, csrno);
++            kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx);
 +
 +    /* Decode register details from CSR number */
 +    virt = false;
 +    switch (csrno) {
 +    case CSR_MIREG:
 +        iprio = env->miprio;
 +        isel = env->miselect;
 +        priv = PRV_M;
 +        break;
 +    case CSR_SIREG:
 +        iprio = env->siprio;
 +        isel = env->siselect;
 +        priv = PRV_S;
 +        break;
 +    case CSR_VSIREG:
 +        iprio = env->hviprio;
 +        isel = env->vsiselect;
 +        priv = PRV_S;
 +        virt = true;
 +        break;
 +    default:
 +         goto done;
 +    };
 +
 +    /* Find the selected guest interrupt file */
 +    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
 +
 +    if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
 +        /* Local interrupt priority registers not available for VS-mode */
 +        if (!virt) {
 +            ret = rmw_iprio(riscv_cpu_mxl_bits(env),
 +                            isel, iprio, val, new_val, wr_mask,
 +                            (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
 +        }
-+    } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
++        kvm_gsi_routing_allowed = true;
-+        /* IMSIC registers only available when machine implements it. */
++        kvm_irqchip_commit_routes(kvm_state);
-+        if (env->aia_ireg_rmw_fn[priv]) {
++    }
-+            /* Selected guest interrupt file should not be zero */
++
-+            if (virt && (!vgein || env->geilen < vgein)) {
++    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL,
-+                goto done;
++                            KVM_DEV_RISCV_AIA_CTRL_INIT,
-+            }
++                            NULL, true, NULL);
-+            /* Call machine specific IMSIC register emulation */
++    if (ret < 0) {
-+            ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
++        error_report("KVM AIA: initialized fail");
-+                                    AIA_MAKE_IREG(isel, priv, virt, vgein,
++        exit(1);
-+                                                  riscv_cpu_mxl_bits(env)),
++    }
-+                                    val, new_val, wr_mask);
++
-+        }
++    kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
-+    }
+ }
 +
 +done:
 +    if (ret) {
 +        return (riscv_cpu_virt_enabled(env) && virt) ?
 +               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
 +    }
 +    return RISCV_EXCP_NONE;
 +}
 +
  static RISCVException read_mtvec(CPURISCVState *env, int csrno,
                                   target_ulong *val)
  {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
      [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 +    /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
 +    [CSR_MISELECT] = { "miselect", aia_any,   NULL, NULL,    rmw_xiselect },
 +    [CSR_MIREG]    = { "mireg",    aia_any,   NULL, NULL,    rmw_xireg },
 +
      /* Machine-Level Interrupts (AIA) */
      [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      /* Supervisor Protection and Translation */
      [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
 +    /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 +    [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
 +    [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },
 +
      /* Supervisor-Level Interrupts (AIA) */
      [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
      [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 +    /*
 +     * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
 +     */
 +    [CSR_VSISELECT]   = { "vsiselect",   aia_hmode, NULL, NULL,      rmw_xiselect },
 +    [CSR_VSIREG]      = { "vsireg",      aia_hmode, NULL, NULL,      rmw_xireg },
 +
      /* VS-Level Interrupts (H-extension with AIA) */
      [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
          VMSTATE_UINTTL(env.vscause, RISCVCPU),
          VMSTATE_UINTTL(env.vstval, RISCVCPU),
          VMSTATE_UINTTL(env.vsatp, RISCVCPU),
 +        VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
          VMSTATE_UINTTL(env.mtval2, RISCVCPU),
          VMSTATE_UINTTL(env.mtinst, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINTTL(env.mepc, RISCVCPU),
          VMSTATE_UINTTL(env.mcause, RISCVCPU),
          VMSTATE_UINTTL(env.mtval, RISCVCPU),
 +        VMSTATE_UINTTL(env.miselect, RISCVCPU),
 +        VMSTATE_UINTTL(env.siselect, RISCVCPU),
          VMSTATE_UINTTL(env.scounteren, RISCVCPU),
          VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
          VMSTATE_UINTTL(env.sscratch, RISCVCPU),
 --
-.34.1
+.41.0

-[PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
+[PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA
-From: Anup Patel <anup.patel@wdc.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-The AIA specification introduces new [m|s|vs]topi CSRs for
+KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
-reporting pending local IRQ number and associated IRQ priority.
+APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
 mmio operations of APLIC when using KVM AIA and send wired interrupt
 signal via KVM_IRQ_LINE API.
 After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
 when the IMSICs receive mmio write requests.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20220204174700.534953-14-anup@brainfault.org
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-[ Changed by AF:
+Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
  - Fixup indentation
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 156 +++++++++++++++++++++++++++++++++++++++++++++
+ hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++-------------
-file changed, 156 insertions(+)
+ hw/intc/riscv_imsic.c | 25 +++++++++++++++----
 files changed, 61 insertions(+), 20 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/hw/intc/riscv_aplic.c
-+++ b/target/riscv/csr.c
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@ static int smode32(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@
-     return smode(env, csrno);
+ #include "hw/irq.h"
- }
+ #include "target/riscv/cpu.h"
+ #include "sysemu/sysemu.h"
-+static int aia_smode(CPURISCVState *env, int csrno)
++#include "sysemu/kvm.h"
  #include "migration/vmstate.h"
  #define APLIC_MAX_IDC                  (1UL << 14)
@@ -XXX,XX +XXX,XX @@
  #define APLIC_IDC_CLAIMI               0x1c
 +/*
 + * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
 + * APLIC Wired.
 + */
 +static bool is_kvm_aia(bool msimode)
 +{
-+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
++    return kvm_irqchip_in_kernel() && msimode;
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    return smode(env, csrno);
 +}
 +
- static int aia_smode32(CPURISCVState *env, int csrno)
+ static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
                                              uint32_t word)
  {
-     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
+     return topi;
  #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
  #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
 +#define VSTOPI_NUM_SRCS 5
 +
  static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
                                             VS_MODE_INTERRUPTS;
  static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
      return ret;
  }
-+static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
++static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
 +{
-+    int irq;
++    kvm_set_irq(kvm_state, irq, !!level);
 +    uint8_t iprio;
 +
 +    irq = riscv_cpu_mirq_pending(env);
 +    if (irq <= 0 || irq > 63) {
 +        *val = 0;
 +    } else {
 +        iprio = env->miprio[irq];
 +        if (!iprio) {
 +            if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
 +                iprio = IPRIO_MMAXIPRIO;
 +            }
 +        }
 +        *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
 +        *val |= iprio;
 +    }
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
- static RISCVException read_mtvec(CPURISCVState *env, int csrno,
+ static void riscv_aplic_request(void *opaque, int irq, int level)
                                   target_ulong *val)
  {
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
+     bool update = false;
-     return RISCV_EXCP_NONE;
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
- }
+     uint32_t i;
+     RISCVAPLICState *aplic = RISCV_APLIC(dev);
-+static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
-+{
+-    aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
-+    int irq, ret;
+-    aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
-+    target_ulong topei;
+-    aplic->state = g_new0(uint32_t, aplic->num_irqs);
-+    uint64_t vseip, vsgein;
+-    aplic->target = g_new0(uint32_t, aplic->num_irqs);
-+    uint32_t iid, iprio, hviid, hviprio, gein;
+-    if (!aplic->msimode) {
-+    uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
+-        for (i = 0; i < aplic->num_irqs; i++) {
 -            aplic->target[i] = 1;
 +    if (!is_kvm_aia(aplic->msimode)) {
 +        aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
 +        aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
 +        aplic->state = g_new0(uint32_t, aplic->num_irqs);
 +        aplic->target = g_new0(uint32_t, aplic->num_irqs);
 +        if (!aplic->msimode) {
 +            for (i = 0; i < aplic->num_irqs; i++) {
 +                aplic->target[i] = 1;
 +            }
          }
 -    }
 -    aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
 -    aplic->iforce = g_new0(uint32_t, aplic->num_harts);
 -    aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
 +        aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
 +        aplic->iforce = g_new0(uint32_t, aplic->num_harts);
 +        aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
 -    memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
 -                          TYPE_RISCV_APLIC, aplic->aperture_size);
 -    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
 +        memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
 +                              aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
 +        sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
 +    }
      /*
       * Only root APLICs have hardware IRQ lines. All non-root APLICs
       * have IRQ lines delegated by their parent APLIC.
       */
      if (!aplic->parent) {
 -        qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
 +        if (is_kvm_aia(aplic->msimode)) {
 +            qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
 +        } else {
 +            qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
 +        }
      }
      /* Create output IRQ lines for non-MSI mode */
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
      qdev_prop_set_bit(dev, "mmode", mmode);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 -    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 +
-+    gein = get_field(env->hstatus, HSTATUS_VGEIN);
++    if (!is_kvm_aia(msimode)) {
-+    hviid = get_field(env->hvictl, HVICTL_IID);
++        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-+    hviprio = get_field(env->hvictl, HVICTL_IPRIO);
++    }
      if (parent) {
          riscv_aplic_add_child(parent, dev);
 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/riscv_imsic.c
 +++ b/hw/intc/riscv_imsic.c
@@ -XXX,XX +XXX,XX @@
  #include "target/riscv/cpu.h"
  #include "target/riscv/cpu_bits.h"
  #include "sysemu/sysemu.h"
 +#include "sysemu/kvm.h"
  #include "migration/vmstate.h"
  #define IMSIC_MMIO_PAGE_LE             0x00
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
          goto err;
      }
 +#if defined(CONFIG_KVM)
 +    if (kvm_irqchip_in_kernel()) {
 +        struct kvm_msi msi;
 +
-+    if (gein) {
++        msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32);
-+        vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
++        msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32);
-+        vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
++        msi.data = le32_to_cpu(value);
-+        if (gein <= env->geilen && vseip) {
++
-+            siid[scount] = IRQ_S_EXT;
++        kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
-+            siprio[scount] = IPRIO_MMAXIPRIO + 1;
++
-+            if (env->aia_ireg_rmw_fn[PRV_S]) {
++        return;
 +                /*
 +                 * Call machine specific IMSIC register emulation for
 +                 * reading TOPEI.
 +                 */
 +                ret = env->aia_ireg_rmw_fn[PRV_S](
 +                        env->aia_ireg_rmw_fn_arg[PRV_S],
 +                        AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
 +                                      riscv_cpu_mxl_bits(env)),
 +                        &topei, 0, 0);
 +                if (!ret && topei) {
 +                    siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
 +                }
 +            }
 +            scount++;
 +        }
 +    } else {
 +        if (hviid == IRQ_S_EXT && hviprio) {
 +            siid[scount] = IRQ_S_EXT;
 +            siprio[scount] = hviprio;
 +            scount++;
 +        }
 +    }
++#endif
 +
-+    if (env->hvictl & HVICTL_VTI) {
+     /* Writes only supported for MSI little-endian registers */
-+        if (hviid != IRQ_S_EXT) {
+     page = addr >> IMSIC_MMIO_PAGE_SHIFT;
-+            siid[scount] = hviid;
+     if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
-+            siprio[scount] = hviprio;
+@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
-+            scount++;
+     CPUState *cpu = cpu_by_arch_id(imsic->hartid);
-+        }
+     CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
-+    } else {
-+        irq = riscv_cpu_vsirq_pending(env);
+-    imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
-+        if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
+-    imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
-+            siid[scount] = irq;
+-    imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
-+            siprio[scount] = env->hviprio[irq];
+-    imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
-+            scount++;
++    if (!kvm_irqchip_in_kernel()) {
-+        }
++        imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
 +        imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
 +        imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
 +        imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
 +    }
-+
-+    iid = 0;
+     memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
-+    iprio = UINT_MAX;
+                           imsic, TYPE_RISCV_IMSIC,
 +    for (s = 0; s < scount; s++) {
 +        if (siprio[s] < iprio) {
 +            iid = siid[s];
 +            iprio = siprio[s];
 +        }
 +    }
 +
 +    if (iid) {
 +        if (env->hvictl & HVICTL_IPRIOM) {
 +            if (iprio > IPRIO_MMAXIPRIO) {
 +                iprio = IPRIO_MMAXIPRIO;
 +            }
 +            if (!iprio) {
 +                if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
 +                    iprio = IPRIO_MMAXIPRIO;
 +                }
 +            }
 +        } else {
 +            iprio = 1;
 +        }
 +    } else {
 +        iprio = 0;
 +    }
 +
 +    *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
 +    *val |= iprio;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
 +{
 +    int irq;
 +    uint8_t iprio;
 +
 +    if (riscv_cpu_virt_enabled(env)) {
 +        return read_vstopi(env, CSR_VSTOPI, val);
 +    }
 +
 +    irq = riscv_cpu_sirq_pending(env);
 +    if (irq <= 0 || irq > 63) {
 +        *val = 0;
 +    } else {
 +        iprio = env->siprio[irq];
 +        if (!iprio) {
 +            if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
 +                iprio = IPRIO_MMAXIPRIO;
 +           }
 +        }
 +        *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
 +        *val |= iprio;
 +    }
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
  /* Hypervisor Extensions */
  static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
      [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 +    /* Machine-Level Interrupts (AIA) */
 +    [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
 +
      /* Virtual Interrupts for Supervisor Level (AIA) */
      [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
      [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      /* Supervisor Protection and Translation */
      [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
 +    /* Supervisor-Level Interrupts (AIA) */
 +    [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
 +
      /* Supervisor-Level High-Half CSRs (AIA) */
      [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
      [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
      [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 +    /* VS-Level Interrupts (H-extension with AIA) */
 +    [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
 +
      /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
      [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
      [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
 --
-.34.1
+.41.0

-[PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine
+[PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine
-From: Anup Patel <anup.patel@wdc.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-We extend virt machine to emulate AIA APLIC devices only when
+Select KVM AIA when the host kernel has in-kernel AIA chip support.
-"aia=aplic" parameter is passed along with machine name in QEMU
+Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
-command-line. When "aia=none" or not specified then we fallback
+devices to KVM APLIC.
 to original PLIC device emulation.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20220204174700.534953-20-anup@brainfault.org
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  26 +++-
+ hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++----------------
- hw/riscv/virt.c         | 291 ++++++++++++++++++++++++++++++++--------
+file changed, 63 insertions(+), 31 deletions(-)
  hw/riscv/Kconfig        |   1 +
 files changed, 259 insertions(+), 59 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVVirtState RISCVVirtState;
- DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
-                          TYPE_RISCV_VIRT_MACHINE)
-+typedef enum RISCVVirtAIAType {
-+    VIRT_AIA_TYPE_NONE = 0,
-+    VIRT_AIA_TYPE_APLIC,
-+} RISCVVirtAIAType;
-+
- struct RISCVVirtState {
-     /*< private >*/
-     MachineState parent;
-     /*< public >*/
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
--    DeviceState *plic[VIRT_SOCKETS_MAX];
-+    DeviceState *irqchip[VIRT_SOCKETS_MAX];
-     PFlashCFI01 *flash[2];
-     FWCfgState *fw_cfg;
-     int fdt_size;
-     bool have_aclint;
-+    RISCVVirtAIAType aia_type;
- };
- enum {
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_CLINT,
-     VIRT_ACLINT_SSWI,
-     VIRT_PLIC,
-+    VIRT_APLIC_M,
-+    VIRT_APLIC_S,
-     VIRT_UART0,
-     VIRT_VIRTIO,
-     VIRT_FW_CFG,
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
- };
--#define VIRT_PLIC_NUM_SOURCES 127
--#define VIRT_PLIC_NUM_PRIORITIES 7
-+#define VIRT_IRQCHIP_NUM_SOURCES 127
-+#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
-+
- #define VIRT_PLIC_PRIORITY_BASE 0x04
- #define VIRT_PLIC_PENDING_BASE 0x1000
- #define VIRT_PLIC_ENABLE_BASE 0x2000
-@@ -XXX,XX +XXX,XX @@ enum {
- #define FDT_PCI_ADDR_CELLS    3
- #define FDT_PCI_INT_CELLS     1
--#define FDT_PLIC_ADDR_CELLS   0
- #define FDT_PLIC_INT_CELLS    1
--#define FDT_INT_MAP_WIDTH     (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
--                               FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
-+#define FDT_APLIC_INT_CELLS   2
-+#define FDT_MAX_INT_CELLS     2
-+#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
-+                                 1 + FDT_MAX_INT_CELLS)
-+#define FDT_PLIC_INT_MAP_WIDTH  (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
-+                                 1 + FDT_PLIC_INT_CELLS)
-+#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
-+                                 1 + FDT_APLIC_INT_CELLS)
- #endif
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
 @@ -XXX,XX +XXX,XX @@
+ #include "hw/riscv/virt.h"
  #include "hw/riscv/boot.h"
  #include "hw/riscv/numa.h"
++#include "kvm_riscv.h"
  #include "hw/intc/riscv_aclint.h"
-+#include "hw/intc/riscv_aplic.h"
+ #include "hw/intc/riscv_aplic.h"
- #include "hw/intc/sifive_plic.h"
+ #include "hw/intc/riscv_imsic.h"
- #include "hw/misc/sifive_test.h"
+@@ -XXX,XX +XXX,XX @@
- #include "chardev/char.h"
+ #error "Can't accommodate all IMSIC groups in address space"
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
+ #endif
-     [VIRT_ACLINT_SSWI] = {  0x2F00000,        0x4000 },
-     [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
++/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
++static bool virt_use_kvm_aia(RISCVVirtState *s)
-+    [VIRT_APLIC_M] =     {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
++{
-+    [VIRT_APLIC_S] =     {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
++    return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
++}
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
++
-     [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
+ static const MemMapEntry virt_memmap[] = {
-@@ -XXX,XX +XXX,XX @@ static void virt_flash_map(RISCVVirtState *s,
+     [VIRT_DEBUG] =        {        0x0,         0x100 },
-                     sysmem);
+     [VIRT_MROM] =         {     0x1000,        0xf000 },
- }
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
+                                  uint32_t *intc_phandles,
--static void create_pcie_irq_map(void *fdt, char *nodename,
+                                  uint32_t aplic_phandle,
--                                uint32_t plic_phandle)
+                                  uint32_t aplic_child_phandle,
-+static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
+-                                 bool m_mode)
-+                                uint32_t irqchip_phandle)
++                                 bool m_mode, int num_harts)
  {
-     int pin, dev;
+     int cpu;
--    uint32_t
+     char *aplic_name;
--        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+     uint32_t *aplic_cells;
-+    uint32_t irq_map_stride = 0;
+     MachineState *ms = MACHINE(s);
-+    uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
-+                          FDT_MAX_INT_MAP_WIDTH] = {};
+-    aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
-     uint32_t *irq_map = full_irq_map;
++    aplic_cells = g_new0(uint32_t, num_harts * 2);
-     /* This code creates a standard swizzle of interrupts such that
+-    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
-@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(void *fdt, char *nodename,
++    for (cpu = 0; cpu < num_harts; cpu++) {
-             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+         aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-             int i = 0;
+         aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
+     }
-+            /* Fill PCI address cells */
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
-             irq_map[i] = cpu_to_be32(devfn << 8);
      if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
          qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
 -                         aplic_cells,
 -                         s->soc[socket].num_harts * sizeof(uint32_t) * 2);
 +                         aplic_cells, num_harts * sizeof(uint32_t) * 2);
      } else {
          qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
                                      uint32_t msi_s_phandle,
                                      uint32_t *phandle,
                                      uint32_t *intc_phandles,
 -                                    uint32_t *aplic_phandles)
 +                                    uint32_t *aplic_phandles,
 +                                    int num_harts)
  {
      char *aplic_name;
      unsigned long aplic_addr;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
          create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
                               msi_m_phandle, intc_phandles,
                               aplic_m_phandle, aplic_s_phandle,
 -                             true);
 +                             true, num_harts);
      }
      /* S-level APLIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
      create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
                           msi_s_phandle, intc_phandles,
                           aplic_s_phandle, 0,
 -                         false);
 +                         false, num_harts);
      aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          *msi_pcie_phandle = msi_s_phandle;
      }
 -    phandle_pos = ms->smp.cpus;
 -    for (socket = (socket_count - 1); socket >= 0; socket--) {
 -        phandle_pos -= s->soc[socket].num_harts;
 -
-             i += FDT_PCI_ADDR_CELLS;
+-        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
--            irq_map[i] = cpu_to_be32(pin + 1);
+-            create_fdt_socket_plic(s, memmap, socket, phandle,
+-                &intc_phandles[phandle_pos], xplic_phandles);
-+            /* Fill PCI Interrupt cells */
+-        } else {
-+            irq_map[i] = cpu_to_be32(pin + 1);
+-            create_fdt_socket_aplic(s, memmap, socket,
-             i += FDT_PCI_INT_CELLS;
+-                msi_m_phandle, msi_s_phandle, phandle,
--            irq_map[i++] = cpu_to_be32(plic_phandle);
+-                &intc_phandles[phandle_pos], xplic_phandles);
++    /* KVM AIA only has one APLIC instance */
--            i += FDT_PLIC_ADDR_CELLS;
++    if (virt_use_kvm_aia(s)) {
--            irq_map[i] = cpu_to_be32(irq_nr);
++        create_fdt_socket_aplic(s, memmap, 0,
-+            /* Fill interrupt controller phandle and cells */
++                                msi_m_phandle, msi_s_phandle, phandle,
-+            irq_map[i++] = cpu_to_be32(irqchip_phandle);
++                                &intc_phandles[0], xplic_phandles,
-+            irq_map[i++] = cpu_to_be32(irq_nr);
++                                ms->smp.cpus);
-+            if (s->aia_type != VIRT_AIA_TYPE_NONE) {
++    } else {
-+                irq_map[i++] = cpu_to_be32(0x4);
++        phandle_pos = ms->smp.cpus;
 +        for (socket = (socket_count - 1); socket >= 0; socket--) {
 +            phandle_pos -= s->soc[socket].num_harts;
 +
 +            if (s->aia_type == VIRT_AIA_TYPE_NONE) {
 +                create_fdt_socket_plic(s, memmap, socket, phandle,
 +                                       &intc_phandles[phandle_pos],
 +                                       xplic_phandles);
 +            } else {
 +                create_fdt_socket_aplic(s, memmap, socket,
 +                                        msi_m_phandle, msi_s_phandle, phandle,
 +                                        &intc_phandles[phandle_pos],
 +                                        xplic_phandles,
 +                                        s->soc[socket].num_harts);
 +            }
--            irq_map += FDT_INT_MAP_WIDTH;
-+            if (!irq_map_stride) {
-+                irq_map_stride = i;
-+            }
-+            irq_map += irq_map_stride;
          }
      }
--    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
+     g_free(intc_phandles);
--                     full_irq_map, sizeof(full_irq_map));
-+    qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+-    for (socket = 0; socket < socket_count; socket++) {
-+                     GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+-        if (socket == 0) {
-+                     irq_map_stride * sizeof(uint32_t));
+-            *irq_mmio_phandle = xplic_phandles[socket];
+-            *irq_virtio_phandle = xplic_phandles[socket];
-     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+-            *irq_pcie_phandle = xplic_phandles[socket];
-x1800, 0, 0, 0x7);
+-        }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
+-        if (socket == 1) {
-     plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
+-            *irq_virtio_phandle = xplic_phandles[socket];
-     plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
+-            *irq_pcie_phandle = xplic_phandles[socket];
-     qemu_fdt_add_subnode(mc->fdt, plic_name);
+-        }
--    qemu_fdt_setprop_cell(mc->fdt, plic_name,
+-        if (socket == 2) {
--        "#address-cells", FDT_PLIC_ADDR_CELLS);
+-            *irq_pcie_phandle = xplic_phandles[socket];
-     qemu_fdt_setprop_cell(mc->fdt, plic_name,
++    if (virt_use_kvm_aia(s)) {
-         "#interrupt-cells", FDT_PLIC_INT_CELLS);
++        *irq_mmio_phandle = xplic_phandles[0];
-     qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
++        *irq_virtio_phandle = xplic_phandles[0];
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
++        *irq_pcie_phandle = xplic_phandles[0];
-     g_free(plic_cells);
++    } else {
- }
++        for (socket = 0; socket < socket_count; socket++) {
++            if (socket == 0) {
-+static void create_fdt_socket_aia(RISCVVirtState *s,
++                *irq_mmio_phandle = xplic_phandles[socket];
-+                                  const MemMapEntry *memmap, int socket,
++                *irq_virtio_phandle = xplic_phandles[socket];
-+                                  uint32_t *phandle, uint32_t *intc_phandles,
++                *irq_pcie_phandle = xplic_phandles[socket];
-+                                  uint32_t *aplic_phandles)
++            }
-+{
++            if (socket == 1) {
-+    int cpu;
++                *irq_virtio_phandle = xplic_phandles[socket];
-+    char *aplic_name;
++                *irq_pcie_phandle = xplic_phandles[socket];
-+    uint32_t *aplic_cells;
++            }
-+    unsigned long aplic_addr;
++            if (socket == 2) {
-+    MachineState *mc = MACHINE(s);
++                *irq_pcie_phandle = xplic_phandles[socket];
-+    uint32_t aplic_m_phandle, aplic_s_phandle;
++            }
 +
 +    aplic_m_phandle = (*phandle)++;
 +    aplic_s_phandle = (*phandle)++;
 +    aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
 +
 +    /* M-level APLIC node */
 +    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
 +        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
 +    }
 +    aplic_addr = memmap[VIRT_APLIC_M].base +
 +                 (memmap[VIRT_APLIC_M].size * socket);
 +    aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
 +    qemu_fdt_add_subnode(mc->fdt, aplic_name);
 +    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
 +        "#interrupt-cells", FDT_APLIC_INT_CELLS);
 +    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
 +        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
 +        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
 +        VIRT_IRQCHIP_NUM_SOURCES);
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
 +        aplic_s_phandle);
 +    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
 +        aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
 +    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
 +    g_free(aplic_name);
 +
 +    /* S-level APLIC node */
 +    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
 +        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
 +    }
 +    aplic_addr = memmap[VIRT_APLIC_S].base +
 +                 (memmap[VIRT_APLIC_S].size * socket);
 +    aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
 +    qemu_fdt_add_subnode(mc->fdt, aplic_name);
 +    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
 +        "#interrupt-cells", FDT_APLIC_INT_CELLS);
 +    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
 +        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
 +        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
 +        VIRT_IRQCHIP_NUM_SOURCES);
 +    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
 +    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 +    g_free(aplic_name);
 +
 +    g_free(aplic_cells);
 +    aplic_phandles[socket] = aplic_s_phandle;
 +}
 +
  static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
                                 bool is_32_bit, uint32_t *phandle,
                                 uint32_t *irq_mmio_phandle,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
              }
          }
--        create_fdt_socket_plic(s, memmap, socket, phandle,
--            intc_phandles, xplic_phandles);
-+        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-+            create_fdt_socket_plic(s, memmap, socket, phandle,
-+                intc_phandles, xplic_phandles);
-+        } else {
-+            create_fdt_socket_aia(s, memmap, socket, phandle,
-+                intc_phandles, xplic_phandles);
-+        }
-         g_free(intc_phandles);
-         g_free(clust_name);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
-x0, memmap[VIRT_VIRTIO].size);
-         qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
-             irq_virtio_phandle);
--        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
-+        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-+            qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
-+                                  VIRTIO_IRQ + i);
-+        } else {
-+            qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
-+                                   VIRTIO_IRQ + i, 0x4);
-+        }
-         g_free(name);
      }
- }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-, virt_high_pcie_memmap.base,
+         }
-, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
+     }
--    create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
++    if (virt_use_kvm_aia(s)) {
-+    create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
++        kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
-     g_free(name);
++                             VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
- }
++                             memmap[VIRT_APLIC_S].base,
++                             memmap[VIRT_IMSIC_S].base,
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
++                             s->aia_guests);
 x0, memmap[VIRT_UART0].size);
      qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
      qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
 -    qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
 +    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
 +        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
 +    } else {
 +        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
 +    }
      qemu_fdt_add_subnode(mc->fdt, "/chosen");
      qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
 x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
      qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
          irq_mmio_phandle);
 -    qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
 +    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
 +        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
 +    } else {
 +        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
 +    }
      g_free(name);
  }
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
                                            hwaddr high_mmio_base,
                                            hwaddr high_mmio_size,
                                            hwaddr pio_base,
 -                                          DeviceState *plic)
 +                                          DeviceState *irqchip)
  {
      DeviceState *dev;
      MemoryRegion *ecam_alias, *ecam_reg;
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
      for (i = 0; i < GPEX_NUM_IRQS; i++) {
 -        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
 +        irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
          sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
          gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
      return fw_cfg;
  }
 +static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
 +                                     int base_hartid, int hart_count)
 +{
 +    DeviceState *ret;
 +    char *plic_hart_config;
 +
 +    /* Per-socket PLIC hart topology configuration string */
 +    plic_hart_config = riscv_plic_hart_config_string(hart_count);
 +
 +    /* Per-socket PLIC */
 +    ret = sifive_plic_create(
 +            memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
 +            plic_hart_config, hart_count, base_hartid,
 +            VIRT_IRQCHIP_NUM_SOURCES,
 +            ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
 +            VIRT_PLIC_PRIORITY_BASE,
 +            VIRT_PLIC_PENDING_BASE,
 +            VIRT_PLIC_ENABLE_BASE,
 +            VIRT_PLIC_ENABLE_STRIDE,
 +            VIRT_PLIC_CONTEXT_BASE,
 +            VIRT_PLIC_CONTEXT_STRIDE,
 +            memmap[VIRT_PLIC].size);
 +
 +    g_free(plic_hart_config);
 +
 +    return ret;
 +}
 +
 +static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
 +                                    const MemMapEntry *memmap, int socket,
 +                                    int base_hartid, int hart_count)
 +{
 +    DeviceState *aplic_m;
 +
 +    /* Per-socket M-level APLIC */
 +    aplic_m = riscv_aplic_create(
 +        memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
 +        memmap[VIRT_APLIC_M].size,
 +        base_hartid, hart_count,
 +        VIRT_IRQCHIP_NUM_SOURCES,
 +        VIRT_IRQCHIP_NUM_PRIO_BITS,
 +        false, true, NULL);
 +
 +    if (aplic_m) {
 +        /* Per-socket S-level APLIC */
 +        riscv_aplic_create(
 +            memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
 +            memmap[VIRT_APLIC_S].size,
 +            base_hartid, hart_count,
 +            VIRT_IRQCHIP_NUM_SOURCES,
 +            VIRT_IRQCHIP_NUM_PRIO_BITS,
 +            false, false, aplic_m);
 +    }
 +
-+    return aplic_m;
+     if (riscv_is_32bit(&s->soc[0])) {
-+}
+ #if HOST_LONG_BITS == 64
-+
+         /* limit RAM size in a 32-bit system */
  static void virt_machine_init(MachineState *machine)
  {
      const MemMapEntry *memmap = virt_memmap;
      RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
      MemoryRegion *system_memory = get_system_memory();
      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 -    char *plic_hart_config, *soc_name;
 +    char *soc_name;
      target_ulong start_addr = memmap[VIRT_DRAM].base;
      target_ulong firmware_end_addr, kernel_start_addr;
      uint32_t fdt_load_addr;
      uint64_t kernel_entry;
 -    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
 +    DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
      int i, base_hartid, hart_count;
      /* Check socket count limit */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      }
      /* Initialize sockets */
 -    mmio_plic = virtio_plic = pcie_plic = NULL;
 +    mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
      for (i = 0; i < riscv_socket_count(machine); i++) {
          if (!riscv_socket_check_hartids(machine, i)) {
              error_report("discontinuous hartids in socket%d", i);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
              }
          }
 -        /* Per-socket PLIC hart topology configuration string */
 -        plic_hart_config = riscv_plic_hart_config_string(hart_count);
 -
 -        /* Per-socket PLIC */
 -        s->plic[i] = sifive_plic_create(
 -            memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
 -            plic_hart_config, hart_count, base_hartid,
 -            VIRT_PLIC_NUM_SOURCES,
 -            VIRT_PLIC_NUM_PRIORITIES,
 -            VIRT_PLIC_PRIORITY_BASE,
 -            VIRT_PLIC_PENDING_BASE,
 -            VIRT_PLIC_ENABLE_BASE,
 -            VIRT_PLIC_ENABLE_STRIDE,
 -            VIRT_PLIC_CONTEXT_BASE,
 -            VIRT_PLIC_CONTEXT_STRIDE,
 -            memmap[VIRT_PLIC].size);
 -        g_free(plic_hart_config);
 +        /* Per-socket interrupt controller */
 +        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
 +            s->irqchip[i] = virt_create_plic(memmap, i,
 +                                             base_hartid, hart_count);
 +        } else {
 +            s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
 +                                            base_hartid, hart_count);
 +        }
 -        /* Try to use different PLIC instance based device type */
 +        /* Try to use different IRQCHIP instance based device type */
          if (i == 0) {
 -            mmio_plic = s->plic[i];
 -            virtio_plic = s->plic[i];
 -            pcie_plic = s->plic[i];
 +            mmio_irqchip = s->irqchip[i];
 +            virtio_irqchip = s->irqchip[i];
 +            pcie_irqchip = s->irqchip[i];
          }
          if (i == 1) {
 -            virtio_plic = s->plic[i];
 -            pcie_plic = s->plic[i];
 +            virtio_irqchip = s->irqchip[i];
 +            pcie_irqchip = s->irqchip[i];
          }
          if (i == 2) {
 -            pcie_plic = s->plic[i];
 +            pcie_irqchip = s->irqchip[i];
          }
      }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      for (i = 0; i < VIRTIO_COUNT; i++) {
          sysbus_create_simple("virtio-mmio",
              memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 -            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
 +            qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
      }
      gpex_pcie_init(system_memory,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                     virt_high_pcie_memmap.base,
                     virt_high_pcie_memmap.size,
                     memmap[VIRT_PCIE_PIO].base,
 -                   DEVICE(pcie_plic));
 +                   DEVICE(pcie_irqchip));
      serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 -        0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
 +        0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
          serial_hd(0), DEVICE_LITTLE_ENDIAN);
      sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
 -        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
 +        qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
      virt_flash_create(s);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
  {
  }
 +static char *virt_get_aia(Object *obj, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +    const char *val;
 +
 +    switch (s->aia_type) {
 +    case VIRT_AIA_TYPE_APLIC:
 +        val = "aplic";
 +        break;
 +    default:
 +        val = "none";
 +        break;
 +    };
 +
 +    return g_strdup(val);
 +}
 +
 +static void virt_set_aia(Object *obj, const char *val, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +
 +    if (!strcmp(val, "none")) {
 +        s->aia_type = VIRT_AIA_TYPE_NONE;
 +    } else if (!strcmp(val, "aplic")) {
 +        s->aia_type = VIRT_AIA_TYPE_APLIC;
 +    } else {
 +        error_setg(errp, "Invalid AIA interrupt controller type");
 +        error_append_hint(errp, "Valid values are none, and aplic.\n");
 +    }
 +}
 +
  static bool virt_get_aclint(Object *obj, Error **errp)
  {
      MachineState *ms = MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      object_class_property_set_description(oc, "aclint",
                                            "Set on/off to enable/disable "
                                            "emulating ACLINT devices");
 +
 +    object_class_property_add_str(oc, "aia", virt_get_aia,
 +                                  virt_set_aia);
 +    object_class_property_set_description(oc, "aia",
 +                                          "Set type of AIA interrupt "
 +                                          "conttoller. Valid values are "
 +                                          "none, and aplic.");
  }
  static const TypeInfo virt_machine_typeinfo = {
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PFLASH_CFI01
      select SERIAL
      select RISCV_ACLINT
 +    select RISCV_APLIC
      select SIFIVE_PLIC
      select SIFIVE_TEST
      select VIRTIO_MMIO
 --
-.34.1
+.41.0

-[PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs
+[PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path
-From: Anup Patel <anup.patel@wdc.com>
+From: Conor Dooley <conor.dooley@microchip.com>
-To facilitate software development of RISC-V systems with large number
+On a dtb dumped from the virt machine, dt-validate complains:
-of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
+soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
         from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
 That's pretty cryptic, but running the dtb back through dtc produces
 something a lot more reasonable:
 Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
-We also add a detailed source level comments about limit defines which
+Moving the riscv,pmu node out of the soc bus solves the problem.
 impact the physical address space utilization.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
 Message-id: 20220204174700.534953-24-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 +-
+ hw/riscv/virt.c | 2 +-
- hw/riscv/virt.c         | 10 ++++++++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 11 insertions(+), 1 deletion(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/block/flash.h"
- #include "qom/object.h"
--#define VIRT_CPUS_MAX_BITS             3
-+#define VIRT_CPUS_MAX_BITS             9
- #define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
- #define VIRT_SOCKETS_MAX_BITS          2
- #define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s)
- #include "hw/pci-host/gpex.h"
+     MachineState *ms = MACHINE(s);
- #include "hw/display/ramfb.h"
+     RISCVCPU hart = s->soc[0].harts[0];
-+/*
+-    pmu_name = g_strdup_printf("/soc/pmu");
-+ * The virt machine physical address space used by some of the devices
++    pmu_name = g_strdup_printf("/pmu");
-+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+     qemu_fdt_add_subnode(ms->fdt, pmu_name);
-+ * number of CPUs, and number of IMSIC guest files.
+     qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
-+ *
+     riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
 + * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
 + * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
 + * of virt machine physical address space.
 + */
 +
  #define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
  #if VIRT_IMSIC_GROUP_MAX_SIZE < \
      IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
 --
-.34.1
+.41.0

-[PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs
+[PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension
-From: Anup Patel <anup.patel@wdc.com>
+From: Weiwei Li <liweiwei@iscas.ac.cn>
-A hypervisor can optionally take guest external interrupts using
+The Svadu specification updated the name of the *envcfg bit from
-SGEIP bit of hip and hie CSRs.
+HADE to ADUE.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
 Message-id: 20220204174700.534953-3-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h |  3 +++
+ target/riscv/cpu_bits.h   |  8 ++++----
- target/riscv/cpu.c      |  3 ++-
+ target/riscv/cpu.c        |  4 ++--
- target/riscv/csr.c      | 18 +++++++++++-------
+ target/riscv/cpu_helper.c |  6 +++---
-files changed, 16 insertions(+), 8 deletions(-)
+ target/riscv/csr.c        | 12 ++++++------
 files changed, 15 insertions(+), 15 deletions(-)
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
 @@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- #define IRQ_S_EXT                          9
+ #define MENVCFG_CBIE                       (3UL << 4)
- #define IRQ_VS_EXT                         10
+ #define MENVCFG_CBCFE                      BIT(6)
- #define IRQ_M_EXT                          11
+ #define MENVCFG_CBZE                       BIT(7)
-+#define IRQ_S_GEXT                         12
+-#define MENVCFG_HADE                       (1ULL << 61)
-+#define IRQ_LOCAL_MAX                      16
++#define MENVCFG_ADUE                       (1ULL << 61)
+ #define MENVCFG_PBMTE                      (1ULL << 62)
- /* mip masks */
+ #define MENVCFG_STCE                       (1ULL << 63)
- #define MIP_USIP                           (1 << IRQ_U_SOFT)
  /* For RV32 */
 -#define MENVCFGH_HADE                      BIT(29)
 +#define MENVCFGH_ADUE                      BIT(29)
  #define MENVCFGH_PBMTE                     BIT(30)
  #define MENVCFGH_STCE                      BIT(31)
 @@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- #define MIP_SEIP                           (1 << IRQ_S_EXT)
+ #define HENVCFG_CBIE                       MENVCFG_CBIE
- #define MIP_VSEIP                          (1 << IRQ_VS_EXT)
+ #define HENVCFG_CBCFE                      MENVCFG_CBCFE
- #define MIP_MEIP                           (1 << IRQ_M_EXT)
+ #define HENVCFG_CBZE                       MENVCFG_CBZE
-+#define MIP_SGEIP                          (1 << IRQ_S_GEXT)
+-#define HENVCFG_HADE                       MENVCFG_HADE
++#define HENVCFG_ADUE                       MENVCFG_ADUE
- /* sip masks */
+ #define HENVCFG_PBMTE                      MENVCFG_PBMTE
- #define SIP_SSIP                           MIP_SSIP
+ #define HENVCFG_STCE                       MENVCFG_STCE
  /* For RV32 */
 -#define HENVCFGH_HADE                       MENVCFGH_HADE
 +#define HENVCFGH_ADUE                       MENVCFGH_ADUE
  #define HENVCFGH_PBMTE                      MENVCFGH_PBMTE
  #define HENVCFGH_STCE                       MENVCFGH_STCE
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
      env->two_stage_lookup = false;
      env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
 -                   (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
 +                   (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
      env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
 -                   (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
 +                   (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
      /* Initialized default priorities of local interrupts. */
      for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      }
      bool pbmte = env->menvcfg & MENVCFG_PBMTE;
 -    bool hade = env->menvcfg & MENVCFG_HADE;
 +    bool adue = env->menvcfg & MENVCFG_ADUE;
      if (first_stage && two_stage && env->virt_enabled) {
          pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
 -        hade = hade && (env->henvcfg & HENVCFG_HADE);
 +        adue = adue && (env->henvcfg & HENVCFG_ADUE);
      }
      int ptshift = (levels - 1) * ptidxbits;
@@ -XXX,XX +XXX,XX @@ restart:
      /* Page table updates need to be atomic with MTTCG enabled */
      if (updated_pte != pte && !is_debug) {
 -        if (!hade) {
 +        if (!adue) {
              return TRANSLATE_FAIL;
          }
-     }
-     env->mcause = 0;
-+    env->miclaim = MIP_SGEIP;
-     env->pc = env->resetvec;
-     env->two_stage_lookup = false;
-     /* mmte is supposed to have pm.current hardwired to 1 */
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
-     cpu_set_cpustate_pointers(cpu);
- #ifndef CONFIG_USER_ONLY
--    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
-+    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
- #endif /* CONFIG_USER_ONLY */
- }
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
- #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
+     if (riscv_cpu_mxl(env) == MXL_RV64) {
- #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
+         mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
- #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+                 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
-+#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
+-                (cfg->ext_svadu ? MENVCFG_HADE : 0);
++                (cfg->ext_svadu ? MENVCFG_ADUE : 0);
  static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                             VS_MODE_INTERRUPTS;
  static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
  static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 -                                     VS_MODE_INTERRUPTS;
 +                                     HS_MODE_INTERRUPTS;
  #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
                           (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
                           (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
  {
      env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
      if (riscv_has_ext(env, RVH)) {
 -        env->mideleg |= VS_MODE_INTERRUPTS;
 +        env->mideleg |= HS_MODE_INTERRUPTS;
      }
+     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
+     const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
+     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+-                    (cfg->ext_svadu ? MENVCFG_HADE : 0);
++                    (cfg->ext_svadu ? MENVCFG_ADUE : 0);
+     uint64_t valh = (uint64_t)val << 32;
+     env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
+      * henvcfg.stce is read_only 0 when menvcfg.stce = 0
+      * henvcfg.hade is read_only 0 when menvcfg.hade = 0
+      */
+-    *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
++    *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
+                            env->menvcfg);
      return RISCV_EXCP_NONE;
  }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
-                                 target_ulong val)
+     }
- {
-     env->mie = (env->mie & ~all_ints) | (val & all_ints);
+     if (riscv_cpu_mxl(env) == MXL_RV64) {
-+    if (!riscv_has_ext(env, RVH)) {
+-        mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
-+        env->mie &= ~MIP_SGEIP;
++        mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
-+    }
+     }
      env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
          return ret;
      }
 -    *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
 +    *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
                              env->menvcfg)) >> 32;
      return RISCV_EXCP_NONE;
  }
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
+                                      target_ulong val)
      }
      if (ret_value) {
 -        *ret_value &= env->mideleg;
 +        *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
      }
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
                        write_mask & hvip_writable_mask);
      if (ret_value) {
 -        *ret_value &= hvip_writable_mask;
 +        *ret_value &= VS_MODE_INTERRUPTS;
      }
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
                        write_mask & hip_writable_mask);
      if (ret_value) {
 -        *ret_value &= hip_writable_mask;
 +        *ret_value &= HS_MODE_INTERRUPTS;
      }
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
  static RISCVException read_hie(CPURISCVState *env, int csrno,
                                 target_ulong *val)
  {
--    *val = env->mie & VS_MODE_INTERRUPTS;
+     uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
-+    *val = env->mie & HS_MODE_INTERRUPTS;
+-                                    HENVCFG_HADE);
-     return RISCV_EXCP_NONE;
++                                    HENVCFG_ADUE);
- }
+     uint64_t valh = (uint64_t)val << 32;
+     RISCVException ret;
  static RISCVException write_hie(CPURISCVState *env, int csrno,
                                  target_ulong val)
  {
 -    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
 +    target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
      return write_mie(env, CSR_MIE, newval);
  }
 --
-.34.1
+.41.0

-[PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128
+[PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
-From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The addition of uxl support in gdbstub adds a few checks on the maximum
+In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
-register length, but omitted MXL_RV128, an experimental feature.
+longer to boot than the 'rv64' KVM CPU.
 This patch makes rv128 react as rv64, as previously.
-Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+when satp_mode.supported = 0, i.e. when cpu_init() does not set
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+satp_mode_max_supported(). satp_mode_max_from_map(map) does:
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
+- __builtin_clz(map)
 This means that, if satp_mode.supported = 0, satp_mode_supported_max
 wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly
 set it to UINT_MAX (4294967295). After that, if the user didn't set a
 satp_mode, set_satp_mode_default_map(cpu) will make
 cfg.satp_mode.map = cfg.satp_mode.supported
 So satp_mode.map = 0. And then satp_mode_map_max will be set to
 satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The
 guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us
 here since both are UINT_MAX.
 And finally we have 2 loops:
         for (int i = satp_mode_map_max - 1; i >= 0; --i) {
 Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the
 extra delay when booting the 'host' CPU is coming from.
 Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0
 in a different manner. We're doing the same here. If supported == 0,
 interpret as 'the CPU wants the OS to handle satp mode alone' and skip
 satp_mode_finalize().
 We'll also put a guard in satp_mode_max_from_map() to assert out if map
 is 0 since the function is not ready to deal with it.
 Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
 Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c     | 3 +--
+ target/riscv/cpu.c | 23 ++++++++++++++++++++---
- target/riscv/gdbstub.c | 3 +++
+file changed, 20 insertions(+), 3 deletions(-)
 files changed, 4 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static uint8_t satp_mode_from_str(const char *satp_mode_str)
-     switch (env->misa_mxl_max) {
- #ifdef TARGET_RISCV64
+ uint8_t satp_mode_max_from_map(uint32_t map)
-     case MXL_RV64:
+ {
--        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
++    /*
--        break;
++     * 'map = 0' will make us return (31 - 32), which C will
-     case MXL_RV128:
++     * happily overflow to UINT_MAX. There's no good result to
-+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
++     * return if 'map = 0' (e.g. returning 0 will be ambiguous
-         break;
++     * with the result for 'map = 1').
- #endif
++     *
-     case MXL_RV32:
++     * Assert out if map = 0. Callers will have to deal with
-diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
++     * it outside of this function.
-index XXXXXXX..XXXXXXX 100644
++     */
---- a/target/riscv/gdbstub.c
++    g_assert(map > 0);
-+++ b/target/riscv/gdbstub.c
++
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+     /* map here has at least one bit set, so no problem with clz */
-     case MXL_RV32:
+     return 31 - __builtin_clz(map);
-         return gdb_get_reg32(mem_buf, tmp);
+ }
-     case MXL_RV64:
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+    case MXL_RV128:
+ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
-         return gdb_get_reg64(mem_buf, tmp);
+ {
-     default:
+     bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
-         g_assert_not_reached();
+-    uint8_t satp_mode_map_max;
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+-    uint8_t satp_mode_supported_max =
-         length = 4;
+-                        satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
-         break;
++    uint8_t satp_mode_map_max, satp_mode_supported_max;
-     case MXL_RV64:
++
-+    case MXL_RV128:
++    /* The CPU wants the OS to decide which satp mode to use */
-         if (env->xl < MXL_RV64) {
++    if (cpu->cfg.satp_mode.supported == 0) {
-             tmp = (int32_t)ldq_p(mem_buf);
++        return;
-         } else {
++    }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
++
-, "riscv-32bit-virtual.xml", 0);
++    satp_mode_supported_max =
-         break;
++                    satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
-     case MXL_RV64:
-+    case MXL_RV128:
+     if (cpu->cfg.satp_mode.map == 0) {
-         gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+         if (cpu->cfg.satp_mode.init == 0) {
                                   riscv_gdb_set_virtual,
 , "riscv-64bit-virtual.xml", 0);
 --
-.34.1
+.41.0

-[PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART
+[PULL v2 37/45] riscv: zicond: make non-experimental
-From: Anup Patel <anup.patel@wdc.com>
+From: Vineet Gupta <vineetg@rivosinc.com>
-We add "x-aia" command-line option for RISC-V HART using which
+zicond is now codegen supported in both llvm and gcc.
 allows users to force enable CPU AIA CSRs without changing the
 interrupt controller available in RISC-V machine.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+This change allows seamless enabling/testing of zicond in downstream
-Signed-off-by: Anup Patel <anup@brainfault.org>
+projects. e.g. currently riscv-gnu-toolchain parses elf attributes
 to create a cmdline for qemu but fails short of enabling it because of
 the "x-" prefix.
 Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
 Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20220204174700.534953-18-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 1 +
+ target/riscv/cpu.c | 2 +-
- target/riscv/cpu.c | 5 +++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 6 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     bool mmu;
-     bool pmp;
-     bool epmp;
-+    bool aia;
-     uint64_t resetvec;
- };
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-         }
+     DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
-     }
+     DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
+     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
-+    if (cpu->cfg.aia) {
++    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
-+        riscv_set_feature(env, RISCV_FEATURE_AIA);
-+    }
+     /* Vendor-specific custom extensions */
-+
+     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-     set_resetvec(env, cpu->cfg.resetvec);
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
-     /* Validate that MISA_MXL is set properly. */
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     /* These are experimental so mark with 'x-' */
-     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+-    DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
      /* ePMP 0.9.3 */
      DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-+    DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
-     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
-     DEFINE_PROP_END_OF_LIST(),
 --
-.34.1
+.41.0

-[PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available
+[PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build
-From: Anup Patel <anup.patel@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We should use the AIA INTC compatible string in the CPU INTC
+A build with --enable-debug and without KVM will fail as follows:
 DT nodes when the CPUs support AIA feature. This will allow
 Linux INTC driver to use AIA local interrupt CSRs.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `virt_machine_init':
-Signed-off-by: Anup Patel <anup@brainfault.org>
+./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia_create'
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+This happens because the code block with "if virt_use_kvm_aia(s)" isn't
-Message-id: 20220204174700.534953-17-anup@brainfault.org
+being ignored by the debug build, resulting in an undefined reference to
 a KVM only function.
 Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will
 make the compiler crop the kvm_riscv_aia_create() call entirely from a
 non-KVM build. Note that adding the 'kvm_enabled()' conditional inside
 virt_use_kvm_aia() won't fix the build because this function would need
 to be inlined multiple times to make the compiler zero out the entire
 block.
 While we're at it, use kvm_enabled() in all instances where
 virt_use_kvm_aia() is checked to allow the compiler to elide these other
 kvm-only instances as well.
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 13 +++++++++++--
+ hw/riscv/virt.c | 6 +++---
-file changed, 11 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
-         qemu_fdt_add_subnode(mc->fdt, intc_name);
+     }
-         qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
-             intc_phandles[cpu]);
+     /* KVM AIA only has one APLIC instance */
--        qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+-    if (virt_use_kvm_aia(s)) {
--            "riscv,cpu-intc");
++    if (kvm_enabled() && virt_use_kvm_aia(s)) {
-+        if (riscv_feature(&s->soc[socket].harts[cpu].env,
+         create_fdt_socket_aplic(s, memmap, 0,
-+                          RISCV_FEATURE_AIA)) {
+                                 msi_m_phandle, msi_s_phandle, phandle,
-+            static const char * const compat[2] = {
+                                 &intc_phandles[0], xplic_phandles,
-+                "riscv,cpu-intc-aia", "riscv,cpu-intc"
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
-+            };
-+            qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
+     g_free(intc_phandles);
-+                                      (char **)&compat, ARRAY_SIZE(compat));
-+        } else {
+-    if (virt_use_kvm_aia(s)) {
-+            qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
++    if (kvm_enabled() && virt_use_kvm_aia(s)) {
-+                "riscv,cpu-intc");
+         *irq_mmio_phandle = xplic_phandles[0];
-+        }
+         *irq_virtio_phandle = xplic_phandles[0];
-         qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
+         *irq_pcie_phandle = xplic_phandles[0];
-         qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+         }
      }
 -    if (virt_use_kvm_aia(s)) {
 +    if (kvm_enabled() && virt_use_kvm_aia(s)) {
          kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
                               VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
                               memmap[VIRT_APLIC_S].base,
 --
-.34.1
+.41.0

-[PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs
+[PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
-From: Anup Patel <anup.patel@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The AIA specificaiton adds interrupt filtering support for M-mode
+Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
-and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
+environment with the following error:
 take local interrupt 13 or above and selectively inject same local
 interrupt to lower privilege modes.
-At the moment, we don't have any local interrupts above 12 so we
+/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request':
-add dummy implementation (i.e. read zero and ignore write) of AIA
+./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq'
-interrupt filtering CSRs.
+collect2: error: ld returned 1 exit status
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+This happens because the debug build will poke into the
-Signed-off-by: Anup Patel <anup@brainfault.org>
+'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+the KVM only function riscv_kvm_aplic_request().
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20220204174700.534953-13-anup@brainfault.org
+There are multiple solutions to fix this. We'll go with the same
 solution from the previous patch, i.e. add a kvm_enabled() conditional
 to filter out the block. But there's a catch: riscv_kvm_aplic_request()
 is a local function that would end up being used if the compiler crops
 the block, and this won't work. Quoting Richard Henderson's explanation
 in [1]:
 "(...) the compiler won't eliminate entire unused functions with -O0"
 We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its
 declaration in kvm_riscv.h, where all other KVM specific public
 functions are already declared. Other archs handles KVM specific code in
 this manner and we expect to do the same from now on.
 [1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 23 +++++++++++++++++++++++
+ target/riscv/kvm_riscv.h | 1 +
-file changed, 23 insertions(+)
+ hw/intc/riscv_aplic.c    | 8 ++------
  target/riscv/kvm.c       | 5 +++++
 files changed, 8 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/csr.c
++++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@ static RISCVException any32(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+                           uint64_t aia_irq_num, uint64_t aia_msi_num,
                            uint64_t aplic_base, uint64_t imsic_base,
                            uint64_t guest_num);
 +void riscv_kvm_aplic_request(void *opaque, int irq, int level);
  #endif
 diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/riscv_aplic.c
 +++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
  #include "target/riscv/cpu.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
 +#include "kvm_riscv.h"
  #include "migration/vmstate.h"
  #define APLIC_MAX_IDC                  (1UL << 14)
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
      return topi;
  }
-+static int aia_any(CPURISCVState *env, int csrno)
+-static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
 -{
 -    kvm_set_irq(kvm_state, irq, !!level);
 -}
 -
  static void riscv_aplic_request(void *opaque, int irq, int level)
  {
      bool update = false;
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
       * have IRQ lines delegated by their parent APLIC.
       */
      if (!aplic->parent) {
 -        if (is_kvm_aia(aplic->msimode)) {
 +        if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
              qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
          } else {
              qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/runstate.h"
  #include "hw/riscv/numa.h"
 +void riscv_kvm_aplic_request(void *opaque, int irq, int level)
 +{
-+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
++    kvm_set_irq(kvm_state, irq, !!level);
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    return any(env, csrno);
 +}
 +
- static int aia_any32(CPURISCVState *env, int csrno)
+ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                   uint64_t idx)
  {
-     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
-+static RISCVException write_ignore(CPURISCVState *env, int csrno,
-+                                   target_ulong val)
-+{
-+    return RISCV_EXCP_NONE;
-+}
-+
- static RISCVException read_mhartid(CPURISCVState *env, int csrno,
-                                    target_ulong *val)
- {
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
-     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
-+    /* Virtual Interrupts for Supervisor Level (AIA) */
-+    [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
-+    [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
-+
-     /* Machine-Level High-Half CSRs (AIA) */
-     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
-     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
-+    [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
-+    [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
-     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
-     /* Supervisor Trap Setup */
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
-     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
-+    [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
-     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
-     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
-     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
-     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
-     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
-+    [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
-     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
-     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
-     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
 --
-.34.1
+.41.0

-[PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
+[PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Robbin Ehn <rehn@rivosinc.com>
-As the number of extensions is growing, copying them individiually
+This patch adds the new extensions in
-into the DisasContext will scale less and less... instead we populate
+linux 6.5 to the hwprobe syscall.
 a pointer to the RISCVCPUConfig structure in the DisasContext.
-This adds an extra indirection when checking for the availability of
+And fixes RVC check to OR with correct value.
-an extension (compared to copying the fields into DisasContext).
+The previous variable contains 0 therefore it
-While not a performance problem today, we can always (shallow) copy
+did work.
 the entire structure into the DisasContext (instead of putting a
 pointer to it) if this is ever deemed necessary.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
 Message-Id: <20220202005249.3566542-3-philipp.tomsich@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 2 ++
+ linux-user/syscall.c | 14 +++++++++++++-
-file changed, 2 insertions(+)
+file changed, 13 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/linux-user/syscall.c b/linux-user/syscall.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/linux-user/syscall.c
-+++ b/target/riscv/translate.c
++++ b/linux-user/syscall.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
-     int frm;
+ #define RISCV_HWPROBE_KEY_IMA_EXT_0     4
-     RISCVMXL ol;
+ #define     RISCV_HWPROBE_IMA_FD       (1 << 0)
-     bool virt_enabled;
+ #define     RISCV_HWPROBE_IMA_C        (1 << 1)
-+    const RISCVCPUConfig *cfg_ptr;
++#define     RISCV_HWPROBE_IMA_V        (1 << 2)
-     bool ext_ifencei;
++#define     RISCV_HWPROBE_EXT_ZBA      (1 << 3)
-     bool ext_zfh;
++#define     RISCV_HWPROBE_EXT_ZBB      (1 << 4)
-     bool ext_zfhmin;
++#define     RISCV_HWPROBE_EXT_ZBS      (1 << 5)
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- #endif
+ #define RISCV_HWPROBE_KEY_CPUPERF_0     5
-     ctx->misa_ext = env->misa_ext;
+ #define     RISCV_HWPROBE_MISALIGNED_UNKNOWN     (0 << 0)
-     ctx->frm = -1;  /* unknown rounding mode */
+@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
-+    ctx->cfg_ptr = &(cpu->cfg);
+                     riscv_has_ext(env, RVD) ?
-     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+                     RISCV_HWPROBE_IMA_FD : 0;
-     ctx->ext_zfh = cpu->cfg.ext_zfh;
+             value |= riscv_has_ext(env, RVC) ?
-     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+-                     RISCV_HWPROBE_IMA_C : pair->value;
 +                     RISCV_HWPROBE_IMA_C : 0;
 +            value |= riscv_has_ext(env, RVV) ?
 +                     RISCV_HWPROBE_IMA_V : 0;
 +            value |= cfg->ext_zba ?
 +                     RISCV_HWPROBE_EXT_ZBA : 0;
 +            value |= cfg->ext_zbb ?
 +                     RISCV_HWPROBE_EXT_ZBB : 0;
 +            value |= cfg->ext_zbs ?
 +                     RISCV_HWPROBE_EXT_ZBS : 0;
              __put_user(value, &pair->value);
              break;
          case RISCV_HWPROBE_KEY_CPUPERF_0:
 --
-.34.1
+.41.0

-[PULL 15/40] target/riscv: Improve delivery of guest external interrupts
+[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I
-From: Anup Patel <anup.patel@wdc.com>
+From: Ard Biesheuvel <ardb@kernel.org>
-The guest external interrupts from an interrupt controller are
+Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
-delivered only when the Guest/VM is running (i.e. V=1). This means
+implement the first half of the key schedule derivation. This does not
-any guest external interrupt which is triggered while the Guest/VM
+actually involve shifting rows, so clone the same value into all four
-is not running (i.e. V=0) will be missed on QEMU resulting in Guest
+columns of the AES vector to counter that operation.
 with sluggish response to serial console input and other I/O events.
-To solve this, we check and inject interrupt after setting V=1.
+Cc: Richard Henderson <richard.henderson@linaro.org>
+Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Cc: Palmer Dabbelt <palmer@dabbelt.com>
-Signed-off-by: Anup Patel <anup@brainfault.org>
+Cc: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20220204174700.534953-5-anup@brainfault.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20230831154118.138727-1-ardb@kernel.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 13 +++++++++++++
+ target/riscv/crypto_helper.c | 17 +++++------------
-file changed, 13 insertions(+)
+file changed, 5 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/crypto_helper.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/crypto_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
      uint8_t enc_rnum = rnum;
      uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
 -    uint8_t rcon_ = 0;
 -    target_ulong result;
 +    AESState t, rc = {};
      if (enc_rnum != 0xA) {
          temp = ror32(temp, 8); /* Rotate right by 8 */
 -        rcon_ = round_consts[enc_rnum];
 +        rc.w[0] = rc.w[1] = round_consts[enc_rnum];
      }
-     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+-    temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
-+
+-           ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
-+    if (enable) {
+-           ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
-+        /*
+-           ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
-+         * The guest external interrupts from an interrupt controller are
++    t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp;
-+         * delivered only when the Guest/VM is running (i.e. V=1). This means
++    aesenc_SB_SR_AK(&t, &t, &rc, false);
-+         * any guest external interrupt which is triggered while the Guest/VM
-+         * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+-    temp ^= rcon_;
-+         * with sluggish response to serial console input and other I/O events.
+-
-+         *
+-    result = ((uint64_t)temp << 32) | temp;
-+         * To solve this, we check and inject interrupt after setting V=1.
+-
-+         */
+-    return result;
-+        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
++    return t.d[0];
 +    }
  }
- bool riscv_cpu_two_stage_lookup(int mmu_idx)
+ target_ulong HELPER(aes64im)(target_ulong rs1)
 --
-.34.1
+.41.0

-[PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback
+[PULL v2 42/45] target/riscv: Allocate itrigger timers only once
-From: Anup Patel <anup.patel@wdc.com>
+From: Akihiko Odaki <akihiko.odaki@daynix.com>
-The AIA device emulation (such as AIA IMSIC) should be able to set
+riscv_trigger_init() had been called on reset events that can happen
-(or provide) AIA ireg read-modify-write callback for each privilege
+several times for a CPU and it allocated timers for itrigger. If old
-level of a RISC-V HART.
+timers were present, they were simply overwritten by the new timers,
 resulting in a memory leak.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Divide riscv_trigger_init() into two functions, namely
-Signed-off-by: Anup Patel <anup@brainfault.org>
+riscv_trigger_realize() and riscv_trigger_reset() and call them in
 appropriate timing. The timer allocation will happen only once for a
 CPU in riscv_trigger_realize().
 Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
 Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
 Message-id: 20220204174700.534953-9-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 23 +++++++++++++++++++++++
+ target/riscv/debug.h |  3 ++-
- target/riscv/cpu_helper.c | 14 ++++++++++++++
+ target/riscv/cpu.c   |  8 +++++++-
-files changed, 37 insertions(+)
+ target/riscv/debug.c | 15 ++++++++++++---
 files changed, 21 insertions(+), 5 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/debug.h b/target/riscv/debug.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/debug.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/debug.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
-     uint64_t (*rdtime_fn)(uint32_t);
+ bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
-     uint32_t rdtime_fn_arg;
+ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
-+    /* machine specific AIA ireg read-modify-write callback */
+-void riscv_trigger_init(CPURISCVState *env);
-+#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
++void riscv_trigger_realize(CPURISCVState *env);
-+    ((((__xlen) & 0xff) << 24) | \
++void riscv_trigger_reset_hold(CPURISCVState *env);
-+     (((__vgein) & 0x3f) << 20) | \
-+     (((__virt) & 0x1) << 18) | \
+ bool riscv_itrigger_enabled(CPURISCVState *env);
-+     (((__priv) & 0x3) << 16) | \
+ void riscv_itrigger_update_priv(CPURISCVState *env);
-+     (__isel & 0xffff))
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-+#define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
+index XXXXXXX..XXXXXXX 100644
-+#define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
+--- a/target/riscv/cpu.c
-+#define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
++++ b/target/riscv/cpu.c
-+#define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
-+#define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
-+    int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
+ #ifndef CONFIG_USER_ONLY
-+        target_ulong *val, target_ulong new_val, target_ulong write_mask);
+     if (cpu->cfg.debug) {
-+    void *aia_ireg_rmw_fn_arg[4];
+-        riscv_trigger_init(env);
 +        riscv_trigger_reset_hold(env);
      }
      if (kvm_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      riscv_cpu_register_gdb_regs_for_features(cs);
 +#ifndef CONFIG_USER_ONLY
 +    if (cpu->cfg.debug) {
 +        riscv_trigger_realize(&cpu->env);
 +    }
 +#endif
 +
-     /* True if in debugger mode.  */
+     qemu_init_vcpu(cs);
-     bool debugger;
+     cpu_reset(cs);
-@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
  #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
  void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
                               uint32_t arg);
 +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
 +                                   int (*rmw_fn)(void *arg,
 +                                                 target_ulong reg,
 +                                                 target_ulong *val,
 +                                                 target_ulong new_val,
 +                                                 target_ulong write_mask),
 +                                   void *rmw_fn_arg);
  #endif
  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/debug.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
-     env->rdtime_fn_arg = arg;
+     return false;
  }
-+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+-void riscv_trigger_init(CPURISCVState *env)
-+                                   int (*rmw_fn)(void *arg,
++void riscv_trigger_realize(CPURISCVState *env)
 +                                                 target_ulong reg,
 +                                                 target_ulong *val,
 +                                                 target_ulong new_val,
 +                                                 target_ulong write_mask),
 +                                   void *rmw_fn_arg)
 +{
-+    if (priv <= PRV_M) {
++    int i;
-+        env->aia_ireg_rmw_fn[priv] = rmw_fn;
++
-+        env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
++    for (i = 0; i < RV_MAX_TRIGGERS; i++) {
 +        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 +                                              riscv_itrigger_timer_cb, env);
 +    }
 +}
 +
- void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
++void riscv_trigger_reset_hold(CPURISCVState *env)
  {
-     if (newpriv > PRV_M) {
+     target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
      int i;
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
          env->tdata3[i] = 0;
          env->cpu_breakpoint[i] = NULL;
          env->cpu_watchpoint[i] = NULL;
 -        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 -                                              riscv_itrigger_timer_cb, env);
 +        timer_del(env->itrigger_timer[i]);
      }
  }
 --
-.34.1
+.41.0

-[PULL 01/40] include: hw: remove ibex_plic.h
+[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+From: Leon Schuermann <leons@opentitan.org>
-This patch removes the left-over/unused `ibex_plic.h` file. Previously
+When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
-used by opentitan, which now follows the RISC-V standard and uses the
+configuration lock bits must not apply. While this behavior is
-SiFivePlicState.
+implemented for the pmpcfgX CSRs, this bit is not respected for
 changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
 writes work even on locked regions when the global rule-lock bypass is
 enabled.
-Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
+Signed-off-by: Leon Schuermann <leons@opentitan.org>
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
 Message-id: 20220121055005.3159846-1-alistair.francis@opensource.wdc.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/intc/ibex_plic.h | 67 -------------------------------------
+ target/riscv/pmp.c | 4 ++++
-file changed, 67 deletions(-)
+file changed, 4 insertions(+)
  delete mode 100644 include/hw/intc/ibex_plic.h
-diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-deleted file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/pmp.c
---- a/include/hw/intc/ibex_plic.h
++++ b/target/riscv/pmp.c
-+++ /dev/null
+@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
-@@ -XXX,XX +XXX,XX @@
+  */
--/*
+ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
-- * QEMU RISC-V lowRISC Ibex PLIC
+ {
-- *
++    /* mseccfg.RLB is set */
-- * Copyright (c) 2020 Western Digital
++    if (MSECCFG_RLB_ISSET(env)) {
-- *
++        return 0;
-- * This program is free software; you can redistribute it and/or modify it
++    }
-- * under the terms and conditions of the GNU General Public License,
-- * version 2 or later, as published by the Free Software Foundation.
+     if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
-- *
+         return 1;
 - * This program is distributed in the hope it will be useful, but WITHOUT
 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 - * more details.
 - *
 - * You should have received a copy of the GNU General Public License along with
 - * this program.  If not, see <http://www.gnu.org/licenses/>.
 - */
 -
 -#ifndef HW_IBEX_PLIC_H
 -#define HW_IBEX_PLIC_H
 -
 -#include "hw/sysbus.h"
 -#include "qom/object.h"
 -
 -#define TYPE_IBEX_PLIC "ibex-plic"
 -OBJECT_DECLARE_SIMPLE_TYPE(IbexPlicState, IBEX_PLIC)
 -
 -struct IbexPlicState {
 -    /*< private >*/
 -    SysBusDevice parent_obj;
 -
 -    /*< public >*/
 -    MemoryRegion mmio;
 -
 -    uint32_t *pending;
 -    uint32_t *hidden_pending;
 -    uint32_t *claimed;
 -    uint32_t *source;
 -    uint32_t *priority;
 -    uint32_t *enable;
 -    uint32_t threshold;
 -    uint32_t claim;
 -
 -    /* config */
 -    uint32_t num_cpus;
 -    uint32_t num_sources;
 -
 -    uint32_t pending_base;
 -    uint32_t pending_num;
 -
 -    uint32_t source_base;
 -    uint32_t source_num;
 -
 -    uint32_t priority_base;
 -    uint32_t priority_num;
 -
 -    uint32_t enable_base;
 -    uint32_t enable_num;
 -
 -    uint32_t threshold_base;
 -
 -    uint32_t claim_base;
 -
 -    qemu_irq *external_irqs;
 -};
 -
 -#endif /* HW_IBEX_PLIC_H */
 --
-.34.1
+.41.0

-[PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs
+[PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified spec
-From: Anup Patel <anup.patel@wdc.com>
+From: Tommy Wu <tommy.wu@sifive.com>
-The AIA hvictl and hviprioX CSRs allow hypervisor to control
+According to the new spec, when vsiselect has a reserved value, attempts
-interrupts visible at VS-level. This patch implements AIA hvictl
+from M-mode or HS-mode to access vsireg, or from VS-mode to access
-and hviprioX CSRs.
+sireg, should preferably raise an illegal instruction exception.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
 Signed-off-by: Anup Patel <anup@brainfault.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20220204174700.534953-12-anup@brainfault.org
+Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
 [ Changes by AF:
  - Fix possible unintilised variable error in rmw_sie()
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h     |   2 +
+ target/riscv/csr.c | 7 +++++--
- target/riscv/csr.c     | 128 ++++++++++++++++++++++++++++++++++++++++-
+file changed, 5 insertions(+), 2 deletions(-)
  target/riscv/machine.c |   2 +
 files changed, 131 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     uint64_t htimedelta;
-     /* Hypervisor controlled virtual interrupt priorities */
-+    target_ulong hvictl;
-     uint8_t hviprio[64];
-     /* Upper 64-bits of 128-bit CSRs */
-@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
-     return env->misa_mxl;
- }
- #endif
-+#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
- #if defined(TARGET_RISCV32)
- #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static int rmw_iprio(target_ulong xlen,
-     return RISCV_EXCP_ILLEGAL_INST;
+ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
- }
+                      target_ulong new_val, target_ulong wr_mask)
 +static int aia_hmode(CPURISCVState *env, int csrno)
 +{
 +    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +     }
 +
 +     return hmode(env, csrno);
 +}
 +
  static int aia_hmode32(CPURISCVState *env, int csrno)
  {
-     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+-    bool virt;
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
++    bool virt, isel_reserved;
-     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
+     uint8_t *iprio;
+     int ret = -EINVAL;
-     if (riscv_cpu_virt_enabled(env)) {
+     target_ulong priv, isel, vgein;
-+        if (env->hvictl & HVICTL_VTI) {
+@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
-+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+        }
+     /* Decode register details from CSR number */
-         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
+     virt = false;
-     } else {
++    isel_reserved = false;
-         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
+     switch (csrno) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sie(CPURISCVState *env, int csrno,
+     case CSR_MIREG:
-     RISCVException ret;
+         iprio = env->miprio;
+@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
-     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
+                                                   riscv_cpu_mxl_bits(env)),
--    if (ret_val) {
+                                     val, new_val, wr_mask);
-+    if (ret == RISCV_EXCP_NONE && ret_val) {
+         }
-         *ret_val = rval;
++    } else {
 +        isel_reserved = true;
      }
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
+ done:
-     uint64_t mask = env->mideleg & sip_writable_mask;
+     if (ret) {
+-        return (env->virt_enabled && virt) ?
-     if (riscv_cpu_virt_enabled(env)) {
++        return (env->virt_enabled && virt && !isel_reserved) ?
-+        if (env->hvictl & HVICTL_VTI) {
+                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
-+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+     }
 +        }
          ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
      } else {
          ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
- }
-+static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
-+{
-+    *val = env->hvictl;
-+    return RISCV_EXCP_NONE;
-+}
-+
-+static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
-+{
-+    env->hvictl = val & HVICTL_VALID_MASK;
-+    return RISCV_EXCP_NONE;
-+}
-+
-+static int read_hvipriox(CPURISCVState *env, int first_index,
-+                         uint8_t *iprio, target_ulong *val)
-+{
-+    int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
-+
-+    /* First index has to be a multiple of number of irqs per register */
-+    if (first_index % num_irqs) {
-+        return (riscv_cpu_virt_enabled(env)) ?
-+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
-+    }
-+
-+    /* Fill-up return value */
-+    *val = 0;
-+    for (i = 0; i < num_irqs; i++) {
-+        if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
-+            continue;
-+        }
-+        if (rdzero) {
-+            continue;
-+        }
-+        *val |= ((target_ulong)iprio[irq]) << (i * 8);
-+    }
-+
-+    return RISCV_EXCP_NONE;
-+}
-+
-+static int write_hvipriox(CPURISCVState *env, int first_index,
-+                          uint8_t *iprio, target_ulong val)
-+{
-+    int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
-+
-+    /* First index has to be a multiple of number of irqs per register */
-+    if (first_index % num_irqs) {
-+        return (riscv_cpu_virt_enabled(env)) ?
-+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
-+    }
-+
-+    /* Fill-up priority arrary */
-+    for (i = 0; i < num_irqs; i++) {
-+        if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
-+            continue;
-+        }
-+        if (rdzero) {
-+            iprio[irq] = 0;
-+        } else {
-+            iprio[irq] = (val >> (i * 8)) & 0xff;
-+        }
-+    }
-+
-+    return RISCV_EXCP_NONE;
-+}
-+
-+static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
-+{
-+    return read_hvipriox(env, 0, env->hviprio, val);
-+}
-+
-+static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
-+{
-+    return write_hvipriox(env, 0, env->hviprio, val);
-+}
-+
-+static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
-+{
-+    return read_hvipriox(env, 4, env->hviprio, val);
-+}
-+
-+static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
-+{
-+    return write_hvipriox(env, 4, env->hviprio, val);
-+}
-+
-+static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
-+{
-+    return read_hvipriox(env, 8, env->hviprio, val);
-+}
-+
-+static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
-+{
-+    return write_hvipriox(env, 8, env->hviprio, val);
-+}
-+
-+static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
-+{
-+    return read_hvipriox(env, 12, env->hviprio, val);
-+}
-+
-+static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
-+{
-+    return write_hvipriox(env, 12, env->hviprio, val);
-+}
-+
- /* Virtual CSR Registers */
- static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
-                                     target_ulong *val)
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
-     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
-+    /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
-+    [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
-+    [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
-+    [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
-+
-     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
-     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
-     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
-+    [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
-+    [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
-     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
-     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
-diff --git a/target/riscv/machine.c b/target/riscv/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/machine.c
-+++ b/target/riscv/machine.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
-         VMSTATE_UINTTL(env.hgeie, RISCVCPU),
-         VMSTATE_UINTTL(env.hgeip, RISCVCPU),
-         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
-+
-+        VMSTATE_UINTTL(env.hvictl, RISCVCPU),
-         VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
-         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
 --
-.34.1
+.41.0

-[PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
+[PULL v2 45/45] target/riscv: don't read CSR in riscv_csrrw_do64
-From: Anup Patel <anup.patel@wdc.com>
+From: Nikita Shubin <n.shubin@yadro.com>
-We should be returning illegal instruction trap when RV64 HS-mode tries
+As per ISA:
 to access RV32 HS-mode CSR.
-Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
+"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+shall not cause any of the side effects that might occur on a CSR read."
-Signed-off-by: Anup Patel <anup@brainfault.org>
 trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
 riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.
 Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Message-id: 20220204174700.534953-2-anup@brainfault.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/csr.c | 24 +++++++++++++++---------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 15 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
- static RISCVException hmode32(CPURISCVState *env, int csrno)
+                                        target_ulong write_mask)
  {
-     if (riscv_cpu_mxl(env) != MXL_RV32) {
+     RISCVException ret;
--        if (riscv_cpu_virt_enabled(env)) {
+-    target_ulong old_value;
-+        if (!riscv_cpu_virt_enabled(env)) {
++    target_ulong old_value = 0;
-             return RISCV_EXCP_ILLEGAL_INST;
-         } else {
+     /* execute combined read/write operation if it exists */
-             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+     if (csr_ops[csrno].op) {
          return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
      }
 -    /* if no accessor exists then return failure */
 -    if (!csr_ops[csrno].read) {
 -        return RISCV_EXCP_ILLEGAL_INST;
 -    }
 -    /* read old value */
 -    ret = csr_ops[csrno].read(env, csrno, &old_value);
 -    if (ret != RISCV_EXCP_NONE) {
 -        return ret;
 +    /*
 +     * ret_value == NULL means that rd=x0 and we're coming from helper_csrw()
 +     * and we can't throw side effects caused by CSR reads.
 +     */
 +    if (ret_value) {
 +        /* if no accessor exists then return failure */
 +        if (!csr_ops[csrno].read) {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +        /* read old value */
 +        ret = csr_ops[csrno].read(env, csrno, &old_value);
 +        if (ret != RISCV_EXCP_NONE) {
 +            return ret;
 +        }
      }
      /* write value if writable and write mask set, otherwise drop writes */
 --
-.34.1
+.41.0

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212

for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:

docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 7.0

* Remove old Ibex PLIC header file
 * Allow writing 8 bytes with generic loader
 * Fixes for RV128
 * Refactor RISC-V CPU configs
 * Initial support for XVentanaCondOps custom extension
 * Fix for vill field in vtype
 * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
 * RISC-V AIA support for virt machine
 * Support for svnapot, svinval and svpbmt extensions

----------------------------------------------------------------
Anup Patel (23):
      target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
      target/riscv: Implement SGEIP bit in hip and hie CSRs
      target/riscv: Implement hgeie and hgeip CSRs
      target/riscv: Improve delivery of guest external interrupts
      target/riscv: Allow setting CPU feature from machine/device emulation
      target/riscv: Add AIA cpu feature
      target/riscv: Add defines for AIA CSRs
      target/riscv: Allow AIA device emulation to set ireg rmw callback
      target/riscv: Implement AIA local interrupt priorities
      target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
      target/riscv: Implement AIA hvictl and hviprioX CSRs
      target/riscv: Implement AIA interrupt filtering CSRs
      target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
      target/riscv: Implement AIA xiselect and xireg CSRs
      target/riscv: Implement AIA IMSIC interface CSRs
      hw/riscv: virt: Use AIA INTC compatible string when available
      target/riscv: Allow users to force enable AIA CSRs in HART
      hw/intc: Add RISC-V AIA APLIC device emulation
      hw/riscv: virt: Add optional AIA APLIC support to virt machine
      hw/intc: Add RISC-V AIA IMSIC device emulation
      hw/riscv: virt: Add optional AIA IMSIC support to virt machine
      docs/system: riscv: Document AIA options for virt machine
      hw/riscv: virt: Increase maximum number of allowed CPUs

Frédéric Pétrot (1):
      target/riscv: correct "code should not be reached" for x-rv128

Guo Ren (1):
      target/riscv: Ignore reserved bits in PTE for RV64

LIU Zhiwei (1):
      target/riscv: Fix vill field write in vtype

Petr Tesarik (1):
      Allow setting up to 8 bytes with the generic loader

Philipp Tomsich (7):
      target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
      target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
      target/riscv: access configuration through cfg_ptr in DisasContext
      target/riscv: access cfg structure through DisasContext
      target/riscv: iterate over a table of decoders
      target/riscv: Add XVentanaCondOps custom extension
      target/riscv: add a MAINTAINERS entry for XVentanaCondOps

Weiwei Li (4):
      target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
      target/riscv: add support for svnapot extension
      target/riscv: add support for svinval extension
      target/riscv: add support for svpbmt extension

Wilfred Mallawa (1):
      include: hw: remove ibex_plic.h

Yu Li (1):
      docs/system: riscv: Update description of CPU

docs/system/riscv/virt.rst                         |   22 +-
 include/hw/intc/ibex_plic.h                        |   67 -
 include/hw/intc/riscv_aplic.h                      |   79 ++
 include/hw/intc/riscv_imsic.h                      |   68 ++
 include/hw/riscv/virt.h                            |   41 +-
 target/riscv/cpu.h                                 |  169 ++-
 target/riscv/cpu_bits.h                            |  129 ++
 target/riscv/XVentanaCondOps.decode                |   25 +
 target/riscv/insn32.decode                         |    7 +
 hw/core/generic-loader.c                           |    2 +-
 hw/intc/riscv_aplic.c                              |  978 +++++++++++++++
 hw/intc/riscv_imsic.c                              |  448 +++++++
 hw/riscv/virt.c                                    |  712 +++++++++--
 target/riscv/cpu.c                                 |  113 +-
 target/riscv/cpu_helper.c                          |  377 +++++-
 target/riscv/csr.c                                 | 1282 ++++++++++++++++++--
 target/riscv/gdbstub.c                             |    3 +
 target/riscv/machine.c                             |   24 +-
 target/riscv/translate.c                           |   61 +-
 target/riscv/vector_helper.c                       |    1 +
 target/riscv/insn_trans/trans_rvb.c.inc            |    8 +-
 target/riscv/insn_trans/trans_rvi.c.inc            |    2 +-
 target/riscv/insn_trans/trans_rvv.c.inc            |  146 ++-
 target/riscv/insn_trans/trans_rvzfh.c.inc          |    4 +-
 target/riscv/insn_trans/trans_svinval.c.inc        |   75 ++
 .../riscv/insn_trans/trans_xventanacondops.c.inc   |   39 +
 MAINTAINERS                                        |    7 +
 hw/intc/Kconfig                                    |    6 +
 hw/intc/meson.build                                |    2 +
 hw/riscv/Kconfig                                   |    2 +
 target/riscv/meson.build                           |    1 +
 31 files changed, 4409 insertions(+), 491 deletions(-)
 delete mode 100644 include/hw/intc/ibex_plic.h
 create mode 100644 include/hw/intc/riscv_aplic.h
 create mode 100644 include/hw/intc/riscv_imsic.h
 create mode 100644 target/riscv/XVentanaCondOps.decode
 create mode 100644 hw/intc/riscv_aplic.c
 create mode 100644 hw/intc/riscv_imsic.c
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
 create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This patch removes the left-over/unused `ibex_plic.h` file. Previously
used by opentitan, which now follows the RISC-V standard and uses the
SiFivePlicState.

Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220121055005.3159846-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/ibex_plic.h | 67 -------------------------------------
 1 file changed, 67 deletions(-)
 delete mode 100644 include/hw/intc/ibex_plic.h

diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/include/hw/intc/ibex_plic.h
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_IBEX_PLIC_H
-#define HW_IBEX_PLIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IBEX_PLIC "ibex-plic"
-OBJECT_DECLARE_SIMPLE_TYPE(IbexPlicState, IBEX_PLIC)
-
-struct IbexPlicState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-
-    uint32_t *pending;
-    uint32_t *hidden_pending;
-    uint32_t *claimed;
-    uint32_t *source;
-    uint32_t *priority;
-    uint32_t *enable;
-    uint32_t threshold;
-    uint32_t claim;
-
-    /* config */
-    uint32_t num_cpus;
-    uint32_t num_sources;
-
-    uint32_t pending_base;
-    uint32_t pending_num;
-
-    uint32_t source_base;
-    uint32_t source_num;
-
-    uint32_t priority_base;
-    uint32_t priority_num;
-
-    uint32_t enable_base;
-    uint32_t enable_num;
-
-    uint32_t threshold_base;
-
-    uint32_t claim_base;
-
-    qemu_irq *external_irqs;
-};
-
-#endif /* HW_IBEX_PLIC_H */
-- 
2.34.1

From: Petr Tesarik <ptesarik@suse.com>

The documentation for the generic loader says that "the maximum size of
the data is 8 bytes". However, attempts to set data-len=8 trigger the
following assertion failure:

../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len < sizeof(s->data)' failed.

The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this
assert should use <= instead of <.

Fixes: e481a1f63c93 ("generic-loader: Add a generic loader")
Signed-off-by: Petr Tesarik <ptesarik@suse.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120092715.7805-1-ptesarik@suse.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/core/generic-loader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -XXX,XX +XXX,XX @@ static void generic_loader_reset(void *opaque)
     }
 
     if (s->data_len) {
-        assert(s->data_len < sizeof(s->data));
+        assert(s->data_len <= sizeof(s->data));
         dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len,
                          MEMTXATTRS_UNSPECIFIED);
     }
-- 
2.34.1

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c     | 3 +--
 target/riscv/gdbstub.c | 3 +++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     switch (env->misa_mxl_max) {
 #ifdef TARGET_RISCV64
     case MXL_RV64:
-        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-        break;
     case MXL_RV128:
+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
         break;
 #endif
     case MXL_RV32:
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
     case MXL_RV32:
         return gdb_get_reg32(mem_buf, tmp);
     case MXL_RV64:
+    case MXL_RV128:
         return gdb_get_reg64(mem_buf, tmp);
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         length = 4;
         break;
     case MXL_RV64:
+    case MXL_RV128:
         if (env->xl < MXL_RV64) {
             tmp = (int32_t)ldq_p(mem_buf);
         } else {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  1, "riscv-32bit-virtual.xml", 0);
         break;
     case MXL_RV64:
+    case MXL_RV128:
         gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
                                  riscv_gdb_set_virtual,
                                  1, "riscv-64bit-virtual.xml", 0);
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 78 ++++++++++++++++++++++++----------------------
 1 file changed, 41 insertions(+), 37 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUClass {
     DeviceReset parent_reset;
 };
 
+struct RISCVCPUConfig {
+    bool ext_i;
+    bool ext_e;
+    bool ext_g;
+    bool ext_m;
+    bool ext_a;
+    bool ext_f;
+    bool ext_d;
+    bool ext_c;
+    bool ext_s;
+    bool ext_u;
+    bool ext_h;
+    bool ext_j;
+    bool ext_v;
+    bool ext_zba;
+    bool ext_zbb;
+    bool ext_zbc;
+    bool ext_zbs;
+    bool ext_counters;
+    bool ext_ifencei;
+    bool ext_icsr;
+    bool ext_zfh;
+    bool ext_zfhmin;
+    bool ext_zve32f;
+    bool ext_zve64f;
+
+    char *priv_spec;
+    char *user_spec;
+    char *bext_spec;
+    char *vext_spec;
+    uint16_t vlen;
+    uint16_t elen;
+    bool mmu;
+    bool pmp;
+    bool epmp;
+    uint64_t resetvec;
+};
+
+typedef struct RISCVCPUConfig RISCVCPUConfig;
+
 /**
  * RISCVCPU:
  * @env: #CPURISCVState
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
     char *dyn_vreg_xml;
 
     /* Configuration Settings */
-    struct {
-        bool ext_i;
-        bool ext_e;
-        bool ext_g;
-        bool ext_m;
-        bool ext_a;
-        bool ext_f;
-        bool ext_d;
-        bool ext_c;
-        bool ext_s;
-        bool ext_u;
-        bool ext_h;
-        bool ext_j;
-        bool ext_v;
-        bool ext_zba;
-        bool ext_zbb;
-        bool ext_zbc;
-        bool ext_zbs;
-        bool ext_counters;
-        bool ext_ifencei;
-        bool ext_icsr;
-        bool ext_zfh;
-        bool ext_zfhmin;
-        bool ext_zve32f;
-        bool ext_zve64f;
-
-        char *priv_spec;
-        char *user_spec;
-        char *bext_spec;
-        char *vext_spec;
-        uint16_t vlen;
-        uint16_t elen;
-        bool mmu;
-        bool pmp;
-        bool epmp;
-        uint64_t resetvec;
-    } cfg;
+    RISCVCPUConfig cfg;
 };
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.

This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure.  This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
[ Changes by AF:
 - Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                  |  14 ---
 target/riscv/insn_trans/trans_rvi.c.inc   |   2 +-
 target/riscv/insn_trans/trans_rvv.c.inc   | 146 ++++++++++++++--------
 target/riscv/insn_trans/trans_rvzfh.c.inc |   4 +-
 4 files changed, 97 insertions(+), 69 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     RISCVMXL ol;
     bool virt_enabled;
     const RISCVCPUConfig *cfg_ptr;
-    bool ext_ifencei;
-    bool ext_zfh;
-    bool ext_zfhmin;
-    bool ext_zve32f;
-    bool ext_zve64f;
     bool hlsx;
     /* vector extension */
     bool vill;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      */
     int8_t lmul;
     uint8_t sew;
-    uint16_t vlen;
-    uint16_t elen;
     target_ulong vstart;
     bool vl_eq_vlmax;
     uint8_t ntemp;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->cfg_ptr = &(cpu->cfg);
-    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
-    ctx->ext_zfh = cpu->cfg.ext_zfh;
-    ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
-    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
-    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
-    ctx->vlen = cpu->cfg.vlen;
-    ctx->elen = cpu->cfg.elen;
     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
     ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
 
 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 {
-    if (!ctx->ext_ifencei) {
+    if (!ctx->cfg_ptr->ext_ifencei) {
         return false;
     }
 
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_zve32f(DisasContext *s)
     }
 
     /* Zve32f doesn't support FP64. (Section 18.2) */
-    return s->ext_zve32f ? s->sew <= MO_32 : true;
+    return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
 }
 
 static bool require_scale_zve32f(DisasContext *s)
@@ -XXX,XX +XXX,XX @@ static bool require_scale_zve32f(DisasContext *s)
     }
 
     /* Zve32f doesn't support FP64. (Section 18.2) */
-    return s->ext_zve64f ? s->sew <= MO_16 : true;
+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
 }
 
 static bool require_zve64f(DisasContext *s)
@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
     }
 
     /* Zve64f doesn't support FP64. (Section 18.2) */
-    return s->ext_zve64f ? s->sew <= MO_32 : true;
+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
 static bool require_scale_zve64f(DisasContext *s)
@@ -XXX,XX +XXX,XX @@ static bool require_scale_zve64f(DisasContext *s)
     }
 
     /* Zve64f doesn't support FP64. (Section 18.2) */
-    return s->ext_zve64f ? s->sew <= MO_16 : true;
+    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
 }
 
 /* Destination vector register group cannot overlap source mask register. */
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     TCGv s1, dst;
 
     if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
+          s->cfg_ptr->ext_zve64f)) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     TCGv dst;
 
     if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
+          s->cfg_ptr->ext_zve64f)) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
 /* vector register offset from env */
 static uint32_t vreg_ofs(DisasContext *s, int reg)
 {
-    return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
+    return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
 }
 
 /* check functions */
@@ -XXX,XX +XXX,XX @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
      * when XLEN=32. (Section 18.2)
      */
     if (get_xl(s) == MXL_RV32) {
-        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+        ret &= (!has_ext(s, RVV) &&
+                s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
     }
 
     return ret;
@@ -XXX,XX +XXX,XX @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm)
 {
     return (s->lmul <= 2) &&
            (s->sew < MO_64) &&
-           ((s->sew + 1) <= (s->elen >> 4)) &&
+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
            require_align(vd, s->lmul + 1) &&
            require_vm(vm, vd);
 }
@@ -XXX,XX +XXX,XX @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
 {
     return (s->lmul <= 2) &&
            (s->sew < MO_64) &&
-           ((s->sew + 1) <= (s->elen >> 4)) &&
+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
            require_align(vs2, s->lmul + 1) &&
            require_align(vd, s->lmul) &&
            require_vm(vm, vd);
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      * The first part is vlen in bytes, encoded in maxsz of simd_desc.
      * The second part is lmul, encoded in data of simd_desc.
      */
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     mask = tcg_temp_new_ptr();
     base = get_gpr(s, rs1, EXT_NONE);
     stride = get_gpr(s, rs2, EXT_NONE);
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
     base = get_gpr(s, rs1, EXT_NONE);
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     base = get_gpr(s, rs1, EXT_NONE);
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
 
     uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
     dest = tcg_temp_new_ptr();
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     base = get_gpr(s, rs1, EXT_NONE);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
 static inline uint32_t MAXSZ(DisasContext *s)
 {
     int scale = s->lmul - 3;
-    return scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
 }
 
 static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
-                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
+                           cpu_env, s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8, data, fn);
     }
     mark_vs_dirty(s);
     gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
 
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
 
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
-                           cpu_env, s->vlen / 8, s->vlen / 8,
+                           cpu_env, s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8,
                            data, fn);
         mark_vs_dirty(s);
         gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
-                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
+                           cpu_env, s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8, data, fn);
         mark_vs_dirty(s);
         gen_set_label(over);
         return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew]);                           \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew]);                           \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
      * are not included for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivv_check(s, a) &&
-           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) &&
+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
 }
 
 static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
@@ -XXX,XX +XXX,XX @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
      * are not included for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivx_check(s, a) &&
-           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) &&
+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
 }
 
 GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
-                               cpu_env, s->vlen / 8, s->vlen / 8, data,
+                               cpu_env, s->cfg_ptr->vlen / 8,
+                               s->cfg_ptr->vlen / 8, data,
                                fns[s->sew]);
             gen_set_label(over);
         }
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             };
 
             tcg_gen_ext_tl_i64(s1_i64, s1);
-            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                              s->cfg_ptr->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1_i64, cpu_env, desc);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
 
             s1 = tcg_constant_i64(simm);
             dest = tcg_temp_new_ptr();
-            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                              s->cfg_ptr->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1, cpu_env, desc);
 
@@ -XXX,XX +XXX,XX @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
      * for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivv_check(s, a) &&
-           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) &&
+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
 }
 
 static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
@@ -XXX,XX +XXX,XX @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
      * for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivx_check(s, a) &&
-           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) &&
+            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
 }
 
 GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew - 1]);                       \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
-    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                      s->cfg_ptr->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                            vreg_ofs(s, a->rs1),                  \
                            vreg_ofs(s, a->rs2), cpu_env,         \
-                           s->vlen / 8, s->vlen / 8, data,       \
+                           s->cfg_ptr->vlen / 8,                 \
+                           s->cfg_ptr->vlen / 8, data,           \
                            fns[s->sew - 1]);                     \
         mark_vs_dirty(s);                                        \
         gen_set_label(over);                                     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew - 1]);                       \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs2), cpu_env,
-                           s->vlen / 8, s->vlen / 8, data, fn);
+                           s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8, data, fn);
         mark_vs_dirty(s);
         gen_set_label(over);
         return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             do_nanbox(s, t1, cpu_fpr[a->rs1]);
 
             dest = tcg_temp_new_ptr();
-            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                              s->cfg_ptr->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
 
             fns[s->sew - 1](dest, t1, cpu_env, desc);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew - 1]);                       \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew]);                           \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew - 1]);                       \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data,         \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data,             \
                            fns[s->sew]);                           \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
 static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) && (s->sew < MO_64) &&
-           ((s->sew + 1) <= (s->elen >> 4));
+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
 }
 
 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->vlen / 8, s->vlen / 8, data, fn);    \
+                           s->cfg_ptr->vlen / 8,                   \
+                           s->cfg_ptr->vlen / 8, data, fn);        \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
         return true;                                               \
@@ -XXX,XX +XXX,XX @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = dest_gpr(s, a->rd);
-        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                          s->cfg_ptr->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = dest_gpr(s, a->rd);
-        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
+                                          s->cfg_ptr->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
-                           cpu_env, s->vlen / 8, s->vlen / 8,      \
+                           cpu_env, s->cfg_ptr->vlen / 8,          \
+                           s->cfg_ptr->vlen / 8,                   \
                            data, fn);                              \
         mark_vs_dirty(s);                                          \
         gen_set_label(over);                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
         };
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs2), cpu_env,
-                           s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
+                           s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8, data, fns[s->sew]);
         mark_vs_dirty(s);
         gen_set_label(over);
         return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
             gen_helper_vid_v_w, gen_helper_vid_v_d,
         };
         tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                           cpu_env, s->vlen / 8, s->vlen / 8,
+                           cpu_env, s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8,
                            data, fns[s->sew]);
         mark_vs_dirty(s);
         gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
 
     if (a->vm && s->vl_eq_vlmax) {
         int scale = s->lmul - (s->sew + 3);
-        int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+        int vlmax = scale < 0 ?
+                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
         TCGv_i64 dest = tcg_temp_new_i64();
 
         if (a->rs1 == 0) {
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
 
     if (a->vm && s->vl_eq_vlmax) {
         int scale = s->lmul - (s->sew + 3);
-        int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+        int vlmax = scale < 0 ?
+                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
         if (a->rs1 >= vlmax) {
             tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
                                  MAXSZ(s), MAXSZ(s), 0);
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
-                           cpu_env, s->vlen / 8, s->vlen / 8, data,
+                           cpu_env, s->cfg_ptr->vlen / 8,
+                           s->cfg_ptr->vlen / 8, data,
                            fns[s->sew]);
         mark_vs_dirty(s);
         gen_set_label(over);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
     if (require_rvv(s) &&                                               \
         QEMU_IS_ALIGNED(a->rd, LEN) &&                                  \
         QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
-        uint32_t maxsz = (s->vlen >> 3) * LEN;                          \
+        uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
         if (s->vstart == 0) {                                           \
             /* EEW = 8 */                                               \
             tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),                  \
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
 
     tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                        vreg_ofs(s, a->rs2), cpu_env,
-                       s->vlen / 8, s->vlen / 8, data, fn);
+                       s->cfg_ptr->vlen / 8,
+                       s->cfg_ptr->vlen / 8, data, fn);
 
     mark_vs_dirty(s);
     gen_set_label(over);
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -XXX,XX +XXX,XX @@
  */
 
 #define REQUIRE_ZFH(ctx) do { \
-    if (!ctx->ext_zfh) {      \
+    if (!ctx->cfg_ptr->ext_zfh) {      \
         return false;         \
     }                         \
 } while (0)
 
 #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do {       \
-    if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \
+    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
         return false;                         \
     }                                         \
 } while (0)
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled).  Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  */
 
 #define REQUIRE_ZBA(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
+    if (ctx->cfg_ptr->ext_zba) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBB(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
+    if (ctx->cfg_ptr->ext_zbb) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBC(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
+    if (ctx->cfg_ptr->ext_zbc) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBS(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
+    if (ctx->cfg_ptr->ext_zbs) {                 \
         return false;                            \
     }                                            \
 } while (0)
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.

This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
     return ctx->misa_ext & ext;
 }
 
+static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
+{
+    return true;
+}
+
 #ifdef TARGET_RISCV32
 #define get_xl(ctx)    MXL_RV32
 #elif defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /* check for compressed insn */
+    /*
+     * A table with predicate (i.e., guard) functions and decoder functions
+     * that are tested in-order until a decoder matches onto the opcode.
+     */
+    static const struct {
+        bool (*guard_func)(DisasContext *);
+        bool (*decode_func)(DisasContext *, uint32_t);
+    } decoders[] = {
+        { always_true_p,  decode_insn32 },
+    };
+
+    /* Check for compressed insn */
     if (extract16(opcode, 0, 2) != 3) {
         if (!has_ext(ctx, RVC)) {
             gen_exception_illegal(ctx);
         } else {
             ctx->opcode = opcode;
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
-            if (!decode_insn16(ctx, opcode)) {
-                gen_exception_illegal(ctx);
+            if (decode_insn16(ctx, opcode)) {
+                return;
             }
         }
     } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
-        if (!decode_insn32(ctx, opcode32)) {
-            gen_exception_illegal(ctx);
+
+        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+            if (decoders[i].guard_func(ctx) &&
+                decoders[i].decode_func(ctx, opcode32)) {
+                return;
+            }
         }
     }
+
+    gen_exception_illegal(ctx);
 }
 
 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf

This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                            |  3 ++
 target/riscv/XVentanaCondOps.decode           | 25 ++++++++++++
 target/riscv/cpu.c                            |  3 ++
 target/riscv/translate.c                      | 12 ++++++
 .../insn_trans/trans_xventanacondops.c.inc    | 39 +++++++++++++++++++
 target/riscv/meson.build                      |  1 +
 6 files changed, 83 insertions(+)
 create mode 100644 target/riscv/XVentanaCondOps.decode
 create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
 
+    /* Vendor-specific custom extensions */
+    bool ext_XVentanaCondOps;
+
     char *priv_spec;
     char *user_spec;
     char *bext_spec;
diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/XVentanaCondOps.decode
@@ -XXX,XX +XXX,XX @@
+#
+# RISC-V translation routines for the XVentanaCondOps extension
+#
+# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: VTx-family custom instructions
+#            Custom ISA extensions for Ventana Micro Systems RISC-V cores
+#            (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
+
+# Fields
+%rs2  20:5
+%rs1  15:5
+%rd    7:5
+
+# Argument sets
+&r    rd rs1 rs2  !extern
+
+# Formats
+@r         .......  ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
+
+# *** RV64 Custom-3 Extension ***
+vt_maskc   0000000  ..... ..... 110 ..... 1111011 @r
+vt_maskcn  0000000  ..... ..... 111 ..... 1111011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
 
+    /* Vendor-specific custom extensions */
+    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+
     /* These are experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     /* ePMP 0.9.3 */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
     return true;
 }
 
+#define MATERIALISE_EXT_PREDICATE(ext)  \
+    static bool has_ ## ext ## _p(DisasContext *ctx)    \
+    { \
+        return ctx->cfg_ptr->ext_ ## ext ; \
+    }
+
+MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
+
 #ifdef TARGET_RISCV32
 #define get_xl(ctx)    MXL_RV32
 #elif defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_rvzfh.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_xventanacondops.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
 #include "decode-insn16.c.inc"
+/* Include decoders for factored-out extensions */
+#include "decode-XVentanaCondOps.c.inc"
 
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         bool (*decode_func)(DisasContext *, uint32_t);
     } decoders[] = {
         { always_true_p,  decode_insn32 },
+        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
     };
 
     /* Check for compressed insn */
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the XVentanaCondOps extension.
+ *
+ * Copyright (c) 2021-2022 VRULL GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
+
+static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
+{
+    return gen_vt_condmask(ctx, a, TCG_COND_NE);
+}
+
+static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
+{
+    return gen_vt_condmask(ctx, a, TCG_COND_EQ);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ dir = meson.current_source_dir()
 gen = [
   decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+  decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
 ]
 
 riscv_ss = ss.source_set()
-- 
2.34.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro.  Add myself as a point-of-contact.

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/
 
+RISC-V XVentanaCondOps extension
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/XVentanaCondOps.decode
+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+
 RENESAS RX CPUs
 R: Yoshinori Sato <ysato@users.sourceforge.jp>
 S: Orphan
-- 
2.34.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

The guest should be able to set the vill bit as part of vsetvl.

Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     env->vl = vl;
     env->vtype = s2;
     env->vstart = 0;
+    env->vill = 0;
     return vl;
 }
 
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.

Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Anup Patel <anup.patel@wdc.com>

A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/cpu.c      |  3 ++-
 target/riscv/csr.c      | 18 +++++++++++-------
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define IRQ_S_EXT                          9
 #define IRQ_VS_EXT                         10
 #define IRQ_M_EXT                          11
+#define IRQ_S_GEXT                         12
+#define IRQ_LOCAL_MAX                      16
 
 /* mip masks */
 #define MIP_USIP                           (1 << IRQ_U_SOFT)
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define MIP_SEIP                           (1 << IRQ_S_EXT)
 #define MIP_VSEIP                          (1 << IRQ_VS_EXT)
 #define MIP_MEIP                           (1 << IRQ_M_EXT)
+#define MIP_SGEIP                          (1 << IRQ_S_GEXT)
 
 /* sip masks */
 #define SIP_SSIP                           MIP_SSIP
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
         }
     }
     env->mcause = 0;
+    env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
     /* mmte is supposed to have pm.current hardwired to 1 */
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     cpu_set_cpustate_pointers(cpu);
 
 #ifndef CONFIG_USER_ONLY
-    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
+    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
 #endif /* CONFIG_USER_ONLY */
 }
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
 
 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                            VS_MODE_INTERRUPTS;
 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
-                                     VS_MODE_INTERRUPTS;
+                                     HS_MODE_INTERRUPTS;
 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
     if (riscv_has_ext(env, RVH)) {
-        env->mideleg |= VS_MODE_INTERRUPTS;
+        env->mideleg |= HS_MODE_INTERRUPTS;
     }
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
                                 target_ulong val)
 {
     env->mie = (env->mie & ~all_ints) | (val & all_ints);
+    if (!riscv_has_ext(env, RVH)) {
+        env->mie &= ~MIP_SGEIP;
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
     }
 
     if (ret_value) {
-        *ret_value &= env->mideleg;
+        *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
                       write_mask & hvip_writable_mask);
 
     if (ret_value) {
-        *ret_value &= hvip_writable_mask;
+        *ret_value &= VS_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
                       write_mask & hip_writable_mask);
 
     if (ret_value) {
-        *ret_value &= hip_writable_mask;
+        *ret_value &= HS_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
 static RISCVException read_hie(CPURISCVState *env, int csrno,
                                target_ulong *val)
 {
-    *val = env->mie & VS_MODE_INTERRUPTS;
+    *val = env->mie & HS_MODE_INTERRUPTS;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_hie(CPURISCVState *env, int csrno,
                                 target_ulong val)
 {
-    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
+    target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
     return write_mie(env, CSR_MIE, newval);
 }
 
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  5 +++
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu.c        | 67 +++++++++++++++++++++++++++------------
 target/riscv/cpu_helper.c | 37 +++++++++++++++++++--
 target/riscv/csr.c        | 43 +++++++++++++++++--------
 target/riscv/machine.c    |  6 ++--
 6 files changed, 121 insertions(+), 38 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong priv;
     /* This contains QEMU specific information about the virt state. */
     target_ulong virt;
+    target_ulong geilen;
     target_ulong resetvec;
 
     target_ulong mhartid;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong htval;
     target_ulong htinst;
     target_ulong hgatp;
+    target_ulong hgeie;
+    target_ulong hgeip;
     uint64_t htimedelta;
 
     /* Upper 64-bits of 128-bit CSRs */
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 bool riscv_cpu_fp_enabled(CPURISCVState *env);
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define IRQ_M_EXT                          11
 #define IRQ_S_GEXT                         12
 #define IRQ_LOCAL_MAX                      16
+#define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
 
 /* mip masks */
 #define MIP_USIP                           (1 << IRQ_U_SOFT)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 {
     RISCVCPU *cpu = RISCV_CPU(opaque);
+    CPURISCVState *env = &cpu->env;
 
-    switch (irq) {
-    case IRQ_U_SOFT:
-    case IRQ_S_SOFT:
-    case IRQ_VS_SOFT:
-    case IRQ_M_SOFT:
-    case IRQ_U_TIMER:
-    case IRQ_S_TIMER:
-    case IRQ_VS_TIMER:
-    case IRQ_M_TIMER:
-    case IRQ_U_EXT:
-    case IRQ_S_EXT:
-    case IRQ_VS_EXT:
-    case IRQ_M_EXT:
-        if (kvm_enabled()) {
-            kvm_riscv_set_irq(cpu, irq, level);
-        } else {
-            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+    if (irq < IRQ_LOCAL_MAX) {
+        switch (irq) {
+        case IRQ_U_SOFT:
+        case IRQ_S_SOFT:
+        case IRQ_VS_SOFT:
+        case IRQ_M_SOFT:
+        case IRQ_U_TIMER:
+        case IRQ_S_TIMER:
+        case IRQ_VS_TIMER:
+        case IRQ_M_TIMER:
+        case IRQ_U_EXT:
+        case IRQ_S_EXT:
+        case IRQ_VS_EXT:
+        case IRQ_M_EXT:
+             if (kvm_enabled()) {
+                kvm_riscv_set_irq(cpu, irq, level);
+             } else {
+                riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+             }
+             break;
+        default:
+            g_assert_not_reached();
         }
-        break;
-    default:
+    } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
+        /* Require H-extension for handling guest local interrupts */
+        if (!riscv_has_ext(env, RVH)) {
+            g_assert_not_reached();
+        }
+
+        /* Compute bit position in HGEIP CSR */
+        irq = irq - IRQ_LOCAL_MAX + 1;
+        if (env->geilen < irq) {
+            g_assert_not_reached();
+        }
+
+        /* Update HGEIP CSR */
+        env->hgeip &= ~((target_ulong)1 << irq);
+        if (level) {
+            env->hgeip |= (target_ulong)1 << irq;
+        }
+
+        /* Update mip.SGEIP bit */
+        riscv_cpu_update_mip(cpu, MIP_SGEIP,
+                             BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+    } else {
         g_assert_not_reached();
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     cpu_set_cpustate_pointers(cpu);
 
 #ifndef CONFIG_USER_ONLY
-    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
+    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
+                      IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
 #endif /* CONFIG_USER_ONLY */
 }
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
     target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
     target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
 
-    target_ulong pending = env->mip & env->mie;
+    target_ulong vsgemask =
+                (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
+    target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
+
+    target_ulong pending = (env->mip | vsgein) & env->mie;
 
     target_ulong mie    = env->priv < PRV_M ||
                           (env->priv == PRV_M && mstatus_mie);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
     }
 }
 
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return 0;
+    }
+
+    return env->geilen;
+}
+
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return;
+    }
+
+    if (geilen > (TARGET_LONG_BITS - 1)) {
+        return;
+    }
+
+    env->geilen = geilen;
+}
+
 bool riscv_cpu_virt_enabled(CPURISCVState *env)
 {
     if (!riscv_has_ext(env, RVH)) {
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 {
     CPURISCVState *env = &cpu->env;
     CPUState *cs = CPU(cpu);
-    uint32_t old = env->mip;
+    uint32_t gein, vsgein = 0, old = env->mip;
     bool locked = false;
 
+    if (riscv_cpu_virt_enabled(env)) {
+        gein = get_field(env->hstatus, HSTATUS_VGEIN);
+        vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+    }
+
     if (!qemu_mutex_iothread_locked()) {
         locked = true;
         qemu_mutex_lock_iothread();
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 
     env->mip = (env->mip & ~mask) | (value & mask);
 
-    if (env->mip) {
+    if (env->mip | vsgein) {
         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
     } else {
         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
     RISCVCPU *cpu = env_archcpu(env);
     /* Allow software control of delegable interrupts not claimed by hardware */
     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
-    uint32_t old_mip;
+    uint32_t gin, old_mip;
 
     if (mask) {
         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
         old_mip = env->mip;
     }
 
+    if (csrno != CSR_HVIP) {
+        gin = get_field(env->hstatus, HSTATUS_VGEIN);
+        old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
+    }
+
     if (ret_value) {
         *ret_value = old_mip;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
                                target_ulong new_value, target_ulong write_mask)
 {
     /* Shift the S bits to their VS bit location in mip */
-    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+    int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
 
     if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
     if (riscv_cpu_virt_enabled(env)) {
         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+        ret = rmw_mip(env, csrno, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
                                target_ulong *ret_value,
                                target_ulong new_value, target_ulong write_mask)
 {
-    int ret = rmw_mip(env, 0, ret_value, new_value,
+    int ret = rmw_mip(env, csrno, ret_value, new_value,
                       write_mask & hvip_writable_mask);
 
     if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
                               target_ulong *ret_value,
                               target_ulong new_value, target_ulong write_mask)
 {
-    int ret = rmw_mip(env, 0, ret_value, new_value,
+    int ret = rmw_mip(env, csrno, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
     if (ret_value) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException write_hgeie(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     if (val) {
-        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+        *val = env->hgeie;
     }
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
+                                  target_ulong val)
+{
+    /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
+    val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
+    env->hgeie = val;
+    /* Update mip.SGEIP bit */
+    riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+                         BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_htval(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException write_hgeip(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     if (val) {
-        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+        *val = env->hgeip;
     }
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
-    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
+    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
-    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
+    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       NULL              },
     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
 
 static const VMStateDescription vmstate_hyper = {
     .name = "cpu/hyper",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .needed = hyper_needed,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
         VMSTATE_UINTTL(env.htval, RISCVCPU),
         VMSTATE_UINTTL(env.htinst, RISCVCPU),
         VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+        VMSTATE_UINTTL(env.hgeie, RISCVCPU),
+        VMSTATE_UINTTL(env.hgeip, RISCVCPU),
         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
 
         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.

To solve this, we check and inject interrupt after setting V=1.

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
     }
 
     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+    if (enable) {
+        /*
+         * The guest external interrupts from an interrupt controller are
+         * delivered only when the Guest/VM is running (i.e. V=1). This means
+         * any guest external interrupt which is triggered while the Guest/VM
+         * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+         * with sluggish response to serial console input and other I/O events.
+         *
+         * To solve this, we check and inject interrupt after setting V=1.
+         */
+        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+    }
 }
 
 bool riscv_cpu_two_stage_lookup(int mmu_idx)
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
   but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
   AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  5 +++++
 target/riscv/cpu.c | 11 +++--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
     return env->features & (1ULL << feature);
 }
 
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+    env->features |= (1ULL << feature);
+}
+
 #include "cpu_user.h"
 
 extern const char * const riscv_int_regnames[];
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
     env->vext_ver = vext_ver;
 }
 
-static void set_feature(CPURISCVState *env, int feature)
-{
-    env->features |= (1ULL << feature);
-}
-
 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (cpu->cfg.mmu) {
-        set_feature(env, RISCV_FEATURE_MMU);
+        riscv_set_feature(env, RISCV_FEATURE_MMU);
     }
 
     if (cpu->cfg.pmp) {
-        set_feature(env, RISCV_FEATURE_PMP);
+        riscv_set_feature(env, RISCV_FEATURE_PMP);
 
         /*
          * Enhanced PMP should only be available
          * on harts with PMP support
          */
         if (cpu->cfg.epmp) {
-            set_feature(env, RISCV_FEATURE_EPMP);
+            riscv_set_feature(env, RISCV_FEATURE_EPMP);
         }
     }
 
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
     RISCV_FEATURE_EPMP,
-    RISCV_FEATURE_MISA
+    RISCV_FEATURE_MISA,
+    RISCV_FEATURE_AIA
 };
 
 #define PRIV_VERSION_1_10_0 0x00011000
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTVAL           0x343
 #define CSR_MIP             0x344
 
+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_MISELECT        0x350
+#define CSR_MIREG           0x351
+
+/* Machine-Level Interrupts (AIA) */
+#define CSR_MTOPI           0xfb0
+
+/* Machine-Level IMSIC Interface (AIA) */
+#define CSR_MSETEIPNUM      0x358
+#define CSR_MCLREIPNUM      0x359
+#define CSR_MSETEIENUM      0x35a
+#define CSR_MCLREIENUM      0x35b
+#define CSR_MTOPEI          0x35c
+
+/* Virtual Interrupts for Supervisor Level (AIA) */
+#define CSR_MVIEN           0x308
+#define CSR_MVIP            0x309
+
+/* Machine-Level High-Half CSRs (AIA) */
+#define CSR_MIDELEGH        0x313
+#define CSR_MIEH            0x314
+#define CSR_MVIENH          0x318
+#define CSR_MVIPH           0x319
+#define CSR_MIPH            0x354
+
 /* Supervisor Trap Setup */
 #define CSR_SSTATUS         0x100
 #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
 
+/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_SISELECT        0x150
+#define CSR_SIREG           0x151
+
+/* Supervisor-Level Interrupts (AIA) */
+#define CSR_STOPI           0xdb0
+
+/* Supervisor-Level IMSIC Interface (AIA) */
+#define CSR_SSETEIPNUM      0x158
+#define CSR_SCLREIPNUM      0x159
+#define CSR_SSETEIENUM      0x15a
+#define CSR_SCLREIENUM      0x15b
+#define CSR_STOPEI          0x15c
+
+/* Supervisor-Level High-Half CSRs (AIA) */
+#define CSR_SIEH            0x114
+#define CSR_SIPH            0x154
+
 /* Hpervisor CSRs */
 #define CSR_HSTATUS         0x600
 #define CSR_HEDELEG         0x602
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+#define CSR_HVIEN           0x608
+#define CSR_HVICTL          0x609
+#define CSR_HVIPRIO1        0x646
+#define CSR_HVIPRIO2        0x647
+
+/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+#define CSR_VSISELECT       0x250
+#define CSR_VSIREG          0x251
+
+/* VS-Level Interrupts (H-extension with AIA) */
+#define CSR_VSTOPI          0xeb0
+
+/* VS-Level IMSIC Interface (H-extension with AIA) */
+#define CSR_VSSETEIPNUM     0x258
+#define CSR_VSCLREIPNUM     0x259
+#define CSR_VSSETEIENUM     0x25a
+#define CSR_VSCLREIENUM     0x25b
+#define CSR_VSTOPEI         0x25c
+
+/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+#define CSR_HIDELEGH        0x613
+#define CSR_HVIENH          0x618
+#define CSR_HVIPH           0x655
+#define CSR_HVIPRIO1H       0x656
+#define CSR_HVIPRIO2H       0x657
+#define CSR_VSIEH           0x214
+#define CSR_VSIPH           0x254
+
 /* Enhanced Physical Memory Protection (ePMP) */
 #define CSR_MSECCFG         0x747
 #define CSR_MSECCFGH        0x757
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define UMTE_U_PM_INSN      U_PM_INSN
 #define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
 
+/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
+#define ISELECT_IPRIO0                     0x30
+#define ISELECT_IPRIO15                    0x3f
+#define ISELECT_IMSIC_EIDELIVERY           0x70
+#define ISELECT_IMSIC_EITHRESHOLD          0x72
+#define ISELECT_IMSIC_EIP0                 0x80
+#define ISELECT_IMSIC_EIP63                0xbf
+#define ISELECT_IMSIC_EIE0                 0xc0
+#define ISELECT_IMSIC_EIE63                0xff
+#define ISELECT_IMSIC_FIRST                ISELECT_IMSIC_EIDELIVERY
+#define ISELECT_IMSIC_LAST                 ISELECT_IMSIC_EIE63
+#define ISELECT_MASK                       0x1ff
+
+/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
+#define ISELECT_IMSIC_TOPEI                (ISELECT_MASK + 1)
+
+/* IMSIC bits (AIA) */
+#define IMSIC_TOPEI_IID_SHIFT              16
+#define IMSIC_TOPEI_IID_MASK               0x7ff
+#define IMSIC_TOPEI_IPRIO_MASK             0x7ff
+#define IMSIC_EIPx_BITS                    32
+#define IMSIC_EIEx_BITS                    32
+
+/* MTOPI and STOPI bits (AIA) */
+#define TOPI_IID_SHIFT                     16
+#define TOPI_IID_MASK                      0xfff
+#define TOPI_IPRIO_MASK                    0xff
+
+/* Interrupt priority bits (AIA) */
+#define IPRIO_IRQ_BITS                     8
+#define IPRIO_MMAXIPRIO                    255
+#define IPRIO_DEFAULT_UPPER                4
+#define IPRIO_DEFAULT_MIDDLE               (IPRIO_DEFAULT_UPPER + 24)
+#define IPRIO_DEFAULT_M                    IPRIO_DEFAULT_MIDDLE
+#define IPRIO_DEFAULT_S                    (IPRIO_DEFAULT_M + 3)
+#define IPRIO_DEFAULT_SGEXT                (IPRIO_DEFAULT_S + 3)
+#define IPRIO_DEFAULT_VS                   (IPRIO_DEFAULT_SGEXT + 1)
+#define IPRIO_DEFAULT_LOWER                (IPRIO_DEFAULT_VS + 3)
+
+/* HVICTL bits (AIA) */
+#define HVICTL_VTI                         0x40000000
+#define HVICTL_IID                         0x0fff0000
+#define HVICTL_IPRIOM                      0x00000100
+#define HVICTL_IPRIO                       0x000000ff
+#define HVICTL_VALID_MASK                  \
+    (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
+
 #endif
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint64_t (*rdtime_fn)(uint32_t);
     uint32_t rdtime_fn_arg;
 
+    /* machine specific AIA ireg read-modify-write callback */
+#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
+    ((((__xlen) & 0xff) << 24) | \
+     (((__vgein) & 0x3f) << 20) | \
+     (((__virt) & 0x1) << 18) | \
+     (((__priv) & 0x3) << 16) | \
+     (__isel & 0xffff))
+#define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
+#define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
+#define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
+#define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
+#define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
+    int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
+        target_ulong *val, target_ulong new_val, target_ulong write_mask);
+    void *aia_ireg_rmw_fn_arg[4];
+
     /* True if in debugger mode.  */
     bool debugger;
 
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
                              uint32_t arg);
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+                                   int (*rmw_fn)(void *arg,
+                                                 target_ulong reg,
+                                                 target_ulong *val,
+                                                 target_ulong new_val,
+                                                 target_ulong write_mask),
+                                   void *rmw_fn_arg);
 #endif
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
     env->rdtime_fn_arg = arg;
 }
 
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+                                   int (*rmw_fn)(void *arg,
+                                                 target_ulong reg,
+                                                 target_ulong *val,
+                                                 target_ulong new_val,
+                                                 target_ulong write_mask),
+                                   void *rmw_fn_arg)
+{
+    if (priv <= PRV_M) {
+        env->aia_ireg_rmw_fn[priv] = rmw_fn;
+        env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
+    }
+}
+
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 {
     if (newpriv > PRV_M) {
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  12 ++
 target/riscv/cpu.c        |  19 +++
 target/riscv/cpu_helper.c | 281 +++++++++++++++++++++++++++++++++++---
 target/riscv/machine.c    |   3 +
 4 files changed, 294 insertions(+), 21 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong mcause;
     target_ulong mtval;  /* since: priv-1.10.0 */
 
+    /* Machine and Supervisor interrupt priorities */
+    uint8_t miprio[64];
+    uint8_t siprio[64];
+
     /* Hypervisor CSRs */
     target_ulong hstatus;
     target_ulong hedeleg;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong hgeip;
     uint64_t htimedelta;
 
+    /* Hypervisor controlled virtual interrupt priorities */
+    uint8_t hviprio[64];
+
     /* Upper 64-bits of 128-bit CSRs */
     uint64_t mscratchh;
     uint64_t sscratchh;
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
                                int cpuid, void *opaque);
 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
+uint8_t riscv_cpu_default_priority(int irq);
+int riscv_cpu_mirq_pending(CPURISCVState *env);
+int riscv_cpu_sirq_pending(CPURISCVState *env);
+int riscv_cpu_vsirq_pending(CPURISCVState *env);
 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 
 static void riscv_cpu_reset(DeviceState *dev)
 {
+#ifndef CONFIG_USER_ONLY
+    uint8_t iprio;
+    int i, irq, rdzero;
+#endif
     CPUState *cs = CPU(dev);
     RISCVCPU *cpu = RISCV_CPU(cs);
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
+
+    /* Initialized default priorities of local interrupts. */
+    for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
+        iprio = riscv_cpu_default_priority(i);
+        env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
+        env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
+        env->hviprio[i] = 0;
+    }
+    i = 0;
+    while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
+        if (!rdzero) {
+            env->hviprio[irq] = env->miprio[irq];
+        }
+        i++;
+    }
     /* mmte is supposed to have pm.current hardwired to 1 */
     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_update_mask(CPURISCVState *env)
 }
 
 #ifndef CONFIG_USER_ONLY
-static int riscv_cpu_local_irq_pending(CPURISCVState *env)
+
+/*
+ * The HS-mode is allowed to configure priority only for the
+ * following VS-mode local interrupts:
+ *
+ * 0  (Reserved interrupt, reads as zero)
+ * 1  Supervisor software interrupt
+ * 4  (Reserved interrupt, reads as zero)
+ * 5  Supervisor timer interrupt
+ * 8  (Reserved interrupt, reads as zero)
+ * 13 (Reserved interrupt)
+ * 14 "
+ * 15 "
+ * 16 "
+ * 18 Debug/trace interrupt
+ * 20 (Reserved interrupt)
+ * 22 "
+ * 24 "
+ * 26 "
+ * 28 "
+ * 30 (Reserved for standard reporting of bus or system errors)
+ */
+
+static const int hviprio_index2irq[] = {
+    0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
+static const int hviprio_index2rdzero[] = {
+    1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
+
+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
+{
+    if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
+        return -EINVAL;
+    }
+
+    if (out_irq) {
+        *out_irq = hviprio_index2irq[index];
+    }
+
+    if (out_rdzero) {
+        *out_rdzero = hviprio_index2rdzero[index];
+    }
+
+    return 0;
+}
+
+/*
+ * Default priorities of local interrupts are defined in the
+ * RISC-V Advanced Interrupt Architecture specification.
+ *
+ * ----------------------------------------------------------------
+ *  Default  |
+ *  Priority | Major Interrupt Numbers
+ * ----------------------------------------------------------------
+ *  Highest  | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c),
+ *           | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38),
+ *           | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34),
+ *           | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30)
+ *           |
+ *           | 11 (0b),  3 (03),  7 (07)
+ *           |  9 (09),  1 (01),  5 (05)
+ *           | 12 (0c)
+ *           | 10 (0a),  2 (02),  6 (06)
+ *           |
+ *           | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c),
+ *           | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28),
+ *           | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24),
+ *  Lowest   | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20)
+ * ----------------------------------------------------------------
+ */
+static const uint8_t default_iprio[64] = {
+ [63] = IPRIO_DEFAULT_UPPER,
+ [62] = IPRIO_DEFAULT_UPPER + 1,
+ [31] = IPRIO_DEFAULT_UPPER + 2,
+ [30] = IPRIO_DEFAULT_UPPER + 3,
+ [61] = IPRIO_DEFAULT_UPPER + 4,
+ [60] = IPRIO_DEFAULT_UPPER + 5,
+
+ [59] = IPRIO_DEFAULT_UPPER + 6,
+ [58] = IPRIO_DEFAULT_UPPER + 7,
+ [29] = IPRIO_DEFAULT_UPPER + 8,
+ [28] = IPRIO_DEFAULT_UPPER + 9,
+ [57] = IPRIO_DEFAULT_UPPER + 10,
+ [56] = IPRIO_DEFAULT_UPPER + 11,
+
+ [55] = IPRIO_DEFAULT_UPPER + 12,
+ [54] = IPRIO_DEFAULT_UPPER + 13,
+ [27] = IPRIO_DEFAULT_UPPER + 14,
+ [26] = IPRIO_DEFAULT_UPPER + 15,
+ [53] = IPRIO_DEFAULT_UPPER + 16,
+ [52] = IPRIO_DEFAULT_UPPER + 17,
+
+ [51] = IPRIO_DEFAULT_UPPER + 18,
+ [50] = IPRIO_DEFAULT_UPPER + 19,
+ [25] = IPRIO_DEFAULT_UPPER + 20,
+ [24] = IPRIO_DEFAULT_UPPER + 21,
+ [49] = IPRIO_DEFAULT_UPPER + 22,
+ [48] = IPRIO_DEFAULT_UPPER + 23,
+
+ [11] = IPRIO_DEFAULT_M,
+ [3]  = IPRIO_DEFAULT_M + 1,
+ [7]  = IPRIO_DEFAULT_M + 2,
+
+ [9]  = IPRIO_DEFAULT_S,
+ [1]  = IPRIO_DEFAULT_S + 1,
+ [5]  = IPRIO_DEFAULT_S + 2,
+
+ [12] = IPRIO_DEFAULT_SGEXT,
+
+ [10] = IPRIO_DEFAULT_VS,
+ [2]  = IPRIO_DEFAULT_VS + 1,
+ [6]  = IPRIO_DEFAULT_VS + 2,
+
+ [47] = IPRIO_DEFAULT_LOWER,
+ [46] = IPRIO_DEFAULT_LOWER + 1,
+ [23] = IPRIO_DEFAULT_LOWER + 2,
+ [22] = IPRIO_DEFAULT_LOWER + 3,
+ [45] = IPRIO_DEFAULT_LOWER + 4,
+ [44] = IPRIO_DEFAULT_LOWER + 5,
+
+ [43] = IPRIO_DEFAULT_LOWER + 6,
+ [42] = IPRIO_DEFAULT_LOWER + 7,
+ [21] = IPRIO_DEFAULT_LOWER + 8,
+ [20] = IPRIO_DEFAULT_LOWER + 9,
+ [41] = IPRIO_DEFAULT_LOWER + 10,
+ [40] = IPRIO_DEFAULT_LOWER + 11,
+
+ [39] = IPRIO_DEFAULT_LOWER + 12,
+ [38] = IPRIO_DEFAULT_LOWER + 13,
+ [19] = IPRIO_DEFAULT_LOWER + 14,
+ [18] = IPRIO_DEFAULT_LOWER + 15,
+ [37] = IPRIO_DEFAULT_LOWER + 16,
+ [36] = IPRIO_DEFAULT_LOWER + 17,
+
+ [35] = IPRIO_DEFAULT_LOWER + 18,
+ [34] = IPRIO_DEFAULT_LOWER + 19,
+ [17] = IPRIO_DEFAULT_LOWER + 20,
+ [16] = IPRIO_DEFAULT_LOWER + 21,
+ [33] = IPRIO_DEFAULT_LOWER + 22,
+ [32] = IPRIO_DEFAULT_LOWER + 23,
+};
+
+uint8_t riscv_cpu_default_priority(int irq)
 {
-    target_ulong virt_enabled = riscv_cpu_virt_enabled(env);
+    if (irq < 0 || irq > 63) {
+        return IPRIO_MMAXIPRIO;
+    }
+
+    return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
+};
 
-    target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
-    target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
+static int riscv_cpu_pending_to_irq(CPURISCVState *env,
+                                    int extirq, unsigned int extirq_def_prio,
+                                    uint64_t pending, uint8_t *iprio)
+{
+    int irq, best_irq = RISCV_EXCP_NONE;
+    unsigned int prio, best_prio = UINT_MAX;
 
-    target_ulong vsgemask =
-                (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
-    target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
+    if (!pending) {
+        return RISCV_EXCP_NONE;
+    }
 
-    target_ulong pending = (env->mip | vsgein) & env->mie;
+    irq = ctz64(pending);
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return irq;
+    }
 
-    target_ulong mie    = env->priv < PRV_M ||
-                          (env->priv == PRV_M && mstatus_mie);
-    target_ulong sie    = env->priv < PRV_S ||
-                          (env->priv == PRV_S && mstatus_sie);
-    target_ulong hsie   = virt_enabled || sie;
-    target_ulong vsie   = virt_enabled && sie;
+    pending = pending >> irq;
+    while (pending) {
+        prio = iprio[irq];
+        if (!prio) {
+            if (irq == extirq) {
+                prio = extirq_def_prio;
+            } else {
+                prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
+                       1 : IPRIO_MMAXIPRIO;
+            }
+        }
+        if ((pending & 0x1) && (prio <= best_prio)) {
+            best_irq = irq;
+            best_prio = prio;
+        }
+        irq++;
+        pending = pending >> 1;
+    }
 
-    target_ulong irqs =
-            (pending & ~env->mideleg & -mie) |
-            (pending &  env->mideleg & ~env->hideleg & -hsie) |
-            (pending &  env->mideleg &  env->hideleg & -vsie);
+    return best_irq;
+}
 
-    if (irqs) {
-        return ctz64(irqs); /* since non-zero */
+static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+{
+    uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
+    uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+
+    return (env->mip | vsgein) & env->mie;
+}
+
+int riscv_cpu_mirq_pending(CPURISCVState *env)
+{
+    uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
+                    ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+    return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
+                                    irqs, env->miprio);
+}
+
+int riscv_cpu_sirq_pending(CPURISCVState *env)
+{
+    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
+                    ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+    return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+                                    irqs, env->siprio);
+}
+
+int riscv_cpu_vsirq_pending(CPURISCVState *env)
+{
+    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
+                    (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+    return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+                                    irqs >> 1, env->hviprio);
+}
+
+static int riscv_cpu_local_irq_pending(CPURISCVState *env)
+{
+    int virq;
+    uint64_t irqs, pending, mie, hsie, vsie;
+
+    /* Determine interrupt enable state of all privilege modes */
+    if (riscv_cpu_virt_enabled(env)) {
+        mie = 1;
+        hsie = 1;
+        vsie = (env->priv < PRV_S) ||
+               (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
     } else {
-        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
+        mie = (env->priv < PRV_M) ||
+              (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
+        hsie = (env->priv < PRV_S) ||
+               (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
+        vsie = 0;
+    }
+
+    /* Determine all pending interrupts */
+    pending = riscv_cpu_all_pending(env);
+
+    /* Check M-mode interrupts */
+    irqs = pending & ~env->mideleg & -mie;
+    if (irqs) {
+        return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
+                                        irqs, env->miprio);
     }
+
+    /* Check HS-mode interrupts */
+    irqs = pending & env->mideleg & ~env->hideleg & -hsie;
+    if (irqs) {
+        return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+                                        irqs, env->siprio);
+    }
+
+    /* Check VS-mode interrupts */
+    irqs = pending & env->mideleg & env->hideleg & -vsie;
+    if (irqs) {
+        virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+                                        irqs >> 1, env->hviprio);
+        return (virq <= 0) ? virq : virq + 1;
+    }
+
+    /* Indicate no pending interrupt */
+    return RISCV_EXCP_NONE;
 }
 
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
         VMSTATE_UINTTL(env.hgeie, RISCVCPU),
         VMSTATE_UINTTL(env.hgeip, RISCVCPU),
         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+        VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
 
         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
         VMSTATE_UINTTL(env.vstvec, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+        VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
+        VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
         VMSTATE_UINTTL(env.pc, RISCVCPU),
         VMSTATE_UINTTL(env.load_res, RISCVCPU),
         VMSTATE_UINTTL(env.load_val, RISCVCPU),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  14 +-
 target/riscv/cpu_helper.c |  10 +-
 target/riscv/csr.c        | 560 +++++++++++++++++++++++++++++++-------
 target/riscv/machine.c    |  10 +-
 4 files changed, 474 insertions(+), 120 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
      */
     uint64_t mstatus;
 
-    target_ulong mip;
+    uint64_t mip;
 
-    uint32_t miclaim;
+    uint64_t miclaim;
 
-    target_ulong mie;
-    target_ulong mideleg;
+    uint64_t mie;
+    uint64_t mideleg;
 
     target_ulong satp;   /* since: priv-1.10.0 */
     target_ulong stval;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     /* Hypervisor CSRs */
     target_ulong hstatus;
     target_ulong hedeleg;
-    target_ulong hideleg;
+    uint64_t hideleg;
     target_ulong hcounteren;
     target_ulong htval;
     target_ulong htinst;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_list(void);
 #ifndef CONFIG_USER_ONLY
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
-int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
+uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
                              uint32_t arg);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_two_stage_lookup(int mmu_idx)
     return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
 }
 
-int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
 {
     CPURISCVState *env = &cpu->env;
     if (env->miclaim & interrupts) {
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
     }
 }
 
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
 {
     CPURISCVState *env = &cpu->env;
     CPUState *cs = CPU(cpu);
-    uint32_t gein, vsgein = 0, old = env->mip;
+    uint64_t gein, vsgein = 0, old = env->mip;
     bool locked = false;
 
     if (riscv_cpu_virt_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      */
     bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
-    target_ulong deleg = async ? env->mideleg : env->medeleg;
+    uint64_t deleg = async ? env->mideleg : env->medeleg;
     target_ulong tval = 0;
     target_ulong htval = 0;
     target_ulong mtval2 = 0;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
-            target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+            uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
 
             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
                 /* Trap to VS mode */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException any32(CPURISCVState *env, int csrno)
 
 }
 
+static int aia_any32(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return any32(env, csrno);
+}
+
 static RISCVException smode(CPURISCVState *env, int csrno)
 {
     if (riscv_has_ext(env, RVS)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException smode(CPURISCVState *env, int csrno)
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
+static int smode32(CPURISCVState *env, int csrno)
+{
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return smode(env, csrno);
+}
+
+static int aia_smode32(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return smode32(env, csrno);
+}
+
 static RISCVException hmode(CPURISCVState *env, int csrno)
 {
     if (riscv_has_ext(env, RVS) &&
@@ -XXX,XX +XXX,XX @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
+static int aia_hmode32(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return hmode32(env, csrno);
+}
+
 static RISCVException pmp(CPURISCVState *env, int csrno)
 {
     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
 
 /* Machine constants */
 
-#define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
-#define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
-#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
-#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
+#define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
+#define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
+#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
+#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
 
-static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
+static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
                                            VS_MODE_INTERRUPTS;
-static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
-static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
+static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
+static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
                                      HS_MODE_INTERRUPTS;
 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
@@ -XXX,XX +XXX,XX @@ static RISCVException write_medeleg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_mideleg(CPURISCVState *env, int csrno,
-                                   target_ulong *val)
+static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
+                                    uint64_t *ret_val,
+                                    uint64_t new_val, uint64_t wr_mask)
 {
-    *val = env->mideleg;
-    return RISCV_EXCP_NONE;
-}
+    uint64_t mask = wr_mask & delegable_ints;
+
+    if (ret_val) {
+        *ret_val = env->mideleg;
+    }
+
+    env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
 
-static RISCVException write_mideleg(CPURISCVState *env, int csrno,
-                                    target_ulong val)
-{
-    env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
     if (riscv_has_ext(env, RVH)) {
         env->mideleg |= HS_MODE_INTERRUPTS;
     }
+
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_mie(CPURISCVState *env, int csrno,
-                               target_ulong *val)
+static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
+                                  target_ulong *ret_val,
+                                  target_ulong new_val, target_ulong wr_mask)
 {
-    *val = env->mie;
-    return RISCV_EXCP_NONE;
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
 }
 
-static RISCVException write_mie(CPURISCVState *env, int csrno,
-                                target_ulong val)
+static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
+                                   target_ulong *ret_val,
+                                   target_ulong new_val,
+                                   target_ulong wr_mask)
 {
-    env->mie = (env->mie & ~all_ints) | (val & all_ints);
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mideleg64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
+                                uint64_t *ret_val,
+                                uint64_t new_val, uint64_t wr_mask)
+{
+    uint64_t mask = wr_mask & all_ints;
+
+    if (ret_val) {
+        *ret_val = env->mie;
+    }
+
+    env->mie = (env->mie & ~mask) | (new_val & mask);
+
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~MIP_SGEIP;
+        env->mie &= ~((uint64_t)MIP_SGEIP);
     }
+
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException rmw_mie(CPURISCVState *env, int csrno,
+                              target_ulong *ret_val,
+                              target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mie64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
+}
+
 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException rmw_mip(CPURISCVState *env, int csrno,
-                              target_ulong *ret_value,
-                              target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
+                                uint64_t *ret_val,
+                                uint64_t new_val, uint64_t wr_mask)
 {
     RISCVCPU *cpu = env_archcpu(env);
     /* Allow software control of delegable interrupts not claimed by hardware */
-    target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
-    uint32_t gin, old_mip;
+    uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
+    uint32_t gin;
 
     if (mask) {
-        old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
+        old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
     } else {
         old_mip = env->mip;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
     }
 
-    if (ret_value) {
-        *ret_value = old_mip;
+    if (ret_val) {
+        *ret_val = old_mip;
     }
 
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_val,
+                              target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_miph(CPURISCVState *env, int csrno,
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_mip64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
+}
+
 /* Supervisor Trap Setup */
 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
                                         Int128 *val)
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
-static RISCVException read_vsie(CPURISCVState *env, int csrno,
-                                target_ulong *val)
+static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
+                                 uint64_t *ret_val,
+                                 uint64_t new_val, uint64_t wr_mask)
 {
-    /* Shift the VS bits to their S bit location in vsie */
-    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
-    return RISCV_EXCP_NONE;
+    RISCVException ret;
+    uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
+
+    /* Bring VS-level bits to correct position */
+    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
+    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
+    new_val |= vsbits << 1;
+    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
+    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
+    wr_mask |= vsbits << 1;
+
+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
+    if (ret_val) {
+        rval &= mask;
+        vsbits = rval & VS_MODE_INTERRUPTS;
+        rval &= ~VS_MODE_INTERRUPTS;
+        *ret_val = rval | (vsbits >> 1);
+    }
+
+    return ret;
 }
 
-static RISCVException read_sie(CPURISCVState *env, int csrno,
-                               target_ulong *val)
+static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
 {
-    if (riscv_cpu_virt_enabled(env)) {
-        read_vsie(env, CSR_VSIE, val);
-    } else {
-        *val = env->mie & env->mideleg;
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
     }
-    return RISCV_EXCP_NONE;
+
+    return ret;
 }
 
-static RISCVException write_vsie(CPURISCVState *env, int csrno,
-                                 target_ulong val)
+static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
+                                target_ulong *ret_val,
+                                target_ulong new_val, target_ulong wr_mask)
 {
-    /* Shift the S bits to their VS bit location in mie */
-    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
-    return write_mie(env, CSR_MIE, newval);
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_vsie64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
+                                uint64_t *ret_val,
+                                uint64_t new_val, uint64_t wr_mask)
 {
+    RISCVException ret;
+    uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
+
     if (riscv_cpu_virt_enabled(env)) {
-        write_vsie(env, CSR_VSIE, val);
+        ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
     } else {
-        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
-                              (val & S_MODE_INTERRUPTS);
-        write_mie(env, CSR_MIE, newval);
+        ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
     }
 
-    return RISCV_EXCP_NONE;
+    if (ret_val) {
+        *ret_val &= mask;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_sie(CPURISCVState *env, int csrno,
+                              target_ulong *ret_val,
+                              target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_sie64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
 }
 
 static RISCVException read_stvec(CPURISCVState *env, int csrno,
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stval(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
+                                 uint64_t *ret_val,
+                                 uint64_t new_val, uint64_t wr_mask)
+{
+    RISCVException ret;
+    uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
+
+    /* Bring VS-level bits to correct position */
+    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
+    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
+    new_val |= vsbits << 1;
+    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
+    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
+    wr_mask |= vsbits << 1;
+
+    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
+    if (ret_val) {
+        rval &= mask;
+        vsbits = rval & VS_MODE_INTERRUPTS;
+        rval &= ~VS_MODE_INTERRUPTS;
+        *ret_val = rval | (vsbits >> 1);
+    }
+
+    return ret;
+}
+
 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value, target_ulong write_mask)
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
 {
-    /* Shift the S bits to their VS bit location in mip */
-    int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
-                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    uint64_t rval;
+    RISCVException ret;
 
-    if (ret_value) {
-        *ret_value &= VS_MODE_INTERRUPTS;
-        /* Shift the VS bits to their S bit location in vsip */
-        *ret_value >>= 1;
+    ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
     }
+
     return ret;
 }
 
-static RISCVException rmw_sip(CPURISCVState *env, int csrno,
-                              target_ulong *ret_value,
-                              target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
+                                target_ulong *ret_val,
+                                target_ulong new_val, target_ulong wr_mask)
 {
-    int ret;
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_vsip64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
+                                uint64_t *ret_val,
+                                uint64_t new_val, uint64_t wr_mask)
+{
+    RISCVException ret;
+    uint64_t mask = env->mideleg & sip_writable_mask;
 
     if (riscv_cpu_virt_enabled(env)) {
-        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
+        ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
     } else {
-        ret = rmw_mip(env, csrno, ret_value, new_value,
-                      write_mask & env->mideleg & sip_writable_mask);
+        ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
     }
 
-    if (ret_value) {
-        *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
+    if (ret_val) {
+        *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_val,
+                              target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
     }
+
+    return ret;
+}
+
+static RISCVException rmw_siph(CPURISCVState *env, int csrno,
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_sip64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_hideleg(CPURISCVState *env, int csrno,
-                                   target_ulong *val)
+static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
+                                    uint64_t *ret_val,
+                                    uint64_t new_val, uint64_t wr_mask)
 {
-    *val = env->hideleg;
+    uint64_t mask = wr_mask & vs_delegable_ints;
+
+    if (ret_val) {
+        *ret_val = env->hideleg & vs_delegable_ints;
+    }
+
+    env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException write_hideleg(CPURISCVState *env, int csrno,
-                                    target_ulong val)
+static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
+                                  target_ulong *ret_val,
+                                  target_ulong new_val, target_ulong wr_mask)
 {
-    env->hideleg = val & vs_delegable_ints;
-    return RISCV_EXCP_NONE;
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
+                                   target_ulong *ret_val,
+                                   target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_hideleg64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
+                                 uint64_t *ret_val,
+                                 uint64_t new_val, uint64_t wr_mask)
+{
+    RISCVException ret;
+
+    ret = rmw_mip64(env, csrno, ret_val, new_val,
+                    wr_mask & hvip_writable_mask);
+    if (ret_val) {
+        *ret_val &= VS_MODE_INTERRUPTS;
+    }
+
+    return ret;
 }
 
 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value, target_ulong write_mask)
+                               target_ulong *ret_val,
+                               target_ulong new_val, target_ulong wr_mask)
 {
-    int ret = rmw_mip(env, csrno, ret_value, new_value,
-                      write_mask & hvip_writable_mask);
+    uint64_t rval;
+    RISCVException ret;
 
-    if (ret_value) {
-        *ret_value &= VS_MODE_INTERRUPTS;
+    ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
+    if (ret_val) {
+        *ret_val = rval;
+    }
+
+    return ret;
+}
+
+static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
+                                target_ulong *ret_val,
+                                target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t rval;
+    RISCVException ret;
+
+    ret = rmw_hvip64(env, csrno, &rval,
+        ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+    if (ret_val) {
+        *ret_val = rval >> 32;
     }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
     return ret;
 }
 
-static RISCVException read_hie(CPURISCVState *env, int csrno,
-                               target_ulong *val)
+static RISCVException rmw_hie(CPURISCVState *env, int csrno,
+                              target_ulong *ret_val,
+                              target_ulong new_val, target_ulong wr_mask)
 {
-    *val = env->mie & HS_MODE_INTERRUPTS;
-    return RISCV_EXCP_NONE;
-}
+    uint64_t rval;
+    RISCVException ret;
 
-static RISCVException write_hie(CPURISCVState *env, int csrno,
-                                target_ulong val)
-{
-    target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
-    return write_mie(env, CSR_MIE, newval);
+    ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
+    if (ret_val) {
+        *ret_val = rval & HS_MODE_INTERRUPTS;
+    }
+
+    return ret;
 }
 
 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
                                                read_mstatus_i128                   },
     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
                                                read_misa_i128                      },
-    [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
+    [CSR_MIDELEG]     = { "mideleg",    any,   NULL,    NULL,    rmw_mideleg       },
     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
-    [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
+    [CSR_MIE]         = { "mie",        any,   NULL,    NULL,    rmw_mie           },
     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
+    /* Machine-Level High-Half CSRs (AIA) */
+    [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
+    [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
+    [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
+
     /* Supervisor Trap Setup */
     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
                                               read_sstatus_i128                 },
-    [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
+    [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie          },
     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Supervisor Protection and Translation */
     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
 
+    /* Supervisor-Level High-Half CSRs (AIA) */
+    [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
+    [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
+
     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
-    [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
+    [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL,     rmw_hideleg       },
     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
-    [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
+    [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL,     rmw_hie           },
     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 
     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
-    [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
+    [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL,    rmw_vsie          },
     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
+    /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+    [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
+    [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
+    [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
+    [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
+
     /* Physical Memory Protection */
     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
         VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
-        VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+        VMSTATE_UINT64(env.hideleg, RISCVCPU),
         VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
         VMSTATE_UINTTL(env.htval, RISCVCPU),
         VMSTATE_UINTTL(env.htinst, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINTTL(env.resetvec, RISCVCPU),
         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
         VMSTATE_UINT64(env.mstatus, RISCVCPU),
-        VMSTATE_UINTTL(env.mip, RISCVCPU),
-        VMSTATE_UINT32(env.miclaim, RISCVCPU),
-        VMSTATE_UINTTL(env.mie, RISCVCPU),
-        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+        VMSTATE_UINT64(env.mip, RISCVCPU),
+        VMSTATE_UINT64(env.miclaim, RISCVCPU),
+        VMSTATE_UINT64(env.mie, RISCVCPU),
+        VMSTATE_UINT64(env.mideleg, RISCVCPU),
         VMSTATE_UINTTL(env.satp, RISCVCPU),
         VMSTATE_UINTTL(env.stval, RISCVCPU),
         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
 - Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h     |   2 +
 target/riscv/csr.c     | 128 ++++++++++++++++++++++++++++++++++++++++-
 target/riscv/machine.c |   2 +
 3 files changed, 131 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint64_t htimedelta;
 
     /* Hypervisor controlled virtual interrupt priorities */
+    target_ulong hvictl;
     uint8_t hviprio[64];
 
     /* Upper 64-bits of 128-bit CSRs */
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
     return env->misa_mxl;
 }
 #endif
+#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
 #if defined(TARGET_RISCV32)
 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
+static int aia_hmode(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+     }
+
+     return hmode(env, csrno);
+}
+
 static int aia_hmode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
 
     if (riscv_cpu_virt_enabled(env)) {
+        if (env->hvictl & HVICTL_VTI) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
     } else {
         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sie(CPURISCVState *env, int csrno,
     RISCVException ret;
 
     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
-    if (ret_val) {
+    if (ret == RISCV_EXCP_NONE && ret_val) {
         *ret_val = rval;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
     uint64_t mask = env->mideleg & sip_writable_mask;
 
     if (riscv_cpu_virt_enabled(env)) {
+        if (env->hvictl & HVICTL_VTI) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
     } else {
         ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    *val = env->hvictl;
+    return RISCV_EXCP_NONE;
+}
+
+static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
+{
+    env->hvictl = val & HVICTL_VALID_MASK;
+    return RISCV_EXCP_NONE;
+}
+
+static int read_hvipriox(CPURISCVState *env, int first_index,
+                         uint8_t *iprio, target_ulong *val)
+{
+    int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
+
+    /* First index has to be a multiple of number of irqs per register */
+    if (first_index % num_irqs) {
+        return (riscv_cpu_virt_enabled(env)) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    /* Fill-up return value */
+    *val = 0;
+    for (i = 0; i < num_irqs; i++) {
+        if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
+            continue;
+        }
+        if (rdzero) {
+            continue;
+        }
+        *val |= ((target_ulong)iprio[irq]) << (i * 8);
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static int write_hvipriox(CPURISCVState *env, int first_index,
+                          uint8_t *iprio, target_ulong val)
+{
+    int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
+
+    /* First index has to be a multiple of number of irqs per register */
+    if (first_index % num_irqs) {
+        return (riscv_cpu_virt_enabled(env)) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    /* Fill-up priority arrary */
+    for (i = 0; i < num_irqs; i++) {
+        if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
+            continue;
+        }
+        if (rdzero) {
+            iprio[irq] = 0;
+        } else {
+            iprio[irq] = (val >> (i * 8)) & 0xff;
+        }
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    return read_hvipriox(env, 0, env->hviprio, val);
+}
+
+static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
+{
+    return write_hvipriox(env, 0, env->hviprio, val);
+}
+
+static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    return read_hvipriox(env, 4, env->hviprio, val);
+}
+
+static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
+{
+    return write_hvipriox(env, 4, env->hviprio, val);
+}
+
+static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    return read_hvipriox(env, 8, env->hviprio, val);
+}
+
+static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
+{
+    return write_hvipriox(env, 8, env->hviprio, val);
+}
+
+static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    return read_hvipriox(env, 12, env->hviprio, val);
+}
+
+static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
+{
+    return write_hvipriox(env, 12, env->hviprio, val);
+}
+
 /* Virtual CSR Registers */
 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
+    /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+    [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
+    [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
+    [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
+
     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
+    [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
+    [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
         VMSTATE_UINTTL(env.hgeie, RISCVCPU),
         VMSTATE_UINTTL(env.hgeip, RISCVCPU),
         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+        VMSTATE_UINTTL(env.hvictl, RISCVCPU),
         VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
 
         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.

At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException any32(CPURISCVState *env, int csrno)
 
 }
 
+static int aia_any(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return any(env, csrno);
+}
+
 static int aia_any32(CPURISCVState *env, int csrno)
 {
     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+                                   target_ulong val)
+{
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
+    /* Virtual Interrupts for Supervisor Level (AIA) */
+    [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
+    [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
+
     /* Machine-Level High-Half CSRs (AIA) */
     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
+    [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
+    [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
 
     /* Supervisor Trap Setup */
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+    [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 
     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
+    [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-14-anup@brainfault.org
[ Changed by AF:
 - Fixup indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 156 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 156 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int smode32(CPURISCVState *env, int csrno)
     return smode(env, csrno);
 }
 
+static int aia_smode(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return smode(env, csrno);
+}
+
 static int aia_smode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
 
+#define VSTOPI_NUM_SRCS 5
+
 static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
                                            VS_MODE_INTERRUPTS;
 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
     return ret;
 }
 
+static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    int irq;
+    uint8_t iprio;
+
+    irq = riscv_cpu_mirq_pending(env);
+    if (irq <= 0 || irq > 63) {
+        *val = 0;
+    } else {
+        iprio = env->miprio[irq];
+        if (!iprio) {
+            if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
+                iprio = IPRIO_MMAXIPRIO;
+            }
+        }
+        *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+        *val |= iprio;
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    int irq, ret;
+    target_ulong topei;
+    uint64_t vseip, vsgein;
+    uint32_t iid, iprio, hviid, hviprio, gein;
+    uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
+
+    gein = get_field(env->hstatus, HSTATUS_VGEIN);
+    hviid = get_field(env->hvictl, HVICTL_IID);
+    hviprio = get_field(env->hvictl, HVICTL_IPRIO);
+
+    if (gein) {
+        vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+        vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
+        if (gein <= env->geilen && vseip) {
+            siid[scount] = IRQ_S_EXT;
+            siprio[scount] = IPRIO_MMAXIPRIO + 1;
+            if (env->aia_ireg_rmw_fn[PRV_S]) {
+                /*
+                 * Call machine specific IMSIC register emulation for
+                 * reading TOPEI.
+                 */
+                ret = env->aia_ireg_rmw_fn[PRV_S](
+                        env->aia_ireg_rmw_fn_arg[PRV_S],
+                        AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
+                                      riscv_cpu_mxl_bits(env)),
+                        &topei, 0, 0);
+                if (!ret && topei) {
+                    siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
+                }
+            }
+            scount++;
+        }
+    } else {
+        if (hviid == IRQ_S_EXT && hviprio) {
+            siid[scount] = IRQ_S_EXT;
+            siprio[scount] = hviprio;
+            scount++;
+        }
+    }
+
+    if (env->hvictl & HVICTL_VTI) {
+        if (hviid != IRQ_S_EXT) {
+            siid[scount] = hviid;
+            siprio[scount] = hviprio;
+            scount++;
+        }
+    } else {
+        irq = riscv_cpu_vsirq_pending(env);
+        if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
+            siid[scount] = irq;
+            siprio[scount] = env->hviprio[irq];
+            scount++;
+        }
+    }
+
+    iid = 0;
+    iprio = UINT_MAX;
+    for (s = 0; s < scount; s++) {
+        if (siprio[s] < iprio) {
+            iid = siid[s];
+            iprio = siprio[s];
+        }
+    }
+
+    if (iid) {
+        if (env->hvictl & HVICTL_IPRIOM) {
+            if (iprio > IPRIO_MMAXIPRIO) {
+                iprio = IPRIO_MMAXIPRIO;
+            }
+            if (!iprio) {
+                if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
+                    iprio = IPRIO_MMAXIPRIO;
+                }
+            }
+        } else {
+            iprio = 1;
+        }
+    } else {
+        iprio = 0;
+    }
+
+    *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+    *val |= iprio;
+    return RISCV_EXCP_NONE;
+}
+
+static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    int irq;
+    uint8_t iprio;
+
+    if (riscv_cpu_virt_enabled(env)) {
+        return read_vstopi(env, CSR_VSTOPI, val);
+    }
+
+    irq = riscv_cpu_sirq_pending(env);
+    if (irq <= 0 || irq > 63) {
+        *val = 0;
+    } else {
+        iprio = env->siprio[irq];
+        if (!iprio) {
+            if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
+                iprio = IPRIO_MMAXIPRIO;
+           }
+        }
+        *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+        *val |= iprio;
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
 /* Hypervisor Extensions */
 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
+    /* Machine-Level Interrupts (AIA) */
+    [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
+
     /* Virtual Interrupts for Supervisor Level (AIA) */
     [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
     [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Supervisor Protection and Translation */
     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
 
+    /* Supervisor-Level Interrupts (AIA) */
+    [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
+
     /* Supervisor-Level High-Half CSRs (AIA) */
     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 
+    /* VS-Level Interrupts (H-extension with AIA) */
+    [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
+
     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h     |   7 ++
 target/riscv/csr.c     | 177 +++++++++++++++++++++++++++++++++++++++++
 target/riscv/machine.c |   3 +
 3 files changed, 187 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint8_t miprio[64];
     uint8_t siprio[64];
 
+    /* AIA CSRs */
+    target_ulong miselect;
+    target_ulong siselect;
+
     /* Hypervisor CSRs */
     target_ulong hstatus;
     target_ulong hedeleg;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong vstval;
     target_ulong vsatp;
 
+    /* AIA VS-mode CSRs */
+    target_ulong vsiselect;
+
     target_ulong mtval2;
     target_ulong mtinst;
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
     return RISCV_EXCP_NONE;
 }
 
+static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
+{
+    if (!riscv_cpu_virt_enabled(env)) {
+        return csrno;
+    }
+
+    switch (csrno) {
+    case CSR_SISELECT:
+        return CSR_VSISELECT;
+    case CSR_SIREG:
+        return CSR_VSIREG;
+    default:
+        return csrno;
+    };
+}
+
+static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
+                        target_ulong new_val, target_ulong wr_mask)
+{
+    target_ulong *iselect;
+
+    /* Translate CSR number for VS-mode */
+    csrno = aia_xlate_vs_csrno(env, csrno);
+
+    /* Find the iselect CSR based on CSR number */
+    switch (csrno) {
+    case CSR_MISELECT:
+        iselect = &env->miselect;
+        break;
+    case CSR_SISELECT:
+        iselect = &env->siselect;
+        break;
+    case CSR_VSISELECT:
+        iselect = &env->vsiselect;
+        break;
+    default:
+         return RISCV_EXCP_ILLEGAL_INST;
+    };
+
+    if (val) {
+        *val = *iselect;
+    }
+
+    wr_mask &= ISELECT_MASK;
+    if (wr_mask) {
+        *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static int rmw_iprio(target_ulong xlen,
+                     target_ulong iselect, uint8_t *iprio,
+                     target_ulong *val, target_ulong new_val,
+                     target_ulong wr_mask, int ext_irq_no)
+{
+    int i, firq, nirqs;
+    target_ulong old_val;
+
+    if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
+        return -EINVAL;
+    }
+    if (xlen != 32 && iselect & 0x1) {
+        return -EINVAL;
+    }
+
+    nirqs = 4 * (xlen / 32);
+    firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
+
+    old_val = 0;
+    for (i = 0; i < nirqs; i++) {
+        old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
+    }
+
+    if (val) {
+        *val = old_val;
+    }
+
+    if (wr_mask) {
+        new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
+        for (i = 0; i < nirqs; i++) {
+            /*
+             * M-level and S-level external IRQ priority always read-only
+             * zero. This means default priority order is always preferred
+             * for M-level and S-level external IRQs.
+             */
+            if ((firq + i) == ext_irq_no) {
+                continue;
+            }
+            iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
+        }
+    }
+
+    return 0;
+}
+
+static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
+                     target_ulong new_val, target_ulong wr_mask)
+{
+    bool virt;
+    uint8_t *iprio;
+    int ret = -EINVAL;
+    target_ulong priv, isel, vgein;
+
+    /* Translate CSR number for VS-mode */
+    csrno = aia_xlate_vs_csrno(env, csrno);
+
+    /* Decode register details from CSR number */
+    virt = false;
+    switch (csrno) {
+    case CSR_MIREG:
+        iprio = env->miprio;
+        isel = env->miselect;
+        priv = PRV_M;
+        break;
+    case CSR_SIREG:
+        iprio = env->siprio;
+        isel = env->siselect;
+        priv = PRV_S;
+        break;
+    case CSR_VSIREG:
+        iprio = env->hviprio;
+        isel = env->vsiselect;
+        priv = PRV_S;
+        virt = true;
+        break;
+    default:
+         goto done;
+    };
+
+    /* Find the selected guest interrupt file */
+    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+    if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
+        /* Local interrupt priority registers not available for VS-mode */
+        if (!virt) {
+            ret = rmw_iprio(riscv_cpu_mxl_bits(env),
+                            isel, iprio, val, new_val, wr_mask,
+                            (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
+        }
+    } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
+        /* IMSIC registers only available when machine implements it. */
+        if (env->aia_ireg_rmw_fn[priv]) {
+            /* Selected guest interrupt file should not be zero */
+            if (virt && (!vgein || env->geilen < vgein)) {
+                goto done;
+            }
+            /* Call machine specific IMSIC register emulation */
+            ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+                                    AIA_MAKE_IREG(isel, priv, virt, vgein,
+                                                  riscv_cpu_mxl_bits(env)),
+                                    val, new_val, wr_mask);
+        }
+    }
+
+done:
+    if (ret) {
+        return (riscv_cpu_virt_enabled(env) && virt) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
+    /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+    [CSR_MISELECT] = { "miselect", aia_any,   NULL, NULL,    rmw_xiselect },
+    [CSR_MIREG]    = { "mireg",    aia_any,   NULL, NULL,    rmw_xireg },
+
     /* Machine-Level Interrupts (AIA) */
     [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Supervisor Protection and Translation */
     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
 
+    /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+    [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
+    [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },
+
     /* Supervisor-Level Interrupts (AIA) */
     [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 
+    /*
+     * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
+     */
+    [CSR_VSISELECT]   = { "vsiselect",   aia_hmode, NULL, NULL,      rmw_xiselect },
+    [CSR_VSIREG]      = { "vsireg",      aia_hmode, NULL, NULL,      rmw_xireg },
+
     /* VS-Level Interrupts (H-extension with AIA) */
     [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
         VMSTATE_UINTTL(env.vscause, RISCVCPU),
         VMSTATE_UINTTL(env.vstval, RISCVCPU),
         VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+        VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
 
         VMSTATE_UINTTL(env.mtval2, RISCVCPU),
         VMSTATE_UINTTL(env.mtinst, RISCVCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINTTL(env.mepc, RISCVCPU),
         VMSTATE_UINTTL(env.mcause, RISCVCPU),
         VMSTATE_UINTTL(env.mtval, RISCVCPU),
+        VMSTATE_UINTTL(env.miselect, RISCVCPU),
+        VMSTATE_UINTTL(env.siselect, RISCVCPU),
         VMSTATE_UINTTL(env.scounteren, RISCVCPU),
         VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
         return CSR_VSISELECT;
     case CSR_SIREG:
         return CSR_VSIREG;
+    case CSR_SSETEIPNUM:
+        return CSR_VSSETEIPNUM;
+    case CSR_SCLREIPNUM:
+        return CSR_VSCLREIPNUM;
+    case CSR_SSETEIENUM:
+        return CSR_VSSETEIENUM;
+    case CSR_SCLREIENUM:
+        return CSR_VSCLREIENUM;
+    case CSR_STOPEI:
+        return CSR_VSTOPEI;
     default:
         return csrno;
     };
@@ -XXX,XX +XXX,XX @@ done:
     return RISCV_EXCP_NONE;
 }
 
+static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
+                            target_ulong new_val, target_ulong wr_mask)
+{
+    int ret = -EINVAL;
+    bool set, pend, virt;
+    target_ulong priv, isel, vgein, xlen, nval, wmask;
+
+    /* Translate CSR number for VS-mode */
+    csrno = aia_xlate_vs_csrno(env, csrno);
+
+    /* Decode register details from CSR number */
+    virt = set = pend = false;
+    switch (csrno) {
+    case CSR_MSETEIPNUM:
+        priv = PRV_M;
+        set = true;
+        pend = true;
+        break;
+    case CSR_MCLREIPNUM:
+        priv = PRV_M;
+        pend = true;
+        break;
+    case CSR_MSETEIENUM:
+        priv = PRV_M;
+        set = true;
+        break;
+    case CSR_MCLREIENUM:
+        priv = PRV_M;
+        break;
+    case CSR_SSETEIPNUM:
+        priv = PRV_S;
+        set = true;
+        pend = true;
+        break;
+    case CSR_SCLREIPNUM:
+        priv = PRV_S;
+        pend = true;
+        break;
+    case CSR_SSETEIENUM:
+        priv = PRV_S;
+        set = true;
+        break;
+    case CSR_SCLREIENUM:
+        priv = PRV_S;
+        break;
+    case CSR_VSSETEIPNUM:
+        priv = PRV_S;
+        virt = true;
+        set = true;
+        pend = true;
+        break;
+    case CSR_VSCLREIPNUM:
+        priv = PRV_S;
+        virt = true;
+        pend = true;
+        break;
+    case CSR_VSSETEIENUM:
+        priv = PRV_S;
+        virt = true;
+        set = true;
+        break;
+    case CSR_VSCLREIENUM:
+        priv = PRV_S;
+        virt = true;
+        break;
+    default:
+         goto done;
+    };
+
+    /* IMSIC CSRs only available when machine implements IMSIC. */
+    if (!env->aia_ireg_rmw_fn[priv]) {
+        goto done;
+    }
+
+    /* Find the selected guest interrupt file */
+    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+    /* Selected guest interrupt file should be valid */
+    if (virt && (!vgein || env->geilen < vgein)) {
+        goto done;
+    }
+
+    /* Set/Clear CSRs always read zero */
+    if (val) {
+        *val = 0;
+    }
+
+    if (wr_mask) {
+        /* Get interrupt number */
+        new_val &= wr_mask;
+
+        /* Find target interrupt pending/enable register */
+        xlen = riscv_cpu_mxl_bits(env);
+        isel = (new_val / xlen);
+        isel *= (xlen / IMSIC_EIPx_BITS);
+        isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
+
+        /* Find the interrupt bit to be set/clear */
+        wmask = ((target_ulong)1) << (new_val % xlen);
+        nval = (set) ? wmask : 0;
+
+        /* Call machine specific IMSIC register emulation */
+        ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+                                         AIA_MAKE_IREG(isel, priv, virt,
+                                                       vgein, xlen),
+                                         NULL, nval, wmask);
+    } else {
+        ret = 0;
+    }
+
+done:
+    if (ret) {
+        return (riscv_cpu_virt_enabled(env) && virt) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+    return RISCV_EXCP_NONE;
+}
+
+static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
+                      target_ulong new_val, target_ulong wr_mask)
+{
+    bool virt;
+    int ret = -EINVAL;
+    target_ulong priv, vgein;
+
+    /* Translate CSR number for VS-mode */
+    csrno = aia_xlate_vs_csrno(env, csrno);
+
+    /* Decode register details from CSR number */
+    virt = false;
+    switch (csrno) {
+    case CSR_MTOPEI:
+        priv = PRV_M;
+        break;
+    case CSR_STOPEI:
+        priv = PRV_S;
+        break;
+    case CSR_VSTOPEI:
+        priv = PRV_S;
+        virt = true;
+        break;
+    default:
+        goto done;
+    };
+
+    /* IMSIC CSRs only available when machine implements IMSIC. */
+    if (!env->aia_ireg_rmw_fn[priv]) {
+        goto done;
+    }
+
+    /* Find the selected guest interrupt file */
+    vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+    /* Selected guest interrupt file should be valid */
+    if (virt && (!vgein || env->geilen < vgein)) {
+        goto done;
+    }
+
+    /* Call machine specific IMSIC register emulation for TOPEI */
+    ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+                    AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
+                                  riscv_cpu_mxl_bits(env)),
+                    val, new_val, wr_mask);
+
+done:
+    if (ret) {
+        return (riscv_cpu_virt_enabled(env) && virt) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Machine-Level Interrupts (AIA) */
     [CSR_MTOPI]    = { "mtopi",    aia_any,   read_mtopi },
 
+    /* Machine-Level IMSIC Interface (AIA) */
+    [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+    [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+    [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+    [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+    [CSR_MTOPEI]     = { "mtopei",     aia_any, NULL, NULL, rmw_xtopei },
+
     /* Virtual Interrupts for Supervisor Level (AIA) */
     [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
     [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Supervisor-Level Interrupts (AIA) */
     [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
 
+    /* Supervisor-Level IMSIC Interface (AIA) */
+    [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_STOPEI]     = { "stopei",     aia_smode, NULL, NULL, rmw_xtopei },
+
     /* Supervisor-Level High-Half CSRs (AIA) */
     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* VS-Level Interrupts (H-extension with AIA) */
     [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
 
+    /* VS-Level IMSIC Interface (H-extension with AIA) */
+    [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+    [CSR_VSTOPEI]     = { "vstopei",     aia_hmode, NULL, NULL, rmw_xtopei },
+
     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
         qemu_fdt_add_subnode(mc->fdt, intc_name);
         qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
             intc_phandles[cpu]);
-        qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
-            "riscv,cpu-intc");
+        if (riscv_feature(&s->soc[socket].harts[cpu].env,
+                          RISCV_FEATURE_AIA)) {
+            static const char * const compat[2] = {
+                "riscv,cpu-intc-aia", "riscv,cpu-intc"
+            };
+            qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
+                                      (char **)&compat, ARRAY_SIZE(compat));
+        } else {
+            qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+                "riscv,cpu-intc");
+        }
         qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
         qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
 
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool mmu;
     bool pmp;
     bool epmp;
+    bool aia;
     uint64_t resetvec;
 };
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    if (cpu->cfg.aia) {
+        riscv_set_feature(env, RISCV_FEATURE_AIA);
+    }
+
     set_resetvec(env, cpu->cfg.resetvec);
 
     /* Validate that MISA_MXL is set properly. */
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+    DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
 
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).

This patch adds device emulation for RISC-V AIA APLIC.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aplic.h |  79 +++
 hw/intc/riscv_aplic.c         | 978 ++++++++++++++++++++++++++++++++++
 hw/intc/Kconfig               |   3 +
 hw/intc/meson.build           |   1 +
 4 files changed, 1061 insertions(+)
 create mode 100644 include/hw/intc/riscv_aplic.h
 create mode 100644 hw/intc/riscv_aplic.c

diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/riscv_aplic.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_APLIC_H
+#define HW_RISCV_APLIC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_APLIC "riscv.aplic"
+
+typedef struct RISCVAPLICState RISCVAPLICState;
+DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
+
+#define APLIC_MIN_SIZE            0x4000
+#define APLIC_SIZE_ALIGN(__x)     (((__x) + (APLIC_MIN_SIZE - 1)) & \
+                                   ~(APLIC_MIN_SIZE - 1))
+#define APLIC_SIZE(__num_harts)   (APLIC_MIN_SIZE + \
+                                   APLIC_SIZE_ALIGN(32 * (__num_harts)))
+
+struct RISCVAPLICState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    qemu_irq *external_irqs;
+
+    /*< public >*/
+    MemoryRegion mmio;
+    uint32_t bitfield_words;
+    uint32_t domaincfg;
+    uint32_t mmsicfgaddr;
+    uint32_t mmsicfgaddrH;
+    uint32_t smsicfgaddr;
+    uint32_t smsicfgaddrH;
+    uint32_t genmsi;
+    uint32_t *sourcecfg;
+    uint32_t *state;
+    uint32_t *target;
+    uint32_t *idelivery;
+    uint32_t *iforce;
+    uint32_t *ithreshold;
+
+    /* topology */
+#define QEMU_APLIC_MAX_CHILDREN        16
+    struct RISCVAPLICState *parent;
+    struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
+    uint16_t num_children;
+
+    /* config */
+    uint32_t aperture_size;
+    uint32_t hartid_base;
+    uint32_t num_harts;
+    uint32_t iprio_mask;
+    uint32_t num_irqs;
+    bool msimode;
+    bool mmode;
+};
+
+void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
+
+DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+    uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
+    uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
+
+#endif
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/bswap.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/riscv_aplic.h"
+#include "hw/irq.h"
+#include "target/riscv/cpu.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+
+#define APLIC_MAX_IDC                  (1UL << 14)
+#define APLIC_MAX_SOURCE               1024
+#define APLIC_MIN_IPRIO_BITS           1
+#define APLIC_MAX_IPRIO_BITS           8
+#define APLIC_MAX_CHILDREN             1024
+
+#define APLIC_DOMAINCFG                0x0000
+#define APLIC_DOMAINCFG_RDONLY         0x80000000
+#define APLIC_DOMAINCFG_IE             (1 << 8)
+#define APLIC_DOMAINCFG_DM             (1 << 2)
+#define APLIC_DOMAINCFG_BE             (1 << 0)
+
+#define APLIC_SOURCECFG_BASE           0x0004
+#define APLIC_SOURCECFG_D              (1 << 10)
+#define APLIC_SOURCECFG_CHILDIDX_MASK  0x000003ff
+#define APLIC_SOURCECFG_SM_MASK        0x00000007
+#define APLIC_SOURCECFG_SM_INACTIVE    0x0
+#define APLIC_SOURCECFG_SM_DETACH      0x1
+#define APLIC_SOURCECFG_SM_EDGE_RISE   0x4
+#define APLIC_SOURCECFG_SM_EDGE_FALL   0x5
+#define APLIC_SOURCECFG_SM_LEVEL_HIGH  0x6
+#define APLIC_SOURCECFG_SM_LEVEL_LOW   0x7
+
+#define APLIC_MMSICFGADDR              0x1bc0
+#define APLIC_MMSICFGADDRH             0x1bc4
+#define APLIC_SMSICFGADDR              0x1bc8
+#define APLIC_SMSICFGADDRH             0x1bcc
+
+#define APLIC_xMSICFGADDRH_L           (1UL << 31)
+#define APLIC_xMSICFGADDRH_HHXS_MASK   0x1f
+#define APLIC_xMSICFGADDRH_HHXS_SHIFT  24
+#define APLIC_xMSICFGADDRH_LHXS_MASK   0x7
+#define APLIC_xMSICFGADDRH_LHXS_SHIFT  20
+#define APLIC_xMSICFGADDRH_HHXW_MASK   0x7
+#define APLIC_xMSICFGADDRH_HHXW_SHIFT  16
+#define APLIC_xMSICFGADDRH_LHXW_MASK   0xf
+#define APLIC_xMSICFGADDRH_LHXW_SHIFT  12
+#define APLIC_xMSICFGADDRH_BAPPN_MASK  0xfff
+
+#define APLIC_xMSICFGADDR_PPN_SHIFT    12
+
+#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
+    ((1UL << (__lhxs)) - 1)
+
+#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
+    ((1UL << (__lhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
+    ((__lhxs))
+#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
+    (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
+     APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
+
+#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
+    ((1UL << (__hhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
+    ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
+#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
+    (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
+     APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
+
+#define APLIC_xMSICFGADDRH_VALID_MASK   \
+    (APLIC_xMSICFGADDRH_L | \
+     (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \
+     (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \
+     (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \
+     (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \
+     APLIC_xMSICFGADDRH_BAPPN_MASK)
+
+#define APLIC_SETIP_BASE               0x1c00
+#define APLIC_SETIPNUM                 0x1cdc
+
+#define APLIC_CLRIP_BASE               0x1d00
+#define APLIC_CLRIPNUM                 0x1ddc
+
+#define APLIC_SETIE_BASE               0x1e00
+#define APLIC_SETIENUM                 0x1edc
+
+#define APLIC_CLRIE_BASE               0x1f00
+#define APLIC_CLRIENUM                 0x1fdc
+
+#define APLIC_SETIPNUM_LE              0x2000
+#define APLIC_SETIPNUM_BE              0x2004
+
+#define APLIC_ISTATE_PENDING           (1U << 0)
+#define APLIC_ISTATE_ENABLED           (1U << 1)
+#define APLIC_ISTATE_ENPEND            (APLIC_ISTATE_ENABLED | \
+                                        APLIC_ISTATE_PENDING)
+#define APLIC_ISTATE_INPUT             (1U << 8)
+
+#define APLIC_GENMSI                   0x3000
+
+#define APLIC_TARGET_BASE              0x3004
+#define APLIC_TARGET_HART_IDX_SHIFT    18
+#define APLIC_TARGET_HART_IDX_MASK     0x3fff
+#define APLIC_TARGET_GUEST_IDX_SHIFT   12
+#define APLIC_TARGET_GUEST_IDX_MASK    0x3f
+#define APLIC_TARGET_IPRIO_MASK        0xff
+#define APLIC_TARGET_EIID_MASK         0x7ff
+
+#define APLIC_IDC_BASE                 0x4000
+#define APLIC_IDC_SIZE                 32
+
+#define APLIC_IDC_IDELIVERY            0x00
+
+#define APLIC_IDC_IFORCE               0x04
+
+#define APLIC_IDC_ITHRESHOLD           0x08
+
+#define APLIC_IDC_TOPI                 0x18
+#define APLIC_IDC_TOPI_ID_SHIFT        16
+#define APLIC_IDC_TOPI_ID_MASK         0x3ff
+#define APLIC_IDC_TOPI_PRIO_MASK       0xff
+
+#define APLIC_IDC_CLAIMI               0x1c
+
+static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
+                                            uint32_t word)
+{
+    uint32_t i, irq, ret = 0;
+
+    for (i = 0; i < 32; i++) {
+        irq = word * 32 + i;
+        if (!irq || aplic->num_irqs <= irq) {
+            continue;
+        }
+
+        ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
+    }
+
+    return ret;
+}
+
+static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic,
+                                              uint32_t word)
+{
+    uint32_t i, irq, ret = 0;
+
+    for (i = 0; i < 32; i++) {
+        irq = word * 32 + i;
+        if (!irq || aplic->num_irqs <= irq) {
+            continue;
+        }
+
+        ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i;
+    }
+
+    return ret;
+}
+
+static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic,
+                                        uint32_t irq, bool pending)
+{
+    if (pending) {
+        aplic->state[irq] |= APLIC_ISTATE_PENDING;
+    } else {
+        aplic->state[irq] &= ~APLIC_ISTATE_PENDING;
+    }
+}
+
+static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
+                                    uint32_t irq, bool pending)
+{
+    uint32_t sourcecfg, sm;
+
+    if ((irq <= 0) || (aplic->num_irqs <= irq)) {
+        return;
+    }
+
+    sourcecfg = aplic->sourcecfg[irq];
+    if (sourcecfg & APLIC_SOURCECFG_D) {
+        return;
+    }
+
+    sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+    if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
+        ((!aplic->msimode || (aplic->msimode && !pending)) &&
+         ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
+          (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
+        return;
+    }
+
+    riscv_aplic_set_pending_raw(aplic, irq, pending);
+}
+
+static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic,
+                                         uint32_t word, uint32_t value,
+                                         bool pending)
+{
+    uint32_t i, irq;
+
+    for (i = 0; i < 32; i++) {
+        irq = word * 32 + i;
+        if (!irq || aplic->num_irqs <= irq) {
+            continue;
+        }
+
+        if (value & (1U << i)) {
+            riscv_aplic_set_pending(aplic, irq, pending);
+        }
+    }
+}
+
+static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic,
+                                              int word)
+{
+    uint32_t i, irq, ret = 0;
+
+    for (i = 0; i < 32; i++) {
+        irq = word * 32 + i;
+        if (!irq || aplic->num_irqs <= irq) {
+            continue;
+        }
+
+        ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i;
+    }
+
+    return ret;
+}
+
+static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic,
+                                        uint32_t irq, bool enabled)
+{
+    if (enabled) {
+        aplic->state[irq] |= APLIC_ISTATE_ENABLED;
+    } else {
+        aplic->state[irq] &= ~APLIC_ISTATE_ENABLED;
+    }
+}
+
+static void riscv_aplic_set_enabled(RISCVAPLICState *aplic,
+                                    uint32_t irq, bool enabled)
+{
+    uint32_t sourcecfg, sm;
+
+    if ((irq <= 0) || (aplic->num_irqs <= irq)) {
+        return;
+    }
+
+    sourcecfg = aplic->sourcecfg[irq];
+    if (sourcecfg & APLIC_SOURCECFG_D) {
+        return;
+    }
+
+    sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+    if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+        return;
+    }
+
+    riscv_aplic_set_enabled_raw(aplic, irq, enabled);
+}
+
+static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic,
+                                         uint32_t word, uint32_t value,
+                                         bool enabled)
+{
+    uint32_t i, irq;
+
+    for (i = 0; i < 32; i++) {
+        irq = word * 32 + i;
+        if (!irq || aplic->num_irqs <= irq) {
+            continue;
+        }
+
+        if (value & (1U << i)) {
+            riscv_aplic_set_enabled(aplic, irq, enabled);
+        }
+    }
+}
+
+static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
+                                 uint32_t hart_idx, uint32_t guest_idx,
+                                 uint32_t eiid)
+{
+    uint64_t addr;
+    MemTxResult result;
+    RISCVAPLICState *aplic_m;
+    uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
+
+    aplic_m = aplic;
+    while (aplic_m && !aplic_m->mmode) {
+        aplic_m = aplic_m->parent;
+    }
+    if (!aplic_m) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
+                      __func__);
+        return;
+    }
+
+    if (aplic->mmode) {
+        msicfgaddr = aplic_m->mmsicfgaddr;
+        msicfgaddrH = aplic_m->mmsicfgaddrH;
+    } else {
+        msicfgaddr = aplic_m->smsicfgaddr;
+        msicfgaddrH = aplic_m->smsicfgaddrH;
+    }
+
+    lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
+            APLIC_xMSICFGADDRH_LHXS_MASK;
+    lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) &
+            APLIC_xMSICFGADDRH_LHXW_MASK;
+    hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) &
+            APLIC_xMSICFGADDRH_HHXS_MASK;
+    hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) &
+            APLIC_xMSICFGADDRH_HHXW_MASK;
+
+    group_idx = hart_idx >> lhxw;
+    hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
+
+    addr = msicfgaddr;
+    addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
+    addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) <<
+             APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs);
+    addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) <<
+             APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs);
+    addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
+    addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
+
+    address_space_stl_le(&address_space_memory, addr,
+                         eiid, MEMTXATTRS_UNSPECIFIED, &result);
+    if (result != MEMTX_OK) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
+                      "hart_index=%d guest_index=%d eiid=%d\n",
+                      __func__, hart_idx, guest_idx, eiid);
+    }
+}
+
+static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq)
+{
+    uint32_t hart_idx, guest_idx, eiid;
+
+    if (!aplic->msimode || (aplic->num_irqs <= irq) ||
+        !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) {
+        return;
+    }
+
+    if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) {
+        return;
+    }
+
+    riscv_aplic_set_pending_raw(aplic, irq, false);
+
+    hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+    hart_idx &= APLIC_TARGET_HART_IDX_MASK;
+    if (aplic->mmode) {
+        /* M-level APLIC ignores guest_index */
+        guest_idx = 0;
+    } else {
+        guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT;
+        guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
+    }
+    eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK;
+    riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid);
+}
+
+static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc)
+{
+    uint32_t best_irq, best_iprio;
+    uint32_t irq, iprio, ihartidx, ithres;
+
+    if (aplic->num_harts <= idc) {
+        return 0;
+    }
+
+    ithres = aplic->ithreshold[idc];
+    best_irq = best_iprio = UINT32_MAX;
+    for (irq = 1; irq < aplic->num_irqs; irq++) {
+        if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=
+            APLIC_ISTATE_ENPEND) {
+            continue;
+        }
+
+        ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+        ihartidx &= APLIC_TARGET_HART_IDX_MASK;
+        if (ihartidx != idc) {
+            continue;
+        }
+
+        iprio = aplic->target[irq] & aplic->iprio_mask;
+        if (ithres && iprio >= ithres) {
+            continue;
+        }
+
+        if (iprio < best_iprio) {
+            best_irq = irq;
+            best_iprio = iprio;
+        }
+    }
+
+    if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) {
+        return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio;
+    }
+
+    return 0;
+}
+
+static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc)
+{
+    uint32_t topi;
+
+    if (aplic->msimode || aplic->num_harts <= idc) {
+        return;
+    }
+
+    topi = riscv_aplic_idc_topi(aplic, idc);
+    if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) &&
+        aplic->idelivery[idc] &&
+        (aplic->iforce[idc] || topi)) {
+        qemu_irq_raise(aplic->external_irqs[idc]);
+    } else {
+        qemu_irq_lower(aplic->external_irqs[idc]);
+    }
+}
+
+static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
+{
+    uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc);
+
+    if (!topi) {
+        aplic->iforce[idc] = 0;
+        return 0;
+    }
+
+    irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;
+    sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
+    state = aplic->state[irq];
+    riscv_aplic_set_pending_raw(aplic, irq, false);
+    if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) &&
+        (state & APLIC_ISTATE_INPUT)) {
+        riscv_aplic_set_pending_raw(aplic, irq, true);
+    } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) &&
+               !(state & APLIC_ISTATE_INPUT)) {
+        riscv_aplic_set_pending_raw(aplic, irq, true);
+    }
+    riscv_aplic_idc_update(aplic, idc);
+
+    return topi;
+}
+
+static void riscv_aplic_request(void *opaque, int irq, int level)
+{
+    bool update = false;
+    RISCVAPLICState *aplic = opaque;
+    uint32_t sourcecfg, childidx, state, idc;
+
+    assert((0 < irq) && (irq < aplic->num_irqs));
+
+    sourcecfg = aplic->sourcecfg[irq];
+    if (sourcecfg & APLIC_SOURCECFG_D) {
+        childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK;
+        if (childidx < aplic->num_children) {
+            riscv_aplic_request(aplic->children[childidx], irq, level);
+        }
+        return;
+    }
+
+    state = aplic->state[irq];
+    switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) {
+    case APLIC_SOURCECFG_SM_EDGE_RISE:
+        if ((level > 0) && !(state & APLIC_ISTATE_INPUT) &&
+            !(state & APLIC_ISTATE_PENDING)) {
+            riscv_aplic_set_pending_raw(aplic, irq, true);
+            update = true;
+        }
+        break;
+    case APLIC_SOURCECFG_SM_EDGE_FALL:
+        if ((level <= 0) && (state & APLIC_ISTATE_INPUT) &&
+            !(state & APLIC_ISTATE_PENDING)) {
+            riscv_aplic_set_pending_raw(aplic, irq, true);
+            update = true;
+        }
+        break;
+    case APLIC_SOURCECFG_SM_LEVEL_HIGH:
+        if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) {
+            riscv_aplic_set_pending_raw(aplic, irq, true);
+            update = true;
+        }
+        break;
+    case APLIC_SOURCECFG_SM_LEVEL_LOW:
+        if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) {
+            riscv_aplic_set_pending_raw(aplic, irq, true);
+            update = true;
+        }
+        break;
+    default:
+        break;
+    }
+
+    if (level <= 0) {
+        aplic->state[irq] &= ~APLIC_ISTATE_INPUT;
+    } else {
+        aplic->state[irq] |= APLIC_ISTATE_INPUT;
+    }
+
+    if (update) {
+        if (aplic->msimode) {
+            riscv_aplic_msi_irq_update(aplic, irq);
+        } else {
+            idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+            idc &= APLIC_TARGET_HART_IDX_MASK;
+            riscv_aplic_idc_update(aplic, idc);
+        }
+    }
+}
+
+static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
+{
+    uint32_t irq, word, idc;
+    RISCVAPLICState *aplic = opaque;
+
+    /* Reads must be 4 byte words */
+    if ((addr & 0x3) != 0) {
+        goto err;
+    }
+
+    if (addr == APLIC_DOMAINCFG) {
+        return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg |
+               (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);
+    } else if ((APLIC_SOURCECFG_BASE <= addr) &&
+            (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
+        irq  = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
+        return aplic->sourcecfg[irq];
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_MMSICFGADDR)) {
+        return aplic->mmsicfgaddr;
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_MMSICFGADDRH)) {
+        return aplic->mmsicfgaddrH;
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_SMSICFGADDR)) {
+        /*
+         * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
+         * (a) the interrupt domain is at machine level
+         * (b) the domain's harts implement supervisor mode
+         * (c) the domain has one or more child supervisor-level domains
+         *     that support MSI delivery mode (domaincfg.DM is not read-
+         *     only zero in at least one of the supervisor-level child
+         * domains).
+         */
+        return (aplic->num_children) ? aplic->smsicfgaddr : 0;
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_SMSICFGADDRH)) {
+        return (aplic->num_children) ? aplic->smsicfgaddrH : 0;
+    } else if ((APLIC_SETIP_BASE <= addr) &&
+            (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_SETIP_BASE) >> 2;
+        return riscv_aplic_read_pending_word(aplic, word);
+    } else if (addr == APLIC_SETIPNUM) {
+        return 0;
+    } else if ((APLIC_CLRIP_BASE <= addr) &&
+            (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_CLRIP_BASE) >> 2;
+        return riscv_aplic_read_input_word(aplic, word);
+    } else if (addr == APLIC_CLRIPNUM) {
+        return 0;
+    } else if ((APLIC_SETIE_BASE <= addr) &&
+            (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_SETIE_BASE) >> 2;
+        return riscv_aplic_read_enabled_word(aplic, word);
+    } else if (addr == APLIC_SETIENUM) {
+        return 0;
+    } else if ((APLIC_CLRIE_BASE <= addr) &&
+            (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
+        return 0;
+    } else if (addr == APLIC_CLRIENUM) {
+        return 0;
+    } else if (addr == APLIC_SETIPNUM_LE) {
+        return 0;
+    } else if (addr == APLIC_SETIPNUM_BE) {
+        return 0;
+    } else if (addr == APLIC_GENMSI) {
+        return (aplic->msimode) ? aplic->genmsi : 0;
+    } else if ((APLIC_TARGET_BASE <= addr) &&
+            (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
+        irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+        return aplic->target[irq];
+    } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
+            (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
+        idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
+        switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
+        case APLIC_IDC_IDELIVERY:
+            return aplic->idelivery[idc];
+        case APLIC_IDC_IFORCE:
+            return aplic->iforce[idc];
+        case APLIC_IDC_ITHRESHOLD:
+            return aplic->ithreshold[idc];
+        case APLIC_IDC_TOPI:
+            return riscv_aplic_idc_topi(aplic, idc);
+        case APLIC_IDC_CLAIMI:
+            return riscv_aplic_idc_claimi(aplic, idc);
+        default:
+            goto err;
+        };
+    }
+
+err:
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
+    return 0;
+}
+
+static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
+        unsigned size)
+{
+    RISCVAPLICState *aplic = opaque;
+    uint32_t irq, word, idc = UINT32_MAX;
+
+    /* Writes must be 4 byte words */
+    if ((addr & 0x3) != 0) {
+        goto err;
+    }
+
+    if (addr == APLIC_DOMAINCFG) {
+        /* Only IE bit writeable at the moment */
+        value &= APLIC_DOMAINCFG_IE;
+        aplic->domaincfg = value;
+    } else if ((APLIC_SOURCECFG_BASE <= addr) &&
+            (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
+        irq  = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
+        if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) {
+            value = 0;
+        }
+        if (value & APLIC_SOURCECFG_D) {
+            value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK);
+        } else {
+            value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK);
+        }
+        aplic->sourcecfg[irq] = value;
+        if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) ||
+            (aplic->sourcecfg[irq] == 0)) {
+            riscv_aplic_set_pending_raw(aplic, irq, false);
+            riscv_aplic_set_enabled_raw(aplic, irq, false);
+        }
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_MMSICFGADDR)) {
+        if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+            aplic->mmsicfgaddr = value;
+        }
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_MMSICFGADDRH)) {
+        if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+            aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
+        }
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_SMSICFGADDR)) {
+        /*
+         * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
+         * (a) the interrupt domain is at machine level
+         * (b) the domain's harts implement supervisor mode
+         * (c) the domain has one or more child supervisor-level domains
+         *     that support MSI delivery mode (domaincfg.DM is not read-
+         *     only zero in at least one of the supervisor-level child
+         * domains).
+         */
+        if (aplic->num_children &&
+            !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+            aplic->smsicfgaddr = value;
+        }
+    } else if (aplic->mmode && aplic->msimode &&
+               (addr == APLIC_SMSICFGADDRH)) {
+        if (aplic->num_children &&
+            !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+            aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
+        }
+    } else if ((APLIC_SETIP_BASE <= addr) &&
+            (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_SETIP_BASE) >> 2;
+        riscv_aplic_set_pending_word(aplic, word, value, true);
+    } else if (addr == APLIC_SETIPNUM) {
+        riscv_aplic_set_pending(aplic, value, true);
+    } else if ((APLIC_CLRIP_BASE <= addr) &&
+            (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_CLRIP_BASE) >> 2;
+        riscv_aplic_set_pending_word(aplic, word, value, false);
+    } else if (addr == APLIC_CLRIPNUM) {
+        riscv_aplic_set_pending(aplic, value, false);
+    } else if ((APLIC_SETIE_BASE <= addr) &&
+            (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_SETIE_BASE) >> 2;
+        riscv_aplic_set_enabled_word(aplic, word, value, true);
+    } else if (addr == APLIC_SETIENUM) {
+        riscv_aplic_set_enabled(aplic, value, true);
+    } else if ((APLIC_CLRIE_BASE <= addr) &&
+            (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
+        word = (addr - APLIC_CLRIE_BASE) >> 2;
+        riscv_aplic_set_enabled_word(aplic, word, value, false);
+    } else if (addr == APLIC_CLRIENUM) {
+        riscv_aplic_set_enabled(aplic, value, false);
+    } else if (addr == APLIC_SETIPNUM_LE) {
+        riscv_aplic_set_pending(aplic, value, true);
+    } else if (addr == APLIC_SETIPNUM_BE) {
+        riscv_aplic_set_pending(aplic, bswap32(value), true);
+    } else if (addr == APLIC_GENMSI) {
+        if (aplic->msimode) {
+            aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK <<
+                                      APLIC_TARGET_GUEST_IDX_SHIFT);
+            riscv_aplic_msi_send(aplic,
+                                 value >> APLIC_TARGET_HART_IDX_SHIFT,
+                                 0,
+                                 value & APLIC_TARGET_EIID_MASK);
+        }
+    } else if ((APLIC_TARGET_BASE <= addr) &&
+            (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
+        irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+        if (aplic->msimode) {
+            aplic->target[irq] = value;
+        } else {
+            aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) |
+                                 ((value & aplic->iprio_mask) ?
+                                  (value & aplic->iprio_mask) : 1);
+        }
+    } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
+            (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
+        idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
+        switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
+        case APLIC_IDC_IDELIVERY:
+            aplic->idelivery[idc] = value & 0x1;
+            break;
+        case APLIC_IDC_IFORCE:
+            aplic->iforce[idc] = value & 0x1;
+            break;
+        case APLIC_IDC_ITHRESHOLD:
+            aplic->ithreshold[idc] = value & aplic->iprio_mask;
+            break;
+        default:
+            goto err;
+        };
+    } else {
+        goto err;
+    }
+
+    if (aplic->msimode) {
+        for (irq = 1; irq < aplic->num_irqs; irq++) {
+            riscv_aplic_msi_irq_update(aplic, irq);
+        }
+    } else {
+        if (idc == UINT32_MAX) {
+            for (idc = 0; idc < aplic->num_harts; idc++) {
+                riscv_aplic_idc_update(aplic, idc);
+            }
+        } else {
+            riscv_aplic_idc_update(aplic, idc);
+        }
+    }
+
+    return;
+
+err:
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
+}
+
+static const MemoryRegionOps riscv_aplic_ops = {
+    .read = riscv_aplic_read,
+    .write = riscv_aplic_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4
+    }
+};
+
+static void riscv_aplic_realize(DeviceState *dev, Error **errp)
+{
+    uint32_t i;
+    RISCVAPLICState *aplic = RISCV_APLIC(dev);
+
+    aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
+    aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
+    aplic->state = g_new(uint32_t, aplic->num_irqs);
+    aplic->target = g_new0(uint32_t, aplic->num_irqs);
+    if (!aplic->msimode) {
+        for (i = 0; i < aplic->num_irqs; i++) {
+            aplic->target[i] = 1;
+        }
+    }
+    aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
+    aplic->iforce = g_new0(uint32_t, aplic->num_harts);
+    aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
+
+    memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
+                          TYPE_RISCV_APLIC, aplic->aperture_size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+
+    /*
+     * Only root APLICs have hardware IRQ lines. All non-root APLICs
+     * have IRQ lines delegated by their parent APLIC.
+     */
+    if (!aplic->parent) {
+        qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+    }
+
+    /* Create output IRQ lines for non-MSI mode */
+    if (!aplic->msimode) {
+        aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
+        qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
+
+        /* Claim the CPU interrupt to be triggered by this APLIC */
+        for (i = 0; i < aplic->num_harts; i++) {
+            RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
+            if (riscv_cpu_claim_interrupts(cpu,
+                (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+                error_report("%s already claimed",
+                             (aplic->mmode) ? "MEIP" : "SEIP");
+                exit(1);
+            }
+        }
+    }
+
+    msi_nonbroken = true;
+}
+
+static Property riscv_aplic_properties[] = {
+    DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0),
+    DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
+    DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
+    DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0),
+    DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0),
+    DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0),
+    DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_riscv_aplic = {
+    .name = "riscv_aplic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+            VMSTATE_UINT32(domaincfg, RISCVAPLICState),
+            VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
+            VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState),
+            VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
+            VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
+            VMSTATE_UINT32(genmsi, RISCVAPLICState),
+            VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
+                                  num_irqs, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(state, RISCVAPLICState,
+                                  num_irqs, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(target, RISCVAPLICState,
+                                  num_irqs, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState,
+                                  num_harts, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState,
+                                  num_harts, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState,
+                                  num_harts, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_END_OF_LIST()
+        }
+};
+
+static void riscv_aplic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_props(dc, riscv_aplic_properties);
+    dc->realize = riscv_aplic_realize;
+    dc->vmsd = &vmstate_riscv_aplic;
+}
+
+static const TypeInfo riscv_aplic_info = {
+    .name          = TYPE_RISCV_APLIC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(RISCVAPLICState),
+    .class_init    = riscv_aplic_class_init,
+};
+
+static void riscv_aplic_register_types(void)
+{
+    type_register_static(&riscv_aplic_info);
+}
+
+type_init(riscv_aplic_register_types)
+
+/*
+ * Add a APLIC device to another APLIC device as child for
+ * interrupt delegation.
+ */
+void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
+{
+    RISCVAPLICState *caplic, *paplic;
+
+    assert(parent && child);
+    caplic = RISCV_APLIC(child);
+    paplic = RISCV_APLIC(parent);
+
+    assert(paplic->num_irqs == caplic->num_irqs);
+    assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
+
+    caplic->parent = paplic;
+    paplic->children[paplic->num_children] = caplic;
+    paplic->num_children++;
+}
+
+/*
+ * Create APLIC device.
+ */
+DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+    uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
+    uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
+    uint32_t i;
+
+    assert(num_harts < APLIC_MAX_IDC);
+    assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
+    assert(num_sources < APLIC_MAX_SOURCE);
+    assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
+    assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
+
+    qdev_prop_set_uint32(dev, "aperture-size", size);
+    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
+    qdev_prop_set_uint32(dev, "num-harts", num_harts);
+    qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
+    qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
+    qdev_prop_set_bit(dev, "msimode", msimode);
+    qdev_prop_set_bit(dev, "mmode", mmode);
+
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
+    if (!msimode) {
+        for (i = 0; i < num_harts; i++) {
+            CPUState *cpu = qemu_get_cpu(hartid_base + i);
+
+            qdev_connect_gpio_out_named(dev, NULL, i,
+                                        qdev_get_gpio_in(DEVICE(cpu),
+                                            (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
+        }
+    }
+
+    return dev;
+}
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
 config RISCV_ACLINT
     bool
 
+config RISCV_APLIC
+    bool
+
 config SIFIVE_PLIC
     bool
 
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
 specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
+specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
 specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-20-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  26 +++-
 hw/riscv/virt.c         | 291 ++++++++++++++++++++++++++++++++--------
 hw/riscv/Kconfig        |   1 +
 3 files changed, 259 insertions(+), 59 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVVirtState RISCVVirtState;
 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
                          TYPE_RISCV_VIRT_MACHINE)
 
+typedef enum RISCVVirtAIAType {
+    VIRT_AIA_TYPE_NONE = 0,
+    VIRT_AIA_TYPE_APLIC,
+} RISCVVirtAIAType;
+
 struct RISCVVirtState {
     /*< private >*/
     MachineState parent;
 
     /*< public >*/
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
-    DeviceState *plic[VIRT_SOCKETS_MAX];
+    DeviceState *irqchip[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
     FWCfgState *fw_cfg;
 
     int fdt_size;
     bool have_aclint;
+    RISCVVirtAIAType aia_type;
 };
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_CLINT,
     VIRT_ACLINT_SSWI,
     VIRT_PLIC,
+    VIRT_APLIC_M,
+    VIRT_APLIC_S,
     VIRT_UART0,
     VIRT_VIRTIO,
     VIRT_FW_CFG,
@@ -XXX,XX +XXX,XX @@ enum {
     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
 };
 
-#define VIRT_PLIC_NUM_SOURCES 127
-#define VIRT_PLIC_NUM_PRIORITIES 7
+#define VIRT_IRQCHIP_NUM_SOURCES 127
+#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
+
 #define VIRT_PLIC_PRIORITY_BASE 0x04
 #define VIRT_PLIC_PENDING_BASE 0x1000
 #define VIRT_PLIC_ENABLE_BASE 0x2000
@@ -XXX,XX +XXX,XX @@ enum {
 
 #define FDT_PCI_ADDR_CELLS    3
 #define FDT_PCI_INT_CELLS     1
-#define FDT_PLIC_ADDR_CELLS   0
 #define FDT_PLIC_INT_CELLS    1
-#define FDT_INT_MAP_WIDTH     (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
-                               FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
+#define FDT_APLIC_INT_CELLS   2
+#define FDT_MAX_INT_CELLS     2
+#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+                                 1 + FDT_MAX_INT_CELLS)
+#define FDT_PLIC_INT_MAP_WIDTH  (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+                                 1 + FDT_PLIC_INT_CELLS)
+#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+                                 1 + FDT_APLIC_INT_CELLS)
 
 #endif
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/riscv_aclint.h"
+#include "hw/intc/riscv_aplic.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_ACLINT_SSWI] = {  0x2F00000,        0x4000 },
     [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+    [VIRT_APLIC_M] =     {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
+    [VIRT_APLIC_S] =     {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
     [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
@@ -XXX,XX +XXX,XX @@ static void virt_flash_map(RISCVVirtState *s,
                     sysmem);
 }
 
-static void create_pcie_irq_map(void *fdt, char *nodename,
-                                uint32_t plic_phandle)
+static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
+                                uint32_t irqchip_phandle)
 {
     int pin, dev;
-    uint32_t
-        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+    uint32_t irq_map_stride = 0;
+    uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+                          FDT_MAX_INT_MAP_WIDTH] = {};
     uint32_t *irq_map = full_irq_map;
 
     /* This code creates a standard swizzle of interrupts such that
@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(void *fdt, char *nodename,
             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
             int i = 0;
 
+            /* Fill PCI address cells */
             irq_map[i] = cpu_to_be32(devfn << 8);
-
             i += FDT_PCI_ADDR_CELLS;
-            irq_map[i] = cpu_to_be32(pin + 1);
 
+            /* Fill PCI Interrupt cells */
+            irq_map[i] = cpu_to_be32(pin + 1);
             i += FDT_PCI_INT_CELLS;
-            irq_map[i++] = cpu_to_be32(plic_phandle);
 
-            i += FDT_PLIC_ADDR_CELLS;
-            irq_map[i] = cpu_to_be32(irq_nr);
+            /* Fill interrupt controller phandle and cells */
+            irq_map[i++] = cpu_to_be32(irqchip_phandle);
+            irq_map[i++] = cpu_to_be32(irq_nr);
+            if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+                irq_map[i++] = cpu_to_be32(0x4);
+            }
 
-            irq_map += FDT_INT_MAP_WIDTH;
+            if (!irq_map_stride) {
+                irq_map_stride = i;
+            }
+            irq_map += irq_map_stride;
         }
     }
 
-    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
-                     full_irq_map, sizeof(full_irq_map));
+    qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+                     GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+                     irq_map_stride * sizeof(uint32_t));
 
     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
                            0x1800, 0, 0, 0x7);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
     plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
     qemu_fdt_add_subnode(mc->fdt, plic_name);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name,
-        "#address-cells", FDT_PLIC_ADDR_CELLS);
     qemu_fdt_setprop_cell(mc->fdt, plic_name,
         "#interrupt-cells", FDT_PLIC_INT_CELLS);
     qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     g_free(plic_cells);
 }
 
+static void create_fdt_socket_aia(RISCVVirtState *s,
+                                  const MemMapEntry *memmap, int socket,
+                                  uint32_t *phandle, uint32_t *intc_phandles,
+                                  uint32_t *aplic_phandles)
+{
+    int cpu;
+    char *aplic_name;
+    uint32_t *aplic_cells;
+    unsigned long aplic_addr;
+    MachineState *mc = MACHINE(s);
+    uint32_t aplic_m_phandle, aplic_s_phandle;
+
+    aplic_m_phandle = (*phandle)++;
+    aplic_s_phandle = (*phandle)++;
+    aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+    /* M-level APLIC node */
+    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+    }
+    aplic_addr = memmap[VIRT_APLIC_M].base +
+                 (memmap[VIRT_APLIC_M].size * socket);
+    aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
+    qemu_fdt_add_subnode(mc->fdt, aplic_name);
+    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+        "#interrupt-cells", FDT_APLIC_INT_CELLS);
+    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+        VIRT_IRQCHIP_NUM_SOURCES);
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
+        aplic_s_phandle);
+    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
+        aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
+    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
+    g_free(aplic_name);
+
+    /* S-level APLIC node */
+    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+    }
+    aplic_addr = memmap[VIRT_APLIC_S].base +
+                 (memmap[VIRT_APLIC_S].size * socket);
+    aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
+    qemu_fdt_add_subnode(mc->fdt, aplic_name);
+    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+        "#interrupt-cells", FDT_APLIC_INT_CELLS);
+    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+        VIRT_IRQCHIP_NUM_SOURCES);
+    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+    g_free(aplic_name);
+
+    g_free(aplic_cells);
+    aplic_phandles[socket] = aplic_s_phandle;
+}
+
 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
                                bool is_32_bit, uint32_t *phandle,
                                uint32_t *irq_mmio_phandle,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
             }
         }
 
-        create_fdt_socket_plic(s, memmap, socket, phandle,
-            intc_phandles, xplic_phandles);
+        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+            create_fdt_socket_plic(s, memmap, socket, phandle,
+                intc_phandles, xplic_phandles);
+        } else {
+            create_fdt_socket_aia(s, memmap, socket, phandle,
+                intc_phandles, xplic_phandles);
+        }
 
         g_free(intc_phandles);
         g_free(clust_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
             0x0, memmap[VIRT_VIRTIO].size);
         qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
             irq_virtio_phandle);
-        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
+        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+            qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
+                                  VIRTIO_IRQ + i);
+        } else {
+            qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
+                                   VIRTIO_IRQ + i, 0x4);
+        }
         g_free(name);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
         2, virt_high_pcie_memmap.base,
         2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
 
-    create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
+    create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
     g_free(name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
         0x0, memmap[VIRT_UART0].size);
     qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
     qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
-    qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+    } else {
+        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
+    }
 
     qemu_fdt_add_subnode(mc->fdt, "/chosen");
     qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
         0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
     qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
         irq_mmio_phandle);
-    qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+    } else {
+        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
+    }
     g_free(name);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
                                           hwaddr high_mmio_base,
                                           hwaddr high_mmio_size,
                                           hwaddr pio_base,
-                                          DeviceState *plic)
+                                          DeviceState *irqchip)
 {
     DeviceState *dev;
     MemoryRegion *ecam_alias, *ecam_reg;
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
 
     for (i = 0; i < GPEX_NUM_IRQS; i++) {
-        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
+        irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
 
         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
     return fw_cfg;
 }
 
+static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
+                                     int base_hartid, int hart_count)
+{
+    DeviceState *ret;
+    char *plic_hart_config;
+
+    /* Per-socket PLIC hart topology configuration string */
+    plic_hart_config = riscv_plic_hart_config_string(hart_count);
+
+    /* Per-socket PLIC */
+    ret = sifive_plic_create(
+            memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
+            plic_hart_config, hart_count, base_hartid,
+            VIRT_IRQCHIP_NUM_SOURCES,
+            ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
+            VIRT_PLIC_PRIORITY_BASE,
+            VIRT_PLIC_PENDING_BASE,
+            VIRT_PLIC_ENABLE_BASE,
+            VIRT_PLIC_ENABLE_STRIDE,
+            VIRT_PLIC_CONTEXT_BASE,
+            VIRT_PLIC_CONTEXT_STRIDE,
+            memmap[VIRT_PLIC].size);
+
+    g_free(plic_hart_config);
+
+    return ret;
+}
+
+static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
+                                    const MemMapEntry *memmap, int socket,
+                                    int base_hartid, int hart_count)
+{
+    DeviceState *aplic_m;
+
+    /* Per-socket M-level APLIC */
+    aplic_m = riscv_aplic_create(
+        memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
+        memmap[VIRT_APLIC_M].size,
+        base_hartid, hart_count,
+        VIRT_IRQCHIP_NUM_SOURCES,
+        VIRT_IRQCHIP_NUM_PRIO_BITS,
+        false, true, NULL);
+
+    if (aplic_m) {
+        /* Per-socket S-level APLIC */
+        riscv_aplic_create(
+            memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
+            memmap[VIRT_APLIC_S].size,
+            base_hartid, hart_count,
+            VIRT_IRQCHIP_NUM_SOURCES,
+            VIRT_IRQCHIP_NUM_PRIO_BITS,
+            false, false, aplic_m);
+    }
+
+    return aplic_m;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    char *plic_hart_config, *soc_name;
+    char *soc_name;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
-    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
+    DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
     int i, base_hartid, hart_count;
 
     /* Check socket count limit */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     }
 
     /* Initialize sockets */
-    mmio_plic = virtio_plic = pcie_plic = NULL;
+    mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
     for (i = 0; i < riscv_socket_count(machine); i++) {
         if (!riscv_socket_check_hartids(machine, i)) {
             error_report("discontinuous hartids in socket%d", i);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
             }
         }
 
-        /* Per-socket PLIC hart topology configuration string */
-        plic_hart_config = riscv_plic_hart_config_string(hart_count);
-
-        /* Per-socket PLIC */
-        s->plic[i] = sifive_plic_create(
-            memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
-            plic_hart_config, hart_count, base_hartid,
-            VIRT_PLIC_NUM_SOURCES,
-            VIRT_PLIC_NUM_PRIORITIES,
-            VIRT_PLIC_PRIORITY_BASE,
-            VIRT_PLIC_PENDING_BASE,
-            VIRT_PLIC_ENABLE_BASE,
-            VIRT_PLIC_ENABLE_STRIDE,
-            VIRT_PLIC_CONTEXT_BASE,
-            VIRT_PLIC_CONTEXT_STRIDE,
-            memmap[VIRT_PLIC].size);
-        g_free(plic_hart_config);
+        /* Per-socket interrupt controller */
+        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+            s->irqchip[i] = virt_create_plic(memmap, i,
+                                             base_hartid, hart_count);
+        } else {
+            s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
+                                            base_hartid, hart_count);
+        }
 
-        /* Try to use different PLIC instance based device type */
+        /* Try to use different IRQCHIP instance based device type */
         if (i == 0) {
-            mmio_plic = s->plic[i];
-            virtio_plic = s->plic[i];
-            pcie_plic = s->plic[i];
+            mmio_irqchip = s->irqchip[i];
+            virtio_irqchip = s->irqchip[i];
+            pcie_irqchip = s->irqchip[i];
         }
         if (i == 1) {
-            virtio_plic = s->plic[i];
-            pcie_plic = s->plic[i];
+            virtio_irqchip = s->irqchip[i];
+            pcie_irqchip = s->irqchip[i];
         }
         if (i == 2) {
-            pcie_plic = s->plic[i];
+            pcie_irqchip = s->irqchip[i];
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     for (i = 0; i < VIRTIO_COUNT; i++) {
         sysbus_create_simple("virtio-mmio",
             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
-            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
+            qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
     }
 
     gpex_pcie_init(system_memory,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                    virt_high_pcie_memmap.base,
                    virt_high_pcie_memmap.size,
                    memmap[VIRT_PCIE_PIO].base,
-                   DEVICE(pcie_plic));
+                   DEVICE(pcie_irqchip));
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
-        0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+        0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 
     sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
-        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
+        qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
 
     virt_flash_create(s);
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
 {
 }
 
+static char *virt_get_aia(Object *obj, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+    const char *val;
+
+    switch (s->aia_type) {
+    case VIRT_AIA_TYPE_APLIC:
+        val = "aplic";
+        break;
+    default:
+        val = "none";
+        break;
+    };
+
+    return g_strdup(val);
+}
+
+static void virt_set_aia(Object *obj, const char *val, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+    if (!strcmp(val, "none")) {
+        s->aia_type = VIRT_AIA_TYPE_NONE;
+    } else if (!strcmp(val, "aplic")) {
+        s->aia_type = VIRT_AIA_TYPE_APLIC;
+    } else {
+        error_setg(errp, "Invalid AIA interrupt controller type");
+        error_append_hint(errp, "Valid values are none, and aplic.\n");
+    }
+}
+
 static bool virt_get_aclint(Object *obj, Error **errp)
 {
     MachineState *ms = MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     object_class_property_set_description(oc, "aclint",
                                           "Set on/off to enable/disable "
                                           "emulating ACLINT devices");
+
+    object_class_property_add_str(oc, "aia", virt_get_aia,
+                                  virt_set_aia);
+    object_class_property_set_description(oc, "aia",
+                                          "Set type of AIA interrupt "
+                                          "conttoller. Valid values are "
+                                          "none, and aplic.");
 }
 
 static const TypeInfo virt_machine_typeinfo = {
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PFLASH_CFI01
     select SERIAL
     select RISCV_ACLINT
+    select RISCV_APLIC
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level guest interrupt files.

This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-21-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_imsic.h |  68 ++++++
 hw/intc/riscv_imsic.c         | 448 ++++++++++++++++++++++++++++++++++
 hw/intc/Kconfig               |   3 +
 hw/intc/meson.build           |   1 +
 4 files changed, 520 insertions(+)
 create mode 100644 include/hw/intc/riscv_imsic.h
 create mode 100644 hw/intc/riscv_imsic.c

diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/riscv_imsic.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_IMSIC_H
+#define HW_RISCV_IMSIC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_IMSIC "riscv.imsic"
+
+typedef struct RISCVIMSICState RISCVIMSICState;
+DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
+
+#define IMSIC_MMIO_PAGE_SHIFT          12
+#define IMSIC_MMIO_PAGE_SZ             (1UL << IMSIC_MMIO_PAGE_SHIFT)
+#define IMSIC_MMIO_SIZE(__num_pages)   ((__num_pages) * IMSIC_MMIO_PAGE_SZ)
+
+#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
+#define IMSIC_MMIO_GROUP_MIN_SHIFT     24
+
+#define IMSIC_HART_NUM_GUESTS(__guest_bits)           \
+    (1U << (__guest_bits))
+#define IMSIC_HART_SIZE(__guest_bits)                 \
+    (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
+#define IMSIC_GROUP_NUM_HARTS(__hart_bits)            \
+    (1U << (__hart_bits))
+#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits)   \
+    (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
+
+struct RISCVIMSICState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    qemu_irq *external_irqs;
+
+    /*< public >*/
+    MemoryRegion mmio;
+    uint32_t num_eistate;
+    uint32_t *eidelivery;
+    uint32_t *eithreshold;
+    uint32_t *eistate;
+
+    /* config */
+    bool mmode;
+    uint32_t hartid;
+    uint32_t num_pages;
+    uint32_t num_irqs;
+};
+
+DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
+                                uint32_t num_pages, uint32_t num_ids);
+
+#endif
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/intc/riscv_imsic.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V IMSIC (Incoming Message Signaled Interrupt Controller)
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/bswap.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/riscv_imsic.h"
+#include "hw/irq.h"
+#include "target/riscv/cpu.h"
+#include "target/riscv/cpu_bits.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+
+#define IMSIC_MMIO_PAGE_LE             0x00
+#define IMSIC_MMIO_PAGE_BE             0x04
+
+#define IMSIC_MIN_ID                   ((IMSIC_EIPx_BITS * 2) - 1)
+#define IMSIC_MAX_ID                   (IMSIC_TOPEI_IID_MASK)
+
+#define IMSIC_EISTATE_PENDING          (1U << 0)
+#define IMSIC_EISTATE_ENABLED          (1U << 1)
+#define IMSIC_EISTATE_ENPEND           (IMSIC_EISTATE_ENABLED | \
+                                        IMSIC_EISTATE_PENDING)
+
+static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
+{
+    uint32_t i, max_irq, base;
+
+    base = page * imsic->num_irqs;
+    max_irq = (imsic->eithreshold[page] &&
+               (imsic->eithreshold[page] <= imsic->num_irqs)) ?
+               imsic->eithreshold[page] : imsic->num_irqs;
+    for (i = 1; i < max_irq; i++) {
+        if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
+                IMSIC_EISTATE_ENPEND) {
+            return (i << IMSIC_TOPEI_IID_SHIFT) | i;
+        }
+    }
+
+    return 0;
+}
+
+static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
+{
+    if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
+        qemu_irq_raise(imsic->external_irqs[page]);
+    } else {
+        qemu_irq_lower(imsic->external_irqs[page]);
+    }
+}
+
+static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
+                                      target_ulong *val,
+                                      target_ulong new_val,
+                                      target_ulong wr_mask)
+{
+    target_ulong old_val = imsic->eidelivery[page];
+
+    if (val) {
+        *val = old_val;
+    }
+
+    wr_mask &= 0x1;
+    imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
+
+    riscv_imsic_update(imsic, page);
+    return 0;
+}
+
+static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
+                                      target_ulong *val,
+                                      target_ulong new_val,
+                                      target_ulong wr_mask)
+{
+    target_ulong old_val = imsic->eithreshold[page];
+
+    if (val) {
+        *val = old_val;
+    }
+
+    wr_mask &= IMSIC_MAX_ID;
+    imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
+
+    riscv_imsic_update(imsic, page);
+    return 0;
+}
+
+static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
+                                 target_ulong *val, target_ulong new_val,
+                                 target_ulong wr_mask)
+{
+    uint32_t base, topei = riscv_imsic_topei(imsic, page);
+
+    /* Read pending and enabled interrupt with highest priority */
+    if (val) {
+        *val = topei;
+    }
+
+    /* Writes ignore value and clear top pending interrupt */
+    if (topei && wr_mask) {
+        topei >>= IMSIC_TOPEI_IID_SHIFT;
+        base = page * imsic->num_irqs;
+        if (topei) {
+            imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;
+        }
+
+        riscv_imsic_update(imsic, page);
+    }
+
+    return 0;
+}
+
+static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
+                               uint32_t xlen, uint32_t page,
+                               uint32_t num, bool pend, target_ulong *val,
+                               target_ulong new_val, target_ulong wr_mask)
+{
+    uint32_t i, base;
+    target_ulong mask;
+    uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
+
+    if (xlen != 32) {
+        if (num & 0x1) {
+            return -EINVAL;
+        }
+        num >>= 1;
+    }
+    if (num >= (imsic->num_irqs / xlen)) {
+        return -EINVAL;
+    }
+
+    base = (page * imsic->num_irqs) + (num * xlen);
+
+    if (val) {
+        *val = 0;
+        for (i = 0; i < xlen; i++) {
+            mask = (target_ulong)1 << i;
+            *val |= (imsic->eistate[base + i] & state) ? mask : 0;
+        }
+    }
+
+    for (i = 0; i < xlen; i++) {
+        /* Bit0 of eip0 and eie0 are read-only zero */
+        if (!num && !i) {
+            continue;
+        }
+
+        mask = (target_ulong)1 << i;
+        if (wr_mask & mask) {
+            if (new_val & mask) {
+                imsic->eistate[base + i] |= state;
+            } else {
+                imsic->eistate[base + i] &= ~state;
+            }
+        }
+    }
+
+    riscv_imsic_update(imsic, page);
+    return 0;
+}
+
+static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val,
+                           target_ulong new_val, target_ulong wr_mask)
+{
+    RISCVIMSICState *imsic = arg;
+    uint32_t isel, priv, virt, vgein, xlen, page;
+
+    priv = AIA_IREG_PRIV(reg);
+    virt = AIA_IREG_VIRT(reg);
+    isel = AIA_IREG_ISEL(reg);
+    vgein = AIA_IREG_VGEIN(reg);
+    xlen = AIA_IREG_XLEN(reg);
+
+    if (imsic->mmode) {
+        if (priv == PRV_M && !virt) {
+            page = 0;
+        } else {
+            goto err;
+        }
+    } else {
+        if (priv == PRV_S) {
+            if (virt) {
+                if (vgein && vgein < imsic->num_pages) {
+                    page = vgein;
+                } else {
+                    goto err;
+                }
+            } else {
+                page = 0;
+            }
+        } else {
+            goto err;
+        }
+    }
+
+    switch (isel) {
+    case ISELECT_IMSIC_EIDELIVERY:
+        return riscv_imsic_eidelivery_rmw(imsic, page, val,
+                                          new_val, wr_mask);
+    case ISELECT_IMSIC_EITHRESHOLD:
+        return riscv_imsic_eithreshold_rmw(imsic, page, val,
+                                           new_val, wr_mask);
+    case ISELECT_IMSIC_TOPEI:
+        return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask);
+    case ISELECT_IMSIC_EIP0 ... ISELECT_IMSIC_EIP63:
+        return riscv_imsic_eix_rmw(imsic, xlen, page,
+                                   isel - ISELECT_IMSIC_EIP0,
+                                   true, val, new_val, wr_mask);
+    case ISELECT_IMSIC_EIE0 ... ISELECT_IMSIC_EIE63:
+        return riscv_imsic_eix_rmw(imsic, xlen, page,
+                                   isel - ISELECT_IMSIC_EIE0,
+                                   false, val, new_val, wr_mask);
+    default:
+        break;
+    };
+
+err:
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register priv=%d virt=%d isel=%d vgein=%d\n",
+                  __func__, priv, virt, isel, vgein);
+    return -EINVAL;
+}
+
+static uint64_t riscv_imsic_read(void *opaque, hwaddr addr, unsigned size)
+{
+    RISCVIMSICState *imsic = opaque;
+
+    /* Reads must be 4 byte words */
+    if ((addr & 0x3) != 0) {
+        goto err;
+    }
+
+    /* Reads cannot be out of range */
+    if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
+        goto err;
+    }
+
+    return 0;
+
+err:
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
+    return 0;
+}
+
+static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
+        unsigned size)
+{
+    RISCVIMSICState *imsic = opaque;
+    uint32_t page;
+
+    /* Writes must be 4 byte words */
+    if ((addr & 0x3) != 0) {
+        goto err;
+    }
+
+    /* Writes cannot be out of range */
+    if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
+        goto err;
+    }
+
+    /* Writes only supported for MSI little-endian registers */
+    page = addr >> IMSIC_MMIO_PAGE_SHIFT;
+    if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
+        if (value && (value < imsic->num_irqs)) {
+            imsic->eistate[(page * imsic->num_irqs) + value] |=
+                                                    IMSIC_EISTATE_PENDING;
+        }
+    }
+
+    /* Update CPU external interrupt status */
+    riscv_imsic_update(imsic, page);
+
+    return;
+
+err:
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
+}
+
+static const MemoryRegionOps riscv_imsic_ops = {
+    .read = riscv_imsic_read,
+    .write = riscv_imsic_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4
+    }
+};
+
+static void riscv_imsic_realize(DeviceState *dev, Error **errp)
+{
+    RISCVIMSICState *imsic = RISCV_IMSIC(dev);
+    RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
+    CPUState *cpu = qemu_get_cpu(imsic->hartid);
+    CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+
+    imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
+    imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
+    imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
+    imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
+
+    memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
+                          imsic, TYPE_RISCV_IMSIC,
+                          IMSIC_MMIO_SIZE(imsic->num_pages));
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
+
+    /* Claim the CPU interrupt to be triggered by this IMSIC */
+    if (riscv_cpu_claim_interrupts(rcpu,
+            (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+        error_setg(errp, "%s already claimed",
+                   (imsic->mmode) ? "MEIP" : "SEIP");
+        return;
+    }
+
+    /* Create output IRQ lines */
+    imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
+    qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
+
+    /* Force select AIA feature and setup CSR read-modify-write callback */
+    if (env) {
+        riscv_set_feature(env, RISCV_FEATURE_AIA);
+        if (!imsic->mmode) {
+            riscv_cpu_set_geilen(env, imsic->num_pages - 1);
+        }
+        riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
+                                      riscv_imsic_rmw, imsic);
+    }
+
+    msi_nonbroken = true;
+}
+
+static Property riscv_imsic_properties[] = {
+    DEFINE_PROP_BOOL("mmode", RISCVIMSICState, mmode, 0),
+    DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0),
+    DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0),
+    DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_riscv_imsic = {
+    .name = "riscv_imsic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+            VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState,
+                                  num_pages, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState,
+                                  num_pages, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState,
+                                  num_eistate, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_END_OF_LIST()
+        }
+};
+
+static void riscv_imsic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_props(dc, riscv_imsic_properties);
+    dc->realize = riscv_imsic_realize;
+    dc->vmsd = &vmstate_riscv_imsic;
+}
+
+static const TypeInfo riscv_imsic_info = {
+    .name          = TYPE_RISCV_IMSIC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(RISCVIMSICState),
+    .class_init    = riscv_imsic_class_init,
+};
+
+static void riscv_imsic_register_types(void)
+{
+    type_register_static(&riscv_imsic_info);
+}
+
+type_init(riscv_imsic_register_types)
+
+/*
+ * Create IMSIC device.
+ */
+DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
+                                uint32_t num_pages, uint32_t num_ids)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
+    CPUState *cpu = qemu_get_cpu(hartid);
+    uint32_t i;
+
+    assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
+    if (mmode) {
+        assert(num_pages == 1);
+    } else {
+        assert(num_pages >= 1 && num_pages <= (IRQ_LOCAL_GUEST_MAX + 1));
+    }
+    assert(IMSIC_MIN_ID <= num_ids);
+    assert(num_ids <= IMSIC_MAX_ID);
+    assert((num_ids & IMSIC_MIN_ID) == IMSIC_MIN_ID);
+
+    qdev_prop_set_bit(dev, "mmode", mmode);
+    qdev_prop_set_uint32(dev, "hartid", hartid);
+    qdev_prop_set_uint32(dev, "num-pages", num_pages);
+    qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1);
+
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+    for (i = 0; i < num_pages; i++) {
+        if (!i) {
+            qdev_connect_gpio_out_named(dev, NULL, i,
+                                        qdev_get_gpio_in(DEVICE(cpu),
+                                            (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
+        } else {
+            qdev_connect_gpio_out_named(dev, NULL, i,
+                                        qdev_get_gpio_in(DEVICE(cpu),
+                                            IRQ_LOCAL_MAX + i - 1));
+        }
+    }
+
+    return dev;
+}
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_ACLINT
 config RISCV_APLIC
     bool
 
+config RISCV_IMSIC
+    bool
+
 config SIFIVE_PLIC
     bool
 
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
 specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
 specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
+specific_ss.add(when: 'CONFIG_RISCV_IMSIC', if_true: files('riscv_imsic.c'))
 specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts as MSIs to the AIA IMSIC.

We also provide "aia-guests=<xyz>" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-22-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  17 +-
 hw/riscv/virt.c         | 440 ++++++++++++++++++++++++++++++++--------
 hw/riscv/Kconfig        |   1 +
 3 files changed, 374 insertions(+), 84 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/block/flash.h"
 #include "qom/object.h"
 
-#define VIRT_CPUS_MAX 32
-#define VIRT_SOCKETS_MAX 8
+#define VIRT_CPUS_MAX_BITS             3
+#define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
+#define VIRT_SOCKETS_MAX_BITS          2
+#define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
 
 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
 typedef struct RISCVVirtState RISCVVirtState;
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
 typedef enum RISCVVirtAIAType {
     VIRT_AIA_TYPE_NONE = 0,
     VIRT_AIA_TYPE_APLIC,
+    VIRT_AIA_TYPE_APLIC_IMSIC,
 } RISCVVirtAIAType;
 
 struct RISCVVirtState {
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     int fdt_size;
     bool have_aclint;
     RISCVVirtAIAType aia_type;
+    int aia_guests;
 };
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_UART0,
     VIRT_VIRTIO,
     VIRT_FW_CFG,
+    VIRT_IMSIC_M,
+    VIRT_IMSIC_S,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
@@ -XXX,XX +XXX,XX @@ enum {
     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
 };
 
-#define VIRT_IRQCHIP_NUM_SOURCES 127
+#define VIRT_IRQCHIP_IPI_MSI 1
+#define VIRT_IRQCHIP_NUM_MSIS 255
+#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
+#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
+#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
 
 #define VIRT_PLIC_PRIORITY_BASE 0x04
 #define VIRT_PLIC_PENDING_BASE 0x1000
@@ -XXX,XX +XXX,XX @@ enum {
 #define FDT_PCI_INT_CELLS     1
 #define FDT_PLIC_INT_CELLS    1
 #define FDT_APLIC_INT_CELLS   2
+#define FDT_IMSIC_INT_CELLS   0
 #define FDT_MAX_INT_CELLS     2
 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
                                  1 + FDT_MAX_INT_CELLS)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/numa.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/riscv_aplic.h"
+#include "hw/intc/riscv_imsic.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
 
+#define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+    IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE            (VIRT_SOCKETS_MAX * \
+                                        VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
     [VIRT_MROM] =        {     0x1000,        0xf000 },
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
     [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
+    [VIRT_IMSIC_M] =     { 0x24000000, VIRT_IMSIC_MAX_SIZE },
+    [VIRT_IMSIC_S] =     { 0x28000000, VIRT_IMSIC_MAX_SIZE },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
     [VIRT_DRAM] =        { 0x80000000,           0x0 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
 {
     int cpu;
     char *name;
-    unsigned long addr;
+    unsigned long addr, size;
     uint32_t aclint_cells_size;
     uint32_t *aclint_mswi_cells;
     uint32_t *aclint_sswi_cells;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
     }
     aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
 
-    addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
-    name = g_strdup_printf("/soc/mswi@%lx", addr);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-        0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
-    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
-        aclint_mswi_cells, aclint_cells_size);
-    qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
-    g_free(name);
+    if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+        addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+        name = g_strdup_printf("/soc/mswi@%lx", addr);
+        qemu_fdt_add_subnode(mc->fdt, name);
+        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+            "riscv,aclint-mswi");
+        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+            0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+            aclint_mswi_cells, aclint_cells_size);
+        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+        g_free(name);
+    }
 
-    addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
-        (memmap[VIRT_CLINT].size * socket);
+    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+        addr = memmap[VIRT_CLINT].base +
+               (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
+        size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
+    } else {
+        addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
+            (memmap[VIRT_CLINT].size * socket);
+        size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
+    }
     name = g_strdup_printf("/soc/mtimer@%lx", addr);
     qemu_fdt_add_subnode(mc->fdt, name);
     qemu_fdt_setprop_string(mc->fdt, name, "compatible",
         "riscv,aclint-mtimer");
     qemu_fdt_setprop_cells(mc->fdt, name, "reg",
         0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
-        0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE -
-             RISCV_ACLINT_DEFAULT_MTIME,
+        0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
         0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
         0x0, RISCV_ACLINT_DEFAULT_MTIME);
     qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
     riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
     g_free(name);
 
-    addr = memmap[VIRT_ACLINT_SSWI].base +
-        (memmap[VIRT_ACLINT_SSWI].size * socket);
-    name = g_strdup_printf("/soc/sswi@%lx", addr);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-        0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
-    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
-        aclint_sswi_cells, aclint_cells_size);
-    qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
-    g_free(name);
+    if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+        addr = memmap[VIRT_ACLINT_SSWI].base +
+            (memmap[VIRT_ACLINT_SSWI].size * socket);
+        name = g_strdup_printf("/soc/sswi@%lx", addr);
+        qemu_fdt_add_subnode(mc->fdt, name);
+        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+            "riscv,aclint-sswi");
+        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+            0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
+        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+            aclint_sswi_cells, aclint_cells_size);
+        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+        g_free(name);
+    }
 
     g_free(aclint_mswi_cells);
     g_free(aclint_mtimer_cells);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     g_free(plic_cells);
 }
 
-static void create_fdt_socket_aia(RISCVVirtState *s,
-                                  const MemMapEntry *memmap, int socket,
-                                  uint32_t *phandle, uint32_t *intc_phandles,
-                                  uint32_t *aplic_phandles)
+static uint32_t imsic_num_bits(uint32_t count)
+{
+    uint32_t ret = 0;
+
+    while (BIT(ret) < count) {
+        ret++;
+    }
+
+    return ret;
+}
+
+static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+                             uint32_t *phandle, uint32_t *intc_phandles,
+                             uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
+{
+    int cpu, socket;
+    char *imsic_name;
+    MachineState *mc = MACHINE(s);
+    uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
+    uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
+
+    *msi_m_phandle = (*phandle)++;
+    *msi_s_phandle = (*phandle)++;
+    imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
+    imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+
+    /* M-level IMSIC node */
+    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+    }
+    imsic_max_hart_per_socket = 0;
+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+        imsic_addr = memmap[VIRT_IMSIC_M].base +
+                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+        imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
+        imsic_regs[socket * 4 + 0] = 0;
+        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
+        imsic_regs[socket * 4 + 2] = 0;
+        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
+        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+            imsic_max_hart_per_socket = s->soc[socket].num_harts;
+        }
+    }
+    imsic_name = g_strdup_printf("/soc/imsics@%lx",
+        memmap[VIRT_IMSIC_M].base);
+    qemu_fdt_add_subnode(mc->fdt, imsic_name);
+    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+        "riscv,imsics");
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+        FDT_IMSIC_INT_CELLS);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+        NULL, 0);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+        NULL, 0);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
+        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+        VIRT_IRQCHIP_NUM_MSIS);
+    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
+        VIRT_IRQCHIP_IPI_MSI);
+    if (riscv_socket_count(mc) > 1) {
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+            imsic_num_bits(imsic_max_hart_per_socket));
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+            imsic_num_bits(riscv_socket_count(mc)));
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+            IMSIC_MMIO_GROUP_MIN_SHIFT);
+    }
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+    g_free(imsic_name);
+
+    /* S-level IMSIC node */
+    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+    }
+    imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
+    imsic_max_hart_per_socket = 0;
+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+        imsic_addr = memmap[VIRT_IMSIC_S].base +
+                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+        imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
+                     s->soc[socket].num_harts;
+        imsic_regs[socket * 4 + 0] = 0;
+        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
+        imsic_regs[socket * 4 + 2] = 0;
+        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
+        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+            imsic_max_hart_per_socket = s->soc[socket].num_harts;
+        }
+    }
+    imsic_name = g_strdup_printf("/soc/imsics@%lx",
+        memmap[VIRT_IMSIC_S].base);
+    qemu_fdt_add_subnode(mc->fdt, imsic_name);
+    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+        "riscv,imsics");
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+        FDT_IMSIC_INT_CELLS);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+        NULL, 0);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+        NULL, 0);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
+        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+        VIRT_IRQCHIP_NUM_MSIS);
+    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
+        VIRT_IRQCHIP_IPI_MSI);
+    if (imsic_guest_bits) {
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+            imsic_guest_bits);
+    }
+    if (riscv_socket_count(mc) > 1) {
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+            imsic_num_bits(imsic_max_hart_per_socket));
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+            imsic_num_bits(riscv_socket_count(mc)));
+        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+            IMSIC_MMIO_GROUP_MIN_SHIFT);
+    }
+    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
+    g_free(imsic_name);
+
+    g_free(imsic_regs);
+    g_free(imsic_cells);
+}
+
+static void create_fdt_socket_aplic(RISCVVirtState *s,
+                                    const MemMapEntry *memmap, int socket,
+                                    uint32_t msi_m_phandle,
+                                    uint32_t msi_s_phandle,
+                                    uint32_t *phandle,
+                                    uint32_t *intc_phandles,
+                                    uint32_t *aplic_phandles)
 {
     int cpu;
     char *aplic_name;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aia(RISCVVirtState *s,
     qemu_fdt_setprop_cell(mc->fdt, aplic_name,
         "#interrupt-cells", FDT_APLIC_INT_CELLS);
     qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
-        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    } else {
+        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+            msi_m_phandle);
+    }
     qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
         0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aia(RISCVVirtState *s,
     qemu_fdt_setprop_cell(mc->fdt, aplic_name,
         "#interrupt-cells", FDT_APLIC_INT_CELLS);
     qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
-        aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+    } else {
+        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+            msi_s_phandle);
+    }
     qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
         0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
                                bool is_32_bit, uint32_t *phandle,
                                uint32_t *irq_mmio_phandle,
                                uint32_t *irq_pcie_phandle,
-                               uint32_t *irq_virtio_phandle)
+                               uint32_t *irq_virtio_phandle,
+                               uint32_t *msi_pcie_phandle)
 {
-    int socket;
     char *clust_name;
-    uint32_t *intc_phandles;
+    int socket, phandle_pos;
     MachineState *mc = MACHINE(s);
-    uint32_t xplic_phandles[MAX_NODES];
+    uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
+    uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
 
     qemu_fdt_add_subnode(mc->fdt, "/cpus");
     qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
     qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
 
+    intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+
+    phandle_pos = mc->smp.cpus;
     for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+        phandle_pos -= s->soc[socket].num_harts;
+
         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
         qemu_fdt_add_subnode(mc->fdt, clust_name);
 
-        intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
-
         create_fdt_socket_cpus(s, socket, clust_name, phandle,
-            is_32_bit, intc_phandles);
+            is_32_bit, &intc_phandles[phandle_pos]);
 
         create_fdt_socket_memory(s, memmap, socket);
 
+        g_free(clust_name);
+
         if (!kvm_enabled()) {
             if (s->have_aclint) {
-                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
+                create_fdt_socket_aclint(s, memmap, socket,
+                    &intc_phandles[phandle_pos]);
             } else {
-                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+                create_fdt_socket_clint(s, memmap, socket,
+                    &intc_phandles[phandle_pos]);
             }
         }
+    }
+
+    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+        create_fdt_imsic(s, memmap, phandle, intc_phandles,
+            &msi_m_phandle, &msi_s_phandle);
+        *msi_pcie_phandle = msi_s_phandle;
+    }
+
+    phandle_pos = mc->smp.cpus;
+    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+        phandle_pos -= s->soc[socket].num_harts;
 
         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
             create_fdt_socket_plic(s, memmap, socket, phandle,
-                intc_phandles, xplic_phandles);
+                &intc_phandles[phandle_pos], xplic_phandles);
         } else {
-            create_fdt_socket_aia(s, memmap, socket, phandle,
-                intc_phandles, xplic_phandles);
+            create_fdt_socket_aplic(s, memmap, socket,
+                msi_m_phandle, msi_s_phandle, phandle,
+                &intc_phandles[phandle_pos], xplic_phandles);
         }
-
-        g_free(intc_phandles);
-        g_free(clust_name);
     }
 
+    g_free(intc_phandles);
+
     for (socket = 0; socket < riscv_socket_count(mc); socket++) {
         if (socket == 0) {
             *irq_mmio_phandle = xplic_phandles[socket];
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
 }
 
 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
-                            uint32_t irq_pcie_phandle)
+                            uint32_t irq_pcie_phandle,
+                            uint32_t msi_pcie_phandle)
 {
     char *name;
     MachineState *mc = MACHINE(s);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
         memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
     qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+    if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+        qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
+    }
     qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
         memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
     qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
 {
     MachineState *mc = MACHINE(s);
-    uint32_t phandle = 1, irq_mmio_phandle = 1;
+    uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
     uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
 
     if (mc->dtb) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
 
     create_fdt_sockets(s, memmap, is_32_bit, &phandle,
-        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
+        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
+        &msi_pcie_phandle);
 
     create_fdt_virtio(s, memmap, irq_virtio_phandle);
 
-    create_fdt_pcie(s, memmap, irq_pcie_phandle);
+    create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
 
     create_fdt_reset(s, memmap, &phandle);
 
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
     return ret;
 }
 
-static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
+static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
                                     const MemMapEntry *memmap, int socket,
                                     int base_hartid, int hart_count)
 {
+    int i;
+    hwaddr addr;
+    uint32_t guest_bits;
     DeviceState *aplic_m;
+    bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
+
+    if (msimode) {
+        /* Per-socket M-level IMSICs */
+        addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+        for (i = 0; i < hart_count; i++) {
+            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
+                               base_hartid + i, true, 1,
+                               VIRT_IRQCHIP_NUM_MSIS);
+        }
+
+        /* Per-socket S-level IMSICs */
+        guest_bits = imsic_num_bits(aia_guests + 1);
+        addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+        for (i = 0; i < hart_count; i++) {
+            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
+                               base_hartid + i, false, 1 + aia_guests,
+                               VIRT_IRQCHIP_NUM_MSIS);
+        }
+    }
 
     /* Per-socket M-level APLIC */
     aplic_m = riscv_aplic_create(
         memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
         memmap[VIRT_APLIC_M].size,
-        base_hartid, hart_count,
+        (msimode) ? 0 : base_hartid,
+        (msimode) ? 0 : hart_count,
         VIRT_IRQCHIP_NUM_SOURCES,
         VIRT_IRQCHIP_NUM_PRIO_BITS,
-        false, true, NULL);
+        msimode, true, NULL);
 
     if (aplic_m) {
         /* Per-socket S-level APLIC */
         riscv_aplic_create(
             memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
             memmap[VIRT_APLIC_S].size,
-            base_hartid, hart_count,
+            (msimode) ? 0 : base_hartid,
+            (msimode) ? 0 : hart_count,
             VIRT_IRQCHIP_NUM_SOURCES,
             VIRT_IRQCHIP_NUM_PRIO_BITS,
-            false, false, aplic_m);
+            msimode, false, aplic_m);
     }
 
     return aplic_m;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 
         if (!kvm_enabled()) {
-            /* Per-socket CLINT */
-            riscv_aclint_swi_create(
-                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
-                base_hartid, hart_count, false);
-            riscv_aclint_mtimer_create(
-                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
-                    RISCV_ACLINT_SWI_SIZE,
-                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
-                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
-                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
-
-            /* Per-socket ACLINT SSWI */
             if (s->have_aclint) {
+                if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+                    /* Per-socket ACLINT MTIMER */
+                    riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+                            i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
+                        RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
+                        base_hartid, hart_count,
+                        RISCV_ACLINT_DEFAULT_MTIMECMP,
+                        RISCV_ACLINT_DEFAULT_MTIME,
+                        RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+                } else {
+                    /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
+                    riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
+                            i * memmap[VIRT_CLINT].size,
+                        base_hartid, hart_count, false);
+                    riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+                            i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
+                        RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
+                        base_hartid, hart_count,
+                        RISCV_ACLINT_DEFAULT_MTIMECMP,
+                        RISCV_ACLINT_DEFAULT_MTIME,
+                        RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+                    riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
+                            i * memmap[VIRT_ACLINT_SSWI].size,
+                        base_hartid, hart_count, true);
+                }
+            } else {
+                /* Per-socket SiFive CLINT */
                 riscv_aclint_swi_create(
-                    memmap[VIRT_ACLINT_SSWI].base +
-                        i * memmap[VIRT_ACLINT_SSWI].size,
-                    base_hartid, hart_count, true);
+                    memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+                    base_hartid, hart_count, false);
+                riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+                        i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
+                    RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
+                    base_hartid, hart_count,
+                    RISCV_ACLINT_DEFAULT_MTIMECMP,
+                    RISCV_ACLINT_DEFAULT_MTIME,
+                    RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
             }
         }
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
             s->irqchip[i] = virt_create_plic(memmap, i,
                                              base_hartid, hart_count);
         } else {
-            s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
-                                            base_hartid, hart_count);
+            s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
+                                            memmap, i, base_hartid,
+                                            hart_count);
         }
 
         /* Try to use different IRQCHIP instance based device type */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
 {
 }
 
+static char *virt_get_aia_guests(Object *obj, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+    char val[32];
+
+    sprintf(val, "%d", s->aia_guests);
+    return g_strdup(val);
+}
+
+static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+    s->aia_guests = atoi(val);
+    if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
+        error_setg(errp, "Invalid number of AIA IMSIC guests");
+        error_append_hint(errp, "Valid values be between 0 and %d.\n",
+                          VIRT_IRQCHIP_MAX_GUESTS);
+    }
+}
+
 static char *virt_get_aia(Object *obj, Error **errp)
 {
     RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static char *virt_get_aia(Object *obj, Error **errp)
     case VIRT_AIA_TYPE_APLIC:
         val = "aplic";
         break;
+    case VIRT_AIA_TYPE_APLIC_IMSIC:
+        val = "aplic-imsic";
+        break;
     default:
         val = "none";
         break;
@@ -XXX,XX +XXX,XX @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
         s->aia_type = VIRT_AIA_TYPE_NONE;
     } else if (!strcmp(val, "aplic")) {
         s->aia_type = VIRT_AIA_TYPE_APLIC;
+    } else if (!strcmp(val, "aplic-imsic")) {
+        s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
     } else {
         error_setg(errp, "Invalid AIA interrupt controller type");
-        error_append_hint(errp, "Valid values are none, and aplic.\n");
+        error_append_hint(errp, "Valid values are none, aplic, and "
+                          "aplic-imsic.\n");
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
 
 static void virt_machine_class_init(ObjectClass *oc, void *data)
 {
+    char str[128];
     MachineClass *mc = MACHINE_CLASS(oc);
 
     mc->desc = "RISC-V VirtIO board";
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     object_class_property_set_description(oc, "aia",
                                           "Set type of AIA interrupt "
                                           "conttoller. Valid values are "
-                                          "none, and aplic.");
+                                          "none, aplic, and aplic-imsic.");
+
+    object_class_property_add_str(oc, "aia-guests",
+                                  virt_get_aia_guests,
+                                  virt_set_aia_guests);
+    sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
+                 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
+    object_class_property_set_description(oc, "aia-guests", str);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SERIAL
     select RISCV_ACLINT
     select RISCV_APLIC
+    select RISCV_IMSIC
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
   When this option is "on", ACLINT devices will be emulated instead of
   SiFive CLINT. When not specified, this option is assumed to be "off".
 
+- aia=[none|aplic|aplic-imsic]
+
+  This option allows selecting interrupt controller defined by the AIA
+  (advanced interrupt architecture) specification. The "aia=aplic" selects
+  APLIC (advanced platform level interrupt controller) to handle wired
+  interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
+  message signaled interrupt controller) to handle both wired interrupts and
+  MSIs. When not specified, this option is assumed to be "none" which selects
+  SiFive PLIC to handle wired interrupts.
+
+- aia-guests=nnn
+
+  The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+  having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+  the default number of per-HART VS-level AIA IMSIC pages is 0.
+
 Running Linux kernel
 --------------------
 
-- 
2.34.1

From: Anup Patel <anup.patel@wdc.com>

To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).

We also add a detailed source level comments about limit defines which
impact the physical address space utilization.

From: Guo Ren <ren_guo@c-sky.com>

Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 15 +++++++++++++++
 target/riscv/cpu_bits.h   |  3 +++
 target/riscv/cpu_helper.c | 13 ++++++++++++-
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_counters;
     bool ext_ifencei;
     bool ext_icsr;
+    bool ext_svnapot;
+    bool ext_svpbmt;
     bool ext_zfh;
     bool ext_zfhmin;
     bool ext_zve32f;
@@ -XXX,XX +XXX,XX @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
     return 16 << env->xl;
 }
 
+#ifdef TARGET_RISCV32
+#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+{
+#ifdef CONFIG_USER_ONLY
+    return env->misa_mxl;
+#else
+    return get_field(env->mstatus, MSTATUS64_SXL);
+#endif
+}
+#endif
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
 
+/* Page table PPN mask */
+#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
+
 /* Leaf page shift amount */
 #define PGSHIFT             12
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
     int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
     bool use_background = false;
+    hwaddr ppn;
+    RISCVCPU *cpu = env_archcpu(env);
 
     /*
      * Check if we should use the background registers for the two
@@ -XXX,XX +XXX,XX @@ restart:
             return TRANSLATE_FAIL;
         }
 
-        hwaddr ppn = pte >> PTE_PPN_SHIFT;
+        if (riscv_cpu_sxl(env) == MXL_RV32) {
+            ppn = pte >> PTE_PPN_SHIFT;
+        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
+            ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
+        } else {
+            ppn = pte >> PTE_PPN_SHIFT;
+            if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
+                return TRANSLATE_FAIL;
+            }
+        }
 
         if (!(pte & PTE_V)) {
             /* Invalid PTE */
-- 
2.34.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+                return TRANSLATE_FAIL;
+            }
             base = ppn << PGSHIFT;
         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
             /* Reserved leaf PTE flags: PTE_W */
-- 
2.34.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu.c        |  2 ++
 target/riscv/cpu_helper.c | 18 +++++++++++++++---
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define PTE_A               0x040 /* Accessed */
 #define PTE_D               0x080 /* Dirty */
 #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_N               0x8000000000000000ULL /* NAPOT translation */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     bool use_background = false;
     hwaddr ppn;
     RISCVCPU *cpu = env_archcpu(env);
+    int napot_bits = 0;
+    target_ulong napot_mask;
 
     /*
      * Check if we should use the background registers for the two
@@ -XXX,XX +XXX,XX @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
-            if (pte & (PTE_D | PTE_A | PTE_U)) {
+            if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
                 return TRANSLATE_FAIL;
             }
             base = ppn << PGSHIFT;
@@ -XXX,XX +XXX,XX @@ restart:
             /* for superpage mappings, make a fake leaf PTE for the TLB's
                benefit. */
             target_ulong vpn = addr >> PGSHIFT;
-            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
-                        (addr & ~TARGET_PAGE_MASK);
+
+            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+                napot_bits = ctzl(ppn) + 1;
+                if ((i != (levels - 1)) || (napot_bits != 4)) {
+                    return TRANSLATE_FAIL;
+                }
+            }
+
+            napot_mask = (1 << napot_bits) - 1;
+            *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
+                          (vpn & (((target_ulong)1 << ptshift) - 1))
+                         ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
 
             /* set permissions on the TLB entry */
             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
-- 
2.34.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                          |  1 +
 target/riscv/insn32.decode                  |  7 ++
 target/riscv/cpu.c                          |  1 +
 target/riscv/translate.c                    |  1 +
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_counters;
     bool ext_ifencei;
     bool ext_icsr;
+    bool ext_svinval;
     bool ext_svnapot;
     bool ext_svpbmt;
     bool ext_zfh;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
 fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
 fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
 fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma        0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval    0001100 00000 00000 000 00000 1110011
+sfence_inval_ir   0001100 00001 00000 000 00000 1110011
+hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_rvzfh.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
 #include "insn_trans/trans_xventanacondops.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2022 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do {          \
+    if (!ctx->cfg_ptr->ext_svinval) {      \
+        return false;                      \
+    }                                      \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as sfence.vma currently */
+    REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    REQUIRE_EXT(ctx, RVS);
+    /* Do nothing currently */
+    return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    REQUIRE_EXT(ctx, RVS);
+    /* Do nothing currently */
+    return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as hfence.vvma currently */
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as hfence.gvma currently */
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_hyp_gvma_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
-- 
2.34.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define PTE_A               0x040 /* Accessed */
 #define PTE_D               0x080 /* Dirty */
 #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_PBMT            0x6000000000000000ULL /* Page-based memory types */
 #define PTE_N               0x8000000000000000ULL /* NAPOT translation */
+#define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ restart:
         if (!(pte & PTE_V)) {
             /* Invalid PTE */
             return TRANSLATE_FAIL;
+        } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+            return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
-            if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+            if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
                 return TRANSLATE_FAIL;
             }
             base = ppn << PGSHIFT;
-- 
2.34.1

From: Yu Li <liyu.yukiteru@bytedance.com>

Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/virt.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ The ``virt`` machine supports the following devices:
 * 1 generic PCIe host bridge
 * The fw_cfg device that allows a guest to obtain data from QEMU
 
-Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
-can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
-enables the hypervisor extension for RV64.
+The hypervisor extension has been enabled for the default CPU, so virtual
+machines with hypervisor extension can simply be used without explicitly
+declaring.
 
 Hardware configuration information
 ----------------------------------
-- 
2.34.1

The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:

Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911

for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a:

target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000)

----------------------------------------------------------------
First RISC-V PR for 8.2

* Remove 'host' CPU from TCG
 * riscv_htif Fixup printing on big endian hosts
 * Add zmmul isa string
 * Add smepmp isa string
 * Fix page_check_range use in fault-only-first
 * Use existing lookup tables for MixColumns
 * Add RISC-V vector cryptographic instruction set support
 * Implement WARL behaviour for mcountinhibit/mcounteren
 * Add Zihintntl extension ISA string to DTS
 * Fix zfa fleq.d and fltq.d
 * Fix upper/lower mtime write calculation
 * Make rtc variable names consistent
 * Use abi type for linux-user target_ucontext
 * Add RISC-V KVM AIA Support
 * Fix riscv,pmu DT node path in the virt machine
 * Update CSR bits name for svadu extension
 * Mark zicond non-experimental
 * Fix satp_mode_finalize() when satp_mode.supported = 0
 * Fix non-KVM --enable-debug build
 * Add new extensions to hwprobe
 * Use accelerated helper for AES64KS1I
 * Allocate itrigger timers only once
 * Respect mseccfg.RLB for pmpaddrX changes
 * Align the AIA model to v1.0 ratified spec
 * Don't read the CSR in riscv_csrrw_do64

----------------------------------------------------------------
Akihiko Odaki (1):
      target/riscv: Allocate itrigger timers only once

Ard Biesheuvel (2):
      target/riscv: Use existing lookup tables for MixColumns
      target/riscv: Use accelerated helper for AES64KS1I

Conor Dooley (1):
      hw/riscv: virt: Fix riscv,pmu DT node path

Daniel Henrique Barboza (6):
      target/riscv/cpu.c: do not run 'host' CPU with TCG
      target/riscv/cpu.c: add zmmul isa string
      target/riscv/cpu.c: add smepmp isa string
      target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
      hw/riscv/virt.c: fix non-KVM --enable-debug build
      hw/intc/riscv_aplic.c fix non-KVM --enable-debug build

Dickon Hood (2):
      target/riscv: Refactor translation of vector-widening instruction
      target/riscv: Add Zvbb ISA extension support

Jason Chien (3):
      target/riscv: Add Zihintntl extension ISA string to DTS
      hw/intc: Fix upper/lower mtime write calculation
      hw/intc: Make rtc variable names consistent

Kiran Ostrolenk (4):
      target/riscv: Refactor some of the generic vector functionality
      target/riscv: Refactor vector-vector translation macro
      target/riscv: Refactor some of the generic vector functionality
      target/riscv: Add Zvknh ISA extension support

LIU Zhiwei (3):
      target/riscv: Fix page_check_range use in fault-only-first
      target/riscv: Fix zfa fleq.d and fltq.d
      linux-user/riscv: Use abi type for target_ucontext

Lawrence Hunter (2):
      target/riscv: Add Zvbc ISA extension support
      target/riscv: Add Zvksh ISA extension support

Leon Schuermann (1):
      target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes

Max Chou (3):
      crypto: Create sm4_subword
      crypto: Add SM4 constant parameter CK
      target/riscv: Add Zvksed ISA extension support

Nazar Kazakov (4):
      target/riscv: Remove redundant "cpu_vl == 0" checks
      target/riscv: Move vector translation checks
      target/riscv: Add Zvkned ISA extension support
      target/riscv: Add Zvkg ISA extension support

Nikita Shubin (1):
      target/riscv: don't read CSR in riscv_csrrw_do64

Rob Bradford (1):
      target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

Robbin Ehn (1):
      linux-user/riscv: Add new extensions to hwprobe

Thomas Huth (2):
      hw/char/riscv_htif: Fix printing of console characters on big endian hosts
      hw/char/riscv_htif: Fix the console syscall on big endian hosts

Tommy Wu (1):
      target/riscv: Align the AIA model to v1.0 ratified spec

Vineet Gupta (1):
      riscv: zicond: make non-experimental

Weiwei Li (1):
      target/riscv: Update CSR bits name for svadu extension

Yong-Xuan Wang (5):
      target/riscv: support the AIA device emulation with KVM enabled
      target/riscv: check the in-kernel irqchip support
      target/riscv: Create an KVM AIA irqchip
      target/riscv: update APLIC and IMSIC to support KVM AIA
      target/riscv: select KVM AIA in riscv virt machine

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:

$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: H extension requires priv spec 1.12.0

This CPU does not have a priv spec because we don't filter its extensions
via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
with the 'host' CPU.

We don't have a way to filter the 'host' CPU out of the available CPU
options (-cpu help) if the build includes both KVM and TCG. What we can
do is to error out during riscv_cpu_realize_tcg() if the user chooses
the 'host' CPU with accel=tcg:

$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
     CPURISCVState *env = &cpu->env;
     Error *local_err = NULL;
 
+    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
+        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+        return;
+    }
+
     riscv_cpu_validate_misa_mxl(cpu, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
-- 
2.41.0

From: Thomas Huth <thuth@redhat.com>

The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least significant bits
are stored on the lowest address. To do this in a portable way, we have
to store the value in an uint8_t variable instead.

Fixes: 5033606780 ("RISC-V HTIF Console")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721094720.902454-2-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
             s->tohost = 0; /* clear to indicate we read */
             return;
         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
-            qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
+            uint8_t ch = (uint8_t)payload;
+            qemu_chr_fe_write(&s->chr, &ch, 1);
             resp = 0x100 | (uint8_t)payload;
         } else {
             qemu_log("HTIF device %d: unknown command\n", device);
-- 
2.41.0

From: Thomas Huth <thuth@redhat.com>

Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.

Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230721094720.902454-3-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 #include "exec/address-spaces.h"
+#include "exec/tswap.h"
 #include "sysemu/dma.h"
 
 #define RISCV_DEBUG_HTIF 0
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
             } else {
                 uint64_t syscall[8];
                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
-                if (syscall[0] == PK_SYS_WRITE &&
-                    syscall[1] == HTIF_DEV_CONSOLE &&
-                    syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
+                if (tswap64(syscall[0]) == PK_SYS_WRITE &&
+                    tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
+                    tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
                     uint8_t ch;
-                    cpu_physical_memory_read(syscall[2], &ch, 1);
+                    cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
                     qemu_chr_fe_write(&s->chr, &ch, 1);
                     resp = 0x100 | (uint8_t)payload;
                 } else {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.

Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
+    ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
     ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
     ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
     ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+    ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
     ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
-- 
2.41.0

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                                          cpu_mmu_index(env, false));
                 if (host) {
 #ifdef CONFIG_USER_ONLY
-                    if (page_check_range(addr, offset, PAGE_READ)) {
+                    if (!page_check_range(addr, offset, PAGE_READ)) {
                         vl = i;
                         goto ProbeSuccess;
                     }
-- 
2.41.0

From: Ard Biesheuvel <ardb@kernel.org>

The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.

Given that we already carry those tables in QEMU, we can just grab the
right value in the implementation of the RISC-V AES32 instructions. Note
that the tables in question are permuted according to the respective
Sbox, so we can omit the Sbox lookup as well in this case.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Zewen Ye <lustrew@foxmail.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/crypto/aes.h         |  7 +++++++
 crypto/aes.c                 |  4 ++--
 target/riscv/crypto_helper.c | 34 ++++------------------------------
 3 files changed, 13 insertions(+), 32 deletions(-)

diff --git a/include/crypto/aes.h b/include/crypto/aes.h
index XXXXXXX..XXXXXXX 100644
--- a/include/crypto/aes.h
+++ b/include/crypto/aes.h
@@ -XXX,XX +XXX,XX @@ void AES_decrypt(const unsigned char *in, unsigned char *out,
 extern const uint8_t AES_sbox[256];
 extern const uint8_t AES_isbox[256];
 
+/*
+AES_Te0[x] = S [x].[02, 01, 01, 03];
+AES_Td0[x] = Si[x].[0e, 09, 0d, 0b];
+*/
+
+extern const uint32_t AES_Te0[256], AES_Td0[256];
+
 #endif
diff --git a/crypto/aes.c b/crypto/aes.c
index XXXXXXX..XXXXXXX 100644
--- a/crypto/aes.c
+++ b/crypto/aes.c
@@ -XXX,XX +XXX,XX @@ AES_Td3[x] = Si[x].[09, 0d, 0b, 0e];
 AES_Td4[x] = Si[x].[01, 01, 01, 01];
 */
 
-static const uint32_t AES_Te0[256] = {
+const uint32_t AES_Te0[256] = {
     0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
     0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
     0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
@@ -XXX,XX +XXX,XX @@ static const uint32_t AES_Te4[256] = {
     0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
 };
 
-static const uint32_t AES_Td0[256] = {
+const uint32_t AES_Td0[256] = {
     0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
     0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
     0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "crypto/aes-round.h"
 #include "crypto/sm4.h"
 
-#define AES_XTIME(a) \
-    ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
-
-#define AES_GFMUL(a, b) (( \
-    (((b) & 0x1) ? (a) : 0) ^ \
-    (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
-    (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
-    (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
-
-static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
-{
-    uint32_t u;
-
-    if (fwd) {
-        u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
-            (AES_GFMUL(x, 2) << 0);
-    } else {
-        u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
-            (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
-    }
-    return u;
-}
-
 #define sext32_xlen(x) (target_ulong)(int32_t)(x)
 
 static inline target_ulong aes32_operation(target_ulong shamt,
@@ -XXX,XX +XXX,XX @@ static inline target_ulong aes32_operation(target_ulong shamt,
                                            bool enc, bool mix)
 {
     uint8_t si = rs2 >> shamt;
-    uint8_t so;
     uint32_t mixed;
     target_ulong res;
 
     if (enc) {
-        so = AES_sbox[si];
         if (mix) {
-            mixed = aes_mixcolumn_byte(so, true);
+            mixed = be32_to_cpu(AES_Te0[si]);
         } else {
-            mixed = so;
+            mixed = AES_sbox[si];
         }
     } else {
-        so = AES_isbox[si];
         if (mix) {
-            mixed = aes_mixcolumn_byte(so, false);
+            mixed = be32_to_cpu(AES_Td0[si]);
         } else {
-            mixed = so;
+            mixed = AES_isbox[si];
         }
     }
     mixed = rol32(mixed, shamt);
-- 
2.41.0

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++
 target/riscv/vector_helper.c    | 201 +-------------------------------
 target/riscv/vector_internals.c |  81 +++++++++++++
 target/riscv/meson.build        |   1 +
 4 files changed, 265 insertions(+), 200 deletions(-)
 create mode 100644 target/riscv/vector_internals.h
 create mode 100644 target/riscv/vector_internals.c

diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/vector_internals.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V Vector Extension Internals
+ *
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_RISCV_VECTOR_INTERNALS_H
+#define TARGET_RISCV_VECTOR_INTERNALS_H
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "internals.h"
+
+static inline uint32_t vext_nf(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, NF);
+}
+
+/*
+ * Note that vector data is stored in host-endian 64-bit chunks,
+ * so addressing units smaller than that needs a host-endian fixup.
+ */
+#if HOST_BIG_ENDIAN
+#define H1(x)   ((x) ^ 7)
+#define H1_2(x) ((x) ^ 6)
+#define H1_4(x) ((x) ^ 4)
+#define H2(x)   ((x) ^ 3)
+#define H4(x)   ((x) ^ 1)
+#define H8(x)   ((x))
+#else
+#define H1(x)   (x)
+#define H1_2(x) (x)
+#define H1_4(x) (x)
+#define H2(x)   (x)
+#define H4(x)   (x)
+#define H8(x)   (x)
+#endif
+
+/*
+ * Encode LMUL to lmul as following:
+ *     LMUL    vlmul    lmul
+ *      1       000       0
+ *      2       001       1
+ *      4       010       2
+ *      8       011       3
+ *      -       100       -
+ *     1/8      101      -3
+ *     1/4      110      -2
+ *     1/2      111      -1
+ */
+static inline int32_t vext_lmul(uint32_t desc)
+{
+    return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
+}
+
+static inline uint32_t vext_vm(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VM);
+}
+
+static inline uint32_t vext_vma(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
+static inline uint32_t vext_vta(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VTA);
+}
+
+static inline uint32_t vext_vta_all_1s(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
+}
+
+/*
+ * Earlier designs (pre-0.9) had a varying number of bits
+ * per mask value (MLEN). In the 0.9 design, MLEN=1.
+ * (Section 4.5)
+ */
+static inline int vext_elem_mask(void *v0, int index)
+{
+    int idx = index / 64;
+    int pos = index  % 64;
+    return (((uint64_t *)v0)[idx] >> pos) & 1;
+}
+
+/*
+ * Get number of total elements, including prestart, body and tail elements.
+ * Note that when LMUL < 1, the tail includes the elements past VLMAX that
+ * are held in the same vector register.
+ */
+static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
+                                            uint32_t esz)
+{
+    uint32_t vlenb = simd_maxsz(desc);
+    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
+    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
+                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
+    return (vlenb << emul) / esz;
+}
+
+/* set agnostic elements to 1s */
+void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+                       uint32_t tot);
+
+/* expand macro args before macro */
+#define RVVCALL(macro, ...)  macro(__VA_ARGS__)
+
+/* (TD, T1, T2, TX1, TX2) */
+#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
+#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
+#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
+#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
+
+/* operation of two vector elements */
+typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
+
+#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)    \
+static void do_##NAME(void *vd, void *vs1, void *vs2, int i)    \
+{                                                               \
+    TX1 s1 = *((T1 *)vs1 + HS1(i));                             \
+    TX2 s2 = *((T2 *)vs2 + HS2(i));                             \
+    *((TD *)vd + HD(i)) = OP(s2, s1);                           \
+}
+
+void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
+                CPURISCVState *env, uint32_t desc,
+                opivv2_fn *fn, uint32_t esz);
+
+/* generate the helpers for OPIVV */
+#define GEN_VEXT_VV(NAME, ESZ)                            \
+void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
+                  void *vs2, CPURISCVState *env,          \
+                  uint32_t desc)                          \
+{                                                         \
+    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
+               do_##NAME, ESZ);                           \
+}
+
+typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
+
+/*
+ * (T1)s1 gives the real operator type.
+ * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
+ */
+#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
+static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
+{                                                                   \
+    TX2 s2 = *((T2 *)vs2 + HS2(i));                                 \
+    *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1);                      \
+}
+
+void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
+                CPURISCVState *env, uint32_t desc,
+                opivx2_fn fn, uint32_t esz);
+
+/* generate the helpers for OPIVX */
+#define GEN_VEXT_VX(NAME, ESZ)                            \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
+                  void *vs2, CPURISCVState *env,          \
+                  uint32_t desc)                          \
+{                                                         \
+    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
+               do_##NAME, ESZ);                           \
+}
+
+#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "fpu/softfloat.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "internals.h"
+#include "vector_internals.h"
 #include <math.h>
 
 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     return vl;
 }
 
-/*
- * Note that vector data is stored in host-endian 64-bit chunks,
- * so addressing units smaller than that needs a host-endian fixup.
- */
-#if HOST_BIG_ENDIAN
-#define H1(x)   ((x) ^ 7)
-#define H1_2(x) ((x) ^ 6)
-#define H1_4(x) ((x) ^ 4)
-#define H2(x)   ((x) ^ 3)
-#define H4(x)   ((x) ^ 1)
-#define H8(x)   ((x))
-#else
-#define H1(x)   (x)
-#define H1_2(x) (x)
-#define H1_4(x) (x)
-#define H2(x)   (x)
-#define H4(x)   (x)
-#define H8(x)   (x)
-#endif
-
-static inline uint32_t vext_nf(uint32_t desc)
-{
-    return FIELD_EX32(simd_data(desc), VDATA, NF);
-}
-
-static inline uint32_t vext_vm(uint32_t desc)
-{
-    return FIELD_EX32(simd_data(desc), VDATA, VM);
-}
-
-/*
- * Encode LMUL to lmul as following:
- *     LMUL    vlmul    lmul
- *      1       000       0
- *      2       001       1
- *      4       010       2
- *      8       011       3
- *      -       100       -
- *     1/8      101      -3
- *     1/4      110      -2
- *     1/2      111      -1
- */
-static inline int32_t vext_lmul(uint32_t desc)
-{
-    return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
-}
-
-static inline uint32_t vext_vta(uint32_t desc)
-{
-    return FIELD_EX32(simd_data(desc), VDATA, VTA);
-}
-
-static inline uint32_t vext_vma(uint32_t desc)
-{
-    return FIELD_EX32(simd_data(desc), VDATA, VMA);
-}
-
-static inline uint32_t vext_vta_all_1s(uint32_t desc)
-{
-    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
-}
-
 /*
  * Get the maximum number of elements can be operated.
  *
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
-/*
- * Get number of total elements, including prestart, body and tail elements.
- * Note that when LMUL < 1, the tail includes the elements past VLMAX that
- * are held in the same vector register.
- */
-static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
-                                            uint32_t esz)
-{
-    uint32_t vlenb = simd_maxsz(desc);
-    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
-    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
-                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
-    return (vlenb << emul) / esz;
-}
-
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 {
     return (addr & ~env->cur_pmmask) | env->cur_pmbase;
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
     }
 }
 
-/* set agnostic elements to 1s */
-static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-                              uint32_t tot)
-{
-    if (is_agnostic == 0) {
-        /* policy undisturbed */
-        return;
-    }
-    if (tot - cnt == 0) {
-        return;
-    }
-    memset(base + cnt, -1, tot - cnt);
-}
-
 static inline void vext_set_elem_mask(void *v0, int index,
                                       uint8_t value)
 {
@@ -XXX,XX +XXX,XX @@ static inline void vext_set_elem_mask(void *v0, int index,
     ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
 }
 
-/*
- * Earlier designs (pre-0.9) had a varying number of bits
- * per mask value (MLEN). In the 0.9 design, MLEN=1.
- * (Section 4.5)
- */
-static inline int vext_elem_mask(void *v0, int index)
-{
-    int idx = index / 64;
-    int pos = index  % 64;
-    return (((uint64_t *)v0)[idx] >> pos) & 1;
-}
-
 /* elements operations for load and store */
 typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr,
                                uint32_t idx, void *vd, uintptr_t retaddr);
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
  * Vector Integer Arithmetic Instructions
  */
 
-/* expand macro args before macro */
-#define RVVCALL(macro, ...)  macro(__VA_ARGS__)
-
 /* (TD, T1, T2, TX1, TX2) */
 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
-#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
-#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
-#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
-#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
 #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
 #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
 #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
 
-/* operation of two vector elements */
-typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
-
-#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)    \
-static void do_##NAME(void *vd, void *vs1, void *vs2, int i)    \
-{                                                               \
-    TX1 s1 = *((T1 *)vs1 + HS1(i));                             \
-    TX2 s2 = *((T2 *)vs2 + HS2(i));                             \
-    *((TD *)vd + HD(i)) = OP(s2, s1);                           \
-}
 #define DO_SUB(N, M) (N - M)
 #define DO_RSUB(N, M) (M - N)
 
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
 RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
 RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
 
-static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
-                       CPURISCVState *env, uint32_t desc,
-                       opivv2_fn *fn, uint32_t esz)
-{
-    uint32_t vm = vext_vm(desc);
-    uint32_t vl = env->vl;
-    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-    uint32_t vta = vext_vta(desc);
-    uint32_t vma = vext_vma(desc);
-    uint32_t i;
-
-    for (i = env->vstart; i < vl; i++) {
-        if (!vm && !vext_elem_mask(v0, i)) {
-            /* set masked-off elements to 1s */
-            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
-            continue;
-        }
-        fn(vd, vs1, vs2, i);
-    }
-    env->vstart = 0;
-    /* set tail elements to 1s */
-    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
-}
-
-/* generate the helpers for OPIVV */
-#define GEN_VEXT_VV(NAME, ESZ)                            \
-void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-                  void *vs2, CPURISCVState *env,          \
-                  uint32_t desc)                          \
-{                                                         \
-    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
-               do_##NAME, ESZ);                           \
-}
-
 GEN_VEXT_VV(vadd_vv_b, 1)
 GEN_VEXT_VV(vadd_vv_h, 2)
 GEN_VEXT_VV(vadd_vv_w, 4)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VV(vsub_vv_h, 2)
 GEN_VEXT_VV(vsub_vv_w, 4)
 GEN_VEXT_VV(vsub_vv_d, 8)
 
-typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
-
-/*
- * (T1)s1 gives the real operator type.
- * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
- */
-#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
-static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
-{                                                                   \
-    TX2 s2 = *((T2 *)vs2 + HS2(i));                                 \
-    *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1);                      \
-}
 
 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
 RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
 RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
 RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
 
-static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
-                       CPURISCVState *env, uint32_t desc,
-                       opivx2_fn fn, uint32_t esz)
-{
-    uint32_t vm = vext_vm(desc);
-    uint32_t vl = env->vl;
-    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-    uint32_t vta = vext_vta(desc);
-    uint32_t vma = vext_vma(desc);
-    uint32_t i;
-
-    for (i = env->vstart; i < vl; i++) {
-        if (!vm && !vext_elem_mask(v0, i)) {
-            /* set masked-off elements to 1s */
-            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
-            continue;
-        }
-        fn(vd, s1, vs2, i);
-    }
-    env->vstart = 0;
-    /* set tail elements to 1s */
-    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
-}
-
-/* generate the helpers for OPIVX */
-#define GEN_VEXT_VX(NAME, ESZ)                            \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
-                  void *vs2, CPURISCVState *env,          \
-                  uint32_t desc)                          \
-{                                                         \
-    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
-               do_##NAME, ESZ);                           \
-}
-
 GEN_VEXT_VX(vadd_vx_b, 1)
 GEN_VEXT_VX(vadd_vx_h, 2)
 GEN_VEXT_VX(vadd_vx_w, 4)
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V Vector Extension Internals
+ *
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "vector_internals.h"
+
+/* set agnostic elements to 1s */
+void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+                       uint32_t tot)
+{
+    if (is_agnostic == 0) {
+        /* policy undisturbed */
+        return;
+    }
+    if (tot - cnt == 0) {
+        return ;
+    }
+    memset(base + cnt, -1, tot - cnt);
+}
+
+void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
+                CPURISCVState *env, uint32_t desc,
+                opivv2_fn *fn, uint32_t esz)
+{
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);
+    uint32_t i;
+
+    for (i = env->vstart; i < vl; i++) {
+        if (!vm && !vext_elem_mask(v0, i)) {
+            /* set masked-off elements to 1s */
+            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
+            continue;
+        }
+        fn(vd, vs1, vs2, i);
+    }
+    env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
+}
+
+void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
+                CPURISCVState *env, uint32_t desc,
+                opivx2_fn fn, uint32_t esz)
+{
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);
+    uint32_t i;
+
+    for (i = env->vstart; i < vl; i++) {
+        if (!vm && !vext_elem_mask(v0, i)) {
+            /* set masked-off elements to 1s */
+            vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
+            continue;
+        }
+        fn(vd, s1, vs2, i);
+    }
+    env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'gdbstub.c',
   'op_helper.c',
   'vector_helper.c',
+  'vector_internals.c',
   'bitmanip_helper.c',
   'translate.c',
   'm128_helper.c',
-- 
2.41.0

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
 1 file changed, 32 insertions(+), 30 deletions(-)

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

Remove the redundant "vl == 0" check which is already included within the  vstart >= vl check, when vl == 0.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------
 1 file changed, 1 insertion(+), 30 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     TCGv_i32 desc;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     TCGv_i32 desc;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     TCGv_i32 desc;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     TCGv_i32 desc;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
         return false;
     }
 
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     uint32_t data = 0;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
     uint32_t data = 0;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
     if (checkfn(s, a)) {
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
     if (opiwv_widen_check(s, a)) {
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
 {
     uint32_t data = 0;
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     data = FIELD_DP32(data, VDATA, VM, vm);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
             gen_helper_##NAME##_w,                                 \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                 gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
             };
             TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
             tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
         vext_check_ss(s, a->rd, 0, 1)) {
         TCGv s1;
         TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         s1 = get_gpr(s, a->rs1, EXT_SIGN);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
                 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
             };
             TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
             tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             s1 = tcg_constant_i64(simm);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     TCGv_i64 t1;
 
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         };                                                       \
         TCGLabel *over = gen_new_label();                        \
         gen_set_rm(s, RISCV_FRM_DYN);                            \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
                                                                  \
         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
         gen_set_rm_chkfrm(s, rm);
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                 gen_helper_vmv_v_x_d,
             };
             TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
             tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             t1 = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
         uint32_t data = 0;                                         \
         gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
         TCGLabel *over = gen_new_label();                          \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
         require_vm(a->vm, a->rd)) {
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
         TCGv s1;
         TCGLabel *over = gen_new_label();
 
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         t1 = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
         TCGv_i64 t1;
         TCGLabel *over = gen_new_label();
 
-        /* if vl == 0 or vstart >= vl, skip vector register write back */
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        /* if vstart >= vl, skip vector register write back */
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         /* NaN-box f[rs1] */
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
     uint32_t data = 0;
     gen_helper_gvec_3_ptr *fn;
     TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     static gen_helper_gvec_3_ptr * const fns[6][4] = {
-- 
2.41.0

From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>

This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:

* vclmulh.[vx,vv]
* vclmul.[vx,vv]

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
[max.chou@sifive.com: Exposed x-zvbc property]
Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |  1 +
 target/riscv/helper.h                    |  6 +++
 target/riscv/insn32.decode               |  6 +++
 target/riscv/cpu.c                       |  9 ++++
 target/riscv/translate.c                 |  1 +
 target/riscv/vcrypto_helper.c            | 59 ++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++
 target/riscv/meson.build                 |  3 +-
 8 files changed, 146 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/vcrypto_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++--------------
 1 file changed, 12 insertions(+), 16 deletions(-)

From: Dickon Hood <dickon.hood@codethink.co.uk>

Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions.  Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.

Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++--------------
 1 file changed, 23 insertions(+), 29 deletions(-)

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++
 target/riscv/vector_helper.c    | 42 ------------------------------
 2 files changed, 46 insertions(+), 42 deletions(-)

diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
 /* expand macro args before macro */
 #define RVVCALL(macro, ...)  macro(__VA_ARGS__)
 
+/* (TD, T2, TX2) */
+#define OP_UU_B uint8_t, uint8_t, uint8_t
+#define OP_UU_H uint16_t, uint16_t, uint16_t
+#define OP_UU_W uint32_t, uint32_t, uint32_t
+#define OP_UU_D uint64_t, uint64_t, uint64_t
+
 /* (TD, T1, T2, TX1, TX2) */
 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
 
+#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
+static void do_##NAME(void *vd, void *vs2, int i)      \
+{                                                      \
+    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
+    *((TD *)vd + HD(i)) = OP(s2);                      \
+}
+
+#define GEN_VEXT_V(NAME, ESZ)                          \
+void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+                  CPURISCVState *env, uint32_t desc)   \
+{                                                      \
+    uint32_t vm = vext_vm(desc);                       \
+    uint32_t vl = env->vl;                             \
+    uint32_t total_elems =                             \
+        vext_get_total_elems(env, desc, ESZ);          \
+    uint32_t vta = vext_vta(desc);                     \
+    uint32_t vma = vext_vma(desc);                     \
+    uint32_t i;                                        \
+                                                       \
+    for (i = env->vstart; i < vl; i++) {               \
+        if (!vm && !vext_elem_mask(v0, i)) {           \
+            /* set masked-off elements to 1s */        \
+            vext_set_elems_1s(vd, vma, i * ESZ,        \
+                              (i + 1) * ESZ);          \
+            continue;                                  \
+        }                                              \
+        do_##NAME(vd, vs2, i);                         \
+    }                                                  \
+    env->vstart = 0;                                   \
+    /* set tail elements to 1s */                      \
+    vext_set_elems_1s(vd, vta, vl * ESZ,               \
+                      total_elems * ESZ);              \
+}
+
 /* operation of two vector elements */
 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
                do_##NAME, ESZ);                           \
 }
 
+/* Three of the widening shortening macros: */
+/* (TD, T1, T2, TX1, TX2) */
+#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
+#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
+#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
+
 #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
 #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
-#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
-#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
-#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4)
 GEN_VEXT_VF(vfwnmsac_vf_w, 8)
 
 /* Vector Floating-Point Square-Root Instruction */
-/* (TD, T2, TX2) */
-#define OP_UU_H uint16_t, uint16_t, uint16_t
-#define OP_UU_W uint32_t, uint32_t, uint32_t
-#define OP_UU_D uint64_t, uint64_t, uint64_t
-
 #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
 static void do_##NAME(void *vd, void *vs2, int i,      \
                       CPURISCVState *env)              \
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
 GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
 
 /* Vector Floating-Point Classify Instruction */
-#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
-static void do_##NAME(void *vd, void *vs2, int i)      \
-{                                                      \
-    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
-    *((TD *)vd + HD(i)) = OP(s2);                      \
-}
-
-#define GEN_VEXT_V(NAME, ESZ)                          \
-void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
-                  CPURISCVState *env, uint32_t desc)   \
-{                                                      \
-    uint32_t vm = vext_vm(desc);                       \
-    uint32_t vl = env->vl;                             \
-    uint32_t total_elems =                             \
-        vext_get_total_elems(env, desc, ESZ);          \
-    uint32_t vta = vext_vta(desc);                     \
-    uint32_t vma = vext_vma(desc);                     \
-    uint32_t i;                                        \
-                                                       \
-    for (i = env->vstart; i < vl; i++) {               \
-        if (!vm && !vext_elem_mask(v0, i)) {           \
-            /* set masked-off elements to 1s */        \
-            vext_set_elems_1s(vd, vma, i * ESZ,        \
-                              (i + 1) * ESZ);          \
-            continue;                                  \
-        }                                              \
-        do_##NAME(vd, vs2, i);                         \
-    }                                                  \
-    env->vstart = 0;                                   \
-    /* set tail elements to 1s */                      \
-    vext_set_elems_1s(vd, vta, vl * ESZ,               \
-                      total_elems * ESZ);              \
-}
-
 target_ulong fclass_h(uint64_t frs1)
 {
     float16 f = frs1;
-- 
2.41.0

From: Dickon Hood <dickon.hood@codethink.co.uk>

This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:

* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Fix imm mode of vror.vi]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvbb property]
Message-ID: <20230711165917.2629866-9-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |   1 +
 target/riscv/helper.h                    |  62 +++++++++
 target/riscv/insn32.decode               |  20 +++
 target/riscv/cpu.c                       |  12 ++
 target/riscv/vcrypto_helper.c            | 138 +++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++
 6 files changed, 397 insertions(+)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
     bool ext_zve64d;
+    bool ext_zvbb;
     bool ext_zvbc;
     bool ext_zmmul;
     bool ext_zvfbfmin;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %imm_u    12:s20                 !function=ex_shift_12
 %imm_bs   30:2                   !function=ex_shift_3
 %imm_rnum 20:4
+%imm_z6   26:1 15:5
 
 # Argument sets:
 &empty
@@ -XXX,XX +XXX,XX @@
 @r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
 @r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
 @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
+@r2_zimm6  ..... . vm:1 ..... ..... ... ..... .......  &rmrr %rs2 rs1=%imm_z6 %rd
 @r2_zimm11 . zimm:11  ..... ... ..... ....... %rs1 %rd
 @r2_zimm10 .. zimm:10  ..... ... ..... ....... %rs1 %rd
 @r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
@@ -XXX,XX +XXX,XX @@ vclmul_vv   001100 . ..... ..... 010 ..... 1010111 @r_vm
 vclmul_vx   001100 . ..... ..... 110 ..... 1010111 @r_vm
 vclmulh_vv  001101 . ..... ..... 010 ..... 1010111 @r_vm
 vclmulh_vx  001101 . ..... ..... 110 ..... 1010111 @r_vm
+
+# *** Zvbb vector crypto extension ***
+vrol_vv     010101 . ..... ..... 000 ..... 1010111 @r_vm
+vrol_vx     010101 . ..... ..... 100 ..... 1010111 @r_vm
+vror_vv     010100 . ..... ..... 000 ..... 1010111 @r_vm
+vror_vx     010100 . ..... ..... 100 ..... 1010111 @r_vm
+vror_vi     01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
+vbrev8_v    010010 . ..... 01000 010 ..... 1010111 @r2_vm
+vrev8_v     010010 . ..... 01001 010 ..... 1010111 @r2_vm
+vandn_vv    000001 . ..... ..... 000 ..... 1010111 @r_vm
+vandn_vx    000001 . ..... ..... 100 ..... 1010111 @r_vm
+vbrev_v     010010 . ..... 01010 010 ..... 1010111 @r2_vm
+vclz_v      010010 . ..... 01100 010 ..... 1010111 @r2_vm
+vctz_v      010010 . ..... 01101 010 ..... 1010111 @r2_vm
+vcpop_v     010010 . ..... 01110 010 ..... 1010111 @r2_vm
+vwsll_vv    110101 . ..... ..... 000 ..... 1010111 @r_vm
+vwsll_vx    110101 . ..... ..... 100 ..... 1010111 @r_vm
+vwsll_vi    110101 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
+    ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    /*
+     * In principle Zve*x would also suffice here, were they supported
+     * in qemu
+     */
+    if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
+        error_setg(errp,
+                   "Vector crypto extensions require V or Zve* extensions");
+        return;
+    }
+
     if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
         error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
         return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
 
     /* Vector cryptography extensions */
+    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
     DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
 
     DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qemu/host-utils.h"
 #include "qemu/bitops.h"
+#include "qemu/bswap.h"
 #include "cpu.h"
 #include "exec/memop.h"
 #include "exec/exec-all.h"
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
 GEN_VEXT_VV(vclmulh_vv, 8)
 RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
 GEN_VEXT_VX(vclmulh_vx, 8)
+
+RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8)
+RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16)
+RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32)
+RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64)
+GEN_VEXT_VV(vror_vv_b, 1)
+GEN_VEXT_VV(vror_vv_h, 2)
+GEN_VEXT_VV(vror_vv_w, 4)
+GEN_VEXT_VV(vror_vv_d, 8)
+
+RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8)
+RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16)
+RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32)
+RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64)
+GEN_VEXT_VX(vror_vx_b, 1)
+GEN_VEXT_VX(vror_vx_h, 2)
+GEN_VEXT_VX(vror_vx_w, 4)
+GEN_VEXT_VX(vror_vx_d, 8)
+
+RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8)
+RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16)
+RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32)
+RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64)
+GEN_VEXT_VV(vrol_vv_b, 1)
+GEN_VEXT_VV(vrol_vv_h, 2)
+GEN_VEXT_VV(vrol_vv_w, 4)
+GEN_VEXT_VV(vrol_vv_d, 8)
+
+RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8)
+RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16)
+RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32)
+RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64)
+GEN_VEXT_VX(vrol_vx_b, 1)
+GEN_VEXT_VX(vrol_vx_h, 2)
+GEN_VEXT_VX(vrol_vx_w, 4)
+GEN_VEXT_VX(vrol_vx_d, 8)
+
+static uint64_t brev8(uint64_t val)
+{
+    val = ((val & 0x5555555555555555ull) << 1) |
+          ((val & 0xAAAAAAAAAAAAAAAAull) >> 1);
+    val = ((val & 0x3333333333333333ull) << 2) |
+          ((val & 0xCCCCCCCCCCCCCCCCull) >> 2);
+    val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4) |
+          ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4);
+
+    return val;
+}
+
+RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8)
+RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8)
+RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8)
+RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8)
+GEN_VEXT_V(vbrev8_v_b, 1)
+GEN_VEXT_V(vbrev8_v_h, 2)
+GEN_VEXT_V(vbrev8_v_w, 4)
+GEN_VEXT_V(vbrev8_v_d, 8)
+
+#define DO_IDENTITY(a) (a)
+RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY)
+RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16)
+RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32)
+RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64)
+GEN_VEXT_V(vrev8_v_b, 1)
+GEN_VEXT_V(vrev8_v_h, 2)
+GEN_VEXT_V(vrev8_v_w, 4)
+GEN_VEXT_V(vrev8_v_d, 8)
+
+#define DO_ANDN(a, b) ((a) & ~(b))
+RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN)
+RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN)
+RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN)
+RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN)
+GEN_VEXT_VV(vandn_vv_b, 1)
+GEN_VEXT_VV(vandn_vv_h, 2)
+GEN_VEXT_VV(vandn_vv_w, 4)
+GEN_VEXT_VV(vandn_vv_d, 8)
+
+RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN)
+RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN)
+RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN)
+RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN)
+GEN_VEXT_VX(vandn_vx_b, 1)
+GEN_VEXT_VX(vandn_vx_h, 2)
+GEN_VEXT_VX(vandn_vx_w, 4)
+GEN_VEXT_VX(vandn_vx_d, 8)
+
+RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8)
+RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16)
+RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32)
+RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64)
+GEN_VEXT_V(vbrev_v_b, 1)
+GEN_VEXT_V(vbrev_v_h, 2)
+GEN_VEXT_V(vbrev_v_w, 4)
+GEN_VEXT_V(vbrev_v_d, 8)
+
+RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8)
+RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16)
+RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32)
+RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64)
+GEN_VEXT_V(vclz_v_b, 1)
+GEN_VEXT_V(vclz_v_h, 2)
+GEN_VEXT_V(vclz_v_w, 4)
+GEN_VEXT_V(vclz_v_d, 8)
+
+RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8)
+RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16)
+RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32)
+RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64)
+GEN_VEXT_V(vctz_v_b, 1)
+GEN_VEXT_V(vctz_v_h, 2)
+GEN_VEXT_V(vctz_v_w, 4)
+GEN_VEXT_V(vctz_v_d, 8)
+
+RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8)
+RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16)
+RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32)
+RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64)
+GEN_VEXT_V(vcpop_v_b, 1)
+GEN_VEXT_V(vcpop_v_h, 2)
+GEN_VEXT_V(vcpop_v_w, 4)
+GEN_VEXT_V(vcpop_v_d, 8)
+
+#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1)))
+RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL)
+RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL)
+RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL)
+GEN_VEXT_VV(vwsll_vv_b, 2)
+GEN_VEXT_VV(vwsll_vv_h, 4)
+GEN_VEXT_VV(vwsll_vv_w, 8)
+
+RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL)
+RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL)
+RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
+GEN_VEXT_VX(vwsll_vx_b, 2)
+GEN_VEXT_VX(vwsll_vx_h, 4)
+GEN_VEXT_VX(vwsll_vx_w, 8)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
 
 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
 GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
+
+/*
+ * Zvbb
+ */
+
+#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK)   \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)              \
+    {                                                                   \
+        if (CHECK(s, a)) {                                              \
+            static gen_helper_opivx *const fns[4] = {                   \
+                gen_helper_##OPIVX##_b,                                 \
+                gen_helper_##OPIVX##_h,                                 \
+                gen_helper_##OPIVX##_w,                                 \
+                gen_helper_##OPIVX##_d,                                 \
+            };                                                          \
+            return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \
+                                 IMM_MODE);                             \
+        }                                                               \
+        return false;                                                   \
+    }
+
+#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK)                     \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)               \
+    {                                                                    \
+        if (CHECK(s, a)) {                                               \
+            static gen_helper_gvec_4_ptr *const fns[4] = {               \
+                gen_helper_##NAME##_b,                                   \
+                gen_helper_##NAME##_h,                                   \
+                gen_helper_##NAME##_w,                                   \
+                gen_helper_##NAME##_d,                                   \
+            };                                                           \
+            return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+        }                                                                \
+        return false;                                                    \
+    }
+
+#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK)       \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
+    {                                                            \
+        if (CHECK(s, a)) {                                       \
+            static gen_helper_opivx *const fns[4] = {            \
+                gen_helper_##NAME##_b,                           \
+                gen_helper_##NAME##_h,                           \
+                gen_helper_##NAME##_w,                           \
+                gen_helper_##NAME##_d,                           \
+            };                                                   \
+            return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \
+                                       fns[s->sew]);             \
+        }                                                        \
+        return false;                                            \
+    }
+
+static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
+{
+    return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+}
+
+static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
+{
+    return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+}
+
+/* vrol.v[vx] */
+GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
+
+/* vror.v[vxi] */
+GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
+GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
+
+#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK)                     \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)               \
+    {                                                                    \
+        if (CHECK(s, a)) {                                               \
+            static gen_helper_opivx *const fns[4] = {                    \
+                gen_helper_##NAME##_b,                                   \
+                gen_helper_##NAME##_h,                                   \
+                gen_helper_##NAME##_w,                                   \
+                gen_helper_##NAME##_d,                                   \
+            };                                                           \
+            return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+        }                                                                \
+        return false;                                                    \
+    }
+
+/* vandn.v[vx] */
+GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
+GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
+
+#define GEN_OPIV_TRANS(NAME, CHECK)                                        \
+    static bool trans_##NAME(DisasContext *s, arg_rmr *a)                  \
+    {                                                                      \
+        if (CHECK(s, a)) {                                                 \
+            uint32_t data = 0;                                             \
+            static gen_helper_gvec_3_ptr *const fns[4] = {                 \
+                gen_helper_##NAME##_b,                                     \
+                gen_helper_##NAME##_h,                                     \
+                gen_helper_##NAME##_w,                                     \
+                gen_helper_##NAME##_d,                                     \
+            };                                                             \
+            TCGLabel *over = gen_new_label();                              \
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);     \
+                                                                           \
+            data = FIELD_DP32(data, VDATA, VM, a->vm);                     \
+            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                 \
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);                   \
+            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
+            data = FIELD_DP32(data, VDATA, VMA, s->vma);                   \
+            tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),         \
+                               vreg_ofs(s, a->rs2), cpu_env,               \
+                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
+                               data, fns[s->sew]);                         \
+            mark_vs_dirty(s);                                              \
+            gen_set_label(over);                                           \
+            return true;                                                   \
+        }                                                                  \
+        return false;                                                      \
+    }
+
+static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
+{
+    return s->cfg_ptr->ext_zvbb == true &&
+           require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           vext_check_ss(s, a->rd, a->rs2, a->vm);
+}
+
+GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
+GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
+GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
+GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
+GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
+GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check)
+
+static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a)
+{
+    return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a);
+}
+
+static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
+{
+    return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a);
+}
+
+/* OPIVI without GVEC IR */
+#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK)                  \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
+    {                                                                        \
+        if (CHECK(s, a)) {                                                   \
+            static gen_helper_opivx *const fns[3] = {                        \
+                gen_helper_##OPIVX##_b,                                      \
+                gen_helper_##OPIVX##_h,                                      \
+                gen_helper_##OPIVX##_w,                                      \
+            };                                                               \
+            return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
+                               IMM_MODE);                                    \
+        }                                                                    \
+        return false;                                                        \
+    }
+
+GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
+GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
+GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
-- 
2.41.0

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:

* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
[max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |   1 +
 target/riscv/helper.h                    |  14 ++
 target/riscv/insn32.decode               |  14 ++
 target/riscv/cpu.c                       |   4 +-
 target/riscv/vcrypto_helper.c            | 202 +++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++
 6 files changed, 381 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zve64d;
     bool ext_zvbb;
     bool ext_zvbc;
+    bool ext_zvkned;
     bool ext_zmmul;
     bool ext_zvfbfmin;
     bool ext_zvfbfwma;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_2(egs_check, void, i32, env)
+
+DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
+DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
 @r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
+@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -XXX,XX +XXX,XX @@ vcpop_v     010010 . ..... 01110 010 ..... 1010111 @r2_vm
 vwsll_vv    110101 . ..... ..... 000 ..... 1010111 @r_vm
 vwsll_vx    110101 . ..... ..... 100 ..... 1010111 @r_vm
 vwsll_vi    110101 . ..... ..... 011 ..... 1010111 @r_vm
+
+# *** Zvkned vector crypto extension ***
+vaesef_vv   101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
+vaesef_vs   101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
+vaesdf_vv   101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
+vaesdf_vs   101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
+vaesem_vv   101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
+vaesem_vs   101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
+vaesdm_vv   101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
+vaesdm_vs   101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
+vaesz_vs    101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
+vaeskf1_vi  100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
+vaeskf2_vi  101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+    ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      * In principle Zve*x would also suffice here, were they supported
      * in qemu
      */
-    if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
+    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
     DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
+    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "qemu/bswap.h"
 #include "cpu.h"
+#include "crypto/aes.h"
+#include "crypto/aes-round.h"
 #include "exec/memop.h"
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
 GEN_VEXT_VX(vwsll_vx_b, 2)
 GEN_VEXT_VX(vwsll_vx_h, 4)
 GEN_VEXT_VX(vwsll_vx_w, 8)
+
+void HELPER(egs_check)(uint32_t egs, CPURISCVState *env)
+{
+    uint32_t vl = env->vl;
+    uint32_t vstart = env->vstart;
+
+    if (vl % egs != 0 || vstart % egs != 0) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
+static inline void xor_round_key(AESState *round_state, AESState *round_key)
+{
+    round_state->v = round_state->v ^ round_key->v;
+}
+
+#define GEN_ZVKNED_HELPER_VV(NAME, ...)                                   \
+    void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env,            \
+                      uint32_t desc)                                      \
+    {                                                                     \
+        uint32_t vl = env->vl;                                            \
+        uint32_t total_elems = vext_get_total_elems(env, desc, 4);        \
+        uint32_t vta = vext_vta(desc);                                    \
+                                                                          \
+        for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {        \
+            AESState round_key;                                           \
+            round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0));          \
+            round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1));          \
+            AESState round_state;                                         \
+            round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0));         \
+            round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1));         \
+            __VA_ARGS__;                                                  \
+            *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0];         \
+            *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1];         \
+        }                                                                 \
+        env->vstart = 0;                                                  \
+        /* set tail elements to 1s */                                     \
+        vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);              \
+    }
+
+#define GEN_ZVKNED_HELPER_VS(NAME, ...)                                   \
+    void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env,            \
+                      uint32_t desc)                                      \
+    {                                                                     \
+        uint32_t vl = env->vl;                                            \
+        uint32_t total_elems = vext_get_total_elems(env, desc, 4);        \
+        uint32_t vta = vext_vta(desc);                                    \
+                                                                          \
+        for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {        \
+            AESState round_key;                                           \
+            round_key.d[0] = *((uint64_t *)vs2 + H8(0));                  \
+            round_key.d[1] = *((uint64_t *)vs2 + H8(1));                  \
+            AESState round_state;                                         \
+            round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0));         \
+            round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1));         \
+            __VA_ARGS__;                                                  \
+            *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0];         \
+            *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1];         \
+        }                                                                 \
+        env->vstart = 0;                                                  \
+        /* set tail elements to 1s */                                     \
+        vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);              \
+    }
+
+GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state,
+                                                &round_state,
+                                                &round_key,
+                                                false);)
+GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state,
+                                                &round_state,
+                                                &round_key,
+                                                false);)
+GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state,
+                                                  &round_state,
+                                                  &round_key,
+                                                  false);)
+GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state,
+                                                  &round_state,
+                                                  &round_key,
+                                                  false);)
+GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state,
+                                                   &round_state,
+                                                   &round_key,
+                                                   false);)
+GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state,
+                                                   &round_state,
+                                                   &round_key,
+                                                   false);)
+GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state,
+                                                      &round_state,
+                                                      &round_key,
+                                                      false);)
+GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state,
+                                                      &round_state,
+                                                      &round_key,
+                                                      false);)
+GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);)
+
+void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
+                        CPURISCVState *env, uint32_t desc)
+{
+    uint32_t *vd = vd_vptr;
+    uint32_t *vs2 = vs2_vptr;
+    uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
+    uint32_t vta = vext_vta(desc);
+
+    uimm &= 0b1111;
+    if (uimm > 10 || uimm == 0) {
+        uimm ^= 0b1000;
+    }
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        uint32_t rk[8], tmp;
+        static const uint32_t rcon[] = {
+            0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
+            0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
+        };
+
+        rk[0] = vs2[i * 4 + H4(0)];
+        rk[1] = vs2[i * 4 + H4(1)];
+        rk[2] = vs2[i * 4 + H4(2)];
+        rk[3] = vs2[i * 4 + H4(3)];
+        tmp = ror32(rk[3], 8);
+
+        rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
+                         ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
+                         ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
+                         ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
+                      ^ rcon[uimm - 1];
+        rk[5] = rk[1] ^ rk[4];
+        rk[6] = rk[2] ^ rk[5];
+        rk[7] = rk[3] ^ rk[6];
+
+        vd[i * 4 + H4(0)] = rk[4];
+        vd[i * 4 + H4(1)] = rk[5];
+        vd[i * 4 + H4(2)] = rk[6];
+        vd[i * 4 + H4(3)] = rk[7];
+    }
+    env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
+}
+
+void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
+                        CPURISCVState *env, uint32_t desc)
+{
+    uint32_t *vd = vd_vptr;
+    uint32_t *vs2 = vs2_vptr;
+    uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, 4);
+    uint32_t vta = vext_vta(desc);
+
+    uimm &= 0b1111;
+    if (uimm > 14 || uimm < 2) {
+        uimm ^= 0b1000;
+    }
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        uint32_t rk[12], tmp;
+        static const uint32_t rcon[] = {
+            0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
+            0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
+        };
+
+        rk[0] = vd[i * 4 + H4(0)];
+        rk[1] = vd[i * 4 + H4(1)];
+        rk[2] = vd[i * 4 + H4(2)];
+        rk[3] = vd[i * 4 + H4(3)];
+        rk[4] = vs2[i * 4 + H4(0)];
+        rk[5] = vs2[i * 4 + H4(1)];
+        rk[6] = vs2[i * 4 + H4(2)];
+        rk[7] = vs2[i * 4 + H4(3)];
+
+        if (uimm % 2 == 0) {
+            tmp = ror32(rk[7], 8);
+            rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
+                             ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
+                             ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
+                             ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
+                          ^ rcon[(uimm - 1) / 2];
+        } else {
+            rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) |
+                             ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) |
+                             ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) |
+                             ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0));
+        }
+        rk[9] = rk[1] ^ rk[8];
+        rk[10] = rk[2] ^ rk[9];
+        rk[11] = rk[3] ^ rk[10];
+
+        vd[i * 4 + H4(0)] = rk[8];
+        vd[i * 4 + H4(1)] = rk[9];
+        vd[i * 4 + H4(2)] = rk[10];
+        vd[i * 4 + H4(3)] = rk[11];
+    }
+    env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
+}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
 GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
 GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
 GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
+
+/*
+ * Zvkned
+ */
+
+#define ZVKNED_EGS 4
+
+#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS)                                \
+    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)                  \
+    {                                                                         \
+        if (CHECK(s, a)) {                                                    \
+            TCGv_ptr rd_v, rs2_v;                                             \
+            TCGv_i32 desc, egs;                                               \
+            uint32_t data = 0;                                                \
+            TCGLabel *over = gen_new_label();                                 \
+                                                                              \
+            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
+                /* save opcode for unwinding in case we throw an exception */ \
+                decode_save_opc(s);                                           \
+                egs = tcg_constant_i32(EGS);                                  \
+                gen_helper_egs_check(egs, cpu_env);                           \
+                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
+            }                                                                 \
+                                                                              \
+            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
+            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
+            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
+            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
+            rd_v = tcg_temp_new_ptr();                                        \
+            rs2_v = tcg_temp_new_ptr();                                       \
+            desc = tcg_constant_i32(                                          \
+                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+            tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd));              \
+            tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2));            \
+            gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc);                    \
+            mark_vs_dirty(s);                                                 \
+            gen_set_label(over);                                              \
+            return true;                                                      \
+        }                                                                     \
+        return false;                                                         \
+    }
+
+static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
+{
+    int egw_bytes = ZVKNED_EGS << s->sew;
+    return s->cfg_ptr->ext_zvkned == true &&
+           require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           MAXSZ(s) >= egw_bytes &&
+           require_align(a->rd, s->lmul) &&
+           require_align(a->rs2, s->lmul) &&
+           s->sew == MO_32;
+}
+
+static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
+{
+    int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
+    return !is_overlapped(vd, op_size, vs2, 1);
+}
+
+static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
+{
+    int egw_bytes = ZVKNED_EGS << s->sew;
+    return vaes_check_overlap(s, a->rd, a->rs2) &&
+           MAXSZ(s) >= egw_bytes &&
+           s->cfg_ptr->ext_zvkned == true &&
+           require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           require_align(a->rd, s->lmul) &&
+           s->sew == MO_32;
+}
+
+GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS)
+GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
+
+#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS)                               \
+    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)                  \
+    {                                                                         \
+        if (CHECK(s, a)) {                                                    \
+            TCGv_ptr rd_v, rs2_v;                                             \
+            TCGv_i32 uimm_v, desc, egs;                                       \
+            uint32_t data = 0;                                                \
+            TCGLabel *over = gen_new_label();                                 \
+                                                                              \
+            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
+                /* save opcode for unwinding in case we throw an exception */ \
+                decode_save_opc(s);                                           \
+                egs = tcg_constant_i32(EGS);                                  \
+                gen_helper_egs_check(egs, cpu_env);                           \
+                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
+            }                                                                 \
+                                                                              \
+            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
+            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
+            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
+            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
+                                                                              \
+            rd_v = tcg_temp_new_ptr();                                        \
+            rs2_v = tcg_temp_new_ptr();                                       \
+            uimm_v = tcg_constant_i32(a->rs1);                                \
+            desc = tcg_constant_i32(                                          \
+                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+            tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd));              \
+            tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2));            \
+            gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc);            \
+            mark_vs_dirty(s);                                                 \
+            gen_set_label(over);                                              \
+            return true;                                                      \
+        }                                                                     \
+        return false;                                                         \
+    }
+
+static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
+{
+    int egw_bytes = ZVKNED_EGS << s->sew;
+    return s->cfg_ptr->ext_zvkned == true &&
+           require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           MAXSZ(s) >= egw_bytes &&
+           s->sew == MO_32 &&
+           require_align(a->rd, s->lmul) &&
+           require_align(a->rs2, s->lmul);
+}
+
+static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
+{
+    int egw_bytes = ZVKNED_EGS << s->sew;
+    return s->cfg_ptr->ext_zvkned == true &&
+           require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           MAXSZ(s) >= egw_bytes &&
+           s->sew == MO_32 &&
+           require_align(a->rd, s->lmul) &&
+           require_align(a->rs2, s->lmul);
+}
+
+GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
+GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
-- 
2.41.0

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:

* vsha2ms.vv
* vsha2c[hl].vv

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
[max.chou@sifive.com: Replaced SEW selection to happened during
translation]
Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |   2 +
 target/riscv/helper.h                    |   6 +
 target/riscv/insn32.decode               |   5 +
 target/riscv/cpu.c                       |  13 +-
 target/riscv/vcrypto_helper.c            | 238 +++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++
 6 files changed, 390 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zvbb;
     bool ext_zvbc;
     bool ext_zvkned;
+    bool ext_zvknha;
+    bool ext_zvknhb;
     bool ext_zmmul;
     bool ext_zvfbfmin;
     bool ext_zvfbfwma;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
 DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
 DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
 DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
+
+DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vaesdm_vs   101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
 vaesz_vs    101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
 vaeskf1_vi  100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
 vaeskf2_vi  101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
+
+# *** Zvknh vector crypto extension ***
+vsha2ms_vv  101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
+vsha2ch_vv  101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
+vsha2cl_vv  101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
+    ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
+    ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      * In principle Zve*x would also suffice here, were they supported
      * in qemu
      */
-    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
+    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
+        !cpu->cfg.ext_zve32f) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
     }
 
-    if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
-        error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
+    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
+        error_setg(
+            errp,
+            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
     DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
     DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
+    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
+    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
     /* set tail elements to 1s */
     vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
 }
+
+static inline uint32_t sig0_sha256(uint32_t x)
+{
+    return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3);
+}
+
+static inline uint32_t sig1_sha256(uint32_t x)
+{
+    return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
+}
+
+static inline uint64_t sig0_sha512(uint64_t x)
+{
+    return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7);
+}
+
+static inline uint64_t sig1_sha512(uint64_t x)
+{
+    return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
+}
+
+static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2)
+{
+    uint32_t res[4];
+    res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) +
+             vd[H4(0)];
+    res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) +
+             vd[H4(1)];
+    res[2] =
+        sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(2)];
+    res[3] =
+        sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)];
+    vd[H4(3)] = res[3];
+    vd[H4(2)] = res[2];
+    vd[H4(1)] = res[1];
+    vd[H4(0)] = res[0];
+}
+
+static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2)
+{
+    uint64_t res[4];
+    res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0];
+    res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1];
+    res[2] = sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2];
+    res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3];
+    vd[3] = res[3];
+    vd[2] = res[2];
+    vd[1] = res[1];
+    vd[0] = res[0];
+}
+
+void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+    uint32_t esz = sew == MO_32 ? 4 : 8;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        if (sew == MO_32) {
+            vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4,
+                        ((uint32_t *)vs2) + i * 4);
+        } else {
+            /* If not 32 then SEW should be 64 */
+            vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4,
+                        ((uint64_t *)vs2) + i * 4);
+        }
+    }
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
+
+static inline uint64_t sum0_64(uint64_t x)
+{
+    return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39);
+}
+
+static inline uint32_t sum0_32(uint32_t x)
+{
+    return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22);
+}
+
+static inline uint64_t sum1_64(uint64_t x)
+{
+    return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41);
+}
+
+static inline uint32_t sum1_32(uint32_t x)
+{
+    return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25);
+}
+
+#define ch(x, y, z) ((x & y) ^ ((~x) & z))
+
+#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
+
+static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1)
+{
+    uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0];
+    uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0];
+    uint64_t W0 = vs1[0], W1 = vs1[1];
+    uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0;
+    uint64_t T2 = sum0_64(a) + maj(a, b, c);
+
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    T1 = h + sum1_64(e) + ch(e, f, g) + W1;
+    T2 = sum0_64(a) + maj(a, b, c);
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    vd[0] = f;
+    vd[1] = e;
+    vd[2] = b;
+    vd[3] = a;
+}
+
+static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1)
+{
+    uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)];
+    uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)];
+    uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)];
+    uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0;
+    uint32_t T2 = sum0_32(a) + maj(a, b, c);
+
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    T1 = h + sum1_32(e) + ch(e, f, g) + W1;
+    T2 = sum0_32(a) + maj(a, b, c);
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    vd[H4(0)] = f;
+    vd[H4(1)] = e;
+    vd[H4(2)] = b;
+    vd[H4(3)] = a;
+}
+
+void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                          uint32_t desc)
+{
+    const uint32_t esz = 4;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
+                  ((uint32_t *)vs1) + 4 * i + 2);
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
+
+void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                          uint32_t desc)
+{
+    const uint32_t esz = 8;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
+                  ((uint64_t *)vs1) + 4 * i + 2);
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
+
+void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                          uint32_t desc)
+{
+    const uint32_t esz = 4;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
+                  (((uint32_t *)vs1) + 4 * i));
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
+
+void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                          uint32_t desc)
+{
+    uint32_t esz = 8;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
+                  (((uint64_t *)vs1) + 4 * i));
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
 
 GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
 GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
+
+/*
+ * Zvknh
+ */
+
+#define ZVKNH_EGS 4
+
+#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS)                               \
+    static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
+    {                                                                         \
+        if (CHECK(s, a)) {                                                    \
+            uint32_t data = 0;                                                \
+            TCGLabel *over = gen_new_label();                                 \
+            TCGv_i32 egs;                                                     \
+                                                                              \
+            if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {                      \
+                /* save opcode for unwinding in case we throw an exception */ \
+                decode_save_opc(s);                                           \
+                egs = tcg_constant_i32(EGS);                                  \
+                gen_helper_egs_check(egs, cpu_env);                           \
+                tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);    \
+            }                                                                 \
+                                                                              \
+            data = FIELD_DP32(data, VDATA, VM, a->vm);                        \
+            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                    \
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);                      \
+            data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);    \
+            data = FIELD_DP32(data, VDATA, VMA, s->vma);                      \
+                                                                              \
+            tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),       \
+                               vreg_ofs(s, a->rs2), cpu_env,                  \
+                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,    \
+                               data, gen_helper_##NAME);                      \
+                                                                              \
+            mark_vs_dirty(s);                                                 \
+            gen_set_label(over);                                              \
+            return true;                                                      \
+        }                                                                     \
+        return false;                                                         \
+    }
+
+static bool vsha_check_sew(DisasContext *s)
+{
+    return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) ||
+           (s->cfg_ptr->ext_zvknhb == true &&
+            (s->sew == MO_32 || s->sew == MO_64));
+}
+
+static bool vsha_check(DisasContext *s, arg_rmrr *a)
+{
+    int egw_bytes = ZVKNH_EGS << s->sew;
+    int mult = 1 << MAX(s->lmul, 0);
+    return opivv_check(s, a) &&
+           vsha_check_sew(s) &&
+           MAXSZ(s) >= egw_bytes &&
+           !is_overlapped(a->rd, mult, a->rs1, mult) &&
+           !is_overlapped(a->rd, mult, a->rs2, mult) &&
+           s->lmul >= 0;
+}
+
+GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)
+
+static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
+{
+    if (vsha_check(s, a)) {
+        uint32_t data = 0;
+        TCGLabel *over = gen_new_label();
+        TCGv_i32 egs;
+
+        if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
+            /* save opcode for unwinding in case we throw an exception */
+            decode_save_opc(s);
+            egs = tcg_constant_i32(ZVKNH_EGS);
+            gen_helper_egs_check(egs, cpu_env);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+        }
+
+        data = FIELD_DP32(data, VDATA, VM, a->vm);
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);
+
+        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+            vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
+            s->cfg_ptr->vlen / 8, data,
+            s->sew == MO_32 ?
+                gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
+
+        mark_vs_dirty(s);
+        gen_set_label(over);
+        return true;
+    }
+    return false;
+}
+
+static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
+{
+    if (vsha_check(s, a)) {
+        uint32_t data = 0;
+        TCGLabel *over = gen_new_label();
+        TCGv_i32 egs;
+
+        if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
+            /* save opcode for unwinding in case we throw an exception */
+            decode_save_opc(s);
+            egs = tcg_constant_i32(ZVKNH_EGS);
+            gen_helper_egs_check(egs, cpu_env);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+        }
+
+        data = FIELD_DP32(data, VDATA, VM, a->vm);
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);
+
+        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+            vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
+            s->cfg_ptr->vlen / 8, data,
+            s->sew == MO_32 ?
+                gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
+
+        mark_vs_dirty(s);
+        gen_set_label(over);
+        return true;
+    }
+    return false;
+}
-- 
2.41.0

From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>

This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:

* vsm3me.vv
* vsm3c.vi

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvksh property]
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |   1 +
 target/riscv/helper.h                    |   3 +
 target/riscv/insn32.decode               |   4 +
 target/riscv/cpu.c                       |   6 +-
 target/riscv/vcrypto_helper.c            | 134 +++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc |  31 ++++++
 6 files changed, 177 insertions(+), 2 deletions(-)

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:

* vgmul.vv
* vghsh.vv

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvkg property]
[max.chou@sifive.com: Replaced uint by int for cross win32 build]
Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |  1 +
 target/riscv/helper.h                    |  3 +
 target/riscv/insn32.decode               |  4 ++
 target/riscv/cpu.c                       |  6 +-
 target/riscv/vcrypto_helper.c            | 72 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++
 6 files changed, 114 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

Allows sharing of sm4_subword between different targets.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/crypto/sm4.h           |  8 ++++++++
 target/arm/tcg/crypto_helper.c | 10 ++--------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
index XXXXXXX..XXXXXXX 100644
--- a/include/crypto/sm4.h
+++ b/include/crypto/sm4.h
@@ -XXX,XX +XXX,XX @@
 
 extern const uint8_t sm4_sbox[256];
 
+static inline uint32_t sm4_subword(uint32_t word)
+{
+    return sm4_sbox[word & 0xff] |
+           sm4_sbox[(word >> 8) & 0xff] << 8 |
+           sm4_sbox[(word >> 16) & 0xff] << 16 |
+           sm4_sbox[(word >> 24) & 0xff] << 24;
+}
+
 #endif
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/crypto_helper.c
+++ b/target/arm/tcg/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
             CR_ST_WORD(d, (i + 3) % 4) ^
             CR_ST_WORD(n, i);
 
-        t = sm4_sbox[t & 0xff] |
-            sm4_sbox[(t >> 8) & 0xff] << 8 |
-            sm4_sbox[(t >> 16) & 0xff] << 16 |
-            sm4_sbox[(t >> 24) & 0xff] << 24;
+        t = sm4_subword(t);
 
         CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^
                             rol32(t, 24);
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
             CR_ST_WORD(d, (i + 3) % 4) ^
             CR_ST_WORD(m, i);
 
-        t = sm4_sbox[t & 0xff] |
-            sm4_sbox[(t >> 8) & 0xff] << 8 |
-            sm4_sbox[(t >> 16) & 0xff] << 16 |
-            sm4_sbox[(t >> 24) & 0xff] << 24;
+        t = sm4_subword(t);
 
         CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23);
     }
-- 
2.41.0

From: Max Chou <max.chou@sifive.com>

Adds sm4_ck constant for use in sm4 cryptography across different targets.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/crypto/sm4.h |  1 +
 crypto/sm4.c         | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
index XXXXXXX..XXXXXXX 100644
--- a/include/crypto/sm4.h
+++ b/include/crypto/sm4.h
@@ -XXX,XX +XXX,XX @@
 #define QEMU_SM4_H
 
 extern const uint8_t sm4_sbox[256];
+extern const uint32_t sm4_ck[32];
 
 static inline uint32_t sm4_subword(uint32_t word)
 {
diff --git a/crypto/sm4.c b/crypto/sm4.c
index XXXXXXX..XXXXXXX 100644
--- a/crypto/sm4.c
+++ b/crypto/sm4.c
@@ -XXX,XX +XXX,XX @@ uint8_t const sm4_sbox[] = {
     0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
 };
 
+uint32_t const sm4_ck[] = {
+    0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
+    0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
+    0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
+    0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
+    0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
+    0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
+    0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
+    0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
+};
-- 
2.41.0

From: Max Chou <max.chou@sifive.com>

This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:

* vsm4k.vi
* vsm4r.[vv,vs]

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
[lawrence.hunter@codethink.co.uk: Moved SM4 functions from
crypto_helper.c to vcrypto_helper.c]
[nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
use macros, and minor style changes]
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                   |   1 +
 target/riscv/helper.h                    |   4 +
 target/riscv/insn32.decode               |   5 +
 target/riscv/cpu.c                       |   5 +-
 target/riscv/vcrypto_helper.c            | 127 +++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvvk.c.inc |  43 ++++++++
 6 files changed, 184 insertions(+), 1 deletion(-)

From: Rob Bradford <rbradford@rivosinc.com>

These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.

Tested by modifying OpenSBI to write max value to these CSRs and upon
subsequent read the appropriate number of bits for number of PMUs is
enabled and the TM bit is zero in mcountinhibit.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
 {
     int cidx;
     PMUCTRState *counter;
+    RISCVCPU *cpu = env_archcpu(env);
 
-    env->mcountinhibit = val;
+    /* WARL register - disable unavailable counters; TM bit is always 0 */
+    env->mcountinhibit =
+        val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR);
 
     /* Check if any other counter is also monitoring cycles/instructions */
     for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
                                        target_ulong val)
 {
-    env->mcounteren = val;
+    RISCVCPU *cpu = env_archcpu(env);
+
+    /* WARL register - disable unavailable counters */
+    env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
+                             COUNTEREN_IR);
     return RISCV_EXCP_NONE;
 }
 
-- 
2.41.0

From: Jason Chien <jason.chien@sifive.com>

RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable length of time
in the field.

The chapter 4 of the unprivileged spec introduces the Zihintntl extension
and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose
purpose is to enable application and operating system portability across
different implementations. Thus the DTS should contain the Zihintntl ISA
string in order to pass to software.

The unprivileged spec states:
Like any HINTs, these instructions may be freely ignored. Hence, although
they are described in terms of cache-based memory hierarchies, they do not
mandate the provision of caches.

These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2,
which QEMU already supports, and QEMU does not emulate cache. Therefore
these instructions can be considered as a no-op, and we only need to add
a new property for the Zihintntl extension.

Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Message-ID: <20230726074049.19505-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h | 1 +
 target/riscv/cpu.c     | 2 ++
 2 files changed, 3 insertions(+)

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s
helper function.

Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzfa.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfa.c.inc
@@ -XXX,XX +XXX,XX @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
     TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
 
-    gen_helper_fltq_s(dest, cpu_env, src1, src2);
+    gen_helper_fleq_d(dest, cpu_env, src1, src2);
     gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
     TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
 
-    gen_helper_fltq_s(dest, cpu_env, src1, src2);
+    gen_helper_fltq_d(dest, cpu_env, src1, src2);
     gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
-- 
2.41.0

From: Jason Chien <jason.chien@sifive.com>

When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aclint.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
         return;
     } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
         uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
+        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
 
         if (addr == mtimer->time_base) {
             if (size == 4) {
                 /* time_lo for RV32/RV64 */
-                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
+                mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
             } else {
                 /* time for RV64 */
                 mtimer->time_delta = value - rtc_r;
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
         } else {
             if (size == 4) {
                 /* time_hi for RV32/RV64 */
-                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
+                mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
             } else {
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "aclint-mtimer: invalid time_hi write: %08x",
-- 
2.41.0

From: Jason Chien <jason.chien@sifive.com>

The variables whose values are given by cpu_riscv_read_rtc() should be named
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
should be named "rtc_r".

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aclint.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
     uint64_t next;
     uint64_t diff;
 
-    uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
+    uint64_t rtc = cpu_riscv_read_rtc(mtimer);
 
     /* Compute the relative hartid w.r.t the socket */
     hartid = hartid - mtimer->hartid_base;
 
     mtimer->timecmp[hartid] = value;
-    if (mtimer->timecmp[hartid] <= rtc_r) {
+    if (mtimer->timecmp[hartid] <= rtc) {
         /*
          * If we're setting an MTIMECMP value in the "past",
          * immediately raise the timer interrupt
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
 
     /* otherwise, set up the future timer interrupt */
     qemu_irq_lower(mtimer->timer_irqs[hartid]);
-    diff = mtimer->timecmp[hartid] - rtc_r;
+    diff = mtimer->timecmp[hartid] - rtc;
     /* back to ns (note args switched in muldiv64) */
     uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
 
-- 
2.41.0

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

We should not use types dependend on host arch for target_ucontext.
This bug is found when run rv32 applications.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 linux-user/riscv/signal.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -XXX,XX +XXX,XX @@ struct target_sigcontext {
 }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */
 
 struct target_ucontext {
-    unsigned long uc_flags;
-    struct target_ucontext *uc_link;
+    abi_ulong uc_flags;
+    abi_ptr uc_link;
     target_stack_t uc_stack;
     target_sigset_t uc_sigmask;
     uint8_t   __unused[1024 / 8 - sizeof(target_sigset_t)];
-- 
2.41.0

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 290 +++++++++++++++++++++++-------------------------
 1 file changed, 137 insertions(+), 153 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static uint32_t imsic_num_bits(uint32_t count)
     return ret;
 }
 
-static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
-                             uint32_t *phandle, uint32_t *intc_phandles,
-                             uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
+static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
+                                 uint32_t *intc_phandles, uint32_t msi_phandle,
+                                 bool m_mode, uint32_t imsic_guest_bits)
 {
     int cpu, socket;
     char *imsic_name;
     MachineState *ms = MACHINE(s);
     int socket_count = riscv_socket_count(ms);
-    uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
+    uint32_t imsic_max_hart_per_socket;
     uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
 
-    *msi_m_phandle = (*phandle)++;
-    *msi_s_phandle = (*phandle)++;
     imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
     imsic_regs = g_new0(uint32_t, socket_count * 4);
 
-    /* M-level IMSIC node */
     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+        imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
     }
-    imsic_max_hart_per_socket = 0;
-    for (socket = 0; socket < socket_count; socket++) {
-        imsic_addr = memmap[VIRT_IMSIC_M].base +
-                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
-        imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
-        imsic_regs[socket * 4 + 0] = 0;
-        imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
-        imsic_regs[socket * 4 + 2] = 0;
-        imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
-        if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
-            imsic_max_hart_per_socket = s->soc[socket].num_harts;
-        }
-    }
-    imsic_name = g_strdup_printf("/soc/imsics@%lx",
-        (unsigned long)memmap[VIRT_IMSIC_M].base);
-    qemu_fdt_add_subnode(ms->fdt, imsic_name);
-    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
-        "riscv,imsics");
-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
-        FDT_IMSIC_INT_CELLS);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
-        NULL, 0);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
-        NULL, 0);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
-        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
-        socket_count * sizeof(uint32_t) * 4);
-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
-        VIRT_IRQCHIP_NUM_MSIS);
-    if (socket_count > 1) {
-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
-            imsic_num_bits(imsic_max_hart_per_socket));
-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
-            imsic_num_bits(socket_count));
-        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
-            IMSIC_MMIO_GROUP_MIN_SHIFT);
-    }
-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
-
-    g_free(imsic_name);
 
-    /* S-level IMSIC node */
-    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
-        imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
-    }
-    imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
     imsic_max_hart_per_socket = 0;
     for (socket = 0; socket < socket_count; socket++) {
-        imsic_addr = memmap[VIRT_IMSIC_S].base +
-                     socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+        imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
         imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
                      s->soc[socket].num_harts;
         imsic_regs[socket * 4 + 0] = 0;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
             imsic_max_hart_per_socket = s->soc[socket].num_harts;
         }
     }
-    imsic_name = g_strdup_printf("/soc/imsics@%lx",
-        (unsigned long)memmap[VIRT_IMSIC_S].base);
+
+    imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr);
     qemu_fdt_add_subnode(ms->fdt, imsic_name);
-    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
-        "riscv,imsics");
+    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics");
     qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
-        FDT_IMSIC_INT_CELLS);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
-        NULL, 0);
-    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
-        NULL, 0);
+                          FDT_IMSIC_INT_CELLS);
+    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
     qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
-        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+                     imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
     qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
-        socket_count * sizeof(uint32_t) * 4);
+                     socket_count * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
-        VIRT_IRQCHIP_NUM_MSIS);
+                     VIRT_IRQCHIP_NUM_MSIS);
+
     if (imsic_guest_bits) {
         qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
-            imsic_guest_bits);
+                              imsic_guest_bits);
     }
+
     if (socket_count > 1) {
         qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
-            imsic_num_bits(imsic_max_hart_per_socket));
+                              imsic_num_bits(imsic_max_hart_per_socket));
         qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
-            imsic_num_bits(socket_count));
+                              imsic_num_bits(socket_count));
         qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
-            IMSIC_MMIO_GROUP_MIN_SHIFT);
+                              IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
-    g_free(imsic_name);
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
 
+    g_free(imsic_name);
     g_free(imsic_regs);
     g_free(imsic_cells);
 }
 
-static void create_fdt_socket_aplic(RISCVVirtState *s,
-                                    const MemMapEntry *memmap, int socket,
-                                    uint32_t msi_m_phandle,
-                                    uint32_t msi_s_phandle,
-                                    uint32_t *phandle,
-                                    uint32_t *intc_phandles,
-                                    uint32_t *aplic_phandles)
+static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+                             uint32_t *phandle, uint32_t *intc_phandles,
+                             uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
+{
+    *msi_m_phandle = (*phandle)++;
+    *msi_s_phandle = (*phandle)++;
+
+    if (!kvm_enabled()) {
+        /* M-level IMSIC node */
+        create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles,
+                             *msi_m_phandle, true, 0);
+    }
+
+    /* S-level IMSIC node */
+    create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles,
+                         *msi_s_phandle, false,
+                         imsic_num_bits(s->aia_guests + 1));
+
+}
+
+static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
+                                 unsigned long aplic_addr, uint32_t aplic_size,
+                                 uint32_t msi_phandle,
+                                 uint32_t *intc_phandles,
+                                 uint32_t aplic_phandle,
+                                 uint32_t aplic_child_phandle,
+                                 bool m_mode)
 {
     int cpu;
     char *aplic_name;
     uint32_t *aplic_cells;
-    unsigned long aplic_addr;
     MachineState *ms = MACHINE(s);
-    uint32_t aplic_m_phandle, aplic_s_phandle;
 
-    aplic_m_phandle = (*phandle)++;
-    aplic_s_phandle = (*phandle)++;
     aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
 
-    /* M-level APLIC node */
     for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
         aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+        aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
     }
-    aplic_addr = memmap[VIRT_APLIC_M].base +
-                 (memmap[VIRT_APLIC_M].size * socket);
+
     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
     qemu_fdt_add_subnode(ms->fdt, aplic_name);
     qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
     qemu_fdt_setprop_cell(ms->fdt, aplic_name,
-        "#interrupt-cells", FDT_APLIC_INT_CELLS);
+                          "#interrupt-cells", FDT_APLIC_INT_CELLS);
     qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
+
     if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
         qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
-            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+                         aplic_cells,
+                         s->soc[socket].num_harts * sizeof(uint32_t) * 2);
     } else {
-        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
-            msi_m_phandle);
+        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
     }
+
     qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
-        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
+                           0x0, aplic_addr, 0x0, aplic_size);
     qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
-        VIRT_IRQCHIP_NUM_SOURCES);
-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
-        aplic_s_phandle);
-    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
-        aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
+                          VIRT_IRQCHIP_NUM_SOURCES);
+
+    if (aplic_child_phandle) {
+        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
+                              aplic_child_phandle);
+        qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
+                               aplic_child_phandle, 0x1,
+                               VIRT_IRQCHIP_NUM_SOURCES);
+    }
+
     riscv_socket_fdt_write_id(ms, aplic_name, socket);
-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
+
     g_free(aplic_name);
+    g_free(aplic_cells);
+}
 
-    /* S-level APLIC node */
-    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
-        aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+static void create_fdt_socket_aplic(RISCVVirtState *s,
+                                    const MemMapEntry *memmap, int socket,
+                                    uint32_t msi_m_phandle,
+                                    uint32_t msi_s_phandle,
+                                    uint32_t *phandle,
+                                    uint32_t *intc_phandles,
+                                    uint32_t *aplic_phandles)
+{
+    char *aplic_name;
+    unsigned long aplic_addr;
+    MachineState *ms = MACHINE(s);
+    uint32_t aplic_m_phandle, aplic_s_phandle;
+
+    aplic_m_phandle = (*phandle)++;
+    aplic_s_phandle = (*phandle)++;
+
+    if (!kvm_enabled()) {
+        /* M-level APLIC node */
+        aplic_addr = memmap[VIRT_APLIC_M].base +
+                     (memmap[VIRT_APLIC_M].size * socket);
+        create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
+                             msi_m_phandle, intc_phandles,
+                             aplic_m_phandle, aplic_s_phandle,
+                             true);
     }
+
+    /* S-level APLIC node */
     aplic_addr = memmap[VIRT_APLIC_S].base +
                  (memmap[VIRT_APLIC_S].size * socket);
+    create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
+                         msi_s_phandle, intc_phandles,
+                         aplic_s_phandle, 0,
+                         false);
+
     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
-    qemu_fdt_add_subnode(ms->fdt, aplic_name);
-    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
-    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
-        "#interrupt-cells", FDT_APLIC_INT_CELLS);
-    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
-    if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
-        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
-            aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
-    } else {
-        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
-            msi_s_phandle);
-    }
-    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
-        0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
-        VIRT_IRQCHIP_NUM_SOURCES);
-    riscv_socket_fdt_write_id(ms, aplic_name, socket);
-    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
 
     if (!socket) {
         platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
 
     g_free(aplic_name);
 
-    g_free(aplic_cells);
     aplic_phandles[socket] = aplic_s_phandle;
 }
 
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
     int i;
     hwaddr addr;
     uint32_t guest_bits;
-    DeviceState *aplic_m;
-    bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
+    DeviceState *aplic_s = NULL;
+    DeviceState *aplic_m = NULL;
+    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
 
     if (msimode) {
-        /* Per-socket M-level IMSICs */
-        addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
-        for (i = 0; i < hart_count; i++) {
-            riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
-                               base_hartid + i, true, 1,
-                               VIRT_IRQCHIP_NUM_MSIS);
+        if (!kvm_enabled()) {
+            /* Per-socket M-level IMSICs */
+            addr = memmap[VIRT_IMSIC_M].base +
+                   socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+            for (i = 0; i < hart_count; i++) {
+                riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
+                                   base_hartid + i, true, 1,
+                                   VIRT_IRQCHIP_NUM_MSIS);
+            }
         }
 
         /* Per-socket S-level IMSICs */
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
         }
     }
 
-    /* Per-socket M-level APLIC */
-    aplic_m = riscv_aplic_create(
-        memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
-        memmap[VIRT_APLIC_M].size,
-        (msimode) ? 0 : base_hartid,
-        (msimode) ? 0 : hart_count,
-        VIRT_IRQCHIP_NUM_SOURCES,
-        VIRT_IRQCHIP_NUM_PRIO_BITS,
-        msimode, true, NULL);
-
-    if (aplic_m) {
-        /* Per-socket S-level APLIC */
-        riscv_aplic_create(
-            memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
-            memmap[VIRT_APLIC_S].size,
-            (msimode) ? 0 : base_hartid,
-            (msimode) ? 0 : hart_count,
-            VIRT_IRQCHIP_NUM_SOURCES,
-            VIRT_IRQCHIP_NUM_PRIO_BITS,
-            msimode, false, aplic_m);
+    if (!kvm_enabled()) {
+        /* Per-socket M-level APLIC */
+        aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
+                                     socket * memmap[VIRT_APLIC_M].size,
+                                     memmap[VIRT_APLIC_M].size,
+                                     (msimode) ? 0 : base_hartid,
+                                     (msimode) ? 0 : hart_count,
+                                     VIRT_IRQCHIP_NUM_SOURCES,
+                                     VIRT_IRQCHIP_NUM_PRIO_BITS,
+                                     msimode, true, NULL);
     }
 
-    return aplic_m;
+    /* Per-socket S-level APLIC */
+    aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
+                                 socket * memmap[VIRT_APLIC_S].size,
+                                 memmap[VIRT_APLIC_S].size,
+                                 (msimode) ? 0 : base_hartid,
+                                 (msimode) ? 0 : hart_count,
+                                 VIRT_IRQCHIP_NUM_SOURCES,
+                                 VIRT_IRQCHIP_NUM_PRIO_BITS,
+                                 msimode, false, aplic_m);
+
+    return kvm_enabled() ? aplic_s : aplic_m;
 }
 
 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
-- 
2.41.0

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

We check the in-kernel irqchip support when using KVM acceleration.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
 
 int kvm_arch_irqchip_create(KVMState *s)
 {
-    return 0;
+    if (kvm_kernel_irqchip_split()) {
+        error_report("-machine kernel_irqchip=split is not supported on RISC-V.");
+        exit(1);
+    }
+
+    /*
+     * We can create the VAIA using the newer device control API.
+     */
+    return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
 }
 
 int kvm_arch_process_async_events(CPUState *cs)
-- 
2.41.0

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1) "riscv-aia=emul": IMSIC is emulated by hypervisor
2) "riscv-aia=hwaccel": use hardware guest IMSIC
3) "riscv-aia=auto": use the hardware guest IMSICs whenever available
                     otherwise we fallback to software emulation.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h |   4 +
 target/riscv/kvm.c       | 186 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 190 insertions(+)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 void kvm_riscv_init_user_properties(Object *cpu_obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+                          uint64_t aia_irq_num, uint64_t aia_msi_num,
+                          uint64_t aplic_base, uint64_t imsic_base,
+                          uint64_t guest_num);
 
 #endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "hw/boards.h"
 #include "hw/irq.h"
+#include "hw/intc/riscv_imsic.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char-fe.h"
 #include "migration/migration.h"
 #include "sysemu/runstate.h"
+#include "hw/riscv/numa.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_cpu_check_are_resettable(void)
     return true;
 }
 
+static int aia_mode;
+
+static const char *kvm_aia_mode_str(uint64_t mode)
+{
+    switch (mode) {
+    case KVM_DEV_RISCV_AIA_MODE_EMUL:
+        return "emul";
+    case KVM_DEV_RISCV_AIA_MODE_HWACCEL:
+        return "hwaccel";
+    case KVM_DEV_RISCV_AIA_MODE_AUTO:
+    default:
+        return "auto";
+    };
+}
+
+static char *riscv_get_kvm_aia(Object *obj, Error **errp)
+{
+    return g_strdup(kvm_aia_mode_str(aia_mode));
+}
+
+static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp)
+{
+    if (!strcmp(val, "emul")) {
+        aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL;
+    } else if (!strcmp(val, "hwaccel")) {
+        aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL;
+    } else if (!strcmp(val, "auto")) {
+        aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO;
+    } else {
+        error_setg(errp, "Invalid KVM AIA mode");
+        error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n");
+    }
+}
+
 void kvm_arch_accel_class_init(ObjectClass *oc)
 {
+    object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia,
+                                  riscv_set_kvm_aia);
+    object_class_property_set_description(oc, "riscv-aia",
+                                          "Set KVM AIA mode. Valid values are "
+                                          "emul, hwaccel, and auto. Default "
+                                          "is auto.");
+    object_property_set_default_str(object_class_property_find(oc, "riscv-aia"),
+                                    "auto");
+}
+
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+                          uint64_t aia_irq_num, uint64_t aia_msi_num,
+                          uint64_t aplic_base, uint64_t imsic_base,
+                          uint64_t guest_num)
+{
+    int ret, i;
+    int aia_fd = -1;
+    uint64_t default_aia_mode;
+    uint64_t socket_count = riscv_socket_count(machine);
+    uint64_t max_hart_per_socket = 0;
+    uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr;
+    uint64_t socket_bits, hart_bits, guest_bits;
+
+    aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false);
+
+    if (aia_fd < 0) {
+        error_report("Unable to create in-kernel irqchip");
+        exit(1);
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_MODE,
+                            &default_aia_mode, false, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to get current KVM AIA mode");
+        exit(1);
+    }
+    qemu_log("KVM AIA: default mode is %s\n",
+             kvm_aia_mode_str(default_aia_mode));
+
+    if (default_aia_mode != aia_mode) {
+        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                                KVM_DEV_RISCV_AIA_CONFIG_MODE,
+                                &aia_mode, true, NULL);
+        if (ret < 0)
+            warn_report("KVM AIA: failed to set KVM AIA mode");
+        else
+            qemu_log("KVM AIA: set current mode to %s\n",
+                     kvm_aia_mode_str(aia_mode));
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_SRCS,
+                            &aia_irq_num, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set number of input irq lines");
+        exit(1);
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_IDS,
+                            &aia_msi_num, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set number of msi");
+        exit(1);
+    }
+
+    socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1;
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS,
+                            &socket_bits, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set group_bits");
+        exit(1);
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT,
+                            &group_shift, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set group_shift");
+        exit(1);
+    }
+
+    guest_bits = guest_num == 0 ? 0 :
+                 find_last_bit(&guest_num, BITS_PER_LONG) + 1;
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS,
+                            &guest_bits, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set guest_bits");
+        exit(1);
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+                            KVM_DEV_RISCV_AIA_ADDR_APLIC,
+                            &aplic_base, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set the base address of APLIC");
+        exit(1);
+    }
+
+    for (socket = 0; socket < socket_count; socket++) {
+        socket_imsic_base = imsic_base + socket * (1U << group_shift);
+        hart_count = riscv_socket_hart_count(machine, socket);
+        base_hart = riscv_socket_first_hartid(machine, socket);
+
+        if (max_hart_per_socket < hart_count) {
+            max_hart_per_socket = hart_count;
+        }
+
+        for (i = 0; i < hart_count; i++) {
+            imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits);
+            ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+                                    KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart),
+                                    &imsic_addr, true, NULL);
+            if (ret < 0) {
+                error_report("KVM AIA: failed to set the IMSIC address for hart %d", i);
+                exit(1);
+            }
+        }
+    }
+
+    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                            KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
+                            &hart_bits, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: failed to set hart_bits");
+        exit(1);
+    }
+
+    if (kvm_has_gsi_routing()) {
+        for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) {
+            /* KVM AIA only has one APLIC instance */
+            kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx);
+        }
+        kvm_gsi_routing_allowed = true;
+        kvm_irqchip_commit_routes(kvm_state);
+    }
+
+    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL,
+                            KVM_DEV_RISCV_AIA_CTRL_INIT,
+                            NULL, true, NULL);
+    if (ret < 0) {
+        error_report("KVM AIA: initialized fail");
+        exit(1);
+    }
+
+    kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
-- 
2.41.0

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
when the IMSICs receive mmio write requests.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++-------------
 hw/intc/riscv_imsic.c | 25 +++++++++++++++----
 2 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
 #include "migration/vmstate.h"
 
 #define APLIC_MAX_IDC                  (1UL << 14)
@@ -XXX,XX +XXX,XX @@
 
 #define APLIC_IDC_CLAIMI               0x1c
 
+/*
+ * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
+ * APLIC Wired.
+ */
+static bool is_kvm_aia(bool msimode)
+{
+    return kvm_irqchip_in_kernel() && msimode;
+}
+
 static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
                                             uint32_t word)
 {
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
     return topi;
 }
 
+static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
+{
+    kvm_set_irq(kvm_state, irq, !!level);
+}
+
 static void riscv_aplic_request(void *opaque, int irq, int level)
 {
     bool update = false;
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
     uint32_t i;
     RISCVAPLICState *aplic = RISCV_APLIC(dev);
 
-    aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
-    aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
-    aplic->state = g_new0(uint32_t, aplic->num_irqs);
-    aplic->target = g_new0(uint32_t, aplic->num_irqs);
-    if (!aplic->msimode) {
-        for (i = 0; i < aplic->num_irqs; i++) {
-            aplic->target[i] = 1;
+    if (!is_kvm_aia(aplic->msimode)) {
+        aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
+        aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
+        aplic->state = g_new0(uint32_t, aplic->num_irqs);
+        aplic->target = g_new0(uint32_t, aplic->num_irqs);
+        if (!aplic->msimode) {
+            for (i = 0; i < aplic->num_irqs; i++) {
+                aplic->target[i] = 1;
+            }
         }
-    }
-    aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
-    aplic->iforce = g_new0(uint32_t, aplic->num_harts);
-    aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
+        aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
+        aplic->iforce = g_new0(uint32_t, aplic->num_harts);
+        aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
 
-    memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
-                          TYPE_RISCV_APLIC, aplic->aperture_size);
-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+        memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
+                              aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
+        sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+    }
 
     /*
      * Only root APLICs have hardware IRQ lines. All non-root APLICs
      * have IRQ lines delegated by their parent APLIC.
      */
     if (!aplic->parent) {
-        qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+        if (is_kvm_aia(aplic->msimode)) {
+            qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
+        } else {
+            qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+        }
     }
 
     /* Create output IRQ lines for non-MSI mode */
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "mmode", mmode);
 
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+    if (!is_kvm_aia(msimode)) {
+        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+    }
 
     if (parent) {
         riscv_aplic_add_child(parent, dev);
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "target/riscv/cpu_bits.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
 #include "migration/vmstate.h"
 
 #define IMSIC_MMIO_PAGE_LE             0x00
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
         goto err;
     }
 
+#if defined(CONFIG_KVM)
+    if (kvm_irqchip_in_kernel()) {
+        struct kvm_msi msi;
+
+        msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32);
+        msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32);
+        msi.data = le32_to_cpu(value);
+
+        kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
+
+        return;
+    }
+#endif
+
     /* Writes only supported for MSI little-endian registers */
     page = addr >> IMSIC_MMIO_PAGE_SHIFT;
     if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
     CPUState *cpu = cpu_by_arch_id(imsic->hartid);
     CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 
-    imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
-    imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
-    imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
-    imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
+    if (!kvm_irqchip_in_kernel()) {
+        imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
+        imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
+        imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
+        imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
+    }
 
     memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
                           imsic, TYPE_RISCV_IMSIC,
-- 
2.41.0

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 63 insertions(+), 31 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "kvm_riscv.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/riscv_aplic.h"
 #include "hw/intc/riscv_imsic.h"
@@ -XXX,XX +XXX,XX @@
 #error "Can't accommodate all IMSIC groups in address space"
 #endif
 
+/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
+static bool virt_use_kvm_aia(RISCVVirtState *s)
+{
+    return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
+}
+
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =        {        0x0,         0x100 },
     [VIRT_MROM] =         {     0x1000,        0xf000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
                                  uint32_t *intc_phandles,
                                  uint32_t aplic_phandle,
                                  uint32_t aplic_child_phandle,
-                                 bool m_mode)
+                                 bool m_mode, int num_harts)
 {
     int cpu;
     char *aplic_name;
     uint32_t *aplic_cells;
     MachineState *ms = MACHINE(s);
 
-    aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+    aplic_cells = g_new0(uint32_t, num_harts * 2);
 
-    for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+    for (cpu = 0; cpu < num_harts; cpu++) {
         aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
         aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
 
     if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
         qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
-                         aplic_cells,
-                         s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+                         aplic_cells, num_harts * sizeof(uint32_t) * 2);
     } else {
         qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
                                     uint32_t msi_s_phandle,
                                     uint32_t *phandle,
                                     uint32_t *intc_phandles,
-                                    uint32_t *aplic_phandles)
+                                    uint32_t *aplic_phandles,
+                                    int num_harts)
 {
     char *aplic_name;
     unsigned long aplic_addr;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
         create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
                              msi_m_phandle, intc_phandles,
                              aplic_m_phandle, aplic_s_phandle,
-                             true);
+                             true, num_harts);
     }
 
     /* S-level APLIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
                          msi_s_phandle, intc_phandles,
                          aplic_s_phandle, 0,
-                         false);
+                         false, num_harts);
 
     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         *msi_pcie_phandle = msi_s_phandle;
     }
 
-    phandle_pos = ms->smp.cpus;
-    for (socket = (socket_count - 1); socket >= 0; socket--) {
-        phandle_pos -= s->soc[socket].num_harts;
-
-        if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-            create_fdt_socket_plic(s, memmap, socket, phandle,
-                &intc_phandles[phandle_pos], xplic_phandles);
-        } else {
-            create_fdt_socket_aplic(s, memmap, socket,
-                msi_m_phandle, msi_s_phandle, phandle,
-                &intc_phandles[phandle_pos], xplic_phandles);
+    /* KVM AIA only has one APLIC instance */
+    if (virt_use_kvm_aia(s)) {
+        create_fdt_socket_aplic(s, memmap, 0,
+                                msi_m_phandle, msi_s_phandle, phandle,
+                                &intc_phandles[0], xplic_phandles,
+                                ms->smp.cpus);
+    } else {
+        phandle_pos = ms->smp.cpus;
+        for (socket = (socket_count - 1); socket >= 0; socket--) {
+            phandle_pos -= s->soc[socket].num_harts;
+
+            if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+                create_fdt_socket_plic(s, memmap, socket, phandle,
+                                       &intc_phandles[phandle_pos],
+                                       xplic_phandles);
+            } else {
+                create_fdt_socket_aplic(s, memmap, socket,
+                                        msi_m_phandle, msi_s_phandle, phandle,
+                                        &intc_phandles[phandle_pos],
+                                        xplic_phandles,
+                                        s->soc[socket].num_harts);
+            }
         }
     }
 
     g_free(intc_phandles);
 
-    for (socket = 0; socket < socket_count; socket++) {
-        if (socket == 0) {
-            *irq_mmio_phandle = xplic_phandles[socket];
-            *irq_virtio_phandle = xplic_phandles[socket];
-            *irq_pcie_phandle = xplic_phandles[socket];
-        }
-        if (socket == 1) {
-            *irq_virtio_phandle = xplic_phandles[socket];
-            *irq_pcie_phandle = xplic_phandles[socket];
-        }
-        if (socket == 2) {
-            *irq_pcie_phandle = xplic_phandles[socket];
+    if (virt_use_kvm_aia(s)) {
+        *irq_mmio_phandle = xplic_phandles[0];
+        *irq_virtio_phandle = xplic_phandles[0];
+        *irq_pcie_phandle = xplic_phandles[0];
+    } else {
+        for (socket = 0; socket < socket_count; socket++) {
+            if (socket == 0) {
+                *irq_mmio_phandle = xplic_phandles[socket];
+                *irq_virtio_phandle = xplic_phandles[socket];
+                *irq_pcie_phandle = xplic_phandles[socket];
+            }
+            if (socket == 1) {
+                *irq_virtio_phandle = xplic_phandles[socket];
+                *irq_pcie_phandle = xplic_phandles[socket];
+            }
+            if (socket == 2) {
+                *irq_pcie_phandle = xplic_phandles[socket];
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         }
     }
 
+    if (virt_use_kvm_aia(s)) {
+        kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
+                             VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
+                             memmap[VIRT_APLIC_S].base,
+                             memmap[VIRT_IMSIC_S].base,
+                             s->aia_guests);
+    }
+
     if (riscv_is_32bit(&s->soc[0])) {
 #if HOST_LONG_BITS == 64
         /* limit RAM size in a 32-bit system */
-- 
2.41.0

From: Conor Dooley <conor.dooley@microchip.com>

On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
        from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
That's pretty cryptic, but running the dtb back through dtc produces
something a lot more reasonable:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property

Moving the riscv,pmu node out of the soc bus solves the problem.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s)
     MachineState *ms = MACHINE(s);
     RISCVCPU hart = s->soc[0].harts[0];
 
-    pmu_name = g_strdup_printf("/soc/pmu");
+    pmu_name = g_strdup_printf("/pmu");
     qemu_fdt_add_subnode(ms->fdt, pmu_name);
     qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
     riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
-- 
2.41.0

From: Weiwei Li <liweiwei@iscas.ac.cn>

The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  8 ++++----
 target/riscv/cpu.c        |  4 ++--
 target/riscv/cpu_helper.c |  6 +++---
 target/riscv/csr.c        | 12 ++++++------
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define MENVCFG_CBIE                       (3UL << 4)
 #define MENVCFG_CBCFE                      BIT(6)
 #define MENVCFG_CBZE                       BIT(7)
-#define MENVCFG_HADE                       (1ULL << 61)
+#define MENVCFG_ADUE                       (1ULL << 61)
 #define MENVCFG_PBMTE                      (1ULL << 62)
 #define MENVCFG_STCE                       (1ULL << 63)
 
 /* For RV32 */
-#define MENVCFGH_HADE                      BIT(29)
+#define MENVCFGH_ADUE                      BIT(29)
 #define MENVCFGH_PBMTE                     BIT(30)
 #define MENVCFGH_STCE                      BIT(31)
 
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define HENVCFG_CBIE                       MENVCFG_CBIE
 #define HENVCFG_CBCFE                      MENVCFG_CBCFE
 #define HENVCFG_CBZE                       MENVCFG_CBZE
-#define HENVCFG_HADE                       MENVCFG_HADE
+#define HENVCFG_ADUE                       MENVCFG_ADUE
 #define HENVCFG_PBMTE                      MENVCFG_PBMTE
 #define HENVCFG_STCE                       MENVCFG_STCE
 
 /* For RV32 */
-#define HENVCFGH_HADE                       MENVCFGH_HADE
+#define HENVCFGH_ADUE                       MENVCFGH_ADUE
 #define HENVCFGH_PBMTE                      MENVCFGH_PBMTE
 #define HENVCFGH_STCE                       MENVCFGH_STCE
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
     env->two_stage_lookup = false;
 
     env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
-                   (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
+                   (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
     env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
-                   (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
+                   (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
 
     /* Initialized default priorities of local interrupts. */
     for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     }
 
     bool pbmte = env->menvcfg & MENVCFG_PBMTE;
-    bool hade = env->menvcfg & MENVCFG_HADE;
+    bool adue = env->menvcfg & MENVCFG_ADUE;
 
     if (first_stage && two_stage && env->virt_enabled) {
         pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
-        hade = hade && (env->henvcfg & HENVCFG_HADE);
+        adue = adue && (env->henvcfg & HENVCFG_ADUE);
     }
 
     int ptshift = (levels - 1) * ptidxbits;
@@ -XXX,XX +XXX,XX @@ restart:
 
     /* Page table updates need to be atomic with MTTCG enabled */
     if (updated_pte != pte && !is_debug) {
-        if (!hade) {
+        if (!adue) {
             return TRANSLATE_FAIL;
         }
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
     if (riscv_cpu_mxl(env) == MXL_RV64) {
         mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
                 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
-                (cfg->ext_svadu ? MENVCFG_HADE : 0);
+                (cfg->ext_svadu ? MENVCFG_ADUE : 0);
     }
     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
     const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
-                    (cfg->ext_svadu ? MENVCFG_HADE : 0);
+                    (cfg->ext_svadu ? MENVCFG_ADUE : 0);
     uint64_t valh = (uint64_t)val << 32;
 
     env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
      * henvcfg.stce is read_only 0 when menvcfg.stce = 0
      * henvcfg.hade is read_only 0 when menvcfg.hade = 0
      */
-    *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+    *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
                            env->menvcfg);
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
     }
 
     if (riscv_cpu_mxl(env) == MXL_RV64) {
-        mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
+        mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
     }
 
     env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
         return ret;
     }
 
-    *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+    *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
                             env->menvcfg)) >> 32;
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
     uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
-                                    HENVCFG_HADE);
+                                    HENVCFG_ADUE);
     uint64_t valh = (uint64_t)val << 32;
     RISCVException ret;
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
longer to boot than the 'rv64' KVM CPU.

The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
when satp_mode.supported = 0, i.e. when cpu_init() does not set
satp_mode_max_supported(). satp_mode_max_from_map(map) does:

31 - __builtin_clz(map)

This means that, if satp_mode.supported = 0, satp_mode_supported_max
wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly
set it to UINT_MAX (4294967295). After that, if the user didn't set a
satp_mode, set_satp_mode_default_map(cpu) will make

cfg.satp_mode.map = cfg.satp_mode.supported

So satp_mode.map = 0. And then satp_mode_map_max will be set to
satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The
guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us
here since both are UINT_MAX.

And finally we have 2 loops:

for (int i = satp_mode_map_max - 1; i >= 0; --i) {

Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the
extra delay when booting the 'host' CPU is coming from.

Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0
in a different manner. We're doing the same here. If supported == 0,
interpret as 'the CPU wants the OS to handle satp mode alone' and skip
satp_mode_finalize().

We'll also put a guard in satp_mode_max_from_map() to assert out if map
is 0 since the function is not ready to deal with it.

Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static uint8_t satp_mode_from_str(const char *satp_mode_str)
 
 uint8_t satp_mode_max_from_map(uint32_t map)
 {
+    /*
+     * 'map = 0' will make us return (31 - 32), which C will
+     * happily overflow to UINT_MAX. There's no good result to
+     * return if 'map = 0' (e.g. returning 0 will be ambiguous
+     * with the result for 'map = 1').
+     *
+     * Assert out if map = 0. Callers will have to deal with
+     * it outside of this function.
+     */
+    g_assert(map > 0);
+
     /* map here has at least one bit set, so no problem with clz */
     return 31 - __builtin_clz(map);
 }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
 {
     bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
-    uint8_t satp_mode_map_max;
-    uint8_t satp_mode_supported_max =
-                        satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
+    uint8_t satp_mode_map_max, satp_mode_supported_max;
+
+    /* The CPU wants the OS to decide which satp mode to use */
+    if (cpu->cfg.satp_mode.supported == 0) {
+        return;
+    }
+
+    satp_mode_supported_max =
+                    satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
 
     if (cpu->cfg.satp_mode.map == 0) {
         if (cpu->cfg.satp_mode.init == 0) {
-- 
2.41.0

From: Vineet Gupta <vineetg@rivosinc.com>

zicond is now codegen supported in both llvm and gcc.

This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
     DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 
     /* Vendor-specific custom extensions */
     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
     /* These are experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
 
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

A build with --enable-debug and without KVM will fail as follows:

/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `virt_machine_init':
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia_create'

This happens because the code block with "if virt_use_kvm_aia(s)" isn't
being ignored by the debug build, resulting in an undefined reference to
a KVM only function.

Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will
make the compiler crop the kvm_riscv_aia_create() call entirely from a
non-KVM build. Note that adding the 'kvm_enabled()' conditional inside
virt_use_kvm_aia() won't fix the build because this function would need
to be inlined multiple times to make the compiler zero out the entire
block.

While we're at it, use kvm_enabled() in all instances where
virt_use_kvm_aia() is checked to allow the compiler to elide these other
kvm-only instances as well.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
     }
 
     /* KVM AIA only has one APLIC instance */
-    if (virt_use_kvm_aia(s)) {
+    if (kvm_enabled() && virt_use_kvm_aia(s)) {
         create_fdt_socket_aplic(s, memmap, 0,
                                 msi_m_phandle, msi_s_phandle, phandle,
                                 &intc_phandles[0], xplic_phandles,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 
     g_free(intc_phandles);
 
-    if (virt_use_kvm_aia(s)) {
+    if (kvm_enabled() && virt_use_kvm_aia(s)) {
         *irq_mmio_phandle = xplic_phandles[0];
         *irq_virtio_phandle = xplic_phandles[0];
         *irq_pcie_phandle = xplic_phandles[0];
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         }
     }
 
-    if (virt_use_kvm_aia(s)) {
+    if (kvm_enabled() && virt_use_kvm_aia(s)) {
         kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
                              VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
                              memmap[VIRT_APLIC_S].base,
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:

/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq'
collect2: error: ld returned 1 exit status

This happens because the debug build will poke into the
'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to
the KVM only function riscv_kvm_aplic_request().

There are multiple solutions to fix this. We'll go with the same
solution from the previous patch, i.e. add a kvm_enabled() conditional
to filter out the block. But there's a catch: riscv_kvm_aplic_request()
is a local function that would end up being used if the compiler crops
the block, and this won't work. Quoting Richard Henderson's explanation
in [1]:

"(...) the compiler won't eliminate entire unused functions with -O0"

We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its
declaration in kvm_riscv.h, where all other KVM specific public
functions are already declared. Other archs handles KVM specific code in
this manner and we expect to do the same from now on.

[1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h | 1 +
 hw/intc/riscv_aplic.c    | 8 ++------
 target/riscv/kvm.c       | 5 +++++
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
                           uint64_t aia_irq_num, uint64_t aia_msi_num,
                           uint64_t aplic_base, uint64_t imsic_base,
                           uint64_t guest_num);
+void riscv_kvm_aplic_request(void *opaque, int irq, int level);
 
 #endif
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
+#include "kvm_riscv.h"
 #include "migration/vmstate.h"
 
 #define APLIC_MAX_IDC                  (1UL << 14)
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
     return topi;
 }
 
-static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
-{
-    kvm_set_irq(kvm_state, irq, !!level);
-}
-
 static void riscv_aplic_request(void *opaque, int irq, int level)
 {
     bool update = false;
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
      * have IRQ lines delegated by their parent APLIC.
      */
     if (!aplic->parent) {
-        if (is_kvm_aia(aplic->msimode)) {
+        if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
         } else {
             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/runstate.h"
 #include "hw/riscv/numa.h"
 
+void riscv_kvm_aplic_request(void *opaque, int irq, int level)
+{
+    kvm_set_irq(kvm_state, irq, !!level);
+}
+
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
 {
-- 
2.41.0

From: Robbin Ehn <rehn@rivosinc.com>

This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.

And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.

Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 linux-user/syscall.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
 #define RISCV_HWPROBE_KEY_IMA_EXT_0     4
 #define     RISCV_HWPROBE_IMA_FD       (1 << 0)
 #define     RISCV_HWPROBE_IMA_C        (1 << 1)
+#define     RISCV_HWPROBE_IMA_V        (1 << 2)
+#define     RISCV_HWPROBE_EXT_ZBA      (1 << 3)
+#define     RISCV_HWPROBE_EXT_ZBB      (1 << 4)
+#define     RISCV_HWPROBE_EXT_ZBS      (1 << 5)
 
 #define RISCV_HWPROBE_KEY_CPUPERF_0     5
 #define     RISCV_HWPROBE_MISALIGNED_UNKNOWN     (0 << 0)
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
                     riscv_has_ext(env, RVD) ?
                     RISCV_HWPROBE_IMA_FD : 0;
             value |= riscv_has_ext(env, RVC) ?
-                     RISCV_HWPROBE_IMA_C : pair->value;
+                     RISCV_HWPROBE_IMA_C : 0;
+            value |= riscv_has_ext(env, RVV) ?
+                     RISCV_HWPROBE_IMA_V : 0;
+            value |= cfg->ext_zba ?
+                     RISCV_HWPROBE_EXT_ZBA : 0;
+            value |= cfg->ext_zbb ?
+                     RISCV_HWPROBE_EXT_ZBB : 0;
+            value |= cfg->ext_zbs ?
+                     RISCV_HWPROBE_EXT_ZBS : 0;
             __put_user(value, &pair->value);
             break;
         case RISCV_HWPROBE_KEY_CPUPERF_0:
-- 
2.41.0

From: Ard Biesheuvel <ardb@kernel.org>

Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/crypto_helper.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
 
     uint8_t enc_rnum = rnum;
     uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
-    uint8_t rcon_ = 0;
-    target_ulong result;
+    AESState t, rc = {};
 
     if (enc_rnum != 0xA) {
         temp = ror32(temp, 8); /* Rotate right by 8 */
-        rcon_ = round_consts[enc_rnum];
+        rc.w[0] = rc.w[1] = round_consts[enc_rnum];
     }
 
-    temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
-           ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
-           ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
-           ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+    t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp;
+    aesenc_SB_SR_AK(&t, &t, &rc, false);
 
-    temp ^= rcon_;
-
-    result = ((uint64_t)temp << 32) | temp;
-
-    return result;
+    return t.d[0];
 }
 
 target_ulong HELPER(aes64im)(target_ulong rs1)
-- 
2.41.0

From: Akihiko Odaki <akihiko.odaki@daynix.com>

riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.

Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().

Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.h |  3 ++-
 target/riscv/cpu.c   |  8 +++++++-
 target/riscv/debug.c | 15 ++++++++++++---
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
 bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 
-void riscv_trigger_init(CPURISCVState *env);
+void riscv_trigger_realize(CPURISCVState *env);
+void riscv_trigger_reset_hold(CPURISCVState *env);
 
 bool riscv_itrigger_enabled(CPURISCVState *env);
 void riscv_itrigger_update_priv(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.debug) {
-        riscv_trigger_init(env);
+        riscv_trigger_reset_hold(env);
     }
 
     if (kvm_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     riscv_cpu_register_gdb_regs_for_features(cs);
 
+#ifndef CONFIG_USER_ONLY
+    if (cpu->cfg.debug) {
+        riscv_trigger_realize(&cpu->env);
+    }
+#endif
+
     qemu_init_vcpu(cs);
     cpu_reset(cs);
 
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
     return false;
 }
 
-void riscv_trigger_init(CPURISCVState *env)
+void riscv_trigger_realize(CPURISCVState *env)
+{
+    int i;
+
+    for (i = 0; i < RV_MAX_TRIGGERS; i++) {
+        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                                              riscv_itrigger_timer_cb, env);
+    }
+}
+
+void riscv_trigger_reset_hold(CPURISCVState *env)
 {
     target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
     int i;
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
         env->tdata3[i] = 0;
         env->cpu_breakpoint[i] = NULL;
         env->cpu_watchpoint[i] = NULL;
-        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
-                                              riscv_itrigger_timer_cb, env);
+        timer_del(env->itrigger_timer[i]);
     }
 }
-- 
2.41.0

From: Leon Schuermann <leons@opentitan.org>

When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes work even on locked regions when the global rule-lock bypass is
enabled.

Signed-off-by: Leon Schuermann <leons@opentitan.org>
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
  */
 static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
 {
+    /* mseccfg.RLB is set */
+    if (MSECCFG_RLB_ISSET(env)) {
+        return 0;
+    }
 
     if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
         return 1;
-- 
2.41.0

From: Tommy Wu <tommy.wu@sifive.com>

According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.

Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int rmw_iprio(target_ulong xlen,
 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
                      target_ulong new_val, target_ulong wr_mask)
 {
-    bool virt;
+    bool virt, isel_reserved;
     uint8_t *iprio;
     int ret = -EINVAL;
     target_ulong priv, isel, vgein;
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
 
     /* Decode register details from CSR number */
     virt = false;
+    isel_reserved = false;
     switch (csrno) {
     case CSR_MIREG:
         iprio = env->miprio;
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
                                                   riscv_cpu_mxl_bits(env)),
                                     val, new_val, wr_mask);
         }
+    } else {
+        isel_reserved = true;
     }
 
 done:
     if (ret) {
-        return (env->virt_enabled && virt) ?
+        return (env->virt_enabled && virt && !isel_reserved) ?
                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
     }
     return RISCV_EXCP_NONE;
-- 
2.41.0

From: Nikita Shubin <n.shubin@yadro.com>

As per ISA:

"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."

trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
                                        target_ulong write_mask)
 {
     RISCVException ret;
-    target_ulong old_value;
+    target_ulong old_value = 0;
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
     }
 
-    /* if no accessor exists then return failure */
-    if (!csr_ops[csrno].read) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-    /* read old value */
-    ret = csr_ops[csrno].read(env, csrno, &old_value);
-    if (ret != RISCV_EXCP_NONE) {
-        return ret;
+    /*
+     * ret_value == NULL means that rd=x0 and we're coming from helper_csrw()
+     * and we can't throw side effects caused by CSR reads.
+     */
+    if (ret_value) {
+        /* if no accessor exists then return failure */
+        if (!csr_ops[csrno].read) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+        /* read old value */
+        ret = csr_ops[csrno].read(env, csrno, &old_value);
+        if (ret != RISCV_EXCP_NONE) {
+            return ret;
+        }
     }
 
     /* write value if writable and write mask set, otherwise drop writes */
-- 
2.41.0