1. Patchew
  2. QEMU
  3. [PATCH v11 0/4] PMU-EBB support for PPC64 TCG
  4. View patch

[PATCH v11 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c

Daniel Henrique Barboza posted 4 patches 3 years, 12 months ago
There is a newer version of this series
[PATCH v11 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c
Posted by Daniel Henrique Barboza 3 years, 12 months ago 
This patch adds the EBB exception support that are triggered by
Performance Monitor alerts. This happens when a Performance Monitor
alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.

fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that
will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are
set, do_ebb() will attempt to trigger a PERFM EBB event.

If the EBB facility is enabled in both FSCR and HFSCR we consider that
the EBB is valid and set BESCR_PMEO. After that, if we're running in
problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll
queue a PPC_INTERRUPT_EBB.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++
 target/ppc/helper.h      |  1 +
 target/ppc/power8-pmu.c  |  3 +--
 3 files changed, 50 insertions(+), 2 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ad40a0f8e6..0c031e67b1 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1948,6 +1948,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
         env->spr[SPR_BESCR] &= ~BESCR_GE;
     }
 }
+
+/*
+ * Triggers or queues an 'ebb_excp' EBB exception. All checks
+ * but FSCR, HFSCR and msr_pr must be done beforehand.
+ *
+ * PowerISA v3.1 isn't clear about whether an EBB should be
+ * postponed or cancelled if the EBB facility is unavailable.
+ * Our assumption here is that the EBB is cancelled if both
+ * FSCR and HFSCR EBB facilities aren't available.
+ */
+static void do_ebb(CPUPPCState *env, int ebb_excp)
+{
+    PowerPCCPU *cpu = env_archcpu(env);
+    CPUState *cs = CPU(cpu);
+
+    /*
+     * FSCR_EBB and FSCR_IC_EBB are the same bits used with
+     * HFSCR.
+     */
+    helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB);
+    helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB);
+
+    if (ebb_excp == POWERPC_EXCP_PERFM_EBB) {
+        env->spr[SPR_BESCR] |= BESCR_PMEO;
+    } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) {
+        env->spr[SPR_BESCR] |= BESCR_EEO;
+    }
+
+    if (msr_pr == 1) {
+        powerpc_excp(cpu, ebb_excp);
+    } else {
+        env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
+        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+    }
+}
+
+void helper_ebb_perfm_excp(CPUPPCState *env)
+{
+    bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE &&
+                             env->spr[SPR_BESCR] & BESCR_PME &&
+                             env->spr[SPR_BESCR] & BESCR_GE;
+
+    if (!perfm_ebb_enabled) {
+        return;
+    }
+
+    do_ebb(env, POWERPC_EXCP_PERFM_EBB);
+}
 #endif
 
 /*****************************************************************************/
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f2e5060910..adc31235a8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -19,6 +19,7 @@ DEF_HELPER_1(rfid, void, env)
 DEF_HELPER_1(rfscv, void, env)
 DEF_HELPER_1(hrfid, void, env)
 DEF_HELPER_2(rfebb, void, env, tl)
+DEF_HELPER_1(ebb_perfm_excp, void, env)
 DEF_HELPER_2(store_lpcr, void, env, tl)
 DEF_HELPER_2(store_pcr, void, env, tl)
 DEF_HELPER_2(store_mmcr0, void, env, tl)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index d245663158..38e1ecb782 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
         env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
     }
 
-    /* PMC interrupt not implemented yet */
-    return;
+    helper_ebb_perfm_excp(env);
 }
 
 /* This helper assumes that the PMC is running. */
-- 
2.34.1
Re: [PATCH v11 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c
Posted by Cédric Le Goater 3 years, 11 months ago 
On 2/11/22 19:33, Daniel Henrique Barboza wrote:
> This patch adds the EBB exception support that are triggered by
> Performance Monitor alerts. This happens when a Performance Monitor
> alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
> 
> fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that
> will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are
> set, do_ebb() will attempt to trigger a PERFM EBB event.
> 
> If the EBB facility is enabled in both FSCR and HFSCR we consider that
> the EBB is valid and set BESCR_PMEO. After that, if we're running in
> problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll
> queue a PPC_INTERRUPT_EBB.
> 
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>

Looks good. One comment below.


> ---
>   target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++
>   target/ppc/helper.h      |  1 +
>   target/ppc/power8-pmu.c  |  3 +--
>   3 files changed, 50 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index ad40a0f8e6..0c031e67b1 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1948,6 +1948,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
>           env->spr[SPR_BESCR] &= ~BESCR_GE;
>       }
>   }
> +
> +/*
> + * Triggers or queues an 'ebb_excp' EBB exception. All checks
> + * but FSCR, HFSCR and msr_pr must be done beforehand.
> + *
> + * PowerISA v3.1 isn't clear about whether an EBB should be
> + * postponed or cancelled if the EBB facility is unavailable.
> + * Our assumption here is that the EBB is cancelled if both
> + * FSCR and HFSCR EBB facilities aren't available.
> + */
> +static void do_ebb(CPUPPCState *env, int ebb_excp)
> +{
> +    PowerPCCPU *cpu = env_archcpu(env);
> +    CPUState *cs = CPU(cpu);
> +
> +    /*
> +     * FSCR_EBB and FSCR_IC_EBB are the same bits used with
> +     * HFSCR.
> +     */
> +    helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB);
> +    helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB);
> +
> +    if (ebb_excp == POWERPC_EXCP_PERFM_EBB) {
> +        env->spr[SPR_BESCR] |= BESCR_PMEO;
> +    } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) {
> +        env->spr[SPR_BESCR] |= BESCR_EEO;
> +    }
> +
> +    if (msr_pr == 1) {
> +        powerpc_excp(cpu, ebb_excp);
> +    } else {
> +        env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
> +        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> +    }

Don't you need to lock the iothread ?

Thanks,

C.

> +}
> +
> +void helper_ebb_perfm_excp(CPUPPCState *env)
> +{
> +    bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE &&
> +                             env->spr[SPR_BESCR] & BESCR_PME &&
> +                             env->spr[SPR_BESCR] & BESCR_GE;
> +
> +    if (!perfm_ebb_enabled) {
> +        return;
> +    }
> +
> +    do_ebb(env, POWERPC_EXCP_PERFM_EBB);
> +}
>   #endif
>   
>   /*****************************************************************************/
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index f2e5060910..adc31235a8 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -19,6 +19,7 @@ DEF_HELPER_1(rfid, void, env)
>   DEF_HELPER_1(rfscv, void, env)
>   DEF_HELPER_1(hrfid, void, env)
>   DEF_HELPER_2(rfebb, void, env, tl)
> +DEF_HELPER_1(ebb_perfm_excp, void, env)
>   DEF_HELPER_2(store_lpcr, void, env, tl)
>   DEF_HELPER_2(store_pcr, void, env, tl)
>   DEF_HELPER_2(store_mmcr0, void, env, tl)
> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
> index d245663158..38e1ecb782 100644
> --- a/target/ppc/power8-pmu.c
> +++ b/target/ppc/power8-pmu.c
> @@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
>           env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
>       }
>   
> -    /* PMC interrupt not implemented yet */
> -    return;
> +    helper_ebb_perfm_excp(env);
>   }
>   
>   /* This helper assumes that the PMC is running. */
Re: [PATCH v11 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c
Posted by Daniel Henrique Barboza 3 years, 11 months ago 

On 2/15/22 13:37, Cédric Le Goater wrote:
> On 2/11/22 19:33, Daniel Henrique Barboza wrote:
>> This patch adds the EBB exception support that are triggered by
>> Performance Monitor alerts. This happens when a Performance Monitor
>> alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
>>
>> fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that
>> will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are
>> set, do_ebb() will attempt to trigger a PERFM EBB event.
>>
>> If the EBB facility is enabled in both FSCR and HFSCR we consider that
>> the EBB is valid and set BESCR_PMEO. After that, if we're running in
>> problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll
>> queue a PPC_INTERRUPT_EBB.
>>
>> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> 
> Looks good. One comment below.
> 
> 
>> ---
>>   target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++
>>   target/ppc/helper.h      |  1 +
>>   target/ppc/power8-pmu.c  |  3 +--
>>   3 files changed, 50 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index ad40a0f8e6..0c031e67b1 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -1948,6 +1948,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
>>           env->spr[SPR_BESCR] &= ~BESCR_GE;
>>       }
>>   }
>> +
>> +/*
>> + * Triggers or queues an 'ebb_excp' EBB exception. All checks
>> + * but FSCR, HFSCR and msr_pr must be done beforehand.
>> + *
>> + * PowerISA v3.1 isn't clear about whether an EBB should be
>> + * postponed or cancelled if the EBB facility is unavailable.
>> + * Our assumption here is that the EBB is cancelled if both
>> + * FSCR and HFSCR EBB facilities aren't available.
>> + */
>> +static void do_ebb(CPUPPCState *env, int ebb_excp)
>> +{
>> +    PowerPCCPU *cpu = env_archcpu(env);
>> +    CPUState *cs = CPU(cpu);
>> +
>> +    /*
>> +     * FSCR_EBB and FSCR_IC_EBB are the same bits used with
>> +     * HFSCR.
>> +     */
>> +    helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB);
>> +    helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB);
>> +
>> +    if (ebb_excp == POWERPC_EXCP_PERFM_EBB) {
>> +        env->spr[SPR_BESCR] |= BESCR_PMEO;
>> +    } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) {
>> +        env->spr[SPR_BESCR] |= BESCR_EEO;
>> +    }
>> +
>> +    if (msr_pr == 1) {
>> +        powerpc_excp(cpu, ebb_excp);
>> +    } else {
>> +        env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
>> +        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
>> +    }
> 
> Don't you need to lock the iothread ?

I did in the previous version but now, after doing the msr_pr handling like I'm doing
here, handling BQL wasn't necessary. I suppose this change in the logic handled the
race condition in a way that the lock isn't being exercised as before.


Thanks,


Daniel

> 
> Thanks,
> 
> C.
> 
>> +}
>> +
>> +void helper_ebb_perfm_excp(CPUPPCState *env)
>> +{
>> +    bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE &&
>> +                             env->spr[SPR_BESCR] & BESCR_PME &&
>> +                             env->spr[SPR_BESCR] & BESCR_GE;
>> +
>> +    if (!perfm_ebb_enabled) {
>> +        return;
>> +    }
>> +
>> +    do_ebb(env, POWERPC_EXCP_PERFM_EBB);
>> +}
>>   #endif
>>   /*****************************************************************************/
>> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
>> index f2e5060910..adc31235a8 100644
>> --- a/target/ppc/helper.h
>> +++ b/target/ppc/helper.h
>> @@ -19,6 +19,7 @@ DEF_HELPER_1(rfid, void, env)
>>   DEF_HELPER_1(rfscv, void, env)
>>   DEF_HELPER_1(hrfid, void, env)
>>   DEF_HELPER_2(rfebb, void, env, tl)
>> +DEF_HELPER_1(ebb_perfm_excp, void, env)
>>   DEF_HELPER_2(store_lpcr, void, env, tl)
>>   DEF_HELPER_2(store_pcr, void, env, tl)
>>   DEF_HELPER_2(store_mmcr0, void, env, tl)
>> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
>> index d245663158..38e1ecb782 100644
>> --- a/target/ppc/power8-pmu.c
>> +++ b/target/ppc/power8-pmu.c
>> @@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
>>           env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
>>       }
>> -    /* PMC interrupt not implemented yet */
>> -    return;
>> +    helper_ebb_perfm_excp(env);
>>   }
>>   /* This helper assumes that the PMC is running. */
>

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.