PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
exception and External EBB exception. They are being added as
POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
occurred and trigger the appropriate exception. Both exceptions are
doing the same thing in this first implementation: clear BESCR_GE and
enter the branch with env->nip retrieved from SPR_EBBHR.
The checks being done by the interrupt code are msr_pr and BESCR_GE
states. All other checks (EBB facility check, BESCR_PME bit, specific
bits related to the event type) must be done beforehand.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 5 ++++-
target/ppc/cpu_init.c | 4 ++++
target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index dcd83b503c..3962c8f6f4 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -129,8 +129,10 @@ enum {
/* ISA 3.00 additions */
POWERPC_EXCP_HVIRT = 101,
POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
+ POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
+ POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
/* EOL */
- POWERPC_EXCP_NB = 103,
+ POWERPC_EXCP_NB = 105,
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
@@ -2453,6 +2455,7 @@ enum {
PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
+ PPC_INTERRUPT_EBB, /* Event-based Branch exception */
};
/* Processor Compatibility mask (PCR) */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index bf60529d37..136d8ca8b5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2336,6 +2336,10 @@ static void init_excp_POWER8(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
+
+ /* Userland exceptions without vector value in PowerISA v3.1 */
+ env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
#endif
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8a49a4ab90..ad40a0f8e6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -990,6 +990,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
+ case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
+ case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
+ env->spr[SPR_BESCR] &= ~BESCR_GE;
+
+ /*
+ * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
+ * stored in the EBB Handler SPR_EBBHR.
+ */
+ env->spr[SPR_EBBRR] = env->nip;
+ powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
+
+ /*
+ * This exception is handled in userspace. No need to proceed.
+ */
+ return;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
@@ -1681,6 +1696,24 @@ static void ppc_hw_interrupt(CPUPPCState *env)
powerpc_excp(cpu, POWERPC_EXCP_THERM);
return;
}
+ /* EBB exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) {
+ /*
+ * EBB exception must be taken in problem state and
+ * with BESCR_GE set.
+ */
+ if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
+
+ if (env->spr[SPR_BESCR] & BESCR_PMEO) {
+ powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB);
+ } else if (env->spr[SPR_BESCR] & BESCR_EEO) {
+ powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB);
+ }
+
+ return;
+ }
+ }
}
if (env->resume_as_sreset) {
--
2.34.1
On 2/11/22 19:33, Daniel Henrique Barboza wrote:
> PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
> exceptions that had to be postponed because the thread wasn't in problem
> state at the time the event-based branch was supposed to occur.
>
> ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
> exception and External EBB exception. They are being added as
> POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
>
> PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
> occurred and trigger the appropriate exception. Both exceptions are
> doing the same thing in this first implementation: clear BESCR_GE and
> enter the branch with env->nip retrieved from SPR_EBBHR.
>
> The checks being done by the interrupt code are msr_pr and BESCR_GE
> states. All other checks (EBB facility check, BESCR_PME bit, specific
> bits related to the event type) must be done beforehand.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
It looks correct.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Next step is to modify the POWER9 input pins and these routines :
xive_tctx_realize()
xive_tctx_output()
power9_set_irq()
to add an EBB "wire" between the IC and the CPU.
Thanks,
C.
> ---
> target/ppc/cpu.h | 5 ++++-
> target/ppc/cpu_init.c | 4 ++++
> target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++
> 3 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index dcd83b503c..3962c8f6f4 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -129,8 +129,10 @@ enum {
> /* ISA 3.00 additions */
> POWERPC_EXCP_HVIRT = 101,
> POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
> + POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
> + POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
> /* EOL */
> - POWERPC_EXCP_NB = 103,
> + POWERPC_EXCP_NB = 105,
> /* QEMU exceptions: special cases we want to stop translation */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
> };
> @@ -2453,6 +2455,7 @@ enum {
> PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
> PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
> PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
> + PPC_INTERRUPT_EBB, /* Event-based Branch exception */
> };
>
> /* Processor Compatibility mask (PCR) */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index bf60529d37..136d8ca8b5 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2336,6 +2336,10 @@ static void init_excp_POWER8(CPUPPCState *env)
> env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
> env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
> env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
> +
> + /* Userland exceptions without vector value in PowerISA v3.1 */
> + env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
> + env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
> #endif
> }
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 8a49a4ab90..ad40a0f8e6 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -990,6 +990,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> break;
> + case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
> + case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
> + env->spr[SPR_BESCR] &= ~BESCR_GE;
> +
> + /*
> + * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
> + * stored in the EBB Handler SPR_EBBHR.
> + */
> + env->spr[SPR_EBBRR] = env->nip;
> + powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
> +
> + /*
> + * This exception is handled in userspace. No need to proceed.
> + */
> + return;
> case POWERPC_EXCP_THERM: /* Thermal interrupt */
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> case POWERPC_EXCP_VPUA: /* Vector assist exception */
> @@ -1681,6 +1696,24 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> powerpc_excp(cpu, POWERPC_EXCP_THERM);
> return;
> }
> + /* EBB exception */
> + if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) {
> + /*
> + * EBB exception must be taken in problem state and
> + * with BESCR_GE set.
> + */
> + if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
> + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
> +
> + if (env->spr[SPR_BESCR] & BESCR_PMEO) {
> + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB);
> + } else if (env->spr[SPR_BESCR] & BESCR_EEO) {
> + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB);
> + }
> +
> + return;
> + }
> + }
> }
>
> if (env->resume_as_sreset) {
>
On 2/14/22 14:34, Cédric Le Goater wrote:
> On 2/11/22 19:33, Daniel Henrique Barboza wrote:
>> PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
>> exceptions that had to be postponed because the thread wasn't in problem
>> state at the time the event-based branch was supposed to occur.
>>
>> ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
>> exception and External EBB exception. They are being added as
>> POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
>>
>> PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
>> occurred and trigger the appropriate exception. Both exceptions are
>> doing the same thing in this first implementation: clear BESCR_GE and
>> enter the branch with env->nip retrieved from SPR_EBBHR.
>>
>> The checks being done by the interrupt code are msr_pr and BESCR_GE
>> states. All other checks (EBB facility check, BESCR_PME bit, specific
>> bits related to the event type) must be done beforehand.
>>
>> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>
> It looks correct.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> Next step is to modify the POWER9 input pins and these routines :
>
> xive_tctx_realize()
> xive_tctx_output()
> power9_set_irq()
>
> to add an EBB "wire" between the IC and the CPU.
Got it. I'll see if I can get this EBB lane up from the IC and CPU. Any suggestions how I
should test it?
Thanks,
Daniel
>
> Thanks,
>
> C.
>
>
>> ---
>> target/ppc/cpu.h | 5 ++++-
>> target/ppc/cpu_init.c | 4 ++++
>> target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++
>> 3 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index dcd83b503c..3962c8f6f4 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -129,8 +129,10 @@ enum {
>> /* ISA 3.00 additions */
>> POWERPC_EXCP_HVIRT = 101,
>> POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
>> + POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
>> + POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
>> /* EOL */
>> - POWERPC_EXCP_NB = 103,
>> + POWERPC_EXCP_NB = 105,
>> /* QEMU exceptions: special cases we want to stop translation */
>> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
>> };
>> @@ -2453,6 +2455,7 @@ enum {
>> PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
>> PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
>> PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
>> + PPC_INTERRUPT_EBB, /* Event-based Branch exception */
>> };
>> /* Processor Compatibility mask (PCR) */
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index bf60529d37..136d8ca8b5 100644
>> --- a/target/ppc/cpu_init.c
>> +++ b/target/ppc/cpu_init.c
>> @@ -2336,6 +2336,10 @@ static void init_excp_POWER8(CPUPPCState *env)
>> env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
>> env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
>> env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
>> +
>> + /* Userland exceptions without vector value in PowerISA v3.1 */
>> + env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
>> + env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
>> #endif
>> }
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 8a49a4ab90..ad40a0f8e6 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -990,6 +990,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>> new_msr |= (target_ulong)MSR_HVB;
>> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
>> break;
>> + case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
>> + case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
>> + env->spr[SPR_BESCR] &= ~BESCR_GE;
>> +
>> + /*
>> + * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
>> + * stored in the EBB Handler SPR_EBBHR.
>> + */
>> + env->spr[SPR_EBBRR] = env->nip;
>> + powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
>> +
>> + /*
>> + * This exception is handled in userspace. No need to proceed.
>> + */
>> + return;
>> case POWERPC_EXCP_THERM: /* Thermal interrupt */
>> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
>> case POWERPC_EXCP_VPUA: /* Vector assist exception */
>> @@ -1681,6 +1696,24 @@ static void ppc_hw_interrupt(CPUPPCState *env)
>> powerpc_excp(cpu, POWERPC_EXCP_THERM);
>> return;
>> }
>> + /* EBB exception */
>> + if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) {
>> + /*
>> + * EBB exception must be taken in problem state and
>> + * with BESCR_GE set.
>> + */
>> + if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
>> + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
>> +
>> + if (env->spr[SPR_BESCR] & BESCR_PMEO) {
>> + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB);
>> + } else if (env->spr[SPR_BESCR] & BESCR_EEO) {
>> + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB);
>> + }
>> +
>> + return;
>> + }
>> + }
>> }
>> if (env->resume_as_sreset) {
>>
>
On 2/14/22 18:52, Daniel Henrique Barboza wrote: > > > On 2/14/22 14:34, Cédric Le Goater wrote: >> On 2/11/22 19:33, Daniel Henrique Barboza wrote: >>> PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB >>> exceptions that had to be postponed because the thread wasn't in problem >>> state at the time the event-based branch was supposed to occur. >>> >>> ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB >>> exception and External EBB exception. They are being added as >>> POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. >>> >>> PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that >>> occurred and trigger the appropriate exception. Both exceptions are >>> doing the same thing in this first implementation: clear BESCR_GE and >>> enter the branch with env->nip retrieved from SPR_EBBHR. >>> >>> The checks being done by the interrupt code are msr_pr and BESCR_GE >>> states. All other checks (EBB facility check, BESCR_PME bit, specific >>> bits related to the event type) must be done beforehand. >>> >>> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> >> >> It looks correct. >> >> Reviewed-by: Cédric Le Goater <clg@kaod.org> >> >> Next step is to modify the POWER9 input pins and these routines : >> >> xive_tctx_realize() >> xive_tctx_output() >> power9_set_irq() >> >> to add an EBB "wire" between the IC and the CPU. > > Got it. I'll see if I can get this EBB lane up from the IC and CPU. > Any suggestions how I should test it? Without a software stack configuring the IC and handling the EBB, you can not. C.
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