Guest code on highbank may make non-PSCI SMC calls in order to
enable/disable the L2x0 cache controller (see the Linux kernel's
arch/arm/mach-highbank/highbank.c highbank_l2c310_write_sec()
function).  The ABI for this is documented in kernel commit
8e56130dcb as being borrowed from the OMAP44xx ROM.  The OMAP44xx TRM
documents this function ID as having no return value and potentially
trashing all guest registers except SP and PC. For QEMU's purposes
(where our L2x0 model is a stub and enabling or disabling it doesn't
affect the guest behaviour) a simple "do nothing" SMC is fine.

We currently implement this NOP behaviour using a little bit of
Secure code we run before jumping to the guest kernel, which is
written by arm_write_secure_board_setup_dummy_smc().  The code sets
up a set of Secure vectors where the SMC entry point returns without
doing anything.

Now that the PSCI SMC emulation handles all SMC calls (setting r0 to
an error code if the input r0 function identifier is not recognized),
we can use that default behaviour as sufficient for the highbank
cache controller call.  (Because the guest code assumes r0 has no
interesting value on exit it doesn't matter that we set it to the
error code).  We can therefore delete the highbank board code that
sets secure_board_setup to true and writes the secure-code bootstub.

(Note that because the OMAP44xx ABI puts function-identifiers in
r12 and PSCI uses r0, we only avoid a clash because Linux's code
happens to put the function-identifier in both registers. But this
is true also when the kernel is running on real firmware that
implements both ABIs as far as I can see.)

This change fixes in passing booting on the 'midway' board model,
which has been completely broken since we added support for Hyp
mode to the Cortex-A15 CPU. When we did that boot.c was made to
start running the guest code in Hyp mode; this includes the
board_setup hook, which instantly UNDEFs because the NSACR is
not accessible from Hyp. (Put another way, we never made the
secure_board_setup hook support cope with Hyp mode.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/highbank.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 048f8550cb9..a21afd178d1 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -48,12 +48,6 @@
 
 /* Board init.  */
 
-static void hb_write_board_setup(ARMCPU *cpu,
-                                 const struct arm_boot_info *info)
-{
-    arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
-}
-
 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     int n;
@@ -389,8 +383,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
     highbank_binfo.write_secondary_boot = hb_write_secondary;
     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
     highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
-    highbank_binfo.write_board_setup = hb_write_board_setup;
-    highbank_binfo.secure_board_setup = true;
     highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
 
     arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
-- 
2.25.1

On 1/28/22 02:46, Peter Maydell wrote:
> Guest code on highbank may make non-PSCI SMC calls in order to
> enable/disable the L2x0 cache controller (see the Linux kernel's
> arch/arm/mach-highbank/highbank.c highbank_l2c310_write_sec()
> function).  The ABI for this is documented in kernel commit
> 8e56130dcb as being borrowed from the OMAP44xx ROM.  The OMAP44xx TRM
> documents this function ID as having no return value and potentially
> trashing all guest registers except SP and PC. For QEMU's purposes
> (where our L2x0 model is a stub and enabling or disabling it doesn't
> affect the guest behaviour) a simple "do nothing" SMC is fine.
> 
> We currently implement this NOP behaviour using a little bit of
> Secure code we run before jumping to the guest kernel, which is
> written by arm_write_secure_board_setup_dummy_smc().  The code sets
> up a set of Secure vectors where the SMC entry point returns without
> doing anything.
> 
> Now that the PSCI SMC emulation handles all SMC calls (setting r0 to
> an error code if the input r0 function identifier is not recognized),
> we can use that default behaviour as sufficient for the highbank
> cache controller call.  (Because the guest code assumes r0 has no
> interesting value on exit it doesn't matter that we set it to the
> error code).  We can therefore delete the highbank board code that
> sets secure_board_setup to true and writes the secure-code bootstub.
> 
> (Note that because the OMAP44xx ABI puts function-identifiers in
> r12 and PSCI uses r0, we only avoid a clash because Linux's code
> happens to put the function-identifier in both registers. But this
> is true also when the kernel is running on real firmware that
> implements both ABIs as far as I can see.)
> 
> This change fixes in passing booting on the 'midway' board model,
> which has been completely broken since we added support for Hyp
> mode to the Cortex-A15 CPU. When we did that boot.c was made to
> start running the guest code in Hyp mode; this includes the
> board_setup hook, which instantly UNDEFs because the NSACR is
> not accessible from Hyp. (Put another way, we never made the
> secure_board_setup hook support cope with Hyp mode.)
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   hw/arm/highbank.c | 8 --------
>   1 file changed, 8 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~