On Tue, Jan 25, 2022 at 3:33 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
>
> Specification:
> https://github.com/riscv/virtual-memory/tree/main/specs
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v6
>
> To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
>
> This implementation can pass the riscv-tests for rv64ssvnapot.
>
> v6:
> * select ppn mask base on sxl
>
> v5:
> * merge patch https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
> * relax pte attribute check
>
> v4:
> * fix encodings for hinval_vvma and hinval_gvma
> * partition inner PTE check into several steps
> * improve commit messages to describe changes
>
> v3:
> * drop "x-" in exposed properties
>
> v2:
> * add extension check for svnapot and svpbmt
>
> Guo Ren (1):
> target/riscv: Ignore reserved bits in PTE for RV64
>
> Weiwei Li (4):
> target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
> target/riscv: add support for svnapot extension
> target/riscv: add support for svinval extension
> target/riscv: add support for svpbmt extension
>
> target/riscv/cpu.c | 4 ++
> target/riscv/cpu.h | 14 ++++
> target/riscv/cpu_bits.h | 10 +++
> target/riscv/cpu_helper.c | 34 +++++++++-
> target/riscv/insn32.decode | 7 ++
> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 7 files changed, 142 insertions(+), 3 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> --
> 2.17.1
>
>
Tested-by: Guo Ren <guoren@kernel.org>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/