target/riscv/cpu.c | 3 +-- target/riscv/gdbstub.c | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-)
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
---
target/riscv/cpu.c | 3 +--
target/riscv/gdbstub.c | 3 +++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1cb0436187..5ada71e5bf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -528,10 +528,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
switch (env->misa_mxl_max) {
#ifdef TARGET_RISCV64
case MXL_RV64:
+ case MXL_RV128:
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break;
- case MXL_RV128:
- break;
#endif
case MXL_RV32:
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f531a74c2f..9ed049c29e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64:
+ case MXL_RV128:
return gdb_get_reg64(mem_buf, tmp);
default:
g_assert_not_reached();
@@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
length = 4;
break;
case MXL_RV64:
+ case MXL_RV128:
if (env->xl < MXL_RV64) {
tmp = (int32_t)ldq_p(mem_buf);
} else {
@@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
1, "riscv-32bit-virtual.xml", 0);
break;
case MXL_RV64:
+ case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
--
2.34.1
On 24/1/22 21:24, Frédéric Pétrot wrote: > The addition of uxl support in gdbstub adds a few checks on the maximum > register length, but omitted MXL_RV128, an experimental feature. > This patch makes rv128 react as rv64, as previously. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> > --- > target/riscv/cpu.c | 3 +-- > target/riscv/gdbstub.c | 3 +++ > 2 files changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On 2022/1/25 04:24, Frédéric Pétrot wrote: > The addition of uxl support in gdbstub adds a few checks on the maximum > register length, but omitted MXL_RV128, an experimental feature. > This patch makes rv128 react as rv64, as previously. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Thanks, Zhiwei > --- > target/riscv/cpu.c | 3 +-- > target/riscv/gdbstub.c | 3 +++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1cb0436187..5ada71e5bf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -528,10 +528,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > switch (env->misa_mxl_max) { > #ifdef TARGET_RISCV64 > case MXL_RV64: > + case MXL_RV128: > cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > break; > - case MXL_RV128: > - break; > #endif > case MXL_RV32: > cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index f531a74c2f..9ed049c29e 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > case MXL_RV32: > return gdb_get_reg32(mem_buf, tmp); > case MXL_RV64: > + case MXL_RV128: > return gdb_get_reg64(mem_buf, tmp); > default: > g_assert_not_reached(); > @@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > length = 4; > break; > case MXL_RV64: > + case MXL_RV128: > if (env->xl < MXL_RV64) { > tmp = (int32_t)ldq_p(mem_buf); > } else { > @@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > 1, "riscv-32bit-virtual.xml", 0); > break; > case MXL_RV64: > + case MXL_RV128: > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > riscv_gdb_set_virtual, > 1, "riscv-64bit-virtual.xml", 0);
On Tue, Jan 25, 2022 at 6:35 AM Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> wrote: > > The addition of uxl support in gdbstub adds a few checks on the maximum > register length, but omitted MXL_RV128, an experimental feature. > This patch makes rv128 react as rv64, as previously. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 3 +-- > target/riscv/gdbstub.c | 3 +++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1cb0436187..5ada71e5bf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -528,10 +528,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > switch (env->misa_mxl_max) { > #ifdef TARGET_RISCV64 > case MXL_RV64: > + case MXL_RV128: > cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > break; > - case MXL_RV128: > - break; > #endif > case MXL_RV32: > cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index f531a74c2f..9ed049c29e 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > case MXL_RV32: > return gdb_get_reg32(mem_buf, tmp); > case MXL_RV64: > + case MXL_RV128: > return gdb_get_reg64(mem_buf, tmp); > default: > g_assert_not_reached(); > @@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > length = 4; > break; > case MXL_RV64: > + case MXL_RV128: > if (env->xl < MXL_RV64) { > tmp = (int32_t)ldq_p(mem_buf); > } else { > @@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > 1, "riscv-32bit-virtual.xml", 0); > break; > case MXL_RV64: > + case MXL_RV128: > gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > riscv_gdb_set_virtual, > 1, "riscv-64bit-virtual.xml", 0); > -- > 2.34.1 > >
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