[PATCH 0/7] AMX support in Qemu

Yang Zhong posted 7 patches 2 years, 3 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220124075523.108875-1-yang.zhong@intel.com
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, "Michael S. Tsirkin" <mst@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, Cornelia Huck <cohuck@redhat.com>
There is a newer version of this series
linux-headers/asm-x86/kvm.h | 14 ++++++
linux-headers/linux/kvm.h   |  2 +
target/i386/cpu.h           | 46 +++++++++++++++++-
target/i386/cpu.c           | 96 +++++++++++++++++++++++++++++++++++--
target/i386/kvm/kvm-cpu.c   | 12 +++--
target/i386/kvm/kvm.c       | 69 +++++++++++++++++++-------
target/i386/machine.c       | 42 ++++++++++++++++
target/i386/xsave_helper.c  | 35 ++++++++++++++
8 files changed, 291 insertions(+), 25 deletions(-)
[PATCH 0/7] AMX support in Qemu
Posted by Yang Zhong 2 years, 3 months ago
Intel introduces Advanced Matrix Extensions (AMX) [1] feature that
consists of configurable two-dimensional "TILE" registers and new
accelerator instructions that operate on them. TMUL (Tile matrix
MULtiply) is the first accelerator instruction set to use the new
registers.

Since AMX KVM patches have been merged into Linux release, this series
is based on latest Linux release.

According to the KVM design, the userspace VMM (e.g. Qemu) is expected
to request guest permission for the dynamically-enabled XSAVE features
only once when the first vCPU is created, and KVM checks guest permission
in KVM_SET_CPUID2.

Intel AMX is XSAVE supported and XSAVE enabled. Those extended features
has large state while current kvm_xsave only allows 4KB. The AMX KVM has
extended struct kvm_xsave to meet this requirenment and added one extra
KVM_GET_XSAVE2 ioctl to handle extended features. From our test, the AMX
live migration work well.

Notice: This version still includes some definitions in the linux-headers,
once Qemu sync those linux-headers, I will remove those definitions. So
please ignore those changes.

[1] Intel Architecture Instruction Set Extension Programming Reference
    https://software.intel.com/content/dam/develop/external/us/en/documents/\
    architecture-instruction-set-extensions-programming-reference.pdf

Thanks,
Yang
----

change history
--------------
rfc v1->v1:
   - Patch 1 changed commit message(Kevin and Paolo).
   - Patch 2 changed commit message(Kevin and Paolo).
   - Patch 3, below requirements from Paolo,
     - Called ARCH_REQ_XCOMP_GUEST_PERM from x86_cpu_enable_xsave_components.
       Used kvm_request_xsave_components() to replace x86_xsave_req_perm().
       Replaced syscall(ARCH_GET_XCOMP_GUEST_PERM) with kvm_arch_get_supported_cpuid()
       in kvm_request_xsave_components().
     - Changed kvm_cpu_xsave_init() to use host_cpuid() instead of
       kvm_arch_get_supported_cpuid().
     - Added the "function == 0xd" handle in kvm_arch_get_supported_cpuid().   
   - Patch 4, used "uint32_t ecx" to replace "uint32_t need_align, support_xfd".
   - Patch 6, below changes,
     - Changed the commit message(Kevin) and Used the new function
     - kvm_init_xsave() to replace some pieces of code(Wei).
     - Moved KVM_CAP_XSAVE2 extension check to kvm_arch_init_vcpu() to
       make the request permission before KVM_CAP_XSAVE2 extension check(Paolo).
   - Removed RFC prefix.

Jing Liu (5):
  x86: Fix the 64-byte boundary enumeration for extended state
  x86: Add AMX XTILECFG and XTILEDATA components
  x86: Add XFD faulting bit for state components
  x86: Add AMX CPUIDs enumeration
  x86: add support for KVM_CAP_XSAVE2 and AMX state migration

Yang Zhong (1):
  x86: Grant AMX permission for guest

Zeng Guang (1):
  x86: Support XFD and AMX xsave data migration

 linux-headers/asm-x86/kvm.h | 14 ++++++
 linux-headers/linux/kvm.h   |  2 +
 target/i386/cpu.h           | 46 +++++++++++++++++-
 target/i386/cpu.c           | 96 +++++++++++++++++++++++++++++++++++--
 target/i386/kvm/kvm-cpu.c   | 12 +++--
 target/i386/kvm/kvm.c       | 69 +++++++++++++++++++-------
 target/i386/machine.c       | 42 ++++++++++++++++
 target/i386/xsave_helper.c  | 35 ++++++++++++++
 8 files changed, 291 insertions(+), 25 deletions(-)


Re: [PATCH 0/7] AMX support in Qemu
Posted by Paolo Bonzini 2 years, 3 months ago
On 1/24/22 08:55, Yang Zhong wrote:
> Intel introduces Advanced Matrix Extensions (AMX) [1] feature that
> consists of configurable two-dimensional "TILE" registers and new
> accelerator instructions that operate on them. TMUL (Tile matrix
> MULtiply) is the first accelerator instruction set to use the new
> registers.
> 
> Since AMX KVM patches have been merged into Linux release, this series
> is based on latest Linux release.
> 
> According to the KVM design, the userspace VMM (e.g. Qemu) is expected
> to request guest permission for the dynamically-enabled XSAVE features
> only once when the first vCPU is created, and KVM checks guest permission
> in KVM_SET_CPUID2.
> 
> Intel AMX is XSAVE supported and XSAVE enabled. Those extended features
> has large state while current kvm_xsave only allows 4KB. The AMX KVM has
> extended struct kvm_xsave to meet this requirenment and added one extra
> KVM_GET_XSAVE2 ioctl to handle extended features. From our test, the AMX
> live migration work well.
> 
> Notice: This version still includes some definitions in the linux-headers,
> once Qemu sync those linux-headers, I will remove those definitions. So
> please ignore those changes.

Yes, no problem with that.

I think the KVM API is insufficient and needs a small but important 
extra feature, equivalent to ARCH_GET_XCOMP_SUPP.  We can implement that 
easily in 5.17 though.

Paolo

> [1] Intel Architecture Instruction Set Extension Programming Reference
>      https://software.intel.com/content/dam/develop/external/us/en/documents/\
>      architecture-instruction-set-extensions-programming-reference.pdf