Series comparison

-[PULL 00/61] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20 16:13:17 +0000)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Third RISC-V PR for QEMU 7.0
+RISC-V PR for 9.1
- * Fixes for OpenTitan timer
+* APLICs add child earlier than realize
- * Correction of OpenTitan PLIC stride length
+* Fix exposure of Zkr
- * RISC-V KVM support
+* Raise exceptions on wrs.nto
- * Device tree code cleanup
+* Implement SBI debug console (DBCN) calls for KVM
- * Support for the Zve64f and Zve32f extensions
+* Support 64-bit addresses for initrd
- * OpenSBI binary loading support for the Spike machine
+* Change RISCV_EXCP_SEMIHOST exception number to 63
- * Removal of OpenSBI ELFs
+* Tolerate KVM disable ext errors
- * Support for the UXL field in xstatus
+* Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Anup Patel (3):
+Alexei Filippov (1):
-      hw/riscv: spike: Allow using binary firmware as bios
+      target/riscv: do not set mtval2 for non guest-page faults
       hw/riscv: Remove macros for ELF BIOS image names
       roms/opensbi: Remove ELF images
-Frank Chang (17):
+Alistair Francis (2):
-      target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      target/riscv: rvv-1.0: Add Zve64f support for configuration insns
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       target/riscv: rvv-1.0: Add Zve64f support for load and store insns
       target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
       target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
       target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
       target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
       target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
       target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
       target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
       target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
       target/riscv: rvv-1.0: Add Zve32f support for configuration insns
       target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
       target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
       target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
       target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
       target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
-LIU Zhiwei (23):
+Andrew Jones (2):
-      target/riscv: Adjust pmpcfg access with mxl
+      target/riscv/kvm: Fix exposure of Zkr
-      target/riscv: Don't save pc when exception return
+      target/riscv: Raise exceptions on wrs.nto
       target/riscv: Sign extend link reg for jal and jalr
       target/riscv: Sign extend pc for different XLEN
       target/riscv: Create xl field in env
       target/riscv: Ignore the pc bits above XLEN
       target/riscv: Extend pc for runtime pc write
       target/riscv: Use gdb xml according to max mxlen
       target/riscv: Relax debug check for pm write
       target/riscv: Adjust csr write mask with XLEN
       target/riscv: Create current pm fields in env
       target/riscv: Alloc tcg global for cur_pm[mask|base]
       target/riscv: Calculate address according to XLEN
       target/riscv: Split pm_enabled into mask and base
       target/riscv: Split out the vill from vtype
       target/riscv: Adjust vsetvl according to XLEN
       target/riscv: Remove VILL field in VTYPE
       target/riscv: Fix check range for first fault only
       target/riscv: Adjust vector address with mask
       target/riscv: Adjust scalar reg in vector with XLEN
       target/riscv: Set default XLEN for hypervisor
       target/riscv: Enable uxl field write
       target/riscv: Relax UXL field for debugging
-Thomas Huth (1):
+Cheng Yang (1):
-      softmmu/device_tree: Silence compiler warning with --enable-sanitizers
+      hw/riscv/boot.c: Support 64-bit address for initrd
-Wilfred Mallawa (3):
+Christoph Müllner (1):
-      hw: timer: ibex_timer: Fixup reading w/o register
+      riscv: thead: Add th.sxstatus CSR emulation
       riscv: opentitan: fixup plic stride len
       hw: timer: ibex_timer: update/add reg address
-Yanan Wang (1):
+Clément Léger (1):
-      softmmu/device_tree: Remove redundant pointer assignment
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-Yifei Jiang (13):
+Daniel Henrique Barboza (6):
-      update-linux-headers: Add asm-riscv/kvm.h
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
-      target/riscv: Add target/riscv/kvm.c to place the public kvm interface
+      target/riscv/kvm: tolerate KVM disable ext errors
-      target/riscv: Implement function kvm_arch_init_vcpu
+      target/riscv/debug: set tval=pc in breakpoint exceptions
-      target/riscv: Implement kvm_arch_get_registers
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
-      target/riscv: Implement kvm_arch_put_registers
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
-      target/riscv: Support start kernel directly by KVM
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
       target/riscv: Support setting external interrupt by KVM
       target/riscv: Handle KVM_EXIT_RISCV_SBI exit
       target/riscv: Add host cpu type
       target/riscv: Add kvm_riscv_get/put_regs_timer
       target/riscv: Implement virtual time adjusting with vm state changing
       target/riscv: Support virtual time context synchronization
       target/riscv: enable riscv kvm accel
- meson.build                                    |   2 +
+Huang Tao (2):
- include/hw/char/riscv_htif.h                   |   5 +-
+      target/riscv: Fix the element agnostic function problem
- include/hw/riscv/boot.h                        |   3 +-
+      target/riscv: Implement dynamic establishment of custom decoder
- include/hw/riscv/spike.h                       |   1 +
- include/hw/timer/ibex_timer.h                  |   1 -
+Jason Chien (3):
- linux-headers/asm-riscv/kvm.h                  | 128 ++++++
+      target/riscv: Add support for Zve32x extension
- target/riscv/cpu.h                             |  58 ++-
+      target/riscv: Add support for Zve64x extension
- target/riscv/cpu_bits.h                        |   3 +
+      target/riscv: Relax vector register check in RISCV gdbstub
- target/riscv/helper.h                          |   4 +-
- target/riscv/kvm_riscv.h                       |  25 ++
+Max Chou (4):
- target/riscv/sbi_ecall_interface.h             |  72 ++++
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
- hw/char/riscv_htif.c                           |  33 +-
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
- hw/intc/sifive_plic.c                          |  20 +-
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
- hw/riscv/boot.c                                |  16 +-
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
- hw/riscv/opentitan.c                           |   2 +-
- hw/riscv/spike.c                               |  45 ++-
+Rob Bradford (1):
- hw/riscv/virt.c                                |  83 ++--
+      target/riscv: Remove experimental prefix from "B" extension
- hw/timer/ibex_timer.c                          |  25 +-
- softmmu/device_tree.c                          |  11 +-
+Yangyu Chen (1):
- target/riscv/cpu.c                             |  77 +++-
+      target/riscv/cpu.c: fix Zvkb extension config
- target/riscv/cpu_helper.c                      |  99 ++---
- target/riscv/csr.c                             |  90 ++++-
+Yong-Xuan Wang (1):
- target/riscv/gdbstub.c                         |  71 +++-
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
- target/riscv/kvm-stub.c                        |  30 ++
- target/riscv/kvm.c                             | 535 +++++++++++++++++++++++++
+Yu-Ming Chang (1):
- target/riscv/machine.c                         |  46 ++-
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
- target/riscv/op_helper.c                       |   7 +-
- target/riscv/pmp.c                             |  12 +-
+yang.zhang (1):
- target/riscv/translate.c                       |  94 +++--
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
- target/riscv/vector_helper.c                   |  39 +-
- target/riscv/insn_trans/trans_privileged.c.inc |   9 +-
+ MAINTAINERS                                    |   1 +
- target/riscv/insn_trans/trans_rva.c.inc        |   9 +-
+ target/riscv/cpu.h                             |  11 ++
- target/riscv/insn_trans/trans_rvd.c.inc        |  19 +-
+ target/riscv/cpu_bits.h                        |   2 +-
- target/riscv/insn_trans/trans_rvf.c.inc        |  19 +-
+ target/riscv/cpu_cfg.h                         |   2 +
- target/riscv/insn_trans/trans_rvi.c.inc        |  39 +-
+ target/riscv/helper.h                          |   1 +
- target/riscv/insn_trans/trans_rvv.c.inc        | 225 +++++++++--
+ target/riscv/sbi_ecall_interface.h             |  17 +++
- .gitlab-ci.d/opensbi.yml                       |   2 -
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
- pc-bios/meson.build                            |   2 -
+ disas/riscv.c                                  |  65 +++++++++-
- pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
+ hw/intc/riscv_aplic.c                          |   8 +-
- pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
+ hw/riscv/boot.c                                |   4 +-
- roms/Makefile                                  |   2 -
+ target/riscv/cpu.c                             |  10 +-
  target/riscv/cpu_helper.c                      |  37 +++---
  target/riscv/csr.c                             |  71 +++++++++--
  target/riscv/debug.c                           |   3 +
  target/riscv/gdbstub.c                         |   8 +-
  target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
  target/riscv/op_helper.c                       |  17 ++-
  target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
  target/riscv/th_csr.c                          |  79 +++++++++++++
  target/riscv/translate.c                       |  31 +++--
  target/riscv/vector_internals.c                |  22 ++++
  target/riscv/insn_trans/trans_privileged.c.inc |   2 +
  target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
  target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
  target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
  target/riscv/meson.build                       |   1 +
-files changed, 1608 insertions(+), 356 deletions(-)
+files changed, 596 insertions(+), 109 deletions(-)
- create mode 100644 linux-headers/asm-riscv/kvm.h
+ create mode 100644 target/riscv/th_csr.c
  create mode 100644 target/riscv/kvm_riscv.h
  create mode 100644 target/riscv/sbi_ecall_interface.h
  create mode 100644 target/riscv/kvm-stub.c
  create mode 100644 target/riscv/kvm.c
  delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
  delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

-[PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register
+Deleted patch
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-This change fixes a bug where a write only register is read.
-As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
-the 'INTR_TEST0' register is write only.
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/timer/ibex_timer.h |  1 -
- hw/timer/ibex_timer.c         | 14 +++++---------
-files changed, 5 insertions(+), 10 deletions(-)
-diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/ibex_timer.h
-+++ b/include/hw/timer/ibex_timer.h
-@@ -XXX,XX +XXX,XX @@ struct IbexTimerState {
-     uint32_t timer_compare_upper0;
-     uint32_t timer_intr_enable;
-     uint32_t timer_intr_state;
--    uint32_t timer_intr_test;
-     uint32_t timebase_freq;
-diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/ibex_timer.c
-+++ b/hw/timer/ibex_timer.c
-@@ -XXX,XX +XXX,XX @@ static void ibex_timer_reset(DeviceState *dev)
-     s->timer_compare_upper0 = 0xFFFFFFFF;
-     s->timer_intr_enable = 0x00000000;
-     s->timer_intr_state = 0x00000000;
--    s->timer_intr_test = 0x00000000;
-     ibex_timer_update_irqs(s);
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
-         retvalue = s->timer_intr_state;
-         break;
-     case R_INTR_TEST:
--        retvalue = s->timer_intr_test;
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "Attempted to read INTR_TEST, a write only register");
-         break;
-     default:
-         qemu_log_mask(LOG_GUEST_ERROR,
-@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
-         s->timer_intr_state &= ~val;
-         break;
-     case R_INTR_TEST:
--        s->timer_intr_test = val;
--        if (s->timer_intr_enable &
--            s->timer_intr_test &
--            R_INTR_ENABLE_IE_0_MASK) {
-+        if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
-             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
-             qemu_set_irq(s->irq, true);
-         }
-@@ -XXX,XX +XXX,XX @@ static int ibex_timer_post_load(void *opaque, int version_id)
- static const VMStateDescription vmstate_ibex_timer = {
-     .name = TYPE_IBEX_TIMER,
--    .version_id = 1,
--    .minimum_version_id = 1,
-+    .version_id = 2,
-+    .minimum_version_id = 2,
-     .post_load = ibex_timer_post_load,
-     .fields = (VMStateField[]) {
-         VMSTATE_UINT32(timer_ctrl, IbexTimerState),
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ibex_timer = {
-         VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
-         VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
-         VMSTATE_UINT32(timer_intr_state, IbexTimerState),
--        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
-         VMSTATE_END_OF_LIST()
-     }
- };
---
-.31.1

-[PULL 02/61] riscv: opentitan: fixup plic stride len
+Deleted patch
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-The following change was made to rectify incorrectly set stride length
-on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
-discovered whilst attempting to fix a bug where a timer_interrupt was
-not serviced on TockOS-OpenTitan.
-[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Tested-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/opentitan.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/opentitan.c
-+++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-     qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
-     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
-     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
--    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
-     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
-     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
-     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
---
-.31.1

-[PULL 03/61] hw: timer: ibex_timer: update/add reg address
+Deleted patch
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-The following changes:
-. Fixes the incorrectly set CTRL register address. As
-per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
-The CTRL register is @ 0x04.
-This was found when attempting to fixup a bug where a timer_interrupt
-was not serviced on TockOS-OpenTitan.
-. Adds ALERT_TEST register as documented on [1], adding repective
-   switch cases to error handle and later implement functionality.
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Tested-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/timer/ibex_timer.c | 11 ++++++++++-
-file changed, 10 insertions(+), 1 deletion(-)
-diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/ibex_timer.c
-+++ b/hw/timer/ibex_timer.c
-@@ -XXX,XX +XXX,XX @@
- #include "target/riscv/cpu.h"
- #include "migration/vmstate.h"
--REG32(CTRL, 0x00)
-+REG32(ALERT_TEST, 0x00)
-+    FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
-+REG32(CTRL, 0x04)
-     FIELD(CTRL, ACTIVE, 0, 1)
- REG32(CFG0, 0x100)
-     FIELD(CFG0, PRESCALE, 0, 12)
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
-     uint64_t retvalue = 0;
-     switch (addr >> 2) {
-+    case R_ALERT_TEST:
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                        "Attempted to read ALERT_TEST, a write only register");
-+        break;
-     case R_CTRL:
-         retvalue = s->timer_ctrl;
-         break;
-@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
-     uint32_t val = val64;
-     switch (addr >> 2) {
-+    case R_ALERT_TEST:
-+        qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
-+        break;
-     case R_CTRL:
-         s->timer_ctrl = val;
-         break;
---
-.31.1

-[PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Add asm-riscv/kvm.h for RISC-V KVM.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-2-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- linux-headers/asm-riscv/kvm.h | 128 ++++++++++++++++++++++++++++++++++
-file changed, 128 insertions(+)
- create mode 100644 linux-headers/asm-riscv/kvm.h
-diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/linux-headers/asm-riscv/kvm.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-+/*
-+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
-+ *
-+ * Authors:
-+ *     Anup Patel <anup.patel@wdc.com>
-+ */
-+
-+#ifndef __LINUX_KVM_RISCV_H
-+#define __LINUX_KVM_RISCV_H
-+
-+#ifndef __ASSEMBLY__
-+
-+#include <linux/types.h>
-+#include <asm/ptrace.h>
-+
-+#define __KVM_HAVE_READONLY_MEM
-+
-+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
-+
-+#define KVM_INTERRUPT_SET    -1U
-+#define KVM_INTERRUPT_UNSET    -2U
-+
-+/* for KVM_GET_REGS and KVM_SET_REGS */
-+struct kvm_regs {
-+};
-+
-+/* for KVM_GET_FPU and KVM_SET_FPU */
-+struct kvm_fpu {
-+};
-+
-+/* KVM Debug exit structure */
-+struct kvm_debug_exit_arch {
-+};
-+
-+/* for KVM_SET_GUEST_DEBUG */
-+struct kvm_guest_debug_arch {
-+};
-+
-+/* definition of registers in kvm_run */
-+struct kvm_sync_regs {
-+};
-+
-+/* for KVM_GET_SREGS and KVM_SET_SREGS */
-+struct kvm_sregs {
-+};
-+
-+/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
-+struct kvm_riscv_config {
-+    unsigned long isa;
-+};
-+
-+/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
-+struct kvm_riscv_core {
-+    struct user_regs_struct regs;
-+    unsigned long mode;
-+};
-+
-+/* Possible privilege modes for kvm_riscv_core */
-+#define KVM_RISCV_MODE_S    1
-+#define KVM_RISCV_MODE_U    0
-+
-+/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
-+struct kvm_riscv_csr {
-+    unsigned long sstatus;
-+    unsigned long sie;
-+    unsigned long stvec;
-+    unsigned long sscratch;
-+    unsigned long sepc;
-+    unsigned long scause;
-+    unsigned long stval;
-+    unsigned long sip;
-+    unsigned long satp;
-+    unsigned long scounteren;
-+};
-+
-+/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
-+struct kvm_riscv_timer {
-+    __u64 frequency;
-+    __u64 time;
-+    __u64 compare;
-+    __u64 state;
-+};
-+
-+/* Possible states for kvm_riscv_timer */
-+#define KVM_RISCV_TIMER_STATE_OFF    0
-+#define KVM_RISCV_TIMER_STATE_ON    1
-+
-+#define KVM_REG_SIZE(id)        \
-+    (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
-+
-+/* If you need to interpret the index values, here is the key: */
-+#define KVM_REG_RISCV_TYPE_MASK        0x00000000FF000000
-+#define KVM_REG_RISCV_TYPE_SHIFT    24
-+
-+/* Config registers are mapped as type 1 */
-+#define KVM_REG_RISCV_CONFIG        (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_CONFIG_REG(name)    \
-+    (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
-+
-+/* Core registers are mapped as type 2 */
-+#define KVM_REG_RISCV_CORE        (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_CORE_REG(name)    \
-+        (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
-+
-+/* Control and status registers are mapped as type 3 */
-+#define KVM_REG_RISCV_CSR        (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_CSR_REG(name)    \
-+        (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
-+
-+/* Timer registers are mapped as type 4 */
-+#define KVM_REG_RISCV_TIMER        (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_TIMER_REG(name)    \
-+        (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
-+
-+/* F extension registers are mapped as type 5 */
-+#define KVM_REG_RISCV_FP_F        (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_FP_F_REG(name)    \
-+        (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
-+
-+/* D extension registers are mapped as type 6 */
-+#define KVM_REG_RISCV_FP_D        (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
-+#define KVM_REG_RISCV_FP_D_REG(name)    \
-+        (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
-+
-+#endif
-+
-+#endif /* __LINUX_KVM_RISCV_H */
---
-.31.1

-[PULL 61/61] target/riscv: Relax UXL field for debugging
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+be initialized first.
-Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
 Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 8 ++++----
+ hw/intc/riscv_aplic.c | 8 ++++----
 file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/hw/intc/riscv_aplic.c
-+++ b/target/riscv/csr.c
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
-         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+     qdev_prop_set_bit(dev, "msimode", msimode);
-         MSTATUS_TW | MSTATUS_VS;
+     qdev_prop_set_bit(dev, "mmode", mmode);
--    if (xl != MXL_RV32) {
++    if (parent) {
-+    if (xl != MXL_RV32 || env->debugger) {
++        riscv_aplic_add_child(parent, dev);
-         /*
++    }
-          * RV32: MPV and GVA are not in mstatus. The current plan is to
++
-          * add them to mstatush. For now, we just don't support it.
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
- {
+     if (!is_kvm_aia(msimode)) {
-     uint64_t mask = sstatus_v1_10_mask;
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      uint64_t sstatus = env->mstatus & mask;
 -    if (env->xl != MXL_RV32) {
 +    if (env->xl != MXL_RV32 || env->debugger) {
          mask |= SSTATUS64_UXL;
      }
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
+-    if (parent) {
-                                    target_ulong *val)
+-        riscv_aplic_add_child(parent, dev);
- {
+-    }
-     target_ulong mask = (sstatus_v1_10_mask);
+-
--    if (env->xl != MXL_RV32) {
+     if (!msimode) {
-+    if (env->xl != MXL_RV32 || env->debugger) {
+         for (i = 0; i < num_harts; i++) {
-         mask |= SSTATUS64_UXL;
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
      }
      /* TODO: Use SXL not MXL. */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -    if (env->xl != MXL_RV32) {
 +    if (env->xl != MXL_RV32 || env->debugger) {
          if ((val & SSTATUS64_UXL) != 0) {
              mask |= SSTATUS64_UXL;
          }
 --
-.31.1
+.45.1

-[PULL 53/61] target/riscv: Split out the vill from vtype
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-We need not specially process vtype when XLEN changes.
+The Zkr extension may only be exposed to KVM guests if the VMM
 implements the SEED CSR. Use the same implementation as TCG.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Without this patch, running with a KVM which does not forward the
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+SEED CSR access to QEMU will result in an ILL exception being
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+injected into the guest (this results in Linux guests crashing on
-Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
+boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
 Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
 Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h           |  1 +
+ target/riscv/cpu.h         |  3 +++
- target/riscv/cpu_helper.c    |  3 +--
+ target/riscv/csr.c         | 18 ++++++++++++++----
- target/riscv/csr.c           | 13 ++++++++++++-
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
- target/riscv/machine.c       |  5 +++--
+files changed, 42 insertions(+), 4 deletions(-)
  target/riscv/vector_helper.c |  3 ++-
 files changed, 19 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
-     target_ulong vl;
-     target_ulong vstart;
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-     target_ulong vtype;
-+    bool vill;
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask);
-     target_ulong pc;
++
-     target_ulong load_res;
+ uint8_t satp_mode_max_from_map(uint32_t map);
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
          uint32_t maxsz = vlmax << sew;
          bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
                             (maxsz >= 8);
 -        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
 -                    FIELD_EX64(env->vtype, VTYPE, VILL));
 +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
          flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
          flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                      FIELD_EX64(env->vtype, VTYPE, VLMUL));
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
- static RISCVException read_vtype(CPURISCVState *env, int csrno,
+ #endif
-                                  target_ulong *val)
  /* Crypto Extension */
 -static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 -                               target_ulong *ret_value,
 -                               target_ulong new_value,
 -                               target_ulong write_mask)
 +target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
--    *val = env->vtype;
+     uint16_t random_v;
-+    uint64_t vill;
+     Error *random_e = NULL;
-+    switch (env->xl) {
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+    case MXL_RV32:
+         rval = random_v | SEED_OPST_ES16;
-+        vill = (uint32_t)env->vill << 31;
+     }
-+        break;
-+    case MXL_RV64:
++    return rval;
-+        vill = (uint64_t)env->vill << 63;
++}
 +
 +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value,
 +                               target_ulong write_mask)
 +{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
 +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +{
 +    target_ulong csr_num = run->riscv_csr.csr_num;
 +    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
-+        g_assert_not_reached();
++        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
-+    *val = (target_ulong)vill | env->vtype;
++
-     return RISCV_EXCP_NONE;
++    return ret;
- }
++}
++
-diff --git a/target/riscv/machine.c b/target/riscv/machine.c
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/target/riscv/machine.c
+     int ret = 0;
-+++ b/target/riscv/machine.c
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-@@ -XXX,XX +XXX,XX @@ static bool vector_needed(void *opaque)
+     case KVM_EXIT_RISCV_SBI:
+         ret = kvm_riscv_handle_sbi(cs, run);
- static const VMStateDescription vmstate_vector = {
+         break;
-     .name = "cpu/vector",
++    case KVM_EXIT_RISCV_CSR:
--    .version_id = 1,
++        ret = kvm_riscv_handle_csr(cs, run);
--    .minimum_version_id = 1,
++        break;
-+    .version_id = 2,
+     default:
-+    .minimum_version_id = 2,
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-     .needed = vector_needed,
+                       __func__, run->exit_reason);
      .fields = (VMStateField[]) {
              VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
              VMSTATE_UINTTL(env.vl, RISCVCPU),
              VMSTATE_UINTTL(env.vstart, RISCVCPU),
              VMSTATE_UINTTL(env.vtype, RISCVCPU),
 +            VMSTATE_BOOL(env.vill, RISCVCPU),
              VMSTATE_END_OF_LIST()
          }
  };
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
          || (ediv != 0)
          || (reserved != 0)) {
          /* only set vill bit. */
 -        env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
 +        env->vill = 1;
 +        env->vtype = 0;
          env->vl = 0;
          env->vstart = 0;
          return 0;
 --
-.31.1
+.45.1

-[PULL 40/61] target/riscv: Don't save pc when exception return
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-As pc will be written by the xepc in exception return, just ignore
+Implementing wrs.nto to always just return is consistent with the
-pc in translation.
+specification, as the instruction is permitted to terminate the
 stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                          | 4 ++--
+ target/riscv/helper.h                       |  1 +
- target/riscv/op_helper.c                       | 4 ++--
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
-files changed, 6 insertions(+), 9 deletions(-)
+files changed, 32 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(csrr_i128, tl, env, int)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
+ DEF_HELPER_1(sret, tl, env)
- DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
+ DEF_HELPER_1(mret, tl, env)
  #ifndef CONFIG_USER_ONLY
 -DEF_HELPER_2(sret, tl, env, tl)
 -DEF_HELPER_2(mret, tl, env, tl)
 +DEF_HELPER_1(sret, tl, env)
 +DEF_HELPER_1(mret, tl, env)
  DEF_HELPER_1(wfi, void, env)
++DEF_HELPER_1(wrs_nto, void, env)
  DEF_HELPER_1(tlb_flush, void, env)
- #endif
+ DEF_HELPER_1(tlb_flush_all, void, env)
  /* Native Debug */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
+     }
- #ifndef CONFIG_USER_ONLY
+ }
--target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
++void helper_wrs_nto(CPURISCVState *env)
-+target_ulong helper_sret(CPURISCVState *env)
++{
 +    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
 +        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
  void helper_tlb_flush(CPURISCVState *env)
  {
-     uint64_t mstatus;
+     CPUState *cs = env_cpu(env);
-     target_ulong prev_priv, prev_virt;
+diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+index XXXXXXX..XXXXXXX 100644
-     return retpc;
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
--target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+-#define GEN_TRANS_WRS(insn)                                     \
-+target_ulong helper_mret(CPURISCVState *env)
+-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
- {
+-{                                                               \
-     if (!(env->priv >= PRV_M)) {
+-    (void)a;                                                    \
-         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+-    return trans_wrs(ctx);                                      \
-diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+-}
-index XXXXXXX..XXXXXXX 100644
++static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
---- a/target/riscv/insn_trans/trans_privileged.c.inc
++{
-+++ b/target/riscv/insn_trans/trans_privileged.c.inc
++    if (!ctx->cfg_ptr->ext_zawrs) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
++        return false;
- static bool trans_sret(DisasContext *ctx, arg_sret *a)
++    }
- {
- #ifndef CONFIG_USER_ONLY
+-GEN_TRANS_WRS(wrs_nto)
--    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+-GEN_TRANS_WRS(wrs_sto)
--
++    /*
-     if (has_ext(ctx, RVS)) {
++     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
--        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
++     * should raise an exception when the implementation-specific bounded time
-+        gen_helper_sret(cpu_pc, cpu_env);
++     * limit has expired. Our time limit is zero, so we either return
-         tcg_gen_exit_tb(NULL, 0); /* no chaining */
++     * immediately, as does our implementation of wrs.sto, or raise an
-         ctx->base.is_jmp = DISAS_NORETURN;
++     * exception, as handled by the wrs.nto helper.
-     } else {
++     */
-@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
++#ifndef CONFIG_USER_ONLY
- static bool trans_mret(DisasContext *ctx, arg_mret *a)
++    gen_helper_wrs_nto(tcg_env);
- {
++#endif
- #ifndef CONFIG_USER_ONLY
++
--    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
++    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
--    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
++    return trans_wrs_sto(ctx, NULL);
-+    gen_helper_mret(cpu_pc, cpu_env);
++}
      tcg_gen_exit_tb(NULL, 0); /* no chaining */
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
 --
-.31.1
+.45.1

-[PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
-From: Yifei Jiang <jiangyifei@huawei.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Use char-fe to handle console sbi call, which implement early
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-console io while apply 'earlycon=sbi' into kernel parameters.
+the legacy console putchar and getchar SBI extensions.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+The appeal of the DBCN extension is that it allows multiple bytes to be
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
+read/written in the SBI console in a single SBI call.
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
-Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
+module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/kvm.c                 | 42 ++++++++++++++++-
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
-files changed, 113 insertions(+), 1 deletion(-)
+files changed, 128 insertions(+)
  create mode 100644 target/riscv/sbi_ecall_interface.h
 diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/sbi_ecall_interface.h
 --- /dev/null
 +++ b/target/riscv/sbi_ecall_interface.h
 @@ -XXX,XX +XXX,XX @@
-+/*
-+ * SPDX-License-Identifier: BSD-2-Clause
+ /* clang-format off */
-+ *
-+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
++#define SBI_SUCCESS                      0
-+ *
++#define SBI_ERR_FAILED                  -1
-+ * Authors:
++#define SBI_ERR_NOT_SUPPORTED           -2
-+ *   Anup Patel <anup.patel@wdc.com>
++#define SBI_ERR_INVALID_PARAM           -3
-+ */
++#define SBI_ERR_DENIED                  -4
-+
++#define SBI_ERR_INVALID_ADDRESS         -5
-+#ifndef __SBI_ECALL_INTERFACE_H__
++#define SBI_ERR_ALREADY_AVAILABLE       -6
-+#define __SBI_ECALL_INTERFACE_H__
++#define SBI_ERR_ALREADY_STARTED         -7
-+
++#define SBI_ERR_ALREADY_STOPPED         -8
-+/* clang-format off */
++#define SBI_ERR_NO_SHMEM                -9
 +
-+/* SBI Extension IDs */
+ /* SBI Extension IDs */
-+#define SBI_EXT_0_1_SET_TIMER           0x0
+ #define SBI_EXT_0_1_SET_TIMER           0x0
-+#define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
+ #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
-+#define SBI_EXT_0_1_CONSOLE_GETCHAR     0x2
+@@ -XXX,XX +XXX,XX @@
-+#define SBI_EXT_0_1_CLEAR_IPI           0x3
+ #define SBI_EXT_IPI                     0x735049
-+#define SBI_EXT_0_1_SEND_IPI            0x4
+ #define SBI_EXT_RFENCE                  0x52464E43
-+#define SBI_EXT_0_1_REMOTE_FENCE_I      0x5
+ #define SBI_EXT_HSM                     0x48534D
-+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
++#define SBI_EXT_DBCN                    0x4442434E
-+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
-+#define SBI_EXT_0_1_SHUTDOWN            0x8
+ /* SBI function IDs for BASE extension */
-+#define SBI_EXT_BASE                    0x10
+ #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
-+#define SBI_EXT_TIME                    0x54494D45
+@@ -XXX,XX +XXX,XX @@
-+#define SBI_EXT_IPI                     0x735049
+ #define SBI_EXT_HSM_HART_STOP           0x1
-+#define SBI_EXT_RFENCE                  0x52464E43
+ #define SBI_EXT_HSM_HART_GET_STATUS     0x2
-+#define SBI_EXT_HSM                     0x48534D
-+
++/* SBI function IDs for DBCN extension */
-+/* SBI function IDs for BASE extension*/
++#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
-+#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
++#define SBI_EXT_DBCN_CONSOLE_READ       0x1
-+#define SBI_EXT_BASE_GET_IMP_ID         0x1
++#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
-+#define SBI_EXT_BASE_GET_IMP_VERSION    0x2
++
-+#define SBI_EXT_BASE_PROBE_EXT          0x3
+ #define SBI_HSM_HART_STATUS_STARTED     0x0
-+#define SBI_EXT_BASE_GET_MVENDORID      0x4
+ #define SBI_HSM_HART_STATUS_STOPPED     0x1
-+#define SBI_EXT_BASE_GET_MARCHID        0x5
+ #define SBI_HSM_HART_STATUS_START_PENDING   0x2
-+#define SBI_EXT_BASE_GET_MIMPID         0x6
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 +
 +/* SBI function IDs for TIME extension*/
 +#define SBI_EXT_TIME_SET_TIMER          0x0
 +
 +/* SBI function IDs for IPI extension*/
 +#define SBI_EXT_IPI_SEND_IPI            0x0
 +
 +/* SBI function IDs for RFENCE extension*/
 +#define SBI_EXT_RFENCE_REMOTE_FENCE_I       0x0
 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA    0x1
 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID  0x2
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x3
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x5
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
 +
 +/* SBI function IDs for HSM extension */
 +#define SBI_EXT_HSM_HART_START          0x0
 +#define SBI_EXT_HSM_HART_STOP           0x1
 +#define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +
 +#define SBI_HSM_HART_STATUS_STARTED     0x0
 +#define SBI_HSM_HART_STATUS_STOPPED     0x1
 +#define SBI_HSM_HART_STATUS_START_PENDING   0x2
 +#define SBI_HSM_HART_STATUS_STOP_PENDING    0x3
 +
 +#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
 +#define SBI_SPEC_VERSION_MAJOR_MASK     0x7f
 +#define SBI_SPEC_VERSION_MINOR_MASK     0xffffff
 +#define SBI_EXT_VENDOR_START            0x09000000
 +#define SBI_EXT_VENDOR_END              0x09FFFFFF
 +/* clang-format on */
 +
 +#endif
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/kvm.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
- #include "qemu/log.h"
+                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
- #include "hw/loader.h"
+ };
- #include "kvm_riscv.h"
-+#include "sbi_ecall_interface.h"
++static KVMCPUConfig kvm_sbi_dbcn = {
-+#include "chardev/char-fe.h"
++    .name = "sbi_dbcn",
++    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
- static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
++                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
-                                  uint64_t idx)
++};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
 +static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
 +                                             KVMScratchCPU *kvmcpu,
 +                                             struct kvm_reg_list *reglist)
 +{
 +    struct kvm_reg_list *reg_search;
 +
 +    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
 +                         sizeof(uint64_t), uint64_cmp);
 +
 +    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
  static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
 @@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
-+static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
++static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
-+    int ret = 0;
++    g_autofree uint8_t *buf = NULL;
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
-+    switch (run->riscv_sbi.extension_id) {
++    int ret;
-+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
++
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
-+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
++        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
-+        break;
++
-+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
++        if (ret < 0) {
-+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
++            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
-+        if (ret == sizeof(ch)) {
++                         "writing chardev");
-+            run->riscv_sbi.args[0] = ch;
++            exit(1);
-+        } else {
++        }
-+            run->riscv_sbi.args[0] = -1;
++
-+        }
++        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
-+        qemu_log_mask(LOG_UNIMP,
++        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
-+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
++    }
-+                      __func__, run->riscv_sbi.extension_id);
++}
-+        ret = -1;
++
  static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
-+    }
+     default:
-+    return ret;
+         qemu_log_mask(LOG_UNIMP,
-+}
+                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
 -    return 0;
 +    int ret = 0;
 +    switch (run->exit_reason) {
 +    case KVM_EXIT_RISCV_SBI:
 +        ret = kvm_riscv_handle_sbi(cs, run);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
 +                      __func__, run->exit_reason);
 +        ret = -1;
 +        break;
 +    }
 +    return ret;
  }
  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 --
-.31.1
+.45.1

-[PULL 09/61] target/riscv: Support start kernel directly by KVM
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Yifei Jiang <jiangyifei@huawei.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-Get kernel and fdt start address in virt.c, and pass them to KVM
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
-when cpu reset. Add kvm_riscv.h to place riscv specific interface.
+to set the address of initrd in FDT to support 64-bit address.
-In addition, PLIC is created without M-mode PLIC contexts when KVM
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 is enabled.
 Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Mingwang Li <limingwang@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup@brainfault.org>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h  |  1 +
+ hw/riscv/boot.c | 4 ++--
- target/riscv/cpu.h       |  3 ++
+file changed, 2 insertions(+), 2 deletions(-)
  target/riscv/kvm_riscv.h | 24 ++++++++++++
  hw/intc/sifive_plic.c    | 20 +++++++---
  hw/riscv/boot.c          | 16 +++++++-
  hw/riscv/virt.c          | 83 ++++++++++++++++++++++++++++------------
  target/riscv/cpu.c       |  8 ++++
  target/riscv/kvm-stub.c  | 25 ++++++++++++
  target/riscv/kvm.c       | 14 +++++++
  target/riscv/meson.build |  2 +-
 files changed, 164 insertions(+), 32 deletions(-)
  create mode 100644 target/riscv/kvm_riscv.h
  create mode 100644 target/riscv/kvm-stub.c
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
-                                   hwaddr rom_size,
-                                   uint32_t reset_vec_size,
-                                   uint64_t kernel_entry);
-+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
- #endif /* RISCV_BOOT_H */
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     /* Fields from here on are preserved across CPU reset. */
-     QEMUTimer *timer; /* Internal timer */
-+
-+    hwaddr kernel_addr;
-+    hwaddr fdt_addr;
- };
- OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * QEMU KVM support -- RISC-V specific functions.
-+ *
-+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2 or later, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef QEMU_KVM_RISCV_H
-+#define QEMU_KVM_RISCV_H
-+
-+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
-+
-+#endif
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
-+++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@
- #include "target/riscv/cpu.h"
- #include "migration/vmstate.h"
- #include "hw/irq.h"
-+#include "sysemu/kvm.h"
- static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
- {
-@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-     uint32_t context_stride, uint32_t aperture_size)
- {
-     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
--    int i;
-+    int i, j = 0;
-+    SiFivePLICState *plic;
-     assert(enable_stride == (enable_stride & -enable_stride));
-     assert(context_stride == (context_stride & -context_stride));
-@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-+    plic = SIFIVE_PLIC(dev);
-     for (i = 0; i < num_harts; i++) {
-         CPUState *cpu = qemu_get_cpu(hartid_base + i);
--        qdev_connect_gpio_out(dev, i,
--                              qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
--        qdev_connect_gpio_out(dev, num_harts + i,
--                              qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
-+        if (plic->addr_config[j].mode == PLICMode_M) {
-+            j++;
-+            qdev_connect_gpio_out(dev, num_harts + i,
-+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
-+        }
-+
-+        if (plic->addr_config[j].mode == PLICMode_S) {
-+            j++;
-+            qdev_connect_gpio_out(dev, i,
-+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
-+        }
-     }
-     return dev;
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
- #include "elf.h"
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
- #include "sysemu/device_tree.h"
+     if (fdt) {
- #include "sysemu/qtest.h"
+         end = start + size;
-+#include "sysemu/kvm.h"
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
- #include <libfdt.h>
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
-@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
+     }
          CPUState *cs = qemu_get_cpu(i);
          CPURISCVState *env = &RISCV_CPU(cs)->env;
 -        if (riscv_has_ext(env, RVS)) {
 +        if (kvm_enabled()) {
 +            vals[i] = "S";
 +        } else if (riscv_has_ext(env, RVS)) {
              vals[i] = "MS";
          } else {
              vals[i] = "M";
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
      return;
  }
-+
 +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
 +{
 +    CPUState *cs;
 +
 +    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
 +        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
 +        riscv_cpu->env.kernel_addr = kernel_addr;
 +        riscv_cpu->env.fdt_addr = fdt_addr;
 +    }
 +}
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char.h"
  #include "sysemu/device_tree.h"
  #include "sysemu/sysemu.h"
 +#include "sysemu/kvm.h"
  #include "hw/pci/pci.h"
  #include "hw/pci-host/gpex.h"
  #include "hw/display/ramfb.h"
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
          "sifive,plic-1.0.0", "riscv,plic0"
      };
 -    plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 +    if (kvm_enabled()) {
 +        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
 +    } else {
 +        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 +    }
      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
 -        plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
 -        plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 -        plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
 -        plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 +        if (kvm_enabled()) {
 +            plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
 +        } else {
 +            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 +            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 +        }
      }
      plic_phandles[socket] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          create_fdt_socket_memory(s, memmap, socket);
 -        if (s->have_aclint) {
 -            create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
 -        } else {
 -            create_fdt_socket_clint(s, memmap, socket, intc_phandles);
 +        if (!kvm_enabled()) {
 +            if (s->have_aclint) {
 +                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
 +            } else {
 +                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
 +            }
          }
          create_fdt_socket_plic(s, memmap, socket, phandle,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                  hart_count, &error_abort);
          sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 -        /* Per-socket CLINT */
 -        riscv_aclint_swi_create(
 -            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 -            base_hartid, hart_count, false);
 -        riscv_aclint_mtimer_create(
 -            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
 -                RISCV_ACLINT_SWI_SIZE,
 -            RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 -            RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 -            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 -
 -        /* Per-socket ACLINT SSWI */
 -        if (s->have_aclint) {
 +        if (!kvm_enabled()) {
 +            /* Per-socket CLINT */
              riscv_aclint_swi_create(
 -                memmap[VIRT_ACLINT_SSWI].base +
 -                    i * memmap[VIRT_ACLINT_SSWI].size,
 -                base_hartid, hart_count, true);
 +                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 +                base_hartid, hart_count, false);
 +            riscv_aclint_mtimer_create(
 +                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
 +                    RISCV_ACLINT_SWI_SIZE,
 +                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 +                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 +                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 +
 +            /* Per-socket ACLINT SSWI */
 +            if (s->have_aclint) {
 +                riscv_aclint_swi_create(
 +                    memmap[VIRT_ACLINT_SSWI].base +
 +                        i * memmap[VIRT_ACLINT_SSWI].size,
 +                    base_hartid, hart_count, true);
 +            }
          }
          /* Per-socket PLIC hart topology configuration string */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                  mask_rom);
 +    /*
 +     * Only direct boot kernel is currently supported for KVM VM,
 +     * so the "-bios" parameter is ignored and treated like "-bios none"
 +     * when KVM is enabled.
 +     */
 +    if (kvm_enabled()) {
 +        g_free(machine->firmware);
 +        machine->firmware = g_strdup("none");
 +    }
 +
      if (riscv_is_32bit(&s->soc[0])) {
          firmware_end_addr = riscv_find_and_load_firmware(machine,
                                      RISCV32_BIOS_BIN, start_addr, NULL);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                virt_memmap[VIRT_MROM].size, kernel_entry,
                                fdt_load_addr, machine->fdt);
 +    /*
 +     * Only direct boot kernel is currently supported for KVM VM,
 +     * So here setup kernel start address and fdt address.
 +     * TODO:Support firmware loading and integrate to TCG start
 +     */
 +    if (kvm_enabled()) {
 +        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
 +    }
 +
      /* SiFive Test MMIO device */
      sifive_test_create(memmap[VIRT_TEST].base);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
  #include "fpu/softfloat-helpers.h"
 +#include "sysemu/kvm.h"
 +#include "kvm_riscv.h"
  /* RISC-V CPU definitions */
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      cs->exception_index = RISCV_EXCP_NONE;
      env->load_res = -1;
      set_default_nan_mode(1, &env->fp_status);
 +
 +#ifndef CONFIG_USER_ONLY
 +    if (kvm_enabled()) {
 +        kvm_riscv_reset_vcpu(cpu);
 +    }
 +#endif
  }
  static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU KVM RISC-V specific function stubs
 + *
 + * Copyright (c) 2020 Huawei Technologies Co., Ltd
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "kvm_riscv.h"
 +
 +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 +{
 +    abort();
 +}
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/irq.h"
  #include "qemu/log.h"
  #include "hw/loader.h"
 +#include "kvm_riscv.h"
  static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                   uint64_t idx)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
      return 0;
  }
 +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 +{
 +    CPURISCVState *env = &cpu->env;
 +
 +    if (!kvm_enabled()) {
 +        return;
 +    }
 +    env->pc = cpu->env.kernel_addr;
 +    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
 +    env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
 +    env->satp = 0;
 +}
 +
  bool kvm_arch_cpu_check_are_resettable(void)
  {
      return true;
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
    'translate.c',
    'm128_helper.c'
  ))
 -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
  riscv_softmmu_ss = ss.source_set()
  riscv_softmmu_ss.add(files(
 --
-.31.1
+.45.1

-[PULL 60/61] target/riscv: Enable uxl field write
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Clément Léger <cleger@rivosinc.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+The current semihost exception number (16) is a reserved number (range
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+[16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
 Signed-off-by: Clément Léger <cleger@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h |  3 +++
+ target/riscv/cpu_bits.h | 2 +-
- target/riscv/csr.c      | 28 ++++++++++++++++++++++------
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 25 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- #define COUNTEREN_IR         (1 << 2)
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
- #define COUNTEREN_HPM3       (1 << 3)
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-+/* vsstatus CSR bits */
+-    RISCV_EXCP_SEMIHOST = 0x10,
-+#define VSSTATUS64_UXL       0x0000000300000000ULL
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
-+
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
- /* Privilege modes */
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
- #define PRV_U 0
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
- #define PRV_S 1
++    RISCV_EXCP_SEMIHOST = 0x3f,
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+ } RISCVException;
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+ #define RISCV_EXCP_INT_FLAG                0x80000000
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
        (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 -    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
 +    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
  static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
  static const target_ulong hip_writable_mask = MIP_VSSIP;
  static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
  {
      uint64_t mstatus = env->mstatus;
      uint64_t mask = 0;
 +    RISCVMXL xl = riscv_cpu_mxl(env);
      /* flush tlb on mstatus fields that affect VM */
      if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
          MSTATUS_TW | MSTATUS_VS;
 -    if (riscv_cpu_mxl(env) != MXL_RV32) {
 +    if (xl != MXL_RV32) {
          /*
           * RV32: MPV and GVA are not in mstatus. The current plan is to
           * add them to mstatush. For now, we just don't support it.
           */
          mask |= MSTATUS_MPV | MSTATUS_GVA;
 +        if ((val & MSTATUS64_UXL) != 0) {
 +            mask |= MSTATUS64_UXL;
 +        }
      }
      mstatus = (mstatus & ~mask) | (val & mask);
 -    RISCVMXL xl = riscv_cpu_mxl(env);
      if (xl > MXL_RV32) {
 -        /* SXL and UXL fields are for now read only */
 +        /* SXL field is for now read only */
          mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
 -        mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
      }
      env->mstatus = mstatus;
      env->xl = cpu_recompute_xl(env);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
  {
      uint64_t mask = sstatus_v1_10_mask;
      uint64_t sstatus = env->mstatus & mask;
 +    if (env->xl != MXL_RV32) {
 +        mask |= SSTATUS64_UXL;
 +    }
      *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
      return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -
 +    if (env->xl != MXL_RV32) {
 +        mask |= SSTATUS64_UXL;
 +    }
      /* TODO: Use SXL not MXL. */
      *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
      return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
 +
 +    if (env->xl != MXL_RV32) {
 +        if ((val & SSTATUS64_UXL) != 0) {
 +            mask |= SSTATUS64_UXL;
 +        }
 +    }
      target_ulong newval = (env->mstatus & ~mask) | (val & mask);
      return write_mstatus(env, CSR_MSTATUS, newval);
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
                                       target_ulong val)
  {
      uint64_t mask = (target_ulong)-1;
 +    if ((val & VSSTATUS64_UXL) == 0) {
 +        mask &= ~VSSTATUS64_UXL;
 +    }
      env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
      return RISCV_EXCP_NONE;
  }
 --
-.31.1
+.45.1

-[PULL 57/61] target/riscv: Adjust vector address with mask
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The mask comes from the pointer masking extension, or the max value
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-corresponding to XLEN bits.
+enabled, will fail with a kernel oops SIGILL right at the start. The
 reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+In hindsight this is too strict. If we keep proceeding, despite not
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+disabling the extension in the KVM vcpu, we'll not add the extension in
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
-Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
 Change our current logic to not error out if we fail to disable an
 extension in kvm_set_one_reg(), but show a warning and keep booting. It
 is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_helper.c | 25 +++++++++++++++----------
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
-file changed, 15 insertions(+), 10 deletions(-)
+file changed, 8 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_helper.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/vector_helper.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
-     return scale < 0 ? vlenb >> -scale : vlenb << scale;
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
- }
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
-+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+{
+-                         reg ? "enable" : "disable",
-+    return (addr & env->cur_pmmask) | env->cur_pmbase;
+-                         multi_ext_cfg->name, ret);
-+}
+-            exit(EXIT_FAILURE);
-+
++            if (!reg && ret == -EINVAL) {
- /*
++                warn_report("KVM cannot disable extension %s",
-  * This function checks watchpoint before real load operation.
++                            multi_ext_cfg->name);
-  *
++            } else {
-@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
++                error_report("Unable to enable extension %s in KVM, error %d",
-     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
++                             multi_ext_cfg->name, ret);
-     target_ulong curlen = MIN(pagelen, len);
++                exit(EXIT_FAILURE);
++            }
--    probe_access(env, addr, curlen, access_type,
+         }
 +    probe_access(env, adjust_addr(env, addr), curlen, access_type,
                   cpu_mmu_index(env, false), ra);
      if (len > curlen) {
          addr += curlen;
          curlen = len - curlen;
 -        probe_access(env, addr, curlen, access_type,
 +        probe_access(env, adjust_addr(env, addr), curlen, access_type,
                       cpu_mmu_index(env, false), ra);
      }
  }
-@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
-         k = 0;
-         while (k < nf) {
-             target_ulong addr = base + stride * i + (k << esz);
--            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-             k++;
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-         k = 0;
-         while (k < nf) {
-             target_ulong addr = base + ((i * nf + k) << esz);
--            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-             k++;
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
-         k = 0;
-         while (k < nf) {
-             abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
--            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-             k++;
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
-         if (!vm && !vext_elem_mask(v0, i)) {
-             continue;
-         }
--        addr = base + i * (nf << esz);
-+        addr = adjust_addr(env, base + i * (nf << esz));
-         if (i == 0) {
-             probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
-         } else {
-@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
-                     break;
-                 }
-                 remain -= offset;
--                addr += offset;
-+                addr = adjust_addr(env, addr + offset);
-             }
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
-         }
-         while (k < nf) {
-             target_ulong addr = base + ((i * nf + k) << esz);
--            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-             k++;
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-         /* load/store rest of elements of current segment pointed by vstart */
-         for (pos = off; pos < max_elems; pos++, env->vstart++) {
-             target_ulong addr = base + ((pos + k * max_elems) << esz);
--            ldst_elem(env, addr, pos + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
-         }
-         k++;
-     }
-@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-     for (; k < nf; k++) {
-         for (i = 0; i < max_elems; i++, env->vstart++) {
-             target_ulong addr = base + ((i + k * max_elems) << esz);
--            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-         }
-     }
 --
-.31.1
+.45.1

-[PULL 49/61] target/riscv: Create current pm fields in env
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+We're not setting (s/m)tval when triggering breakpoints of type 2
 (mcontrol) and 6 (mcontrol6). According to the debug spec section
 .7.12, "Match Control Type 6":
 "The Privileged Spec says that breakpoint exceptions that occur on
 instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
+Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/cpu_helper.c | 1 +
- target/riscv/cpu.c        |  1 +
+ target/riscv/debug.c      | 3 +++
- target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
+files changed, 4 insertions(+)
  target/riscv/csr.c        | 19 +++++++++++++++++
  target/riscv/machine.c    |  1 +
 files changed, 68 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     target_ulong upmmask;
-     target_ulong upmbase;
- #endif
-+    target_ulong cur_pmmask;
-+    target_ulong cur_pmbase;
-     float_status fp_status;
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
- void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-                           target_ulong *cs_base, uint32_t *pflags);
-+void riscv_cpu_update_mask(CPURISCVState *env);
-+
- RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-                            target_ulong *ret_value,
-                            target_ulong new_value, target_ulong write_mask);
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
-     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
- #endif
-     env->xl = riscv_cpu_mxl(env);
-+    riscv_cpu_update_mask(env);
-     cs->exception_index = RISCV_EXCP_NONE;
-     env->load_res = -1;
-     set_default_nan_mode(1, &env->fp_status);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-     *pflags = flags;
+             tval = env->bins;
- }
+             break;
+         case RISCV_EXCP_BREAKPOINT:
-+void riscv_cpu_update_mask(CPURISCVState *env)
++            tval = env->badaddr;
-+{
+             if (cs->watchpoint_hit) {
-+    target_ulong mask = -1, base = 0;
+                 tval = cs->watchpoint_hit->hitaddr;
-+    /*
+                 cs->watchpoint_hit = NULL;
-+     * TODO: Current RVJ spec does not specify
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 +     * how the extension interacts with XLEN.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    if (riscv_has_ext(env, RVJ)) {
 +        switch (env->priv) {
 +        case PRV_M:
 +            if (env->mmte & M_PM_ENABLE) {
 +                mask = env->mpmmask;
 +                base = env->mpmbase;
 +            }
 +            break;
 +        case PRV_S:
 +            if (env->mmte & S_PM_ENABLE) {
 +                mask = env->spmmask;
 +                base = env->spmbase;
 +            }
 +            break;
 +        case PRV_U:
 +            if (env->mmte & U_PM_ENABLE) {
 +                mask = env->upmmask;
 +                base = env->upmbase;
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    }
 +#endif
 +    if (env->xl == MXL_RV32) {
 +        env->cur_pmmask = mask & UINT32_MAX;
 +        env->cur_pmbase = base & UINT32_MAX;
 +    } else {
 +        env->cur_pmmask = mask;
 +        env->cur_pmbase = base;
 +    }
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static int riscv_cpu_local_irq_pending(CPURISCVState *env)
  {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
      /* tlb_flush is unnecessary as mode is contained in mmu_idx */
      env->priv = newpriv;
      env->xl = cpu_recompute_xl(env);
 +    riscv_cpu_update_mask(env);
      /*
       * Clear the load reservation - otherwise a reservation placed in one
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/debug.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
+                     /* check U/S/M bit against current privilege level */
-     env->mmte = wpri_val | PM_EXT_DIRTY;
+                     if ((ctrl >> 3) & BIT(env->priv)) {
-+    riscv_cpu_update_mask(env);
++                        env->badaddr = pc;
+                         return true;
-     /* Set XS and SD bits, since PM CSRs are dirty */
+                     }
-     mstatus = env->mstatus | MSTATUS_XS;
+                 }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-     uint64_t mstatus;
+                     if (env->virt_enabled) {
+                         /* check VU/VS bit against current privilege level */
-     env->mpmmask = val;
+                         if ((ctrl >> 23) & BIT(env->priv)) {
-+    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
++                            env->badaddr = pc;
-+        env->cur_pmmask = val;
+                             return true;
-+    }
+                         }
-     env->mmte |= PM_EXT_DIRTY;
+                     } else {
+                         /* check U/S/M bit against current privilege level */
-     /* Set XS and SD bits, since PM CSRs are dirty */
+                         if ((ctrl >> 3) & BIT(env->priv)) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
++                            env->badaddr = pc;
-         return RISCV_EXCP_NONE;
+                             return true;
-     }
+                         }
-     env->spmmask = val;
+                     }
 +    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
 +        env->cur_pmmask = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->upmmask = val;
 +    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
 +        env->cur_pmmask = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
      uint64_t mstatus;
      env->mpmbase = val;
 +    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->spmbase = val;
 +    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->upmbase = val;
 +    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
      CPURISCVState *env = &cpu->env;
      env->xl = cpu_recompute_xl(env);
 +    riscv_cpu_update_mask(env);
      return 0;
  }
 --
-.31.1
+.45.1

-[PULL 42/61] target/riscv: Sign extend pc for different XLEN
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-When pc is written, it is sign-extended to fill the widest supported XLEN.
+Privileged spec section 4.1.9 mentions:
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+"When a trap is taken into S-mode, stval is written with
 exception-specific information to assist software in handling the trap.
 (...)
 If stval is written with a nonzero value when a breakpoint,
 address-misaligned, access-fault, or page-fault exception occurs on an
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                      | 25 ++++++++++++++++---
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
- .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
+file changed, 2 insertions(+)
  target/riscv/insn_trans/trans_rvi.c.inc       |  5 ++--
  target/riscv/insn_trans/trans_rvv.c.inc       |  4 +--
 files changed, 27 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
-     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
- }
-+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
-+{
-+    if (get_xl(ctx) == MXL_RV32) {
-+        dest = (int32_t)dest;
-+    }
-+    tcg_gen_movi_tl(cpu_pc, dest);
-+}
-+
-+static void gen_set_pc(DisasContext *ctx, TCGv dest)
-+{
-+    if (get_xl(ctx) == MXL_RV32) {
-+        tcg_gen_ext32s_tl(cpu_pc, dest);
-+    } else {
-+        tcg_gen_mov_tl(cpu_pc, dest);
-+    }
-+}
-+
- static void generate_exception(DisasContext *ctx, int excp)
- {
--    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-+    gen_set_pc_imm(ctx, ctx->base.pc_next);
-     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
-     ctx->base.is_jmp = DISAS_NORETURN;
- }
- static void generate_exception_mtval(DisasContext *ctx, int excp)
- {
--    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-+    gen_set_pc_imm(ctx, ctx->base.pc_next);
-     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
-     ctx->base.is_jmp = DISAS_NORETURN;
-@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
- {
-     if (translator_use_goto_tb(&ctx->base, dest)) {
-         tcg_gen_goto_tb(n);
--        tcg_gen_movi_tl(cpu_pc, dest);
-+        gen_set_pc_imm(ctx, dest);
-         tcg_gen_exit_tb(ctx->base.tb, n);
-     } else {
--        tcg_gen_movi_tl(cpu_pc, dest);
-+        gen_set_pc_imm(ctx, dest);
-         tcg_gen_lookup_and_goto_ptr();
-     }
- }
 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_privileged.c.inc
 +++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
- static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
- {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
- #ifndef CONFIG_USER_ONLY
+     } else {
--    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
-+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
++                      offsetof(CPURISCVState, badaddr));
-     gen_helper_wfi(cpu_env);
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
      }
      return true;
- #else
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
-     tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
-     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-+    gen_set_pc(ctx, cpu_pc);
-     if (!has_ext(ctx, RVC)) {
-         TCGv t0 = tcg_temp_new();
-@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
-      * FENCE_I is a no-op in QEMU,
-      * however we need to end the translation block
-      */
--    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-     tcg_gen_exit_tb(NULL, 0);
-     ctx->base.is_jmp = DISAS_NORETURN;
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
- static bool do_csr_post(DisasContext *ctx)
- {
-     /* We may have changed important cpu state -- exit to main loop. */
--    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-     tcg_gen_exit_tb(NULL, 0);
-     ctx->base.is_jmp = DISAS_NORETURN;
-     return true;
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
-     gen_set_gpr(s, rd, dst);
-     mark_vs_dirty(s);
--    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
-+    gen_set_pc_imm(s, s->pc_succ_insn);
-     tcg_gen_lookup_and_goto_ptr();
-     s->base.is_jmp = DISAS_NORETURN;
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
-     gen_helper_vsetvl(dst, cpu_env, s1, s2);
-     gen_set_gpr(s, rd, dst);
-     mark_vs_dirty(s);
--    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
-+    gen_set_pc_imm(s, s->pc_succ_insn);
-     tcg_gen_lookup_and_goto_ptr();
-     s->base.is_jmp = DISAS_NORETURN;
 --
-.31.1
+.45.1

-[PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Frank Chang <frank.chang@sifive.com>
+From: Jason Chien <jason.chien@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Add support for Zve32x extension and replace some checks for Zve32f with
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Zve32x, since Zve32f depends on Zve32x.
-Message-id: 20220118014522.13613-2-frank.chang@sifive.com
 Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 1 +
+ target/riscv/cpu_cfg.h                  |  1 +
- target/riscv/cpu.c        | 4 ++++
+ target/riscv/cpu.c                      |  2 ++
- target/riscv/cpu_helper.c | 5 ++++-
+ target/riscv/cpu_helper.c               |  2 +-
- target/riscv/csr.c        | 6 +++++-
+ target/riscv/csr.c                      |  2 +-
- target/riscv/translate.c  | 2 ++
+ target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
-files changed, 16 insertions(+), 2 deletions(-)
+ target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-         bool ext_icsr;
+     bool ext_zhinx;
-         bool ext_zfh;
+     bool ext_zhinxmin;
-         bool ext_zfhmin;
+     bool ext_zve32f;
-+        bool ext_zve64f;
++    bool ext_zve32x;
+     bool ext_zve64f;
-         char *priv_spec;
+     bool ext_zve64d;
-         char *user_spec;
+     bool ext_zvbb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-             }
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
-             set_vext_version(env, vext_version);
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
-         }
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
-+        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-+            error_setg(errp, "Zve64f extension depends upon RVF.");
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-+            return;
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+        }
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-         if (cpu->cfg.ext_j) {
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-             ext |= RVJ;
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
-         }
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
      MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
                            target_ulong *cs_base, uint32_t *pflags)
  {
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
      uint32_t flags = 0;
      *pc = env->pc;
      *cs_base = 0;
--    if (riscv_has_ext(env, RVV)) {
+-    if (cpu->cfg.ext_zve32f) {
-+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
++    if (cpu->cfg.ext_zve32x) {
          /*
           * If env->vl equals to VLMAX, we can use generic vector operation
           * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
 @@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
--    if (env->misa_ext & RVV) {
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
-+    CPUState *cs = env_cpu(env);
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    if (env->misa_ext & RVV ||
 +        cpu->cfg.ext_zve64f) {
  #if !defined(CONFIG_USER_ONLY)
          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     bool ext_ifencei;
+         return;
-     bool ext_zfh;
+     }
-     bool ext_zfhmin;
-+    bool ext_zve64f;
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-     bool hlsx;
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-     /* vector extension */
+-        return;
-     bool vill;
++    /* The Zve32f extension depends on the Zve32x extension */
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
++    if (cpu->cfg.ext_zve32f) {
-     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
++        if (!riscv_has_ext(env, RVF)) {
-     ctx->ext_zfh = cpu->cfg.ext_zfh;
++            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
++            return;
-+    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
++        }
-     ctx->vlen = cpu->cfg.vlen;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
-     ctx->elen = cpu->cfg.elen;
+     }
-     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
      TCGv s1, dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
      TCGv dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
 --
-.31.1
+.45.1

-[PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Frank Chang <frank.chang@sifive.com>
+From: Jason Chien <jason.chien@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+enabling Zve64x enables Zve32x according to their dependency.
-Message-id: 20220118014522.13613-11-frank.chang@sifive.com
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
 Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 1 +
+ target/riscv/cpu_cfg.h     |  1 +
-file changed, 1 insertion(+)
+ target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
++    bool ext_zve64x;
+     bool ext_zvbb;
+     bool ext_zvbc;
+     bool ext_zvkb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
-     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
 -    /* The Zve64f extension depends on the Zve32f extension */
 +    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
      if (cpu->cfg.ext_zve64f) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
      }
 -    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 +    /* The Zve64x extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.31.1
+.45.1

-[PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Jason Chien <jason.chien@sifive.com>
-When sew <= 32bits, not need to extend scalar reg.
+In current implementation, the gdbstub allows reading vector registers
-When sew > 32bits, if xlen is less that sew, we should sign extend
+only if V extension is supported. However, all vector extensions and
-the scalar register, except explicitly specified by the spec.
+vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
+ target/riscv/gdbstub.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/target/riscv/gdbstub.c
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-     dest = tcg_temp_new_ptr();
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
-     mask = tcg_temp_new_ptr();
+);
-     src2 = tcg_temp_new_ptr();
+     }
--    src1 = get_gpr(s, rs1, EXT_NONE);
+-    if (env->misa_ext & RVV) {
-+    src1 = get_gpr(s, rs1, EXT_SIGN);
++    if (cpu->cfg.ext_zve32x) {
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
-     data = FIELD_DP32(data, VDATA, VM, vm);
+                                  riscv_gdb_set_vector,
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 --
-.31.1
+.45.1

-[PULL 45/61] target/riscv: Extend pc for runtime pc write
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-In some cases, we must restore the guest PC to the address of the start of
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-the TB, such as when the instruction counter hits zero. So extend pc register
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
-according to current xlen for these cases.
+agnostic policy.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+However, this function can't deal the big endian situation. This patch fixes
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+the problem by adding handling of such case.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 22 +++++++++++++++++++---
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
-file changed, 19 insertions(+), 3 deletions(-)
+file changed, 22 insertions(+)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/vector_internals.c
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
- {
+     if (tot - cnt == 0) {
-     RISCVCPU *cpu = RISCV_CPU(cs);
+         return ;
-     CPURISCVState *env = &cpu->env;
+     }
 -    env->pc = value;
 +
-+    if (env->xl == MXL_RV32) {
++    if (HOST_BIG_ENDIAN) {
-+        env->pc = (int32_t)value;
++        /*
-+    } else {
++         * Deal the situation when the elements are insdie
-+        env->pc = value;
++         * only one uint64 block including setting the
 +         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
+     memset(base + cnt, -1, tot - cnt);
  }
- static void riscv_cpu_synchronize_from_tb(CPUState *cs,
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
- {
-     RISCVCPU *cpu = RISCV_CPU(cs);
-     CPURISCVState *env = &cpu->env;
--    env->pc = tb->pc;
-+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-+
-+    if (xl == MXL_RV32) {
-+        env->pc = (int32_t)tb->pc;
-+    } else {
-+        env->pc = tb->pc;
-+    }
- }
- static bool riscv_cpu_has_work(CPUState *cs)
-@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
- void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
-                           target_ulong *data)
- {
--    env->pc = data[0];
-+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-+    if (xl == MXL_RV32) {
-+        env->pc = (int32_t)data[0];
-+    } else {
-+        env->pc = data[0];
-+    }
- }
- static void riscv_cpu_reset(DeviceState *dev)
 --
-.31.1
+.45.1

-[PULL 59/61] target/riscv: Set default XLEN for hypervisor
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Yangyu Chen <cyy@cyyself.name>
-When swap regs for hypervisor, the value of vsstatus or mstatus_hs
+This code has a typo that writes zvkb to zvkg, causing users can't
-should have the right XLEN. Otherwise, it will propagate to mstatus.
+enable zvkb through the config. This patch gets this fixed.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
 Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 10 ++++++++++
+ target/riscv/cpu.c | 2 +-
-file changed, 10 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-          */
+     /* Vector cryptography extensions */
-         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
-         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-+        if (riscv_has_ext(env, RVH)) {
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-+            env->vsstatus = set_field(env->vsstatus,
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
-+                                      MSTATUS64_SXL, env->misa_mxl);
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
-+            env->vsstatus = set_field(env->vsstatus,
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
-+                                      MSTATUS64_UXL, env->misa_mxl);
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 +            env->mstatus_hs = set_field(env->mstatus_hs,
 +                                        MSTATUS64_SXL, env->misa_mxl);
 +            env->mstatus_hs = set_field(env->mstatus_hs,
 +                                        MSTATUS64_UXL, env->misa_mxl);
 +        }
      }
      env->mcause = 0;
      env->pc = env->resetvec;
 --
-.31.1
+.45.1

-[PULL 52/61] target/riscv: Split pm_enabled into mask and base
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-Use cached cur_pmmask and cur_pmbase to infer the
+In this patch, we modify the decoder to be a freely composable data
-current PM mode.
+structure instead of a hardcoded one. It can be dynamically builded up
 according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-This may decrease the TCG IR by one when pm_enabled
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-is true and pm_base_enabled is false.
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  3 ++-
+ target/riscv/cpu.h         |  1 +
- target/riscv/cpu_helper.c | 24 ++++++------------------
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
- target/riscv/translate.c  | 12 ++++++++----
+ target/riscv/cpu.c         |  1 +
-files changed, 16 insertions(+), 23 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
+     uint32_t pmu_avail_ctrs;
- FIELD(TB_FLAGS, XL, 20, 2)
+     /* Mapping of events to counters */
- /* If PointerMasking should be applied */
+     GHashTable *pmu_event_ctr_map;
--FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
++    const GPtrArray *decoders;
-+FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
+ };
-+FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
+ /**
- #ifdef TARGET_RISCV32
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/tcg/tcg-cpu.h
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/tcg/tcg-cpu.h
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
-         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
+ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
-                            get_field(env->mstatus_hs, MSTATUS_VS));
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 +struct DisasContext;
 +struct RISCVCPUConfig;
 +typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
              error_propagate(errp, local_err);
              return;
          }
 +        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
      } else if (kvm_enabled()) {
          riscv_kvm_cpu_finalize_features(cpu, &local_err);
          if (local_err != NULL) {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
      }
--    if (riscv_has_ext(env, RVJ)) {
+ }
--        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
--        bool pm_enabled = false;
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
--        switch (priv) {
++{
--        case PRV_U:
++    GPtrArray *dynamic_decoders;
--            pm_enabled = env->mmte & U_PM_ENABLE;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
--            break;
++    for (size_t i = 0; i < decoder_table_size; ++i) {
--        case PRV_S:
++        if (decoder_table[i].guard_func &&
--            pm_enabled = env->mmte & S_PM_ENABLE;
++            decoder_table[i].guard_func(&cpu->cfg)) {
--            break;
++            g_ptr_array_add(dynamic_decoders,
--        case PRV_M:
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
--            pm_enabled = env->mmte & M_PM_ENABLE;
++        }
 -            break;
 -        default:
 -            g_assert_not_reached();
 -        }
 -        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
 -    }
  #endif
      flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
 +    if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
 +        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
 +    }
-+    if (env->cur_pmbase != 0) {
++
-+        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
++    cpu->decoders = dynamic_decoders;
-+    }
++}
++
-     *pflags = flags;
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
- }
+ {
      return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/helper-info.c.inc"
+ #undef  HELPER_H
++#include "tcg/tcg-cpu.h"
++
+ /* global register indices */
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     /* Space for 3 operands plus 1 extra for address computation. */
+     /* FRM is known to contain a valid value. */
-     TCGv temp[4];
+     bool frm_valid;
-     /* PointerMasking extension */
+     bool insn_start_updated;
--    bool pm_enabled;
++    const GPtrArray *decoders;
 +    bool pm_mask_enabled;
 +    bool pm_base_enabled;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
+@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
-     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+     return (first_word & 3) == 3 ? 4 : 2;
      tcg_gen_addi_tl(addr, src1, imm);
 -    if (ctx->pm_enabled) {
 +    if (ctx->pm_mask_enabled) {
          tcg_gen_and_tl(addr, addr, pm_mask);
 -        tcg_gen_or_tl(addr, addr, pm_base);
      } else if (get_xl(ctx) == MXL_RV32) {
          tcg_gen_ext32u_tl(addr, addr);
      }
 +    if (ctx->pm_base_enabled) {
 +        tcg_gen_or_tl(addr, addr, pm_base);
 +    }
      return addr;
  }
++const RISCVDecoder decoder_table[] = {
++    { always_true_p, decode_insn32 },
++    { has_xthead_p, decode_xthead},
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
++};
++
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
++
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+ {
+-    /*
+-     * A table with predicate (i.e., guard) functions and decoder functions
+-     * that are tested in-order until a decoder matches onto the opcode.
+-     */
+-    static const struct {
+-        bool (*guard_func)(const RISCVCPUConfig *);
+-        bool (*decode_func)(DisasContext *, uint32_t);
+-    } decoders[] = {
+-        { always_true_p,  decode_insn32 },
+-        { has_xthead_p, decode_xthead },
+-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
+-    };
+-
+     ctx->virt_inst_excp = false;
+     ctx->cur_insn_len = insn_len(opcode);
+     /* Check for compressed insn */
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+                                              ctx->base.pc_next + 2));
+         ctx->opcode = opcode32;
+-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
+-                decoders[i].decode_func(ctx, opcode32)) {
++        for (guint i = 0; i < ctx->decoders->len; ++i) {
++            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
++            if (func(ctx, opcode32)) {
+                 return;
+             }
+         }
 @@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->cs = cs;
+     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->ntemp = 0;
      memset(ctx->temp, 0, sizeof(ctx->temp));
 -    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
 +    ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
 +    ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
      ctx->zero = tcg_constant_tl(0);
+     ctx->virt_inst_excp = false;
++    ctx->decoders = cpu->decoders;
  }
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.31.1
+.45.1

-[PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Yifei Jiang <jiangyifei@huawei.com>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-Add target/riscv/kvm.c to place kvm_arch_* function needed by
+The th.sxstatus CSR can be used to identify available custom extension
-kvm/kvm-all.c.
+on T-Head CPUs. The CSR is documented here:
   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+An important property of this patch is, that the th.sxstatus MAEE field
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
+is not set (indicating that XTheadMae is not available).
 XTheadMae is a memory attribute extension (similar to Svpbmt) which is
 implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
 in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
 Further context can be found on the list:
 https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-id: 20220112081329.1835-3-jiangyifei@huawei.com
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm.c       | 133 +++++++++++++++++++++++++++++++++++++++
+ MAINTAINERS              |  1 +
- target/riscv/meson.build |   1 +
+ target/riscv/cpu.h       |  3 ++
-files changed, 134 insertions(+)
+ target/riscv/cpu.c       |  1 +
- create mode 100644 target/riscv/kvm.c
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
  target/riscv/meson.build |  1 +
 files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
  S: Supported
  F: target/riscv/insn_trans/trans_xthead.c.inc
  F: target/riscv/xthead*.decode
 +F: target/riscv/th_*
  F: disas/riscv-xthead*
  RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
  uint8_t satp_mode_max_from_map(uint32_t map);
  const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 +/* Implemented in th_csr.c */
 +void th_register_custom_csrs(RISCVCPU *cpu);
 +
  #endif /* RISCV_CPU_H */
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
      cpu->cfg.mvendorid = THEAD_VENDOR_ID;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 +    th_register_custom_csrs(cpu);
  #endif
      /* inherited from parent obj via riscv_cpu_init() */
 diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/riscv/kvm.c
++++ b/target/riscv/th_csr.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V implementation of KVM hooks
++ * T-Head-specific CSRs.
 + *
-+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
++ * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
-+#include <sys/ioctl.h>
++#include "cpu.h"
 +#include "cpu_vendorid.h"
 +
-+#include <linux/kvm.h>
++#define CSR_TH_SXSTATUS 0x5c0
 +
-+#include "qemu-common.h"
++/* TH_SXSTATUS bits */
-+#include "qemu/timer.h"
++#define TH_SXSTATUS_UCME        BIT(16)
-+#include "qemu/error-report.h"
++#define TH_SXSTATUS_MAEE        BIT(21)
-+#include "qemu/main-loop.h"
++#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +#include "sysemu/sysemu.h"
 +#include "sysemu/kvm.h"
 +#include "sysemu/kvm_int.h"
 +#include "cpu.h"
 +#include "trace.h"
 +#include "hw/pci/pci.h"
 +#include "exec/memattrs.h"
 +#include "exec/address-spaces.h"
 +#include "hw/boards.h"
 +#include "hw/irq.h"
 +#include "qemu/log.h"
 +#include "hw/loader.h"
 +
-+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
++typedef struct {
-+    KVM_CAP_LAST_INFO
++    int csrno;
-+};
++    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
-+int kvm_arch_get_registers(CPUState *cs)
++static RISCVException smode(CPURISCVState *env, int csrno)
 +{
++    if (riscv_has_ext(env, RVS)) {
++        return RISCV_EXCP_NONE;
++    }
++
++    return RISCV_EXCP_ILLEGAL_INST;
++}
++
++static int test_thead_mvendorid(RISCVCPU *cpu)
++{
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
++        return -1;
++    }
++
 +    return 0;
 +}
 +
-+int kvm_arch_put_registers(CPUState *cs, int level)
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
 +{
-+    return 0;
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
-+int kvm_arch_release_virq_post(int virq)
++static riscv_csr th_csr_list[] = {
 +    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
-+    return 0;
++    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
-+}
++        int csrno = th_csr_list[i].csrno;
-+
++        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
-+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
++        if (!th_csr_list[i].insertion_test(cpu)) {
-+                             uint64_t address, uint32_t data, PCIDevice *dev)
++            riscv_set_csr_ops(csrno, csr_ops);
-+{
++        }
-+    return 0;
++    }
 +}
 +
 +int kvm_arch_destroy_vcpu(CPUState *cs)
 +{
 +    return 0;
 +}
 +
 +unsigned long kvm_arch_vcpu_id(CPUState *cpu)
 +{
 +    return cpu->cpu_index;
 +}
 +
 +void kvm_arch_init_irq_routing(KVMState *s)
 +{
 +}
 +
 +int kvm_arch_init_vcpu(CPUState *cs)
 +{
 +    return 0;
 +}
 +
 +int kvm_arch_msi_data_to_gsi(uint32_t data)
 +{
 +    abort();
 +}
 +
 +int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
 +                                int vector, PCIDevice *dev)
 +{
 +    return 0;
 +}
 +
 +int kvm_arch_init(MachineState *ms, KVMState *s)
 +{
 +    return 0;
 +}
 +
 +int kvm_arch_irqchip_create(KVMState *s)
 +{
 +    return 0;
 +}
 +
 +int kvm_arch_process_async_events(CPUState *cs)
 +{
 +    return 0;
 +}
 +
 +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 +{
 +}
 +
 +MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 +{
 +    return MEMTXATTRS_UNSPECIFIED;
 +}
 +
 +bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 +{
 +    return true;
 +}
 +
 +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 +{
 +    return 0;
 +}
 +
 +bool kvm_arch_cpu_check_are_resettable(void)
 +{
 +    return true;
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
-   'translate.c',
+   'monitor.c',
-   'm128_helper.c'
+   'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
-+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
- riscv_softmmu_ss = ss.source_set()
- riscv_softmmu_ss.add(files(
 --
-.31.1
+.45.1

-[PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Get isa info from kvm while kvm init.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-4-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm.c | 34 +++++++++++++++++++++++++++++++++-
-file changed, 33 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/log.h"
- #include "hw/loader.h"
-+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-+                                 uint64_t idx)
-+{
-+    uint64_t id = KVM_REG_RISCV | type | idx;
-+
-+    switch (riscv_cpu_mxl(env)) {
-+    case MXL_RV32:
-+        id |= KVM_REG_SIZE_U32;
-+        break;
-+    case MXL_RV64:
-+        id |= KVM_REG_SIZE_U64;
-+        break;
-+    default:
-+        g_assert_not_reached();
-+    }
-+    return id;
-+}
-+
- const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-     KVM_CAP_LAST_INFO
- };
-@@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s)
- int kvm_arch_init_vcpu(CPUState *cs)
- {
--    return 0;
-+    int ret = 0;
-+    target_ulong isa;
-+    RISCVCPU *cpu = RISCV_CPU(cs);
-+    CPURISCVState *env = &cpu->env;
-+    uint64_t id;
-+
-+    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
-+                          KVM_REG_RISCV_CONFIG_REG(isa));
-+    ret = kvm_get_one_reg(cs, id, &isa);
-+    if (ret) {
-+        return ret;
-+    }
-+    env->misa_ext = isa;
-+
-+    return ret;
- }
- int kvm_arch_msi_data_to_gsi(uint32_t data)
---
-.31.1

-[PULL 07/61] target/riscv: Implement kvm_arch_get_registers
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-5-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm.c | 112 ++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 111 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-     return id;
- }
-+#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
-+                 KVM_REG_RISCV_CORE_REG(name))
-+
-+#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
-+                 KVM_REG_RISCV_CSR_REG(name))
-+
-+#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
-+
-+#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
-+
-+#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
-+    do { \
-+        int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
-+        if (ret) { \
-+            return ret; \
-+        } \
-+    } while (0)
-+
-+static int kvm_riscv_get_regs_core(CPUState *cs)
-+{
-+    int ret = 0;
-+    int i;
-+    target_ulong reg;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
-+    if (ret) {
-+        return ret;
-+    }
-+    env->pc = reg;
-+
-+    for (i = 1; i < 32; i++) {
-+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
-+        ret = kvm_get_one_reg(cs, id, &reg);
-+        if (ret) {
-+            return ret;
-+        }
-+        env->gpr[i] = reg;
-+    }
-+
-+    return ret;
-+}
-+
-+static int kvm_riscv_get_regs_csr(CPUState *cs)
-+{
-+    int ret = 0;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
-+    KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
-+    KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
-+    KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
-+    KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
-+    KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
-+    KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
-+    KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
-+    KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
-+    return ret;
-+}
-+
-+static int kvm_riscv_get_regs_fp(CPUState *cs)
-+{
-+    int ret = 0;
-+    int i;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    if (riscv_has_ext(env, RVD)) {
-+        uint64_t reg;
-+        for (i = 0; i < 32; i++) {
-+            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
-+            if (ret) {
-+                return ret;
-+            }
-+            env->fpr[i] = reg;
-+        }
-+        return ret;
-+    }
-+
-+    if (riscv_has_ext(env, RVF)) {
-+        uint32_t reg;
-+        for (i = 0; i < 32; i++) {
-+            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
-+            if (ret) {
-+                return ret;
-+            }
-+            env->fpr[i] = reg;
-+        }
-+        return ret;
-+    }
-+
-+    return ret;
-+}
-+
- const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-     KVM_CAP_LAST_INFO
- };
- int kvm_arch_get_registers(CPUState *cs)
- {
--    return 0;
-+    int ret = 0;
-+
-+    ret = kvm_riscv_get_regs_core(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = kvm_riscv_get_regs_csr(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = kvm_riscv_get_regs_fp(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    return ret;
- }
- int kvm_arch_put_registers(CPUState *cs, int level)
---
-.31.1

-[PULL 08/61] target/riscv: Implement kvm_arch_put_registers
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-6-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 103 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-         } \
-     } while (0)
-+#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
-+    do { \
-+        int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
-+        if (ret) { \
-+            return ret; \
-+        } \
-+    } while (0)
-+
- static int kvm_riscv_get_regs_core(CPUState *cs)
- {
-     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_core(CPUState *cs)
-     return ret;
- }
-+static int kvm_riscv_put_regs_core(CPUState *cs)
-+{
-+    int ret = 0;
-+    int i;
-+    target_ulong reg;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    reg = env->pc;
-+    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    for (i = 1; i < 32; i++) {
-+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
-+        reg = env->gpr[i];
-+        ret = kvm_set_one_reg(cs, id, &reg);
-+        if (ret) {
-+            return ret;
-+        }
-+    }
-+
-+    return ret;
-+}
-+
- static int kvm_riscv_get_regs_csr(CPUState *cs)
- {
-     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
-     return ret;
- }
-+static int kvm_riscv_put_regs_csr(CPUState *cs)
-+{
-+    int ret = 0;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
-+    KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
-+    KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
-+    KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
-+    KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
-+    KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
-+    KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
-+    KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
-+    KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
-+
-+    return ret;
-+}
-+
- static int kvm_riscv_get_regs_fp(CPUState *cs)
- {
-     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
-     return ret;
- }
-+static int kvm_riscv_put_regs_fp(CPUState *cs)
-+{
-+    int ret = 0;
-+    int i;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    if (riscv_has_ext(env, RVD)) {
-+        uint64_t reg;
-+        for (i = 0; i < 32; i++) {
-+            reg = env->fpr[i];
-+            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
-+            if (ret) {
-+                return ret;
-+            }
-+        }
-+        return ret;
-+    }
-+
-+    if (riscv_has_ext(env, RVF)) {
-+        uint32_t reg;
-+        for (i = 0; i < 32; i++) {
-+            reg = env->fpr[i];
-+            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
-+            if (ret) {
-+                return ret;
-+            }
-+        }
-+        return ret;
-+    }
-+
-+    return ret;
-+}
-+
-+
- const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-     KVM_CAP_LAST_INFO
- };
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
- int kvm_arch_put_registers(CPUState *cs, int level)
- {
--    return 0;
-+    int ret = 0;
-+
-+    ret = kvm_riscv_put_regs_core(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = kvm_riscv_put_regs_csr(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = kvm_riscv_put_regs_fp(cs);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    return ret;
- }
- int kvm_arch_release_virq_post(int virq)
---
-.31.1

-[PULL 10/61] target/riscv: Support setting external interrupt by KVM
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-When KVM is enabled, set the S-mode external interrupt through
-kvm_riscv_set_irq function.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-8-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm_riscv.h |  1 +
- target/riscv/cpu.c       |  6 +++++-
- target/riscv/kvm-stub.c  |  5 +++++
- target/riscv/kvm.c       | 17 +++++++++++++++++
-files changed, 28 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@
- #define QEMU_KVM_RISCV_H
- void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
-+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
- #endif
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
-     case IRQ_S_EXT:
-     case IRQ_VS_EXT:
-     case IRQ_M_EXT:
--        riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
-+        if (kvm_enabled()) {
-+            kvm_riscv_set_irq(cpu, irq, level);
-+        } else {
-+            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
-+        }
-         break;
-     default:
-         g_assert_not_reached();
-diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm-stub.c
-+++ b/target/riscv/kvm-stub.c
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
- {
-     abort();
- }
-+
-+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-+{
-+    abort();
-+}
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-     env->satp = 0;
- }
-+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-+{
-+    int ret;
-+    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
-+
-+    if (irq != IRQ_S_EXT) {
-+        perror("kvm riscv set irq != IRQ_S_EXT\n");
-+        abort();
-+    }
-+
-+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
-+    if (ret < 0) {
-+        perror("Set irq failed");
-+        abort();
-+    }
-+}
-+
- bool kvm_arch_cpu_check_are_resettable(void)
- {
-     return true;
---
-.31.1

-[PULL 12/61] target/riscv: Add host cpu type
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-'host' type cpu is set isa to RV32 or RV64 simply, more isa info
-will obtain from KVM in kvm_arch_init_vcpu()
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h |  1 +
- target/riscv/cpu.c | 15 +++++++++++++++
-files changed, 16 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
- #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
- #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
-+#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
- #if defined(TARGET_RISCV32)
- # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
- }
- #endif
-+#if defined(CONFIG_KVM)
-+static void riscv_host_cpu_init(Object *obj)
-+{
-+    CPURISCVState *env = &RISCV_CPU(obj)->env;
-+#if defined(TARGET_RISCV32)
-+    set_misa(env, MXL_RV32, 0);
-+#elif defined(TARGET_RISCV64)
-+    set_misa(env, MXL_RV64, 0);
-+#endif
-+}
-+#endif
-+
- static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
- {
-     ObjectClass *oc;
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-         .class_init = riscv_cpu_class_init,
-     },
-     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
-+#if defined(CONFIG_KVM)
-+    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
-+#endif
- #if defined(TARGET_RISCV32)
-     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
-     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
---
-.31.1

-[PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
-from KVM.
-To set register of RISCV_TIMER_REG(state) will occur a error from KVM
-on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
-that adaping in QEMU.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h |  7 +++++
- target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
-files changed, 79 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     hwaddr kernel_addr;
-     hwaddr fdt_addr;
-+
-+    /* kvm timer */
-+    bool kvm_timer_dirty;
-+    uint64_t kvm_timer_time;
-+    uint64_t kvm_timer_compare;
-+    uint64_t kvm_timer_state;
-+    uint64_t kvm_timer_frequency;
- };
- OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@
- #include "kvm_riscv.h"
- #include "sbi_ecall_interface.h"
- #include "chardev/char-fe.h"
-+#include "migration/migration.h"
- static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-                                  uint64_t idx)
-@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
- #define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
-                  KVM_REG_RISCV_CSR_REG(name))
-+#define RISCV_TIMER_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
-+                 KVM_REG_RISCV_TIMER_REG(name))
-+
- #define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
- #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
-@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-         } \
-     } while (0)
-+#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
-+    do { \
-+        int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
-+        if (ret) { \
-+            abort(); \
-+        } \
-+    } while (0)
-+
-+#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
-+    do { \
-+        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
-+        if (ret) { \
-+            abort(); \
-+        } \
-+    } while (0)
-+
- static int kvm_riscv_get_regs_core(CPUState *cs)
- {
-     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
-     return ret;
- }
-+static void kvm_riscv_get_regs_timer(CPUState *cs)
-+{
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    if (env->kvm_timer_dirty) {
-+        return;
-+    }
-+
-+    KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
-+    KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
-+    KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
-+    KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
-+
-+    env->kvm_timer_dirty = true;
-+}
-+
-+static void kvm_riscv_put_regs_timer(CPUState *cs)
-+{
-+    uint64_t reg;
-+    CPURISCVState *env = &RISCV_CPU(cs)->env;
-+
-+    if (!env->kvm_timer_dirty) {
-+        return;
-+    }
-+
-+    KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
-+    KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
-+
-+    /*
-+     * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
-+     * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
-+     * doesn't matter that adaping in QEMU now.
-+     * TODO If KVM changes, adapt here.
-+     */
-+    if (env->kvm_timer_state) {
-+        KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
-+    }
-+
-+    /*
-+     * For now, migration will not work between Hosts with different timer
-+     * frequency. Therefore, we should check whether they are the same here
-+     * during the migration.
-+     */
-+    if (migration_is_running(migrate_get_current()->state)) {
-+        KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
-+        if (reg != env->kvm_timer_frequency) {
-+            error_report("Dst Hosts timer frequency != Src Hosts");
-+        }
-+    }
-+
-+    env->kvm_timer_dirty = false;
-+}
- const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-     KVM_CAP_LAST_INFO
---
-.31.1

-[PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-We hope that virtual time adjusts with vm state changing. When a vm
-is stopped, guest virtual time should stop counting and kvm_timer
-should be stopped. When the vm is resumed, guest virtual time should
-continue to count and kvm_timer should be restored.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220112081329.1835-12-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/kvm.c | 15 +++++++++++++++
-file changed, 15 insertions(+)
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
-+++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@
- #include "sbi_ecall_interface.h"
- #include "chardev/char-fe.h"
- #include "migration/migration.h"
-+#include "sysemu/runstate.h"
- static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-                                  uint64_t idx)
-@@ -XXX,XX +XXX,XX @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
-     return cpu->cpu_index;
- }
-+static void kvm_riscv_vm_state_change(void *opaque, bool running,
-+                                      RunState state)
-+{
-+    CPUState *cs = opaque;
-+
-+    if (running) {
-+        kvm_riscv_put_regs_timer(cs);
-+    } else {
-+        kvm_riscv_get_regs_timer(cs);
-+    }
-+}
-+
- void kvm_arch_init_irq_routing(KVMState *s)
- {
- }
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
-     CPURISCVState *env = &cpu->env;
-     uint64_t id;
-+    qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
-+
-     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
-                           KVM_REG_RISCV_CONFIG_REG(isa));
-     ret = kvm_get_one_reg(cs, id, &isa);
---
-.31.1

-[PULL 15/61] target/riscv: Support virtual time context synchronization
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Add virtual time context description to vmstate_kvmtimer. After cpu being
-loaded, virtual time context is updated to KVM.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Anup Patel <anup.patel@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
-file changed, 30 insertions(+)
-diff --git a/target/riscv/machine.c b/target/riscv/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/machine.c
-+++ b/target/riscv/machine.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_rv128 = {
-     }
- };
-+static bool kvmtimer_needed(void *opaque)
-+{
-+    return kvm_enabled();
-+}
-+
-+static int cpu_post_load(void *opaque, int version_id)
-+{
-+    RISCVCPU *cpu = opaque;
-+    CPURISCVState *env = &cpu->env;
-+
-+    env->kvm_timer_dirty = true;
-+    return 0;
-+}
-+
-+static const VMStateDescription vmstate_kvmtimer = {
-+    .name = "cpu/kvmtimer",
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-+    .needed = kvmtimer_needed,
-+    .post_load = cpu_post_load,
-+    .fields = (VMStateField[]) {
-+        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
-+        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
-+        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
-+
-+        VMSTATE_END_OF_LIST()
-+    }
-+};
-+
- const VMStateDescription vmstate_riscv_cpu = {
-     .name = "cpu",
-     .version_id = 3,
-@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
-         &vmstate_vector,
-         &vmstate_pointermasking,
-         &vmstate_rv128,
-+        &vmstate_kvmtimer,
-         NULL
-     }
- };
---
-.31.1

-[PULL 16/61] target/riscv: enable riscv kvm accel
+Deleted patch
-From: Yifei Jiang <jiangyifei@huawei.com>
-Add riscv kvm support in meson.build file.
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Anup Patel <anup@brainfault.org>
-Message-id: 20220112081329.1835-14-jiangyifei@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- meson.build | 2 ++
-file changed, 2 insertions(+)
-diff --git a/meson.build b/meson.build
-index XXXXXXX..XXXXXXX 100644
---- a/meson.build
-+++ b/meson.build
-@@ -XXX,XX +XXX,XX @@ elif cpu in ['ppc', 'ppc64']
-   kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
- elif cpu in ['mips', 'mips64']
-   kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
-+elif cpu in ['riscv']
-+  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
- else
-   kvm_targets = []
- endif
---
-.31.1

-[PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers
+Deleted patch
-From: Thomas Huth <thuth@redhat.com>
-If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
-complains:
-.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
-.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
- in this function [-Werror=maybe-uninitialized]
-     int namelen, retval;
-                  ^~~~~~
-It's a false warning since the while loop is always executed at least
-once (p has to be non-NULL, otherwise the derefence in the if-statement
-earlier will crash). Thus let's switch to a do-while loop here instead
-to make the compiler happy in all cases.
-Signed-off-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Andrew Jones <drjones@redhat.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
-Message-id: 20220107133844.145039-1-thuth@redhat.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- softmmu/device_tree.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
-index XXXXXXX..XXXXXXX 100644
---- a/softmmu/device_tree.c
-+++ b/softmmu/device_tree.c
-@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
-         return -1;
-     }
--    while (p) {
-+    do {
-         name = p + 1;
-         p = strchr(name, '/');
-         namelen = p != NULL ? p - name : strlen(name);
-@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
-         }
-         parent = retval;
--    }
-+    } while (p);
-     return retval;
- }
---
-.31.1

-[PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment
+Deleted patch
-From: Yanan Wang <wangyanan55@huawei.com>
-The pointer assignment "const char *p = path;" in function
-qemu_fdt_add_path is unnecessary. Let's remove it and just
-use the "path" passed in. No functional change.
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
-Reviewed-by: Andrew Jones <drjones@redhat.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Thomas Huth <thuth@redhat.com>
-Message-id: 20220111032758.27804-1-wangyanan55@huawei.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- softmmu/device_tree.c | 9 ++++-----
-file changed, 4 insertions(+), 5 deletions(-)
-diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
-index XXXXXXX..XXXXXXX 100644
---- a/softmmu/device_tree.c
-+++ b/softmmu/device_tree.c
-@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
- int qemu_fdt_add_path(void *fdt, const char *path)
- {
-     const char *name;
--    const char *p = path;
-     int namelen, retval;
-     int parent = 0;
-@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
-     }
-     do {
--        name = p + 1;
--        p = strchr(name, '/');
--        namelen = p != NULL ? p - name : strlen(name);
-+        name = path + 1;
-+        path = strchr(name, '/');
-+        namelen = path != NULL ? path - name : strlen(name);
-         retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
-         if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
-@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
-         }
-         parent = retval;
--    } while (p);
-+    } while (path);
-     return retval;
- }
---
-.31.1

-[PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-All Zve* extensions support the vector configuration instructions.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-3-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
-file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
- {
-     TCGv s1, dst;
--    if (!require_rvv(s) || !has_ext(s, RVV)) {
-+    if (!require_rvv(s) ||
-+        !(has_ext(s, RVV) || s->ext_zve64f)) {
-         return false;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
- {
-     TCGv dst;
--    if (!require_rvv(s) || !has_ext(s, RVV)) {
-+    if (!require_rvv(s) ||
-+        !(has_ext(s, RVV) || s->ext_zve64f)) {
-         return false;
-     }
---
-.31.1

-[PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-All Zve* extensions support all vector load and store instructions,
-except Zve64* extensions do not support EEW=64 for index values when
-XLEN=32.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-4-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
-file changed, 15 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
-                                 uint8_t eew)
- {
-     int8_t emul = eew - s->sew + s->lmul;
--    return (emul >= -3 && emul <= 3) &&
--            require_align(vs2, emul) &&
--            require_align(vd, s->lmul) &&
--            require_nf(vd, nf, s->lmul);
-+    bool ret = (emul >= -3 && emul <= 3) &&
-+               require_align(vs2, emul) &&
-+               require_align(vd, s->lmul) &&
-+               require_nf(vd, nf, s->lmul);
-+
-+    /*
-+     * All Zve* extensions support all vector load and store instructions,
-+     * except Zve64* extensions do not support EEW=64 for index values
-+     * when XLEN=32. (Section 18.2)
-+     */
-+    if (get_xl(s) == MXL_RV32) {
-+        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
-+    }
-+
-+    return ret;
- }
- /*
---
-.31.1

-[PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-All Zve* extensions support all vector integer instructions,
-except that the vmulh integer multiply variants that return the
-high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
-vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-5-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
-file changed, 33 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
- GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
- /* Vector Single-Width Integer Multiply Instructions */
-+
-+static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
-+{
-+    /*
-+     * All Zve* extensions support all vector integer instructions,
-+     * except that the vmulh integer multiply variants
-+     * that return the high word of the product
-+     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
-+     * are not included for EEW=64 in Zve64*. (Section 18.2)
-+     */
-+    return opivv_check(s, a) &&
-+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
-+}
-+
-+static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
-+{
-+    /*
-+     * All Zve* extensions support all vector integer instructions,
-+     * except that the vmulh integer multiply variants
-+     * that return the high word of the product
-+     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
-+     * are not included for EEW=64 in Zve64*. (Section 18.2)
-+     */
-+    return opivx_check(s, a) &&
-+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
-+}
-+
- GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
--GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
--GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
--GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
-+GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
-+GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
-+GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
- GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
--GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
--GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
--GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
-+GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
-+GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
-+GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
- /* Vector Integer Divide Instructions */
- GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
---
-.31.1

-[PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-All Zve* extensions support all vector fixed-point arithmetic
-instructions, except that vsmul.vv and vsmul.vx are not supported
-for EEW=64 in Zve64*.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-6-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
-file changed, 25 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
- GEN_OPIVX_TRANS(vasubu_vx,  opivx_check)
- /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
--GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
--GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
-+
-+static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
-+{
-+    /*
-+     * All Zve* extensions support all vector fixed-point arithmetic
-+     * instructions, except that vsmul.vv and vsmul.vx are not supported
-+     * for EEW=64 in Zve64*. (Section 18.2)
-+     */
-+    return opivv_check(s, a) &&
-+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
-+}
-+
-+static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
-+{
-+    /*
-+     * All Zve* extensions support all vector fixed-point arithmetic
-+     * instructions, except that vsmul.vv and vsmul.vx are not supported
-+     * for EEW=64 in Zve64*. (Section 18.2)
-+     */
-+    return opivx_check(s, a) &&
-+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
-+}
-+
-+GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
-+GEN_OPIVX_TRANS(vsmul_vx,  vsmul_vx_check)
- /* Vector Single-Width Scaling Shift Instructions */
- GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
---
-.31.1

-[PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Frank Chang <frank.chang@sifive.com>
+From: Max Chou <max.chou@sifive.com>
-Zve32f extension requires the scalar processor to implement the F
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-extension and implement all vector floating-point instructions for
+instructions will be affected by Zvfhmin extension.
-floating-point operands with EEW=32 (i.e., no widening floating-point
+And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
-operations).
+conversions of
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Message-id: 20220118014522.13613-14-frank.chang@sifive.com
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
-file changed, 21 insertions(+)
+file changed, 18 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
      }
  }
-+static bool require_zve32f(DisasContext *s)
++static bool require_rvfmin(DisasContext *s)
 +{
-+    /* RVV + Zve32f = RVV. */
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+    if (has_ext(s, RVV)) {
++        return false;
 +        return true;
 +    }
 +
-+    /* Zve32f doesn't support FP64. (Section 18.2) */
++    switch (s->sew) {
-+    return s->ext_zve32f ? s->sew <= MO_32 : true;
++    case MO_16:
 +        return s->cfg_ptr->ext_zvfhmin;
 +    case MO_32:
 +        return s->cfg_ptr->ext_zve32f;
 +    default:
 +        return false;
 +    }
 +}
 +
- static bool require_zve64f(DisasContext *s)
+ static bool require_scale_rvf(DisasContext *s)
  {
-     /* RVV + Zve64f = RVV. */
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
-            require_rvf(s) &&
+     }
-            vext_check_isa_ill(s) &&
-            vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+     switch (s->sew) {
-+           require_zve32f(s) &&
+-    case MO_8:
-            require_zve64f(s);
+-        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-            require_rvf(s) &&
+ {
-            vext_check_isa_ill(s) &&
+     return opfv_narrow_check(s, a) &&
-            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           require_rvfmin(s) &&
-+           require_zve32f(s) &&
+            require_scale_rvfmin(s) &&
-            require_zve64f(s);
+            (s->sew != MO_8);
  }
-@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
-            vext_check_isa_ill(s) &&
-            /* OPFV instructions ignore vs1 check */
-            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
-            require_rvf(s) &&
-            vext_check_isa_ill(s) &&
-            vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
-            require_rvf(s) &&
-            vext_check_isa_ill(s) &&
-            vext_check_ms(s, a->rd, a->rs2) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
-         require_rvf(s) &&
-         vext_check_isa_ill(s) &&
-         require_align(a->rd, s->lmul) &&
-+        require_zve32f(s) &&
-         require_zve64f(s)) {
-         gen_set_rm(s, RISCV_FRM_DYN);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
-     if (require_rvv(s) &&
-         require_rvf(s) &&
-         vext_check_isa_ill(s) &&
-+        require_zve32f(s) &&
-         require_zve64f(s)) {
-         gen_set_rm(s, RISCV_FRM_DYN);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
-     if (require_rvv(s) &&
-         require_rvf(s) &&
-         vext_check_isa_ill(s) &&
-+        require_zve32f(s) &&
-         require_zve64f(s)) {
-         gen_set_rm(s, RISCV_FRM_DYN);
-@@ -XXX,XX +XXX,XX @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
- {
-     return slideup_check(s, a) &&
-            require_rvf(s) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
- {
-     return slidedown_check(s, a) &&
-            require_rvf(s) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
 --
-.31.1
+.45.1

-[PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Frank Chang <frank.chang@sifive.com>
+From: Max Chou <max.chou@sifive.com>
-Vector widening conversion instructions are provided to and from all
+The require_scale_rvf function only checks the double width operator for
-supported integer EEWs for Zve64f extension.
+the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+integer to double width float, so the opfxv_widen_check function doesn’t
-Message-id: 20220118014522.13613-9-frank.chang@sifive.com
+need require_rvf for the single width operator(integer).
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
-file changed, 25 insertions(+), 7 deletions(-)
+file changed, 5 insertions(+)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
-     return s->ext_zve64f ? s->sew <= MO_32 : true;
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
  }
 +static bool require_scale_zve64f(DisasContext *s)
 +{
 +    /* RVV + Zve64f = RVV. */
 +    if (has_ext(s, RVV)) {
 +        return true;
 +    }
 +
 +    /* Zve64f doesn't support FP64. (Section 18.2) */
 +    return s->ext_zve64f ? s->sew <= MO_16 : true;
 +}
 +
  /* Destination vector register group cannot overlap source mask register. */
  static bool require_vm(int vm, int vd)
  {
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
-+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-+           require_scale_zve64f(s);
+ {
- }
+     return require_rvv(s) &&
++           require_rvf(s) &&
  /* OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_ds(s, a->rd, a->rs2, a->vm);
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
-+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-+           require_scale_zve64f(s);
+ {
- }
+     return require_rvv(s) &&
++           require_rvf(s) &&
  /* OPFVF with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
-+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
-+           require_scale_zve64f(s);
+ {
- }
+     return require_rvv(s) &&
++           require_rvf(s) &&
  /* WIDEN OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_dd(s, a->rd, a->rs2, a->vm);
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
-+           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
-+           require_scale_zve64f(s);
+ {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
- /* WIDEN OPFVF with WIDEN */
-@@ -XXX,XX +XXX,XX @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
- static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
- {
-     return opfv_widen_check(s, a) &&
--           require_rvf(s);
-+           require_rvf(s) &&
-+           require_zve64f(s);
- }
- static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
- {
-     return opfv_widen_check(s, a) &&
-            require_scale_rvf(s) &&
--           (s->sew != MO_8);
-+           (s->sew != MO_8) &&
-+           require_scale_zve64f(s);
- }
- #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
-            require_scale_rvf(s) &&
-            vext_check_isa_ill(s) &&
-            /* OPFV widening instructions ignore vs1 check */
--           vext_check_ds(s, a->rd, a->rs2, a->vm);
-+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve64f(s);
- }
- #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
 --
-.31.1
+.45.1

-[PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Frank Chang <frank.chang@sifive.com>
+From: Max Chou <max.chou@sifive.com>
-Vector single-width floating-point reduction operations for EEW=32 are
+The opfv_narrow_check needs to check the single width float operator by
-supported for Zve32f extension.
+require_rvf.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20220118014522.13613-15-frank.chang@sifive.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 file changed, 1 insertion(+)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
-     return reduction_check(s, a) &&
+     return opfv_narrow_check(s, a) &&
-            require_rvf(s) &&
++           require_rvf(s) &&
-+           require_zve32f(s) &&
+            require_scale_rvf(s) &&
-            require_zve64f(s);
+            (s->sew != MO_8);
  }
 --
-.31.1
+.45.1

-[PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Frank Chang <frank.chang@sifive.com>
+From: Max Chou <max.chou@sifive.com>
-Zve64f extension requires the scalar processor to implement the F
+If the checking functions check both the single and double width
-extension and implement all vector floating-point instructions for
+operators at the same time, then the single width operator checking
-floating-point operands with EEW=32 (i.e., no widening floating-point
+functions (require_rvf[min]) will check whether the SEW is 8.
 operations).
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20220118014522.13613-7-frank.chang@sifive.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
-file changed, 31 insertions(+), 10 deletions(-)
+file changed, 4 insertions(+), 12 deletions(-)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
      }
  }
 +static bool require_zve64f(DisasContext *s)
 +{
 +    /* RVV + Zve64f = RVV. */
 +    if (has_ext(s, RVV)) {
 +        return true;
 +    }
 +
 +    /* Zve64f doesn't support FP64. (Section 18.2) */
 +    return s->ext_zve64f ? s->sew <= MO_32 : true;
 +}
 +
  /* Destination vector register group cannot overlap source mask register. */
  static bool require_vm(int vm, int vd)
  {
@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 +           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
 +           require_zve64f(s);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  /* OPFVV without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_ss(s, a->rd, a->rs2, a->vm);
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
 +           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
 +           require_zve64f(s);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  /* OPFVF without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
             require_rvf(s) &&
             vext_check_isa_ill(s) &&
             /* OPFV instructions ignore vs1 check */
 -           vext_check_ss(s, a->rd, a->rs2, a->vm);
 +           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
 +           require_zve64f(s);
  }
  static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 +           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
 +           require_zve64f(s);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
--           vext_check_ms(s, a->rd, a->rs2);
+            vext_check_dd(s, a->rd, a->rs2, a->vm);
 +           vext_check_ms(s, a->rd, a->rs2) &&
 +           require_zve64f(s);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
      if (require_rvv(s) &&
          require_rvf(s) &&
          vext_check_isa_ill(s) &&
 -        require_align(a->rd, s->lmul)) {
 +        require_align(a->rd, s->lmul) &&
 +        require_zve64f(s)) {
          gen_set_rm(s, RISCV_FRM_DYN);
          TCGv_i64 t1;
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
  {
-     if (require_rvv(s) &&
+     return opfv_widen_check(s, a) &&
-         require_rvf(s) &&
+            require_rvfmin(s) &&
--        vext_check_isa_ill(s)) {
+-           require_scale_rvfmin(s) &&
-+        vext_check_isa_ill(s) &&
+-           (s->sew != MO_8);
-+        require_zve64f(s)) {
++           require_scale_rvfmin(s);
-         gen_set_rm(s, RISCV_FRM_DYN);
+ }
-         unsigned int ofs = (8 << s->sew);
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
-     if (require_rvv(s) &&
+     return opfv_narrow_check(s, a) &&
-         require_rvf(s) &&
+            require_rvfmin(s) &&
--        vext_check_isa_ill(s)) {
+-           require_scale_rvfmin(s) &&
-+        vext_check_isa_ill(s) &&
+-           (s->sew != MO_8);
-+        require_zve64f(s)) {
++           require_scale_rvfmin(s);
-         gen_set_rm(s, RISCV_FRM_DYN);
+ }
-         /* The instructions ignore LMUL and vector register group. */
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
  static bool fslideup_check(DisasContext *s, arg_rmrr *a)
  {
-     return slideup_check(s, a) &&
+     return opfv_narrow_check(s, a) &&
--           require_rvf(s);
+            require_rvf(s) &&
-+           require_rvf(s) &&
+-           require_scale_rvf(s) &&
-+           require_zve64f(s);
+-           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
- static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
-     return slidedown_check(s, a) &&
+     return reduction_widen_check(s, a) &&
--           require_rvf(s);
+            require_rvf(s) &&
-+           require_rvf(s) &&
+-           require_scale_rvf(s) &&
-+           require_zve64f(s);
+-           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
- GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.31.1
+.45.1

-[PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Vector single-width floating-point reduction operations for EEW=32 are
-supported for Zve64f extension.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-8-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
-file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
- static bool freduction_check(DisasContext *s, arg_rmrr *a)
- {
-     return reduction_check(s, a) &&
--           require_rvf(s);
-+           require_rvf(s) &&
-+           require_zve64f(s);
- }
- GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
---
-.31.1

-[PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Vector narrowing conversion instructions are provided to and from all
-supported integer EEWs for Zve64f extension.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-10-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
-file changed, 6 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
- {
-     return opfv_narrow_check(s, a) &&
-            require_rvf(s) &&
--           (s->sew != MO_64);
-+           (s->sew != MO_64) &&
-+           require_zve64f(s);
- }
- static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
- {
-     return opfv_narrow_check(s, a) &&
-            require_scale_rvf(s) &&
--           (s->sew != MO_8);
-+           (s->sew != MO_8) &&
-+           require_scale_zve64f(s);
- }
- #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
-@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
-            require_scale_rvf(s) &&
-            vext_check_isa_ill(s) &&
-            /* OPFV narrowing instructions ignore vs1 check */
--           vext_check_sd(s, a->rd, a->rs2, a->vm);
-+           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve64f(s);
- }
- #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
---
-.31.1

-[PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
-From: Frank Chang <frank.chang@sifive.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
 checking first if virt_enabled && !first_stage, and then considering the
 regular inst/load/store faults.
 There's no mention in the spec about guest page fault being a higher
 priority that PMP faults. In fact, privileged spec section 3.7.1 says:
 "Attempting to fetch an instruction from a PMP region that does not have
 execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
 So, in fact, we're doing it wrong - PMP faults should always be thrown,
 regardless of also being a first or second stage fault.
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-12-frank.chang@sifive.com
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 1 +
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
- target/riscv/cpu.c        | 4 ++--
+file changed, 12 insertions(+), 10 deletions(-)
  target/riscv/cpu_helper.c | 2 +-
  target/riscv/csr.c        | 2 +-
  target/riscv/translate.c  | 2 ++
 files changed, 7 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
-         bool ext_icsr;
-         bool ext_zfh;
-         bool ext_zfhmin;
-+        bool ext_zve32f;
-         bool ext_zve64f;
-         char *priv_spec;
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-             }
-             set_vext_version(env, vext_version);
-         }
--        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
--            error_setg(errp, "Zve64f extension depends upon RVF.");
-+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
-+            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
-             return;
-         }
-         if (cpu->cfg.ext_j) {
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     *pc = env->pc;
-     *cs_base = 0;
+     switch (access_type) {
+     case MMU_INST_FETCH:
--    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+-        if (env->virt_enabled && !first_stage) {
-+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
++        if (pmp_violation) {
-         /*
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-          * If env->vl equals to VLMAX, we can use generic vector operation
++        } else if (env->virt_enabled && !first_stage) {
-          * expanders (GVEC) to accerlate the vector operations.
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+         } else {
-index XXXXXXX..XXXXXXX 100644
+-            cs->exception_index = pmp_violation ?
---- a/target/riscv/csr.c
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-+++ b/target/riscv/csr.c
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
-@@ -XXX,XX +XXX,XX @@ static RISCVException vs(CPURISCVState *env, int csrno)
+         }
-     RISCVCPU *cpu = RISCV_CPU(cs);
+         break;
+     case MMU_DATA_LOAD:
-     if (env->misa_ext & RVV ||
+-        if (two_stage && !first_stage) {
--        cpu->cfg.ext_zve64f) {
++        if (pmp_violation) {
-+        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
- #if !defined(CONFIG_USER_ONLY)
++        } else if (two_stage && !first_stage) {
-         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
-             return RISCV_EXCP_ILLEGAL_INST;
+         } else {
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+-            cs->exception_index = pmp_violation ?
-index XXXXXXX..XXXXXXX 100644
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
---- a/target/riscv/translate.c
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
-+++ b/target/riscv/translate.c
+         }
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+         break;
-     bool ext_ifencei;
+     case MMU_DATA_STORE:
-     bool ext_zfh;
+-        if (two_stage && !first_stage) {
-     bool ext_zfhmin;
++        if (pmp_violation) {
-+    bool ext_zve32f;
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-     bool ext_zve64f;
++        } else if (two_stage && !first_stage) {
-     bool hlsx;
+             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
-     /* vector extension */
+         } else {
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+-            cs->exception_index = pmp_violation ?
-     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-     ctx->ext_zfh = cpu->cfg.ext_zfh;
+-                RISCV_EXCP_STORE_PAGE_FAULT;
-     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
++            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
-+    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
+         }
-     ctx->ext_zve64f = cpu->cfg.ext_zve64f;
+         break;
-     ctx->vlen = cpu->cfg.vlen;
+     default:
      ctx->elen = cpu->cfg.elen;
 --
-.31.1
+.45.1

-[PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-All Zve* extensions support the vector configuration instructions.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-13-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
-     TCGv s1, dst;
-     if (!require_rvv(s) ||
--        !(has_ext(s, RVV) || s->ext_zve64f)) {
-+        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
-         return false;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
-     TCGv dst;
-     if (!require_rvv(s) ||
--        !(has_ext(s, RVV) || s->ext_zve64f)) {
-+        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
-         return false;
-     }
---
-.31.1

-[PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Vector widening conversion instructions are provided to and from all
-supported integer EEWs for Zve32f extension.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-16-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
-file changed, 18 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool require_zve32f(DisasContext *s)
-     return s->ext_zve32f ? s->sew <= MO_32 : true;
- }
-+static bool require_scale_zve32f(DisasContext *s)
-+{
-+    /* RVV + Zve32f = RVV. */
-+    if (has_ext(s, RVV)) {
-+        return true;
-+    }
-+
-+    /* Zve32f doesn't support FP64. (Section 18.2) */
-+    return s->ext_zve64f ? s->sew <= MO_16 : true;
-+}
-+
- static bool require_zve64f(DisasContext *s)
- {
-     /* RVV + Zve64f = RVV. */
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-            (s->sew != MO_8) &&
-            vext_check_isa_ill(s) &&
-            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-            (s->sew != MO_8) &&
-            vext_check_isa_ill(s) &&
-            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-            (s->sew != MO_8) &&
-            vext_check_isa_ill(s) &&
-            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
-            (s->sew != MO_8) &&
-            vext_check_isa_ill(s) &&
-            vext_check_dd(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
- {
-     return opfv_widen_check(s, a) &&
-            require_rvf(s) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
-     return opfv_widen_check(s, a) &&
-            require_scale_rvf(s) &&
-            (s->sew != MO_8) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
-            vext_check_isa_ill(s) &&
-            /* OPFV widening instructions ignore vs1 check */
-            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
---
-.31.1

-[PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Vector narrowing conversion instructions are provided to and from all
-supported integer EEWs for Zve32f extension.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-17-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
-file changed, 3 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
-     return opfv_narrow_check(s, a) &&
-            require_rvf(s) &&
-            (s->sew != MO_64) &&
-+           require_zve32f(s) &&
-            require_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-     return opfv_narrow_check(s, a) &&
-            require_scale_rvf(s) &&
-            (s->sew != MO_8) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
-            vext_check_isa_ill(s) &&
-            /* OPFV narrowing instructions ignore vs1 check */
-            vext_check_sd(s, a->rd, a->rs2, a->vm) &&
-+           require_scale_zve32f(s) &&
-            require_scale_zve64f(s);
- }
---
-.31.1

-[PULL 44/61] target/riscv: Ignore the pc bits above XLEN
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
 setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
 translation part, mtval2 will be set in case of successes 2 stage translation but
 failed pmp check.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ target/riscv/cpu_helper.c | 12 ++++++------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 6 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                               __func__, pa, ret, prot_pmp, tlb_size);
-     uint32_t flags = 0;
+                 prot &= prot_pmp;
--    *pc = env->pc;
+-            }
-+    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+-
-     *cs_base = 0;
+-            if (ret != TRANSLATE_SUCCESS) {
++            } else {
-     if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+                 /*
                   * Guest physical address translation failed, this is a HS
                   * level exception
                   */
                  first_stage_error = false;
 -                env->guest_phys_fault_addr = (im_address |
 -                                              (address &
 -                                               (TARGET_PAGE_SIZE - 1))) >> 2;
 +                if (ret != TRANSLATE_PMP_FAIL) {
 +                    env->guest_phys_fault_addr = (im_address |
 +                                                  (address &
 +                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
 +                }
              }
          }
      } else {
 --
-.31.1
+.45.1

-[PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Frank Chang <frank.chang@sifive.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+This extension has now been ratified:
 https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
 Since this is now a ratified extension add it to the list of extensions
 included in the "max" CPU variant.
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220118014522.13613-18-frank.chang@sifive.com
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 1 +
+ target/riscv/cpu.c         | 2 +-
-file changed, 1 insertion(+)
+ target/riscv/tcg/tcg-cpu.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
-     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-+    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
-     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
-     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ };
-     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
  static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
      const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
 -    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
 +    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
          isa_ext_update_enabled(cpu, prop->offset, true);
 --
-.31.1
+.45.1

-[PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios
+Deleted patch
-From: Anup Patel <apatel@ventanamicro.com>
-Currently, we have to use OpenSBI firmware ELF as bios for the spike
-machine because the HTIF console requires ELF for parsing "fromhost"
-and "tohost" symbols.
-The latest OpenSBI can now optionally pick-up HTIF register address
-from HTIF DT node so using this feature spike machine can now use
-OpenSBI firmware BIN as bios.
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/riscv_htif.h |  5 ++++-
- include/hw/riscv/spike.h     |  1 +
- hw/char/riscv_htif.c         | 33 +++++++++++++++++++----------
- hw/riscv/spike.c             | 41 ++++++++++++++++++++++--------------
-files changed, 52 insertions(+), 28 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
-+++ b/include/hw/char/riscv_htif.h
-@@ -XXX,XX +XXX,XX @@ extern const MemoryRegionOps htif_io_ops;
- void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
-     uint64_t st_size);
-+/* Check if HTIF uses ELF symbols */
-+bool htif_uses_elf_symbols(void);
-+
- /* legacy pre qom */
- HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
--    CPURISCVState *env, Chardev *chr);
-+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
- #endif
-diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/spike.h
-+++ b/include/hw/riscv/spike.h
-@@ -XXX,XX +XXX,XX @@ struct SpikeState {
- enum {
-     SPIKE_MROM,
-+    SPIKE_HTIF,
-     SPIKE_CLINT,
-     SPIKE_DRAM
- };
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
-+++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
-     .write = htif_mm_write,
- };
-+bool htif_uses_elf_symbols(void)
-+{
-+    return (address_symbol_set == 3) ? true : false;
-+}
-+
- HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
--    CPURISCVState *env, Chardev *chr)
-+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
- {
--    uint64_t base = MIN(tohost_addr, fromhost_addr);
--    uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
--    uint64_t tohost_offset = tohost_addr - base;
--    uint64_t fromhost_offset = fromhost_addr - base;
-+    uint64_t base, size, tohost_offset, fromhost_offset;
-+
-+    if (!htif_uses_elf_symbols()) {
-+        fromhost_addr = nonelf_base;
-+        tohost_addr = nonelf_base + 8;
-+    }
-+
-+    base = MIN(tohost_addr, fromhost_addr);
-+    size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
-+    tohost_offset = tohost_addr - base;
-+    fromhost_offset = fromhost_addr - base;
-     HTIFState *s = g_malloc0(sizeof(HTIFState));
-     s->address_space = address_space;
-@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-     qemu_chr_fe_init(&s->chr, chr, &error_abort);
-     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
-         htif_be_change, s, NULL, true);
--    if (address_symbol_set == 3) {
--        memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
--                              TYPE_HTIF_UART, size);
--        memory_region_add_subregion_overlap(address_space, base,
--                                            &s->mmio, 1);
--    }
-+
-+    memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
-+                          TYPE_HTIF_UART, size);
-+    memory_region_add_subregion_overlap(address_space, base,
-+                                        &s->mmio, 1);
-     return s;
- }
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@
- static const MemMapEntry spike_memmap[] = {
-     [SPIKE_MROM] =     {     0x1000,     0xf000 },
-+    [SPIKE_HTIF] =     {  0x1000000,     0x1000 },
-     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
-     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
- };
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-     qemu_fdt_add_subnode(fdt, "/htif");
-     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
-+    if (!htif_uses_elf_symbols()) {
-+        qemu_fdt_setprop_cells(fdt, "/htif", "reg",
-+            0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
-+    }
-     qemu_fdt_add_subnode(fdt, "/soc");
-     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-     if (cmdline) {
-         qemu_fdt_add_subnode(fdt, "/chosen");
-         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-+        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
-         machine->ram);
--    /* create device tree */
--    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
--               riscv_is_32bit(&s->soc[0]));
--
-     /* boot rom */
-     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
-                            memmap[SPIKE_MROM].size, &error_fatal);
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-                                     htif_symbol_callback);
-     }
-+    /* Load kernel */
-     if (machine->kernel_filename) {
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
-                                                          firmware_end_addr);
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                          kernel_start_addr,
-                                          htif_symbol_callback);
--
--        if (machine->initrd_filename) {
--            hwaddr start;
--            hwaddr end = riscv_load_initrd(machine->initrd_filename,
--                                           machine->ram_size, kernel_entry,
--                                           &start);
--            qemu_fdt_setprop_cell(s->fdt, "/chosen",
--                                  "linux,initrd-start", start);
--            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
--                                  end);
--        }
-     } else {
-        /*
-         * If dynamic firmware is used, it doesn't know where is the next mode
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         kernel_entry = 0;
-     }
-+    /* Create device tree */
-+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-+               riscv_is_32bit(&s->soc[0]));
-+
-+    /* Load initrd */
-+    if (machine->kernel_filename && machine->initrd_filename) {
-+        hwaddr start;
-+        hwaddr end = riscv_load_initrd(machine->initrd_filename,
-+                                       machine->ram_size, kernel_entry,
-+                                       &start);
-+        qemu_fdt_setprop_cell(s->fdt, "/chosen",
-+                              "linux,initrd-start", start);
-+        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-+                              end);
-+    }
-+
-     /* Compute the fdt load address in dram */
-     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
-                                    machine->ram_size, s->fdt);
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     /* initialize HTIF using symbols found in load_kernel */
-     htif_mm_init(system_memory, mask_rom,
--                 &s->soc[0].harts[0].env, serial_hd(0));
-+                 &s->soc[0].harts[0].env, serial_hd(0),
-+                 memmap[SPIKE_HTIF].base);
- }
- static void spike_machine_instance_init(Object *obj)
---
-.31.1

-[PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names
+Deleted patch
-From: Anup Patel <apatel@ventanamicro.com>
-Now that RISC-V Spike machine can use BIN BIOS images, we remove
-the macros used for ELF BIOS image names.
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/boot.h | 2 --
- hw/riscv/spike.c        | 4 ++--
-files changed, 2 insertions(+), 4 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/riscv_hart.h"
- #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
--#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
- #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
--#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
- bool riscv_is_32bit(RISCVHartArrayState *harts);
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-      */
-     if (riscv_is_32bit(&s->soc[0])) {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
-+                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                     htif_symbol_callback);
-     } else {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
-+                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                     htif_symbol_callback);
-     }
---
-.31.1

-[PULL 38/61] roms/opensbi: Remove ELF images
+Deleted patch
-From: Anup Patel <apatel@ventanamicro.com>
-Now that all RISC-V machines can use OpenSBI BIN images, we remove
-OpenSBI ELF images and also exclude these images from BIOS build.
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- .gitlab-ci.d/opensbi.yml                       |   2 --
- pc-bios/meson.build                            |   2 --
- pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
- pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
- roms/Makefile                                  |   2 --
-files changed, 6 deletions(-)
- delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
- delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
-diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml
-index XXXXXXX..XXXXXXX 100644
---- a/.gitlab-ci.d/opensbi.yml
-+++ b/.gitlab-ci.d/opensbi.yml
-@@ -XXX,XX +XXX,XX @@ build-opensbi:
-  artifacts:
-    paths: # 'artifacts.zip' will contains the following files:
-    - pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
--   - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
-    - pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
--   - pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
-    - opensbi32-generic-stdout.log
-    - opensbi32-generic-stderr.log
-    - opensbi64-generic-stdout.log
-diff --git a/pc-bios/meson.build b/pc-bios/meson.build
-index XXXXXXX..XXXXXXX 100644
---- a/pc-bios/meson.build
-+++ b/pc-bios/meson.build
-@@ -XXX,XX +XXX,XX @@ blobs = files(
-   'hppa-firmware.img',
-   'opensbi-riscv32-generic-fw_dynamic.bin',
-   'opensbi-riscv64-generic-fw_dynamic.bin',
--  'opensbi-riscv32-generic-fw_dynamic.elf',
--  'opensbi-riscv64-generic-fw_dynamic.elf',
-   'npcm7xx_bootrom.bin',
- )
-diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
-deleted file mode 100644
-index XXXXXXX..XXXXXXX
-Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf and /dev/null differ
-diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
-deleted file mode 100644
-index XXXXXXX..XXXXXXX
-Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf and /dev/null differ
-diff --git a/roms/Makefile b/roms/Makefile
-index XXXXXXX..XXXXXXX 100644
---- a/roms/Makefile
-+++ b/roms/Makefile
-@@ -XXX,XX +XXX,XX @@ opensbi32-generic:
-         CROSS_COMPILE=$(riscv32_cross_prefix) \
-         PLATFORM="generic"
-     cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
--    cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
- opensbi64-generic:
-     $(MAKE) -C opensbi \
-         CROSS_COMPILE=$(riscv64_cross_prefix) \
-         PLATFORM="generic"
-     cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
--    cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
- MESON = meson
- NINJA = ninja
---
-.31.1

-[PULL 39/61] target/riscv: Adjust pmpcfg access with mxl
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 19 +++++++++++++++++++
- target/riscv/pmp.c | 12 ++++--------
-files changed, 23 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
- }
-+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
-+{
-+    /* TODO: RV128 restriction check */
-+    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
-+        return false;
-+    }
-+    return true;
-+}
-+
- static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
-                                   target_ulong *val)
- {
-+    uint32_t reg_index = csrno - CSR_PMPCFG0;
-+
-+    if (!check_pmp_reg_index(env, reg_index)) {
-+        return RISCV_EXCP_ILLEGAL_INST;
-+    }
-     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
-     return RISCV_EXCP_NONE;
- }
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
- static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
-                                    target_ulong val)
- {
-+    uint32_t reg_index = csrno - CSR_PMPCFG0;
-+
-+    if (!check_pmp_reg_index(env, reg_index)) {
-+        return RISCV_EXCP_ILLEGAL_INST;
-+    }
-     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
-     return RISCV_EXCP_NONE;
- }
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
- {
-     int i;
-     uint8_t cfg_val;
-+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
-     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
--    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
--        qemu_log_mask(LOG_GUEST_ERROR,
--                      "ignoring pmpcfg write - incorrect address\n");
--        return;
--    }
--
--    for (i = 0; i < sizeof(target_ulong); i++) {
-+    for (i = 0; i < pmpcfg_nums; i++) {
-         cfg_val = (val >> 8 * i)  & 0xff;
-         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
-     }
-@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
-     int i;
-     target_ulong cfg_val = 0;
-     target_ulong val = 0;
-+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
--    for (i = 0; i < sizeof(target_ulong); i++) {
-+    for (i = 0; i < pmpcfg_nums; i++) {
-         val = pmp_read_cfg(env, (reg_index * 4) + i);
-         cfg_val |= (val << (i * 8));
-     }
---
-.31.1

-[PULL 51/61] target/riscv: Calculate address according to XLEN
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Alistair Francis <alistair23@gmail.com>
-Define one common function to compute a canonical address from a register
+When running the instruction
 plus offset. Merge gen_pm_adjust_address into this function.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+```
     cbo.flush 0(x0)
 ```
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
+Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 25 ++++++++++++-------------
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- target/riscv/insn_trans/trans_rva.c.inc |  9 +++------
+file changed, 12 insertions(+), 4 deletions(-)
  target/riscv/insn_trans/trans_rvd.c.inc | 19 ++-----------------
  target/riscv/insn_trans/trans_rvf.c.inc | 19 ++-----------------
  target/riscv/insn_trans/trans_rvi.c.inc | 18 ++----------------
 files changed, 21 insertions(+), 69 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+@@ -XXX,XX +XXX,XX @@
-     ctx->base.is_jmp = DISAS_NORETURN;
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
  }
 -/*
 - * Generates address adjustment for PointerMasking
 - */
 -static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
 +/* Compute a canonical address from a register plus offset. */
 +static TCGv get_address(DisasContext *ctx, int rs1, int imm)
  {
--    TCGv temp;
+     REQUIRE_ZICBOM(ctx);
--    if (!s->pm_enabled) {
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
--        /* Load unmodified address */
++    TCGv src = get_address(ctx, a->rs1, 0);
 -        return src;
 -    } else {
 -        temp = temp_new(s);
 -        tcg_gen_andc_tl(temp, src, pm_mask);
 -        tcg_gen_or_tl(temp, temp, pm_base);
 -        return temp;
 +    TCGv addr = temp_new(ctx);
 +    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 +
-+    tcg_gen_addi_tl(addr, src1, imm);
++    gen_helper_cbo_clean_flush(tcg_env, src);
 +    if (ctx->pm_enabled) {
 +        tcg_gen_and_tl(addr, addr, pm_mask);
 +        tcg_gen_or_tl(addr, addr, pm_base);
 +    } else if (get_xl(ctx) == MXL_RV32) {
 +        tcg_gen_ext32u_tl(addr, addr);
      }
 +    return addr;
  }
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rva.c.inc
 +++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
  static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
  {
 -    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 +    TCGv src1 = get_address(ctx, a->rs1, 0);
      if (a->rl) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
      }
 -    src1 = gen_pm_adjust_address(ctx, src1);
      tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
      if (a->aq) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      TCGLabel *l1 = gen_new_label();
      TCGLabel *l2 = gen_new_label();
 -    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 -    src1 = gen_pm_adjust_address(ctx, src1);
 +    src1 = get_address(ctx, a->rs1, 0);
      tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
      /*
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                      MemOp mop)
  {
      TCGv dest = dest_gpr(ctx, a->rd);
 -    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +    TCGv src1 = get_address(ctx, a->rs1, 0);
      TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 -    src1 = gen_pm_adjust_address(ctx, src1);
      func(dest, src1, src2, ctx->mem_idx, mop);
      gen_set_gpr(ctx, a->rd, dest);
 diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvd.c.inc
 +++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
      mark_fs_dirty(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
 -
      return true;
  }
-diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/target/riscv/insn_trans/trans_rvf.c.inc
+     REQUIRE_ZICBOM(ctx);
-+++ b/target/riscv/insn_trans/trans_rvf.c.inc
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
++    TCGv src = get_address(ctx, a->rs1, 0);
-     REQUIRE_FPU;
++
-     REQUIRE_EXT(ctx, RVF);
++    gen_helper_cbo_clean_flush(tcg_env, src);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      dest = cpu_fpr[a->rd];
      tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
      gen_nanbox_s(dest, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = tcg_temp_new();
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
 -
      return true;
  }
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
  static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
  {
-     TCGv dest = dest_gpr(ctx, a->rd);
+     REQUIRE_ZICBOM(ctx);
--    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
--
++    TCGv src = get_address(ctx, a->rs1, 0);
--    if (a->imm) {
++
--        TCGv temp = temp_new(ctx);
++    gen_helper_cbo_inval(tcg_env, src);
--        tcg_gen_addi_tl(temp, addr, a->imm);
+     return true;
--        addr = temp;
+ }
--    }
--    addr = gen_pm_adjust_address(ctx, addr);
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 +    TCGv addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
      gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
  static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
  {
--    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+     REQUIRE_ZICBOZ(ctx);
-+    TCGv addr = get_address(ctx, a->rs1, a->imm);
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
-     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
++    TCGv src = get_address(ctx, a->rs1, 0);
++
--    if (a->imm) {
++    gen_helper_cbo_zero(tcg_env, src);
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
      tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
      return true;
  }
 --
-.31.1
+.45.1

-[PULL 41/61] target/riscv: Sign extend link reg for jal and jalr
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+In AIA spec, each hart (or each hart within a group) has a unique hart
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+number to locate the memory pages of interrupt files in the address
-Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
+space. The number of bits required to represent any hart number is equal
 to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
 However, if the largest hart number among groups is a power of 2, QEMU
 will pass an inaccurate hart-index-bit setting to Linux. For example, when
 the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
 to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
 Additionally, a Linux patch[1] is necessary to correctly recover the hart
 index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 4 +---
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
- target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
+file changed, 8 insertions(+), 1 deletion(-)
 files changed, 2 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
              return;
          }
      }
--    if (rd != 0) {
--        tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
--    }
++
++    if (max_hart_per_socket > 1) {
-+    gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
++        max_hart_per_socket--;
-     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-     ctx->base.is_jmp = DISAS_NORETURN;
++    } else {
- }
++        hart_bits = 0;
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
++    }
-index XXXXXXX..XXXXXXX 100644
++
---- a/target/riscv/insn_trans/trans_rvi.c.inc
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+                             &hart_bits, true, NULL);
          tcg_temp_free(t0);
      }
 -    if (a->rd != 0) {
 -        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
 -    }
 +    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
      tcg_gen_lookup_and_goto_ptr();
      if (misaligned) {
 --
-.31.1
+.45.1

-[PULL 46/61] target/riscv: Use gdb xml according to max mxlen
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+in bytes, when in this context we want 'reg_width' as the length in
 bits.
 Fix 'reg_width' back to the value in bits like 7cb59921c05a
 ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c     |  8 ++---
+ target/riscv/gdbstub.c | 6 +++---
- target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++-----------
+file changed, 3 insertions(+), 3 deletions(-)
 files changed, 55 insertions(+), 24 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     RISCVCPU *cpu = RISCV_CPU(dev);
-     CPURISCVState *env = &cpu->env;
-     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-+    CPUClass *cc = CPU_CLASS(mcc);
-     int priv_version = 0;
-     Error *local_err = NULL;
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     switch (env->misa_mxl_max) {
- #ifdef TARGET_RISCV64
-     case MXL_RV64:
-+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-         break;
-     case MXL_RV128:
-         break;
- #endif
-     case MXL_RV32:
-+        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-         break;
-     default:
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
-     cc->gdb_read_register = riscv_cpu_gdb_read_register;
-     cc->gdb_write_register = riscv_cpu_gdb_write_register;
-     cc->gdb_num_core_regs = 33;
--#if defined(TARGET_RISCV32)
--    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
--#elif defined(TARGET_RISCV64)
--    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
--#endif
-     cc->gdb_stop_before_watchpoint = true;
-     cc->disas_set_info = riscv_cpu_disas_set_info;
- #ifndef CONFIG_USER_ONLY
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/gdbstub.c
 +++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
  static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
-     CPURISCVState *env = &cpu->env;
+-    int reg_width = cpu->cfg.vlenb;
-+    target_ulong tmp;
++    int bitsize = cpu->cfg.vlenb << 3;
+     GDBFeatureBuilder builder;
-     if (n < 32) {
+     int i;
--        return gdb_get_regl(mem_buf, env->gpr[n]);
-+        tmp = env->gpr[n];
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     } else if (n == 32) {
--        return gdb_get_regl(mem_buf, env->pc);
+     /* First define types and totals in a whole VL */
-+        tmp = env->pc;
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-+    } else {
+-        int count = reg_width / vec_lanes[i].size;
-+        return 0;
++        int count = bitsize / vec_lanes[i].size;
-+    }
+         gdb_feature_builder_append_tag(
-+
+             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-+    switch (env->misa_mxl_max) {
+             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
-+    case MXL_RV32:
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-+        return gdb_get_reg32(mem_buf, tmp);
+     /* Define vector registers */
-+    case MXL_RV64:
+     for (i = 0; i < 32; i++) {
-+        return gdb_get_reg64(mem_buf, tmp);
+         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-+    default:
+-                                       reg_width, i, "riscv_vector", "vector");
-+        g_assert_not_reached();
++                                       bitsize, i, "riscv_vector", "vector");
      }
-     return 0;
- }
+     gdb_feature_builder_end(&builder);
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
      CPURISCVState *env = &cpu->env;
 -
 -    if (n == 0) {
 -        /* discard writes to x0 */
 -        return sizeof(target_ulong);
 -    } else if (n < 32) {
 -        env->gpr[n] = ldtul_p(mem_buf);
 -        return sizeof(target_ulong);
 +    int length = 0;
 +    target_ulong tmp;
 +
 +    switch (env->misa_mxl_max) {
 +    case MXL_RV32:
 +        tmp = (int32_t)ldl_p(mem_buf);
 +        length = 4;
 +        break;
 +    case MXL_RV64:
 +        if (env->xl < MXL_RV64) {
 +            tmp = (int32_t)ldq_p(mem_buf);
 +        } else {
 +            tmp = ldq_p(mem_buf);
 +        }
 +        length = 8;
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    if (n > 0 && n < 32) {
 +        env->gpr[n] = tmp;
      } else if (n == 32) {
 -        env->pc = ldtul_p(mem_buf);
 -        return sizeof(target_ulong);
 +        env->pc = tmp;
      }
 -    return 0;
 +
 +    return length;
  }
  static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                                                cs->gdb_num_regs),
                                   "riscv-vector.xml", 0);
      }
 -#if defined(TARGET_RISCV32)
 -    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
 -                             1, "riscv-32bit-virtual.xml", 0);
 -#elif defined(TARGET_RISCV64)
 -    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
 -                             1, "riscv-64bit-virtual.xml", 0);
 -#endif
 +    switch (env->misa_mxl_max) {
 +    case MXL_RV32:
 +        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
 +                                 riscv_gdb_set_virtual,
 +                                 1, "riscv-32bit-virtual.xml", 0);
 +        break;
 +    case MXL_RV64:
 +        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
 +                                 riscv_gdb_set_virtual,
 +                                 1, "riscv-64bit-virtual.xml", 0);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
      gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
                               riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
 --
-.31.1
+.45.1

-[PULL 56/61] target/riscv: Fix check range for first fault only
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Alistair Francis <alistair23@gmail.com>
-Only check the range that has passed the address translation.
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
 CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Fixes: ea10325917 ("RISC-V Disassembler")
-Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_helper.c | 4 ++--
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_helper.c
+--- a/disas/riscv.c
-+++ b/target/riscv/vector_helper.c
++++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-                                          cpu_mmu_index(env, false));
+     case 0x0383: return "mibound";
-                 if (host) {
+     case 0x0384: return "mdbase";
- #ifdef CONFIG_USER_ONLY
+     case 0x0385: return "mdbound";
--                    if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+-    case 0x03a0: return "pmpcfg3";
-+                    if (page_check_range(addr, offset, PAGE_READ) < 0) {
++    case 0x03a0: return "pmpcfg0";
-                         vl = i;
++    case 0x03a1: return "pmpcfg1";
-                         goto ProbeSuccess;
++    case 0x03a2: return "pmpcfg2";
-                     }
++    case 0x03a3: return "pmpcfg3";
- #else
++    case 0x03a4: return "pmpcfg4";
--                    probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
++    case 0x03a5: return "pmpcfg5";
-+                    probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
++    case 0x03a6: return "pmpcfg6";
- #endif
++    case 0x03a7: return "pmpcfg7";
-                 } else {
++    case 0x03a8: return "pmpcfg8";
-                     vl = i;
++    case 0x03a9: return "pmpcfg9";
 +    case 0x03aa: return "pmpcfg10";
 +    case 0x03ab: return "pmpcfg11";
 +    case 0x03ac: return "pmpcfg12";
 +    case 0x03ad: return "pmpcfg13";
 +    case 0x03ae: return "pmpcfg14";
 +    case 0x03af: return "pmpcfg15";
      case 0x03b0: return "pmpaddr0";
      case 0x03b1: return "pmpaddr1";
      case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
      case 0x03bd: return "pmpaddr13";
      case 0x03be: return "pmpaddr14";
      case 0x03bf: return "pmpaddr15";
 +    case 0x03c0: return "pmpaddr16";
 +    case 0x03c1: return "pmpaddr17";
 +    case 0x03c2: return "pmpaddr18";
 +    case 0x03c3: return "pmpaddr19";
 +    case 0x03c4: return "pmpaddr20";
 +    case 0x03c5: return "pmpaddr21";
 +    case 0x03c6: return "pmpaddr22";
 +    case 0x03c7: return "pmpaddr23";
 +    case 0x03c8: return "pmpaddr24";
 +    case 0x03c9: return "pmpaddr25";
 +    case 0x03ca: return "pmpaddr26";
 +    case 0x03cb: return "pmpaddr27";
 +    case 0x03cc: return "pmpaddr28";
 +    case 0x03cd: return "pmpaddr29";
 +    case 0x03ce: return "pmpaddr30";
 +    case 0x03cf: return "pmpaddr31";
 +    case 0x03d0: return "pmpaddr32";
 +    case 0x03d1: return "pmpaddr33";
 +    case 0x03d2: return "pmpaddr34";
 +    case 0x03d3: return "pmpaddr35";
 +    case 0x03d4: return "pmpaddr36";
 +    case 0x03d5: return "pmpaddr37";
 +    case 0x03d6: return "pmpaddr38";
 +    case 0x03d7: return "pmpaddr39";
 +    case 0x03d8: return "pmpaddr40";
 +    case 0x03d9: return "pmpaddr41";
 +    case 0x03da: return "pmpaddr42";
 +    case 0x03db: return "pmpaddr43";
 +    case 0x03dc: return "pmpaddr44";
 +    case 0x03dd: return "pmpaddr45";
 +    case 0x03de: return "pmpaddr46";
 +    case 0x03df: return "pmpaddr47";
 +    case 0x03e0: return "pmpaddr48";
 +    case 0x03e1: return "pmpaddr49";
 +    case 0x03e2: return "pmpaddr50";
 +    case 0x03e3: return "pmpaddr51";
 +    case 0x03e4: return "pmpaddr52";
 +    case 0x03e5: return "pmpaddr53";
 +    case 0x03e6: return "pmpaddr54";
 +    case 0x03e7: return "pmpaddr55";
 +    case 0x03e8: return "pmpaddr56";
 +    case 0x03e9: return "pmpaddr57";
 +    case 0x03ea: return "pmpaddr58";
 +    case 0x03eb: return "pmpaddr59";
 +    case 0x03ec: return "pmpaddr60";
 +    case 0x03ed: return "pmpaddr61";
 +    case 0x03ee: return "pmpaddr62";
 +    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
      case 0x0782: return "mreset";
 --
-.31.1
+.45.1

-[PULL 43/61] target/riscv: Create xl field in env
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Yu-Ming Chang <yumin686@andestech.com>
-Current xlen has been used in helper functions and many other places.
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-The computation of current xlen is not so trivial, so that we should
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
-recompute it as little as possible.
+holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Fortunately, xlen only changes in very seldom cases, such as exception,
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-misa write, mstatus write, cpu reset, migration load. So that we can only
+a register holding a zero value, an illegal instruction exception should be
-recompute xlen in this places and cache it into CPURISCVState.
+raised.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 31 +++++++++++++++++++++++++++++++
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/cpu.c        |  1 +
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- target/riscv/cpu_helper.c | 34 ++--------------------------------
+ target/riscv/op_helper.c |  6 ++---
- target/riscv/csr.c        |  2 ++
+files changed, 53 insertions(+), 8 deletions(-)
  target/riscv/machine.c    | 10 ++++++++++
 files changed, 46 insertions(+), 32 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-     uint32_t misa_mxl_max;  /* max mxl for this cpu */
+ void riscv_cpu_update_mask(CPURISCVState *env);
-     uint32_t misa_ext;      /* current extensions */
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-     uint32_t misa_ext_mask; /* max ext for this cpu */
-+    uint32_t xl;            /* current xlen */
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++                          target_ulong *ret_value);
-     /* 128-bit helpers upper part return value */
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-     target_ulong retxh;
+                            target_ulong *ret_value,
-@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+                            target_ulong new_value, target_ulong write_mask);
- }
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
- #endif
+                                           target_ulong new_value,
+                                           target_ulong write_mask);
-+#if defined(TARGET_RISCV32)
-+#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-+#else
++                               Int128 *ret_value);
-+static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-+{
+                                 Int128 *ret_value,
-+    RISCVMXL xl = env->misa_mxl;
+                                 Int128 new_value, Int128 write_mask);
 +#if !defined(CONFIG_USER_ONLY)
 +    /*
 +     * When emulating a 32-bit-only cpu, use RV32.
 +     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 +     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 +     * back to RV64 for lower privs.
 +     */
 +    if (xl != MXL_RV32) {
 +        switch (env->priv) {
 +        case PRV_M:
 +            break;
 +        case PRV_U:
 +            xl = get_field(env->mstatus, MSTATUS64_UXL);
 +            break;
 +        default: /* PRV_S | PRV_H */
 +            xl = get_field(env->mstatus, MSTATUS64_SXL);
 +            break;
 +        }
 +    }
 +#endif
 +    return xl;
 +}
 +#endif
 +
  /*
   * Encode LMUL to lmul as follows:
   *     LMUL    vlmul    lmul
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      /* mmte is supposed to have pm.current hardwired to 1 */
      env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
  #endif
 +    env->xl = riscv_cpu_mxl(env);
      cs->exception_index = RISCV_EXCP_NONE;
      env->load_res = -1;
      set_default_nan_mode(1, &env->fp_status);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  #endif
  }
 -static RISCVMXL cpu_get_xl(CPURISCVState *env)
 -{
 -#if defined(TARGET_RISCV32)
 -    return MXL_RV32;
 -#elif defined(CONFIG_USER_ONLY)
 -    return MXL_RV64;
 -#else
 -    RISCVMXL xl = riscv_cpu_mxl(env);
 -
 -    /*
 -     * When emulating a 32-bit-only cpu, use RV32.
 -     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 -     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 -     * back to RV64 for lower privs.
 -     */
 -    if (xl != MXL_RV32) {
 -        switch (env->priv) {
 -        case PRV_M:
 -            break;
 -        case PRV_U:
 -            xl = get_field(env->mstatus, MSTATUS64_UXL);
 -            break;
 -        default: /* PRV_S | PRV_H */
 -            xl = get_field(env->mstatus, MSTATUS64_SXL);
 -            break;
 -        }
 -    }
 -    return xl;
 -#endif
 -}
 -
  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags)
  {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
      }
  #endif
 -    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
 +    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
      *pflags = flags;
  }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
      }
      /* tlb_flush is unnecessary as mode is contained in mmu_idx */
      env->priv = newpriv;
 +    env->xl = cpu_recompute_xl(env);
      /*
       * Clear the load reservation - otherwise a reservation placed in one
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
-     env->mstatus = mstatus;
-+    env->xl = cpu_recompute_xl(env);
+     /* read / write check */
+-    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
-     /* flush translation cache */
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-     tb_flush(env_cpu(env));
++                           target_ulong *ret_value)
-     env->misa_ext = val;
++{
-+    env->xl = riscv_cpu_mxl(env);
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
 +    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
 +}
 +
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
-diff --git a/target/riscv/machine.c b/target/riscv/machine.c
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-index XXXXXXX..XXXXXXX 100644
++                               Int128 *ret_value)
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kvmtimer = {
      }
  };
 +static int riscv_cpu_post_load(void *opaque, int version_id)
 +{
-+    RISCVCPU *cpu = opaque;
++    RISCVException ret;
 +    CPURISCVState *env = &cpu->env;
 +
-+    env->xl = cpu_recompute_xl(env);
++    ret = riscv_csrrw_check(env, csrno, false);
-+    return 0;
++    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
 +    if (csr_ops[csrno].read128) {
 +        return riscv_csrrw_do128(env, csrno, ret_value,
 +                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
- const VMStateDescription vmstate_riscv_cpu = {
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-     .name = "cpu",
+                                 Int128 *ret_value,
-     .version_id = 3,
+                                 Int128 new_value, Int128 write_mask)
-     .minimum_version_id = 3,
+ {
-+    .post_load = riscv_cpu_post_load,
+     RISCVException ret;
-     .fields = (VMStateField[]) {
-         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
-         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
++    ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
      }
      target_ulong val = 0;
 -    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 +    RISCVException ret = riscv_csrr(env, csr, &val);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
      Int128 rv = int128_zero();
 -    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
 -                                          int128_zero(),
 -                                          int128_zero());
 +    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 --
-.31.1
+.45.1

-[PULL 47/61] target/riscv: Relax debug check for pm write
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
-     int csr_priv = get_field(csrno, 0x300);
-     int pm_current;
-+    if (env->debugger) {
-+        return false;
-+    }
-     /*
-      * If priv lvls differ that means we're accessing csr from higher priv lvl,
-      * so allow the access
---
-.31.1

-[PULL 48/61] target/riscv: Adjust csr write mask with XLEN
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Write mask is representing the bits we care about.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/op_helper.c                |  3 ++-
- target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++----
-files changed, 10 insertions(+), 5 deletions(-)
-diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/op_helper.c
-+++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
- void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
- {
--    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
-+    target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
-+    RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
-     if (ret != RISCV_EXCP_NONE) {
-         riscv_raise_exception(env, ret, GETPC());
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
- static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
- {
--    if (get_xl(ctx) < MXL_RV128) {
-+    RISCVMXL xl = get_xl(ctx);
-+    if (xl < MXL_RV128) {
-         TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
-         /*
-@@ -XXX,XX +XXX,XX @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
-             return do_csrw(ctx, a->csr, src);
-         }
--        TCGv mask = tcg_constant_tl(-1);
-+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
-+                                                     (target_ulong)-1);
-         return do_csrrw(ctx, a->rd, a->csr, src, mask);
-     } else {
-         TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
-@@ -XXX,XX +XXX,XX @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
- static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
- {
--    if (get_xl(ctx) < MXL_RV128) {
-+    RISCVMXL xl = get_xl(ctx);
-+    if (xl < MXL_RV128) {
-         TCGv src = tcg_constant_tl(a->rs1);
-         /*
-@@ -XXX,XX +XXX,XX @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
-             return do_csrw(ctx, a->csr, src);
-         }
--        TCGv mask = tcg_constant_tl(-1);
-+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
-+                                                     (target_ulong)-1);
-         return do_csrrw(ctx, a->rd, a->csr, src, mask);
-     } else {
-         TCGv src = tcg_constant_tl(a->rs1);
---
-.31.1

-[PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base]
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Replace the array of pm_mask/pm_base with scalar variables.
-Remove the cached array value in DisasContext.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/translate.c | 32 ++++++++------------------------
-file changed, 8 insertions(+), 24 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
- static TCGv load_res;
- static TCGv load_val;
- /* globals for PM CSRs */
--static TCGv pm_mask[4];
--static TCGv pm_base[4];
-+static TCGv pm_mask;
-+static TCGv pm_base;
- #include "exec/gen-icount.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     TCGv temp[4];
-     /* PointerMasking extension */
-     bool pm_enabled;
--    TCGv pm_mask;
--    TCGv pm_base;
- } DisasContext;
- static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-@@ -XXX,XX +XXX,XX @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
-         return src;
-     } else {
-         temp = temp_new(s);
--        tcg_gen_andc_tl(temp, src, s->pm_mask);
--        tcg_gen_or_tl(temp, temp, s->pm_base);
-+        tcg_gen_andc_tl(temp, src, pm_mask);
-+        tcg_gen_or_tl(temp, temp, pm_base);
-         return temp;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->ntemp = 0;
-     memset(ctx->temp, 0, sizeof(ctx->temp));
-     ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
--    int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
--    ctx->pm_mask = pm_mask[priv];
--    ctx->pm_base = pm_base[priv];
--
-     ctx->zero = tcg_constant_tl(0);
- }
-@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
-                              "load_res");
-     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
-                              "load_val");
--#ifndef CONFIG_USER_ONLY
-     /* Assign PM CSRs to tcg globals */
--    pm_mask[PRV_U] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
--    pm_base[PRV_U] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
--    pm_mask[PRV_S] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
--    pm_base[PRV_S] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
--    pm_mask[PRV_M] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
--    pm_base[PRV_M] =
--      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
--#endif
-+    pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
-+                                 "pmmask");
-+    pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
-+                                 "pmbase");
- }
---
-.31.1

-[PULL 54/61] target/riscv: Adjust vsetvl according to XLEN
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h           | 5 +++++
- target/riscv/vector_helper.c | 7 +++++--
-files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
- }
- #endif
-+static inline int riscv_cpu_xlen(CPURISCVState *env)
-+{
-+    return 16 << env->xl;
-+}
-+
- /*
-  * Encode LMUL to lmul as follows:
-  *     LMUL    vlmul    lmul
-diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_helper.c
-+++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
-     uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
-     uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
-     uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
--    bool vill = FIELD_EX64(s2, VTYPE, VILL);
--    target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
-+    int xlen = riscv_cpu_xlen(env);
-+    bool vill = (s2 >> (xlen - 1)) & 0x1;
-+    target_ulong reserved = s2 &
-+                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
-+                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
-     if (lmul & 4) {
-         /* Fractional LMUL. */
---
-.31.1

-[PULL 55/61] target/riscv: Remove VILL field in VTYPE
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Acked-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 1 -
-file changed, 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, VTA, 6, 1)
- FIELD(VTYPE, VMA, 7, 1)
- FIELD(VTYPE, VEDIV, 8, 2)
- FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
--FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
- struct CPURISCVState {
-     target_ulong gpr[32];
---
-.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20 16:13:17 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1

for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:

target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.0

* Fixes for OpenTitan timer
 * Correction of OpenTitan PLIC stride length
 * RISC-V KVM support
 * Device tree code cleanup
 * Support for the Zve64f and Zve32f extensions
 * OpenSBI binary loading support for the Spike machine
 * Removal of OpenSBI ELFs
 * Support for the UXL field in xstatus

----------------------------------------------------------------
Anup Patel (3):
      hw/riscv: spike: Allow using binary firmware as bios
      hw/riscv: Remove macros for ELF BIOS image names
      roms/opensbi: Remove ELF images

Frank Chang (17):
      target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
      target/riscv: rvv-1.0: Add Zve64f support for configuration insns
      target/riscv: rvv-1.0: Add Zve64f support for load and store insns
      target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
      target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
      target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
      target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
      target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
      target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
      target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
      target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
      target/riscv: rvv-1.0: Add Zve32f support for configuration insns
      target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
      target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
      target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
      target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
      target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

LIU Zhiwei (23):
      target/riscv: Adjust pmpcfg access with mxl
      target/riscv: Don't save pc when exception return
      target/riscv: Sign extend link reg for jal and jalr
      target/riscv: Sign extend pc for different XLEN
      target/riscv: Create xl field in env
      target/riscv: Ignore the pc bits above XLEN
      target/riscv: Extend pc for runtime pc write
      target/riscv: Use gdb xml according to max mxlen
      target/riscv: Relax debug check for pm write
      target/riscv: Adjust csr write mask with XLEN
      target/riscv: Create current pm fields in env
      target/riscv: Alloc tcg global for cur_pm[mask|base]
      target/riscv: Calculate address according to XLEN
      target/riscv: Split pm_enabled into mask and base
      target/riscv: Split out the vill from vtype
      target/riscv: Adjust vsetvl according to XLEN
      target/riscv: Remove VILL field in VTYPE
      target/riscv: Fix check range for first fault only
      target/riscv: Adjust vector address with mask
      target/riscv: Adjust scalar reg in vector with XLEN
      target/riscv: Set default XLEN for hypervisor
      target/riscv: Enable uxl field write
      target/riscv: Relax UXL field for debugging

Thomas Huth (1):
      softmmu/device_tree: Silence compiler warning with --enable-sanitizers

Wilfred Mallawa (3):
      hw: timer: ibex_timer: Fixup reading w/o register
      riscv: opentitan: fixup plic stride len
      hw: timer: ibex_timer: update/add reg address

Yanan Wang (1):
      softmmu/device_tree: Remove redundant pointer assignment

Yifei Jiang (13):
      update-linux-headers: Add asm-riscv/kvm.h
      target/riscv: Add target/riscv/kvm.c to place the public kvm interface
      target/riscv: Implement function kvm_arch_init_vcpu
      target/riscv: Implement kvm_arch_get_registers
      target/riscv: Implement kvm_arch_put_registers
      target/riscv: Support start kernel directly by KVM
      target/riscv: Support setting external interrupt by KVM
      target/riscv: Handle KVM_EXIT_RISCV_SBI exit
      target/riscv: Add host cpu type
      target/riscv: Add kvm_riscv_get/put_regs_timer
      target/riscv: Implement virtual time adjusting with vm state changing
      target/riscv: Support virtual time context synchronization
      target/riscv: enable riscv kvm accel

meson.build                                    |   2 +
 include/hw/char/riscv_htif.h                   |   5 +-
 include/hw/riscv/boot.h                        |   3 +-
 include/hw/riscv/spike.h                       |   1 +
 include/hw/timer/ibex_timer.h                  |   1 -
 linux-headers/asm-riscv/kvm.h                  | 128 ++++++
 target/riscv/cpu.h                             |  58 ++-
 target/riscv/cpu_bits.h                        |   3 +
 target/riscv/helper.h                          |   4 +-
 target/riscv/kvm_riscv.h                       |  25 ++
 target/riscv/sbi_ecall_interface.h             |  72 ++++
 hw/char/riscv_htif.c                           |  33 +-
 hw/intc/sifive_plic.c                          |  20 +-
 hw/riscv/boot.c                                |  16 +-
 hw/riscv/opentitan.c                           |   2 +-
 hw/riscv/spike.c                               |  45 ++-
 hw/riscv/virt.c                                |  83 ++--
 hw/timer/ibex_timer.c                          |  25 +-
 softmmu/device_tree.c                          |  11 +-
 target/riscv/cpu.c                             |  77 +++-
 target/riscv/cpu_helper.c                      |  99 ++---
 target/riscv/csr.c                             |  90 ++++-
 target/riscv/gdbstub.c                         |  71 +++-
 target/riscv/kvm-stub.c                        |  30 ++
 target/riscv/kvm.c                             | 535 +++++++++++++++++++++++++
 target/riscv/machine.c                         |  46 ++-
 target/riscv/op_helper.c                       |   7 +-
 target/riscv/pmp.c                             |  12 +-
 target/riscv/translate.c                       |  94 +++--
 target/riscv/vector_helper.c                   |  39 +-
 target/riscv/insn_trans/trans_privileged.c.inc |   9 +-
 target/riscv/insn_trans/trans_rva.c.inc        |   9 +-
 target/riscv/insn_trans/trans_rvd.c.inc        |  19 +-
 target/riscv/insn_trans/trans_rvf.c.inc        |  19 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |  39 +-
 target/riscv/insn_trans/trans_rvv.c.inc        | 225 +++++++++--
 .gitlab-ci.d/opensbi.yml                       |   2 -
 pc-bios/meson.build                            |   2 -
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
 roms/Makefile                                  |   2 -
 target/riscv/meson.build                       |   1 +
 42 files changed, 1608 insertions(+), 356 deletions(-)
 create mode 100644 linux-headers/asm-riscv/kvm.h
 create mode 100644 target/riscv/kvm_riscv.h
 create mode 100644 target/riscv/sbi_ecall_interface.h
 create mode 100644 target/riscv/kvm-stub.c
 create mode 100644 target/riscv/kvm.c
 delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/timer/ibex_timer.h |  1 -
 hw/timer/ibex_timer.c         | 14 +++++---------
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -XXX,XX +XXX,XX @@ struct IbexTimerState {
     uint32_t timer_compare_upper0;
     uint32_t timer_intr_enable;
     uint32_t timer_intr_state;
-    uint32_t timer_intr_test;
 
     uint32_t timebase_freq;
 
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_reset(DeviceState *dev)
     s->timer_compare_upper0 = 0xFFFFFFFF;
     s->timer_intr_enable = 0x00000000;
     s->timer_intr_state = 0x00000000;
-    s->timer_intr_test = 0x00000000;
 
     ibex_timer_update_irqs(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
         retvalue = s->timer_intr_state;
         break;
     case R_INTR_TEST:
-        retvalue = s->timer_intr_test;
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Attempted to read INTR_TEST, a write only register");
         break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
         s->timer_intr_state &= ~val;
         break;
     case R_INTR_TEST:
-        s->timer_intr_test = val;
-        if (s->timer_intr_enable &
-            s->timer_intr_test &
-            R_INTR_ENABLE_IE_0_MASK) {
+        if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
             qemu_set_irq(s->irq, true);
         }
@@ -XXX,XX +XXX,XX @@ static int ibex_timer_post_load(void *opaque, int version_id)
 
 static const VMStateDescription vmstate_ibex_timer = {
     .name = TYPE_IBEX_TIMER,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .post_load = ibex_timer_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(timer_ctrl, IbexTimerState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ibex_timer = {
         VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
         VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
         VMSTATE_UINT32(timer_intr_state, IbexTimerState),
-        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.31.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

The following change was made to rectify incorrectly set stride length
on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
discovered whilst attempting to fix a bug where a timer_interrupt was
not serviced on TockOS-OpenTitan.

[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
-    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
-- 
2.31.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table

The CTRL register is @ 0x04.

This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS-OpenTitan.

2. Adds ALERT_TEST register as documented on [1], adding repective
   switch cases to error handle and later implement functionality.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/timer/ibex_timer.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "migration/vmstate.h"
 
-REG32(CTRL, 0x00)
+REG32(ALERT_TEST, 0x00)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
+REG32(CTRL, 0x04)
     FIELD(CTRL, ACTIVE, 0, 1)
 REG32(CFG0, 0x100)
     FIELD(CFG0, PRESCALE, 0, 12)
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
     uint64_t retvalue = 0;
 
     switch (addr >> 2) {
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                        "Attempted to read ALERT_TEST, a write only register");
+        break;
     case R_CTRL:
         retvalue = s->timer_ctrl;
         break;
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
     uint32_t val = val64;
 
     switch (addr >> 2) {
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
+        break;
     case R_CTRL:
         s->timer_ctrl = val;
         break;
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add asm-riscv/kvm.h for RISC-V KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 linux-headers/asm-riscv/kvm.h | 128 ++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 linux-headers/asm-riscv/kvm.h

diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/linux-headers/asm-riscv/kvm.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *     Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __LINUX_KVM_RISCV_H
+#define __LINUX_KVM_RISCV_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#define KVM_INTERRUPT_SET	-1U
+#define KVM_INTERRUPT_UNSET	-2U
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+};
+
+/* KVM Debug exit structure */
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+};
+
+/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_config {
+	unsigned long isa;
+};
+
+/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_core {
+	struct user_regs_struct regs;
+	unsigned long mode;
+};
+
+/* Possible privilege modes for kvm_riscv_core */
+#define KVM_RISCV_MODE_S	1
+#define KVM_RISCV_MODE_U	0
+
+/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_csr {
+	unsigned long sstatus;
+	unsigned long sie;
+	unsigned long stvec;
+	unsigned long sscratch;
+	unsigned long sepc;
+	unsigned long scause;
+	unsigned long stval;
+	unsigned long sip;
+	unsigned long satp;
+	unsigned long scounteren;
+};
+
+/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_timer {
+	__u64 frequency;
+	__u64 time;
+	__u64 compare;
+	__u64 state;
+};
+
+/* Possible states for kvm_riscv_timer */
+#define KVM_RISCV_TIMER_STATE_OFF	0
+#define KVM_RISCV_TIMER_STATE_ON	1
+
+#define KVM_REG_SIZE(id)		\
+	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
+#define KVM_REG_RISCV_TYPE_SHIFT	24
+
+/* Config registers are mapped as type 1 */
+#define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CONFIG_REG(name)	\
+	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
+
+/* Core registers are mapped as type 2 */
+#define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CORE_REG(name)	\
+		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
+
+/* Control and status registers are mapped as type 3 */
+#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_REG(name)	\
+		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
+
+/* Timer registers are mapped as type 4 */
+#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_TIMER_REG(name)	\
+		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
+
+/* F extension registers are mapped as type 5 */
+#define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_F_REG(name)	\
+		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
+
+/* D extension registers are mapped as type 6 */
+#define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_D_REG(name)	\
+		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
+
+#endif
+
+#endif /* __LINUX_KVM_RISCV_H */
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+    return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'translate.c',
   'm128_helper.c'
 ))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get isa info from kvm while kvm init.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+                                 uint64_t idx)
+{
+    uint64_t id = KVM_REG_RISCV | type | idx;
+
+    switch (riscv_cpu_mxl(env)) {
+    case MXL_RV32:
+        id |= KVM_REG_SIZE_U32;
+        break;
+    case MXL_RV64:
+        id |= KVM_REG_SIZE_U64;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+    target_ulong isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    uint64_t id;
+
+    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+                          KVM_REG_RISCV_CONFIG_REG(isa));
+    ret = kvm_get_one_reg(cs, id, &isa);
+    if (ret) {
+        return ret;
+    }
+    env->misa_ext = isa;
+
+    return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
     return id;
 }
 
+#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
+                 KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
+                 KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
+
+#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
+    do { \
+        int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
+        if (ret) { \
+            return ret; \
+        } \
+    } while (0)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    target_ulong reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->pc = reg;
+
+    for (i = 1; i < 32; i++) {
+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+        ret = kvm_get_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+        env->gpr[i] = reg;
+    }
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
+    KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
+    KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
+    KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
+    KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
+    KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
+    KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
+    KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
+    KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
+    return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_get_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_put_registers(CPUState *cs, int level)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
         } \
     } while (0)
 
+#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
+    do { \
+        int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
+        if (ret) { \
+            return ret; \
+        } \
+    } while (0)
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_core(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    target_ulong reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->pc;
+    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    for (i = 1; i < 32; i++) {
+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+        reg = env->gpr[i];
+        ret = kvm_set_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_csr(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
+    KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
+    KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
+    KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
+    KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
+    KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
+    KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
+    KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
+    KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_fp(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
 
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_put_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_release_virq_post(int virq)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.

In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h  |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/kvm_riscv.h | 24 ++++++++++++
 hw/intc/sifive_plic.c    | 20 +++++++---
 hw/riscv/boot.c          | 16 +++++++-
 hw/riscv/virt.c          | 83 ++++++++++++++++++++++++++++------------
 target/riscv/cpu.c       |  8 ++++
 target/riscv/kvm-stub.c  | 25 ++++++++++++
 target/riscv/kvm.c       | 14 +++++++
 target/riscv/meson.build |  2 +-
 10 files changed, 164 insertions(+), 32 deletions(-)
 create mode 100644 target/riscv/kvm_riscv.h
 create mode 100644 target/riscv/kvm-stub.c

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
                                   hwaddr rom_size,
                                   uint32_t reset_vec_size,
                                   uint64_t kernel_entry);
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
 
 #endif /* RISCV_BOOT_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     /* Fields from here on are preserved across CPU reset. */
     QEMUTimer *timer; /* Internal timer */
+
+    hwaddr kernel_addr;
+    hwaddr fdt_addr;
 };
 
 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU KVM support -- RISC-V specific functions.
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_KVM_RISCV_H
+#define QEMU_KVM_RISCV_H
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+
+#endif
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "migration/vmstate.h"
 #include "hw/irq.h"
+#include "sysemu/kvm.h"
 
 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
 {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t context_stride, uint32_t aperture_size)
 {
     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
-    int i;
+    int i, j = 0;
+    SiFivePLICState *plic;
 
     assert(enable_stride == (enable_stride & -enable_stride));
     assert(context_stride == (context_stride & -context_stride));
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 
+    plic = SIFIVE_PLIC(dev);
     for (i = 0; i < num_harts; i++) {
         CPUState *cpu = qemu_get_cpu(hartid_base + i);
 
-        qdev_connect_gpio_out(dev, i,
-                              qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
-        qdev_connect_gpio_out(dev, num_harts + i,
-                              qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+        if (plic->addr_config[j].mode == PLICMode_M) {
+            j++;
+            qdev_connect_gpio_out(dev, num_harts + i,
+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+        }
+
+        if (plic->addr_config[j].mode == PLICMode_S) {
+            j++;
+            qdev_connect_gpio_out(dev, i,
+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
+        }
     }
 
     return dev;
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "elf.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/qtest.h"
+#include "sysemu/kvm.h"
 
 #include <libfdt.h>
 
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
         CPUState *cs = qemu_get_cpu(i);
         CPURISCVState *env = &RISCV_CPU(cs)->env;
 
-        if (riscv_has_ext(env, RVS)) {
+        if (kvm_enabled()) {
+            vals[i] = "S";
+        } else if (riscv_has_ext(env, RVS)) {
             vals[i] = "MS";
         } else {
             vals[i] = "M";
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
 
     return;
 }
+
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
+{
+    CPUState *cs;
+
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+        riscv_cpu->env.kernel_addr = kernel_addr;
+        riscv_cpu->env.fdt_addr = fdt_addr;
+    }
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
         "sifive,plic-1.0.0", "riscv,plic0"
     };
 
-    plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+    if (kvm_enabled()) {
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+    } else {
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+    }
 
     for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
-        plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
-        plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
-        plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+        if (kvm_enabled()) {
+            plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+        } else {
+            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+        }
     }
 
     plic_phandles[socket] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 
         create_fdt_socket_memory(s, memmap, socket);
 
-        if (s->have_aclint) {
-            create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
-        } else {
-            create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+        if (!kvm_enabled()) {
+            if (s->have_aclint) {
+                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
+            } else {
+                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+            }
         }
 
         create_fdt_socket_plic(s, memmap, socket, phandle,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                 hart_count, &error_abort);
         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 
-        /* Per-socket CLINT */
-        riscv_aclint_swi_create(
-            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
-            base_hartid, hart_count, false);
-        riscv_aclint_mtimer_create(
-            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
-                RISCV_ACLINT_SWI_SIZE,
-            RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
-            RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
-            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
-
-        /* Per-socket ACLINT SSWI */
-        if (s->have_aclint) {
+        if (!kvm_enabled()) {
+            /* Per-socket CLINT */
             riscv_aclint_swi_create(
-                memmap[VIRT_ACLINT_SSWI].base +
-                    i * memmap[VIRT_ACLINT_SSWI].size,
-                base_hartid, hart_count, true);
+                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+                base_hartid, hart_count, false);
+            riscv_aclint_mtimer_create(
+                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
+                    RISCV_ACLINT_SWI_SIZE,
+                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+
+            /* Per-socket ACLINT SSWI */
+            if (s->have_aclint) {
+                riscv_aclint_swi_create(
+                    memmap[VIRT_ACLINT_SSWI].base +
+                        i * memmap[VIRT_ACLINT_SSWI].size,
+                    base_hartid, hart_count, true);
+            }
         }
 
         /* Per-socket PLIC hart topology configuration string */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * so the "-bios" parameter is ignored and treated like "-bios none"
+     * when KVM is enabled.
+     */
+    if (kvm_enabled()) {
+        g_free(machine->firmware);
+        machine->firmware = g_strdup("none");
+    }
+
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
                                     RISCV32_BIOS_BIN, start_addr, NULL);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                               virt_memmap[VIRT_MROM].size, kernel_entry,
                               fdt_load_addr, machine->fdt);
 
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * So here setup kernel start address and fdt address.
+     * TODO:Support firmware loading and integrate to TCG start
+     */
+    if (kvm_enabled()) {
+        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
+    }
+
     /* SiFive Test MMIO device */
     sifive_test_create(memmap[VIRT_TEST].base);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "fpu/softfloat-helpers.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
 
 /* RISC-V CPU definitions */
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+
+#ifndef CONFIG_USER_ONLY
+    if (kvm_enabled()) {
+        kvm_riscv_reset_vcpu(cpu);
+    }
+#endif
 }
 
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU KVM RISC-V specific function stubs
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "kvm_riscv.h"
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
+#include "kvm_riscv.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     return 0;
 }
 
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    CPURISCVState *env = &cpu->env;
+
+    if (!kvm_enabled()) {
+        return;
+    }
+    env->pc = cpu->env.kernel_addr;
+    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
+    env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
+    env->satp = 0;
+}
+
 bool kvm_arch_cpu_check_are_resettable(void)
 {
     return true;
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'translate.c',
   'm128_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

When KVM is enabled, set the S-mode external interrupt through
kvm_riscv_set_irq function.

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #define QEMU_KVM_RISCV_H
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
     case IRQ_S_EXT:
     case IRQ_VS_EXT:
     case IRQ_M_EXT:
-        riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+        if (kvm_enabled()) {
+            kvm_riscv_set_irq(cpu, irq, level);
+        } else {
+            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+        }
         break;
     default:
         g_assert_not_reached();
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm-stub.c
+++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 {
     abort();
 }
+
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
     env->satp = 0;
 }
 
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    int ret;
+    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+    if (irq != IRQ_S_EXT) {
+        perror("kvm riscv set irq != IRQ_S_EXT\n");
+        abort();
+    }
+
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+    if (ret < 0) {
+        perror("Set irq failed");
+        abort();
+    }
+}
+
 bool kvm_arch_cpu_check_are_resettable(void)
 {
     return true;
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
 target/riscv/kvm.c                 | 42 ++++++++++++++++-
 2 files changed, 113 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/sbi_ecall_interface.h

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_ECALL_INTERFACE_H__
+#define __SBI_ECALL_INTERFACE_H__
+
+/* clang-format off */
+
+/* SBI Extension IDs */
+#define SBI_EXT_0_1_SET_TIMER           0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR     0x2
+#define SBI_EXT_0_1_CLEAR_IPI           0x3
+#define SBI_EXT_0_1_SEND_IPI            0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I      0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN            0x8
+#define SBI_EXT_BASE                    0x10
+#define SBI_EXT_TIME                    0x54494D45
+#define SBI_EXT_IPI                     0x735049
+#define SBI_EXT_RFENCE                  0x52464E43
+#define SBI_EXT_HSM                     0x48534D
+
+/* SBI function IDs for BASE extension*/
+#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
+#define SBI_EXT_BASE_GET_IMP_ID         0x1
+#define SBI_EXT_BASE_GET_IMP_VERSION    0x2
+#define SBI_EXT_BASE_PROBE_EXT          0x3
+#define SBI_EXT_BASE_GET_MVENDORID      0x4
+#define SBI_EXT_BASE_GET_MARCHID        0x5
+#define SBI_EXT_BASE_GET_MIMPID         0x6
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER          0x0
+
+/* SBI function IDs for IPI extension*/
+#define SBI_EXT_IPI_SEND_IPI            0x0
+
+/* SBI function IDs for RFENCE extension*/
+#define SBI_EXT_RFENCE_REMOTE_FENCE_I       0x0
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA    0x1
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID  0x2
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x3
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x5
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
+
+/* SBI function IDs for HSM extension */
+#define SBI_EXT_HSM_HART_START          0x0
+#define SBI_EXT_HSM_HART_STOP           0x1
+#define SBI_EXT_HSM_HART_GET_STATUS     0x2
+
+#define SBI_HSM_HART_STATUS_STARTED     0x0
+#define SBI_HSM_HART_STATUS_STOPPED     0x1
+#define SBI_HSM_HART_STATUS_START_PENDING   0x2
+#define SBI_HSM_HART_STATUS_STOP_PENDING    0x3
+
+#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
+#define SBI_SPEC_VERSION_MAJOR_MASK     0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK     0xffffff
+#define SBI_EXT_VENDOR_START            0x09000000
+#define SBI_EXT_VENDOR_END              0x09FFFFFF
+/* clang-format on */
+
+#endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
+#include "sbi_ecall_interface.h"
+#include "chardev/char-fe.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+{
+    int ret = 0;
+    unsigned char ch;
+    switch (run->riscv_sbi.extension_id) {
+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+        ch = run->riscv_sbi.args[0];
+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+        break;
+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+        if (ret == sizeof(ch)) {
+            run->riscv_sbi.args[0] = ch;
+        } else {
+            run->riscv_sbi.args[0] = -1;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+                      __func__, run->riscv_sbi.extension_id);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
-    return 0;
+    int ret = 0;
+    switch (run->exit_reason) {
+    case KVM_EXIT_RISCV_SBI:
+        ret = kvm_riscv_handle_sbi(cs, run);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                      __func__, run->exit_reason);
+        ret = -1;
+        break;
+    }
+    return ret;
 }
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 #if defined(TARGET_RISCV32)
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 }
 #endif
 
+#if defined(CONFIG_KVM)
+static void riscv_host_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+#if defined(TARGET_RISCV32)
+    set_misa(env, MXL_RV32, 0);
+#elif defined(TARGET_RISCV64)
+    set_misa(env, MXL_RV64, 0);
+#endif
+}
+#endif
+
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .class_init = riscv_cpu_class_init,
     },
     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
+#if defined(CONFIG_KVM)
+    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
+#endif
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.

To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  7 +++++
 target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     hwaddr kernel_addr;
     hwaddr fdt_addr;
+
+    /* kvm timer */
+    bool kvm_timer_dirty;
+    uint64_t kvm_timer_time;
+    uint64_t kvm_timer_compare;
+    uint64_t kvm_timer_state;
+    uint64_t kvm_timer_frequency;
 };
 
 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "kvm_riscv.h"
 #include "sbi_ecall_interface.h"
 #include "chardev/char-fe.h"
+#include "migration/migration.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
 #define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
                  KVM_REG_RISCV_CSR_REG(name))
 
+#define RISCV_TIMER_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
+                 KVM_REG_RISCV_TIMER_REG(name))
+
 #define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
 
 #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
         } \
     } while (0)
 
+#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
+    do { \
+        int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
+        if (ret) { \
+            abort(); \
+        } \
+    } while (0)
+
+#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
+    do { \
+        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
+        if (ret) { \
+            abort(); \
+        } \
+    } while (0)
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
     return ret;
 }
 
+static void kvm_riscv_get_regs_timer(CPUState *cs)
+{
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (env->kvm_timer_dirty) {
+        return;
+    }
+
+    KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
+    KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
+    KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
+    KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
+
+    env->kvm_timer_dirty = true;
+}
+
+static void kvm_riscv_put_regs_timer(CPUState *cs)
+{
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (!env->kvm_timer_dirty) {
+        return;
+    }
+
+    KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
+    KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
+
+    /*
+     * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
+     * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
+     * doesn't matter that adaping in QEMU now.
+     * TODO If KVM changes, adapt here.
+     */
+    if (env->kvm_timer_state) {
+        KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
+    }
+
+    /*
+     * For now, migration will not work between Hosts with different timer
+     * frequency. Therefore, we should check whether they are the same here
+     * during the migration.
+     */
+    if (migration_is_running(migrate_get_current()->state)) {
+        KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
+        if (reg != env->kvm_timer_frequency) {
+            error_report("Dst Hosts timer frequency != Src Hosts");
+        }
+    }
+
+    env->kvm_timer_dirty = false;
+}
 
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

We hope that virtual time adjusts with vm state changing. When a vm
is stopped, guest virtual time should stop counting and kvm_timer
should be stopped. When the vm is resumed, guest virtual time should
continue to count and kvm_timer should be restored.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-12-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "sbi_ecall_interface.h"
 #include "chardev/char-fe.h"
 #include "migration/migration.h"
+#include "sysemu/runstate.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
+static void kvm_riscv_vm_state_change(void *opaque, bool running,
+                                      RunState state)
+{
+    CPUState *cs = opaque;
+
+    if (running) {
+        kvm_riscv_put_regs_timer(cs);
+    } else {
+        kvm_riscv_get_regs_timer(cs);
+    }
+}
+
 void kvm_arch_init_irq_routing(KVMState *s)
 {
 }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     CPURISCVState *env = &cpu->env;
     uint64_t id;
 
+    qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
+
     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
                           KVM_REG_RISCV_CONFIG_REG(isa));
     ret = kvm_get_one_reg(cs, id, &isa);
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_rv128 = {
     }
 };
 
+static bool kvmtimer_needed(void *opaque)
+{
+    return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->kvm_timer_dirty = true;
+    return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+    .name = "cpu/kvmtimer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = kvmtimer_needed,
+    .post_load = cpu_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_vector,
         &vmstate_pointermasking,
         &vmstate_rv128,
+        &vmstate_kvmtimer,
         NULL
     }
 };
-- 
2.31.1

From: Thomas Huth <thuth@redhat.com>

If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
complains:

.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
 in this function [-Werror=maybe-uninitialized]
     int namelen, retval;
                  ^~~~~~

It's a false warning since the while loop is always executed at least
once (p has to be non-NULL, otherwise the derefence in the if-statement
earlier will crash). Thus let's switch to a do-while loop here instead
to make the compiler happy in all cases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220107133844.145039-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 softmmu/device_tree.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         return -1;
     }
 
-    while (p) {
+    do {
         name = p + 1;
         p = strchr(name, '/');
         namelen = p != NULL ? p - name : strlen(name);
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         }
 
         parent = retval;
-    }
+    } while (p);
 
     return retval;
 }
-- 
2.31.1

From: Yanan Wang <wangyanan55@huawei.com>

The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20220111032758.27804-1-wangyanan55@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 softmmu/device_tree.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
 int qemu_fdt_add_path(void *fdt, const char *path)
 {
     const char *name;
-    const char *p = path;
     int namelen, retval;
     int parent = 0;
 
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
     }
 
     do {
-        name = p + 1;
-        p = strchr(name, '/');
-        namelen = p != NULL ? p - name : strlen(name);
+        name = path + 1;
+        path = strchr(name, '/');
+        namelen = path != NULL ? path - name : strlen(name);
 
         retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
         if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         }
 
         parent = retval;
-    } while (p);
+    } while (path);
 
     return retval;
 }
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu.c        | 4 ++++
 target/riscv/cpu_helper.c | 5 ++++-
 target/riscv/csr.c        | 6 +++++-
 target/riscv/translate.c  | 2 ++
 5 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve64f;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
+        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve64f extension depends upon RVF.");
+            return;
+        }
         if (cpu->cfg.ext_j) {
             ext |= RVJ;
         }
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
     uint32_t flags = 0;
 
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV)) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (env->misa_ext & RVV) {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (env->misa_ext & RVV ||
+        cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve64f;
     bool hlsx;
     /* vector extension */
     bool vill;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
 1 file changed, 33 insertions(+), 6 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_32 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVV without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVF without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
-        require_align(a->rd, s->lmul)) {
+        require_align(a->rd, s->lmul) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         TCGv_i64 t1;
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         unsigned int ofs = (8 << s->sew);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         /* The instructions ignore LMUL and vector register group. */
@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
 static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
     return s->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVF with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dd(s, a->rd, a->rs2, a->vm);
+           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu.c        | 4 ++--
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/translate.c  | 2 ++
 5 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve32f;
         bool ext_zve64f;
 
         char *priv_spec;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
-        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve64f extension depends upon RVF.");
+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
             return;
         }
         if (cpu->cfg.ext_j) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException vs(CPURISCVState *env, int csrno)
     RISCVCPU *cpu = RISCV_CPU(cs);
 
     if (env->misa_ext & RVV ||
-        cpu->cfg.ext_zve64f) {
+        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve32f;
     bool ext_zve64f;
     bool hlsx;
     /* vector extension */
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
     ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve32f(DisasContext *s)
+{
+    /* RVV + Zve32f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve32f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve32f ? s->sew <= MO_32 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
     /* RVV + Zve64f = RVV. */
@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
         require_align(a->rd, s->lmul) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

From: Anup Patel <apatel@ventanamicro.com>

Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.

The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/riscv_htif.h |  5 ++++-
 include/hw/riscv/spike.h     |  1 +
 hw/char/riscv_htif.c         | 33 +++++++++++++++++++----------
 hw/riscv/spike.c             | 41 ++++++++++++++++++++++--------------
 4 files changed, 52 insertions(+), 28 deletions(-)

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ extern const MemoryRegionOps htif_io_ops;
 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
     uint64_t st_size);
 
+/* Check if HTIF uses ELF symbols */
+bool htif_uses_elf_symbols(void);
+
 /* legacy pre qom */
 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr);
+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
 
 #endif
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -XXX,XX +XXX,XX @@ struct SpikeState {
 
 enum {
     SPIKE_MROM,
+    SPIKE_HTIF,
     SPIKE_CLINT,
     SPIKE_DRAM
 };
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
     .write = htif_mm_write,
 };
 
+bool htif_uses_elf_symbols(void)
+{
+    return (address_symbol_set == 3) ? true : false;
+}
+
 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr)
+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
 {
-    uint64_t base = MIN(tohost_addr, fromhost_addr);
-    uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
-    uint64_t tohost_offset = tohost_addr - base;
-    uint64_t fromhost_offset = fromhost_addr - base;
+    uint64_t base, size, tohost_offset, fromhost_offset;
+
+    if (!htif_uses_elf_symbols()) {
+        fromhost_addr = nonelf_base;
+        tohost_addr = nonelf_base + 8;
+    }
+
+    base = MIN(tohost_addr, fromhost_addr);
+    size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
+    tohost_offset = tohost_addr - base;
+    fromhost_offset = fromhost_addr - base;
 
     HTIFState *s = g_malloc0(sizeof(HTIFState));
     s->address_space = address_space;
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
         htif_be_change, s, NULL, true);
-    if (address_symbol_set == 3) {
-        memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
-                              TYPE_HTIF_UART, size);
-        memory_region_add_subregion_overlap(address_space, base,
-                                            &s->mmio, 1);
-    }
+
+    memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
+                          TYPE_HTIF_UART, size);
+    memory_region_add_subregion_overlap(address_space, base,
+                                        &s->mmio, 1);
 
     return s;
 }
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 
 static const MemMapEntry spike_memmap[] = {
     [SPIKE_MROM] =     {     0x1000,     0xf000 },
+    [SPIKE_HTIF] =     {  0x1000000,     0x1000 },
     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
 };
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/htif");
     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
+    if (!htif_uses_elf_symbols()) {
+        qemu_fdt_setprop_cells(fdt, "/htif", "reg",
+            0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
+    }
 
     qemu_fdt_add_subnode(fdt, "/soc");
     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     if (cmdline) {
         qemu_fdt_add_subnode(fdt, "/chosen");
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
         machine->ram);
 
-    /* create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]));
-
     /* boot rom */
     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
                            memmap[SPIKE_MROM].size, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                     htif_symbol_callback);
     }
 
+    /* Load kernel */
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                          kernel_start_addr,
                                          htif_symbol_callback);
-
-        if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-                                  end);
-        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = 0;
     }
 
+    /* Create device tree */
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+               riscv_is_32bit(&s->soc[0]));
+
+    /* Load initrd */
+    if (machine->kernel_filename && machine->initrd_filename) {
+        hwaddr start;
+        hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                       machine->ram_size, kernel_entry,
+                                       &start);
+        qemu_fdt_setprop_cell(s->fdt, "/chosen",
+                              "linux,initrd-start", start);
+        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+                              end);
+    }
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
                                    machine->ram_size, s->fdt);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     /* initialize HTIF using symbols found in load_kernel */
     htif_mm_init(system_memory, mask_rom,
-                 &s->soc[0].harts[0].env, serial_hd(0));
+                 &s->soc[0].harts[0].env, serial_hd(0),
+                 memmap[SPIKE_HTIF].base);
 }
 
 static void spike_machine_instance_init(Object *obj)
-- 
2.31.1

From: Anup Patel <apatel@ventanamicro.com>

Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h | 2 --
 hw/riscv/spike.c        | 4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 
 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
-#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
-#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
 
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     }
 
-- 
2.31.1

From: Anup Patel <apatel@ventanamicro.com>

Now that all RISC-V machines can use OpenSBI BIN images, we remove
OpenSBI ELF images and also exclude these images from BIOS build.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 .gitlab-ci.d/opensbi.yml                       |   2 --
 pc-bios/meson.build                            |   2 --
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
 roms/Makefile                                  |   2 --
 5 files changed, 6 deletions(-)
 delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml
index XXXXXXX..XXXXXXX 100644
--- a/.gitlab-ci.d/opensbi.yml
+++ b/.gitlab-ci.d/opensbi.yml
@@ -XXX,XX +XXX,XX @@ build-opensbi:
  artifacts:
    paths: # 'artifacts.zip' will contains the following files:
    - pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
-   - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    - pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
-   - pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
    - opensbi32-generic-stdout.log
    - opensbi32-generic-stderr.log
    - opensbi64-generic-stdout.log
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -XXX,XX +XXX,XX @@ blobs = files(
   'hppa-firmware.img',
   'opensbi-riscv32-generic-fw_dynamic.bin',
   'opensbi-riscv64-generic-fw_dynamic.bin',
-  'opensbi-riscv32-generic-fw_dynamic.elf',
-  'opensbi-riscv64-generic-fw_dynamic.elf',
   'npcm7xx_bootrom.bin',
 )
 
diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
deleted file mode 100644
index XXXXXXX..XXXXXXX
Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf and /dev/null differ
diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
deleted file mode 100644
index XXXXXXX..XXXXXXX
Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf and /dev/null differ
diff --git a/roms/Makefile b/roms/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -XXX,XX +XXX,XX @@ opensbi32-generic:
 		CROSS_COMPILE=$(riscv32_cross_prefix) \
 		PLATFORM="generic"
 	cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
-	cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 
 opensbi64-generic:
 	$(MAKE) -C opensbi \
 		CROSS_COMPILE=$(riscv64_cross_prefix) \
 		PLATFORM="generic"
 	cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
-	cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
 
 MESON = meson
 NINJA = ninja
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
+{
+    /* TODO: RV128 restriction check */
+    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+        return false;
+    }
+    return true;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
                                    target_ulong val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
     return RISCV_EXCP_NONE;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 {
     int i;
     uint8_t cfg_val;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
 
-    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "ignoring pmpcfg write - incorrect address\n");
-        return;
-    }
-
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
     int i;
     target_ulong cfg_val = 0;
     target_ulong val = 0;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         val = pmp_read_cfg(env, (reg_index * 4) + i);
         cfg_val |= (val << (i * 8));
     }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                          | 4 ++--
 target/riscv/op_helper.c                       | 4 ++--
 target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(csrr_i128, tl, env, int)
 DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
 DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
 
 #ifndef CONFIG_USER_ONLY
 
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt;
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
     return retpc;
 }
 
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
 static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
     if (has_ext(ctx, RVS)) {
-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 4 +---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                      | 25 ++++++++++++++++---
 .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |  5 ++--
 target/riscv/insn_trans/trans_rvv.c.inc       |  4 +--
 4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        dest = (int32_t)dest;
+    }
+    tcg_gen_movi_tl(cpu_pc, dest);
+}
+
+static void gen_set_pc(DisasContext *ctx, TCGv dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32s_tl(cpu_pc, dest);
+    } else {
+        tcg_gen_mov_tl(cpu_pc, dest);
+    }
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
         tcg_gen_goto_tb(n);
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_lookup_and_goto_ptr();
     }
 }
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     gen_helper_wfi(cpu_env);
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
+    gen_set_pc(ctx, cpu_pc);
     if (!has_ext(ctx, RVC)) {
         TCGv t0 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * FENCE_I is a no-op in QEMU,
      * however we need to end the translation block
      */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 static bool do_csr_post(DisasContext *ctx)
 {
     /* We may have changed important cpu state -- exit to main loop. */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
 
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.

Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 31 +++++++++++++++++++++++++++++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 34 ++--------------------------------
 target/riscv/csr.c        |  2 ++
 target/riscv/machine.c    | 10 ++++++++++
 5 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint32_t misa_mxl_max;  /* max mxl for this cpu */
     uint32_t misa_ext;      /* current extensions */
     uint32_t misa_ext_mask; /* max ext for this cpu */
+    uint32_t xl;            /* current xlen */
 
     /* 128-bit helpers upper part return value */
     target_ulong retxh;
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 }
 #endif
 
+#if defined(TARGET_RISCV32)
+#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+{
+    RISCVMXL xl = env->misa_mxl;
+#if !defined(CONFIG_USER_ONLY)
+    /*
+     * When emulating a 32-bit-only cpu, use RV32.
+     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
+     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
+     * back to RV64 for lower privs.
+     */
+    if (xl != MXL_RV32) {
+        switch (env->priv) {
+        case PRV_M:
+            break;
+        case PRV_U:
+            xl = get_field(env->mstatus, MSTATUS64_UXL);
+            break;
+        default: /* PRV_S | PRV_H */
+            xl = get_field(env->mstatus, MSTATUS64_SXL);
+            break;
+        }
+    }
+#endif
+    return xl;
+}
+#endif
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     /* mmte is supposed to have pm.current hardwired to 1 */
     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 #endif
+    env->xl = riscv_cpu_mxl(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
-static RISCVMXL cpu_get_xl(CPURISCVState *env)
-{
-#if defined(TARGET_RISCV32)
-    return MXL_RV32;
-#elif defined(CONFIG_USER_ONLY)
-    return MXL_RV64;
-#else
-    RISCVMXL xl = riscv_cpu_mxl(env);
-
-    /*
-     * When emulating a 32-bit-only cpu, use RV32.
-     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
-     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
-     * back to RV64 for lower privs.
-     */
-    if (xl != MXL_RV32) {
-        switch (env->priv) {
-        case PRV_M:
-            break;
-        case PRV_U:
-            xl = get_field(env->mstatus, MSTATUS64_UXL);
-            break;
-        default: /* PRV_S | PRV_H */
-            xl = get_field(env->mstatus, MSTATUS64_SXL);
-            break;
-        }
-    }
-    return xl;
-#endif
-}
-
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     }
 #endif
 
-    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
 
     *pflags = flags;
 }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     }
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
+    env->xl = cpu_recompute_xl(env);
 
     /*
      * Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
     }
     env->mstatus = mstatus;
+    env->xl = cpu_recompute_xl(env);
 
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     /* flush translation cache */
     tb_flush(env_cpu(env));
     env->misa_ext = val;
+    env->xl = riscv_cpu_mxl(env);
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kvmtimer = {
     }
 };
 
+static int riscv_cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->xl = cpu_recompute_xl(env);
+    return 0;
+}
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
     .minimum_version_id = 3,
+    .post_load = riscv_cpu_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    env->pc = value;
+
+    if (env->xl == MXL_RV32) {
+        env->pc = (int32_t)value;
+    } else {
+        env->pc = value;
+    }
 }
 
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    env->pc = tb->pc;
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)tb->pc;
+    } else {
+        env->pc = tb->pc;
+    }
 }
 
 static bool riscv_cpu_has_work(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
                           target_ulong *data)
 {
-    env->pc = data[0];
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)data[0];
+    } else {
+        env->pc = data[0];
+    }
 }
 
 static void riscv_cpu_reset(DeviceState *dev)
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+    CPUClass *cc = CPU_CLASS(mcc);
     int priv_version = 0;
     Error *local_err = NULL;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     switch (env->misa_mxl_max) {
 #ifdef TARGET_RISCV64
     case MXL_RV64:
+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
         break;
     case MXL_RV128:
         break;
 #endif
     case MXL_RV32:
+        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
         break;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
     cc->gdb_write_register = riscv_cpu_gdb_write_register;
     cc->gdb_num_core_regs = 33;
-#if defined(TARGET_RISCV32)
-    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-#elif defined(TARGET_RISCV64)
-    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-#endif
     cc->gdb_stop_before_watchpoint = true;
     cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
+    target_ulong tmp;
 
     if (n < 32) {
-        return gdb_get_regl(mem_buf, env->gpr[n]);
+        tmp = env->gpr[n];
     } else if (n == 32) {
-        return gdb_get_regl(mem_buf, env->pc);
+        tmp = env->pc;
+    } else {
+        return 0;
+    }
+
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        return gdb_get_reg32(mem_buf, tmp);
+    case MXL_RV64:
+        return gdb_get_reg64(mem_buf, tmp);
+    default:
+        g_assert_not_reached();
     }
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-
-    if (n == 0) {
-        /* discard writes to x0 */
-        return sizeof(target_ulong);
-    } else if (n < 32) {
-        env->gpr[n] = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+    int length = 0;
+    target_ulong tmp;
+
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        tmp = (int32_t)ldl_p(mem_buf);
+        length = 4;
+        break;
+    case MXL_RV64:
+        if (env->xl < MXL_RV64) {
+            tmp = (int32_t)ldq_p(mem_buf);
+        } else {
+            tmp = ldq_p(mem_buf);
+        }
+        length = 8;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    if (n > 0 && n < 32) {
+        env->gpr[n] = tmp;
     } else if (n == 32) {
-        env->pc = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+        env->pc = tmp;
     }
-    return 0;
+
+    return length;
 }
 
 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                                               cs->gdb_num_regs),
                                  "riscv-vector.xml", 0);
     }
-#if defined(TARGET_RISCV32)
-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
-                             1, "riscv-32bit-virtual.xml", 0);
-#elif defined(TARGET_RISCV64)
-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
-                             1, "riscv-64bit-virtual.xml", 0);
-#endif
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+                                 riscv_gdb_set_virtual,
+                                 1, "riscv-32bit-virtual.xml", 0);
+        break;
+    case MXL_RV64:
+        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+                                 riscv_gdb_set_virtual,
+                                 1, "riscv-64bit-virtual.xml", 0);
+        break;
+    default:
+        g_assert_not_reached();
+    }
 
     gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
                              riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Write mask is representing the bits we care about.

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
 
 void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
 {
-    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+    target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
+    RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
 
 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 {
-    if (get_xl(ctx) < MXL_RV128) {
+    RISCVMXL xl = get_xl(ctx);
+    if (xl < MXL_RV128) {
         TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
 
         /*
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
             return do_csrw(ctx, a->csr, src);
         }
 
-        TCGv mask = tcg_constant_tl(-1);
+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+                                                     (target_ulong)-1);
         return do_csrrw(ctx, a->rd, a->csr, src, mask);
     } else {
         TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 
 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 {
-    if (get_xl(ctx) < MXL_RV128) {
+    RISCVMXL xl = get_xl(ctx);
+    if (xl < MXL_RV128) {
         TCGv src = tcg_constant_tl(a->rs1);
 
         /*
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
             return do_csrw(ctx, a->csr, src);
         }
 
-        TCGv mask = tcg_constant_tl(-1);
+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+                                                     (target_ulong)-1);
         return do_csrrw(ctx, a->rd, a->csr, src, mask);
     } else {
         TCGv src = tcg_constant_tl(a->rs1);
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
 target/riscv/csr.c        | 19 +++++++++++++++++
 target/riscv/machine.c    |  1 +
 5 files changed, 68 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong upmmask;
     target_ulong upmbase;
 #endif
+    target_ulong cur_pmmask;
+    target_ulong cur_pmbase;
 
     float_status fp_status;
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags);
 
+void riscv_cpu_update_mask(CPURISCVState *env);
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 #endif
     env->xl = riscv_cpu_mxl(env);
+    riscv_cpu_update_mask(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pflags = flags;
 }
 
+void riscv_cpu_update_mask(CPURISCVState *env)
+{
+    target_ulong mask = -1, base = 0;
+    /*
+     * TODO: Current RVJ spec does not specify
+     * how the extension interacts with XLEN.
+     */
+#ifndef CONFIG_USER_ONLY
+    if (riscv_has_ext(env, RVJ)) {
+        switch (env->priv) {
+        case PRV_M:
+            if (env->mmte & M_PM_ENABLE) {
+                mask = env->mpmmask;
+                base = env->mpmbase;
+            }
+            break;
+        case PRV_S:
+            if (env->mmte & S_PM_ENABLE) {
+                mask = env->spmmask;
+                base = env->spmbase;
+            }
+            break;
+        case PRV_U:
+            if (env->mmte & U_PM_ENABLE) {
+                mask = env->upmmask;
+                base = env->upmbase;
+            }
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+#endif
+    if (env->xl == MXL_RV32) {
+        env->cur_pmmask = mask & UINT32_MAX;
+        env->cur_pmbase = base & UINT32_MAX;
+    } else {
+        env->cur_pmmask = mask;
+        env->cur_pmbase = base;
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
 
     /*
      * Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
     env->mmte = wpri_val | PM_EXT_DIRTY;
+    riscv_cpu_update_mask(env);
 
     /* Set XS and SD bits, since PM CSRs are dirty */
     mstatus = env->mstatus | MSTATUS_XS;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmmask = val;
+    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmmask = val;
+    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmmask = val;
+    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmbase = val;
+    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmbase = val;
+    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmbase = val;
+    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
     CPURISCVState *env = &cpu->env;
 
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
     return 0;
 }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
 /* globals for PM CSRs */
-static TCGv pm_mask[4];
-static TCGv pm_base[4];
+static TCGv pm_mask;
+static TCGv pm_base;
 
 #include "exec/gen-icount.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     TCGv temp[4];
     /* PointerMasking extension */
     bool pm_enabled;
-    TCGv pm_mask;
-    TCGv pm_base;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
         return src;
     } else {
         temp = temp_new(s);
-        tcg_gen_andc_tl(temp, src, s->pm_mask);
-        tcg_gen_or_tl(temp, temp, s->pm_base);
+        tcg_gen_andc_tl(temp, src, pm_mask);
+        tcg_gen_or_tl(temp, temp, pm_base);
         return temp;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
     ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
-    int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
-    ctx->pm_mask = pm_mask[priv];
-    ctx->pm_base = pm_base[priv];
-
     ctx->zero = tcg_constant_tl(0);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
                              "load_res");
     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
                              "load_val");
-#ifndef CONFIG_USER_ONLY
     /* Assign PM CSRs to tcg globals */
-    pm_mask[PRV_U] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
-    pm_base[PRV_U] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
-    pm_mask[PRV_S] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
-    pm_base[PRV_S] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
-    pm_mask[PRV_M] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
-    pm_base[PRV_M] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
-#endif
+    pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+                                 "pmmask");
+    pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+                                 "pmbase");
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 25 ++++++++++++-------------
 target/riscv/insn_trans/trans_rva.c.inc |  9 +++------
 target/riscv/insn_trans/trans_rvd.c.inc | 19 ++-----------------
 target/riscv/insn_trans/trans_rvf.c.inc | 19 ++-----------------
 target/riscv/insn_trans/trans_rvi.c.inc | 18 ++----------------
 5 files changed, 21 insertions(+), 69 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-/*
- * Generates address adjustment for PointerMasking
- */
-static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
+/* Compute a canonical address from a register plus offset. */
+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 {
-    TCGv temp;
-    if (!s->pm_enabled) {
-        /* Load unmodified address */
-        return src;
-    } else {
-        temp = temp_new(s);
-        tcg_gen_andc_tl(temp, src, pm_mask);
-        tcg_gen_or_tl(temp, temp, pm_base);
-        return temp;
+    TCGv addr = temp_new(ctx);
+    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+    tcg_gen_addi_tl(addr, src1, imm);
+    if (ctx->pm_enabled) {
+        tcg_gen_and_tl(addr, addr, pm_mask);
+        tcg_gen_or_tl(addr, addr, pm_base);
+    } else if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32u_tl(addr, addr);
     }
+    return addr;
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
 
 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+    TCGv src1 = get_address(ctx, a->rs1, 0);
 
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
-    src1 = gen_pm_adjust_address(ctx, src1);
     tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
     if (a->aq) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
-    src1 = gen_pm_adjust_address(ctx, src1);
+    src1 = get_address(ctx, a->rs1, 0);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
     /*
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     MemOp mop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src1 = get_address(ctx, a->rs1, 0);
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    src1 = gen_pm_adjust_address(ctx, src1);
     func(dest, src1, src2, ctx->mem_idx, mop);
 
     gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
 
     mark_fs_dirty(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     dest = cpu_fpr[a->rd];
     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
     gen_nanbox_s(dest, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = tcg_temp_new();
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
 
     tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
     gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
 
 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.

This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  3 ++-
 target/riscv/cpu_helper.c | 24 ++++++------------------
 target/riscv/translate.c  | 12 ++++++++----
 3 files changed, 16 insertions(+), 23 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 FIELD(TB_FLAGS, XL, 20, 2)
 /* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
                            get_field(env->mstatus_hs, MSTATUS_VS));
     }
-    if (riscv_has_ext(env, RVJ)) {
-        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
-        bool pm_enabled = false;
-        switch (priv) {
-        case PRV_U:
-            pm_enabled = env->mmte & U_PM_ENABLE;
-            break;
-        case PRV_S:
-            pm_enabled = env->mmte & S_PM_ENABLE;
-            break;
-        case PRV_M:
-            pm_enabled = env->mmte & M_PM_ENABLE;
-            break;
-        default:
-            g_assert_not_reached();
-        }
-        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
-    }
 #endif
 
     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
+    if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
+    }
+    if (env->cur_pmbase != 0) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
+    }
 
     *pflags = flags;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* Space for 3 operands plus 1 extra for address computation. */
     TCGv temp[4];
     /* PointerMasking extension */
-    bool pm_enabled;
+    bool pm_mask_enabled;
+    bool pm_base_enabled;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (ctx->pm_enabled) {
+    if (ctx->pm_mask_enabled) {
         tcg_gen_and_tl(addr, addr, pm_mask);
-        tcg_gen_or_tl(addr, addr, pm_base);
     } else if (get_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }
+    if (ctx->pm_base_enabled) {
+        tcg_gen_or_tl(addr, addr, pm_base);
+    }
     return addr;
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->cs = cs;
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
-    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+    ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
+    ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
     ctx->zero = tcg_constant_tl(0);
 }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

We need not specially process vtype when XLEN changes.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h           |  1 +
 target/riscv/cpu_helper.c    |  3 +--
 target/riscv/csr.c           | 13 ++++++++++++-
 target/riscv/machine.c       |  5 +++--
 target/riscv/vector_helper.c |  3 ++-
 5 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong vl;
     target_ulong vstart;
     target_ulong vtype;
+    bool vill;
 
     target_ulong pc;
     target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         uint32_t maxsz = vlmax << sew;
         bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
                            (maxsz >= 8);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-                    FIELD_EX64(env->vtype, VTYPE, VILL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
         flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                     FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 static RISCVException read_vtype(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
-    *val = env->vtype;
+    uint64_t vill;
+    switch (env->xl) {
+    case MXL_RV32:
+        vill = (uint32_t)env->vill << 31;
+        break;
+    case MXL_RV64:
+        vill = (uint64_t)env->vill << 63;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    *val = (target_ulong)vill | env->vtype;
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static bool vector_needed(void *opaque)
 
 static const VMStateDescription vmstate_vector = {
     .name = "cpu/vector",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .needed = vector_needed,
     .fields = (VMStateField[]) {
             VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
             VMSTATE_UINTTL(env.vl, RISCVCPU),
             VMSTATE_UINTTL(env.vstart, RISCVCPU),
             VMSTATE_UINTTL(env.vtype, RISCVCPU),
+            VMSTATE_BOOL(env.vill, RISCVCPU),
             VMSTATE_END_OF_LIST()
         }
 };
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
         || (ediv != 0)
         || (reserved != 0)) {
         /* only set vill bit. */
-        env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+        env->vill = 1;
+        env->vtype = 0;
         env->vl = 0;
         env->vstart = 0;
         return 0;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 }
 #endif
 
+static inline int riscv_cpu_xlen(CPURISCVState *env)
+{
+    return 16 << env->xl;
+}
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
     uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
     uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
-    bool vill = FIELD_EX64(s2, VTYPE, VILL);
-    target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+    int xlen = riscv_cpu_xlen(env);
+    bool vill = (s2 >> (xlen - 1)) & 0x1;
+    target_ulong reserved = s2 &
+                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
 
     if (lmul & 4) {
         /* Fractional LMUL. */
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Only check the range that has passed the address translation.

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                                          cpu_mmu_index(env, false));
                 if (host) {
 #ifdef CONFIG_USER_ONLY
-                    if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+                    if (page_check_range(addr, offset, PAGE_READ) < 0) {
                         vl = i;
                         goto ProbeSuccess;
                     }
 #else
-                    probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+                    probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
 #endif
                 } else {
                     vl = i;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+    return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
 /*
  * This function checks watchpoint before real load operation.
  *
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
     target_ulong curlen = MIN(pagelen, len);
 
-    probe_access(env, addr, curlen, access_type,
+    probe_access(env, adjust_addr(env, addr), curlen, access_type,
                  cpu_mmu_index(env, false), ra);
     if (len > curlen) {
         addr += curlen;
         curlen = len - curlen;
-        probe_access(env, addr, curlen, access_type,
+        probe_access(env, adjust_addr(env, addr), curlen, access_type,
                      cpu_mmu_index(env, false), ra);
     }
 }
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + stride * i + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
         if (!vm && !vext_elem_mask(v0, i)) {
             continue;
         }
-        addr = base + i * (nf << esz);
+        addr = adjust_addr(env, base + i * (nf << esz));
         if (i == 0) {
             probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
         } else {
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                     break;
                 }
                 remain -= offset;
-                addr += offset;
+                addr = adjust_addr(env, addr + offset);
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
         }
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         /* load/store rest of elements of current segment pointed by vstart */
         for (pos = off; pos < max_elems; pos++, env->vstart++) {
             target_ulong addr = base + ((pos + k * max_elems) << esz);
-            ldst_elem(env, addr, pos + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
         }
         k++;
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     for (; k < nf; k++) {
         for (i = 0; i < max_elems; i++, env->vstart++) {
             target_ulong addr = base + ((i + k * max_elems) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
         }
     }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
          */
         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+        if (riscv_has_ext(env, RVH)) {
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_SXL, env->misa_mxl);
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_UXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_SXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_UXL, env->misa_mxl);
+        }
     }
     env->mcause = 0;
     env->pc = env->resetvec;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define COUNTEREN_IR         (1 << 2)
 #define COUNTEREN_HPM3       (1 << 3)
 
+/* vsstatus CSR bits */
+#define VSSTATUS64_UXL       0x0000000300000000ULL
+
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
+    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 static const target_ulong hip_writable_mask = MIP_VSSIP;
 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
+    RISCVMXL xl = riscv_cpu_mxl(env);
 
     /* flush tlb on mstatus fields that affect VM */
     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW | MSTATUS_VS;
 
-    if (riscv_cpu_mxl(env) != MXL_RV32) {
+    if (xl != MXL_RV32) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
          */
         mask |= MSTATUS_MPV | MSTATUS_GVA;
+        if ((val & MSTATUS64_UXL) != 0) {
+            mask |= MSTATUS64_UXL;
+        }
     }
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    RISCVMXL xl = riscv_cpu_mxl(env);
     if (xl > MXL_RV32) {
-        /* SXL and UXL fields are for now read only */
+        /* SXL field is for now read only */
         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
-        mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
     }
     env->mstatus = mstatus;
     env->xl = cpu_recompute_xl(env);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 {
     uint64_t mask = sstatus_v1_10_mask;
     uint64_t sstatus = env->mstatus & mask;
+    if (env->xl != MXL_RV32) {
+        mask |= SSTATUS64_UXL;
+    }
 
     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
-
+    if (env->xl != MXL_RV32) {
+        mask |= SSTATUS64_UXL;
+    }
     /* TODO: Use SXL not MXL. */
     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
+
+    if (env->xl != MXL_RV32) {
+        if ((val & SSTATUS64_UXL) != 0) {
+            mask |= SSTATUS64_UXL;
+        }
+    }
     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
     uint64_t mask = (target_ulong)-1;
+    if ((val & VSSTATUS64_UXL) == 0) {
+        mask &= ~VSSTATUS64_UXL;
+    }
     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
     return RISCV_EXCP_NONE;
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW | MSTATUS_VS;
 
-    if (xl != MXL_RV32) {
+    if (xl != MXL_RV32 || env->debugger) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 {
     uint64_t mask = sstatus_v1_10_mask;
     uint64_t sstatus = env->mstatus & mask;
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
     /* TODO: Use SXL not MXL. */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         if ((val & SSTATUS64_UXL) != 0) {
             mask |= SSTATUS64_UXL;
         }
-- 
2.31.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1