On Wed, Jan 19, 2022 at 9:39 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - reuse partial instructions of zbc extension, update extension check for them
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 3 ++-
> target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index bf080cb489..9fd900f4bd 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -770,9 +770,10 @@ clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>
> -# *** RV32 Zbc Standard Extension ***
> +# *** RV32 Zbc/Zbkc Standard Extension ***
> clmul 0000101 .......... 001 ..... 0110011 @r
> clmulh 0000101 .......... 011 ..... 0110011 @r
> +# *** RV32 extra Zbc Standard Extension ***
> clmulr 0000101 .......... 010 ..... 0110011 @r
>
> # *** RV32 Zbs Standard Extension ***
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 7590c0538e..2a565b98c0 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -489,7 +489,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>
> static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
> }
>
> @@ -501,7 +501,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
>
> static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
> }
>
> --
> 2.17.1
>
>