[v2] target/ppc: powerpc_excp improvements [40x] (3/n)

[PATCH v2 07/14] target/ppc: 405: External exception cleanup

Posted by Fabiano Rosas 4 years ago

405 has no MSR_HV and EPR is BookE only so we can remove it all.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/excp_helper.c | 37 -------------------------------------
 1 file changed, 37 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e98d783ecd..8fae8aa0be 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
         msr |= env->error_code;
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
-    {
-        bool lpes0;
-
-        cs = CPU(cpu);
-
-        /*
-         * Exception targeting modifiers
-         *
-         * LPES0 is supported on POWER7/8/9
-         * LPES1 is not supported (old iSeries mode)
-         *
-         * On anything else, we behave as if LPES0 is 1
-         * (externals don't alter MSR:HV)
-         */
-#if defined(TARGET_PPC64)
-        if (excp_model == POWERPC_EXCP_POWER7 ||
-            excp_model == POWERPC_EXCP_POWER8 ||
-            excp_model == POWERPC_EXCP_POWER9 ||
-            excp_model == POWERPC_EXCP_POWER10) {
-            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-        } else
-#endif /* defined(TARGET_PPC64) */
-        {
-            lpes0 = true;
-        }
-
-        if (!lpes0) {
-            new_msr |= (target_ulong)MSR_HVB;
-            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-            srr0 = SPR_HSRR0;
-            srr1 = SPR_HSRR1;
-        }
-        if (env->mpic_proxy) {
-            /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
-        }
         break;
-    }
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
         /* Get rS/rD and rA from faulting opcode */
         /*
-- 
2.33.1

Re: [PATCH v2 07/14] target/ppc: 405: External exception cleanup

Posted by Richard Henderson 4 years ago

On 1/19/22 5:44 AM, Fabiano Rosas wrote:
> 405 has no MSR_HV and EPR is BookE only so we can remove it all.
> 
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>   target/ppc/excp_helper.c | 37 -------------------------------------
>   1 file changed, 37 deletions(-)
> 
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e98d783ecd..8fae8aa0be 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>           msr |= env->error_code;
>           break;
>       case POWERPC_EXCP_EXTERNAL:  /* External input                           */
> -    {
> -        bool lpes0;
> -
> -        cs = CPU(cpu);
> -
> -        /*
> -         * Exception targeting modifiers
> -         *
> -         * LPES0 is supported on POWER7/8/9
> -         * LPES1 is not supported (old iSeries mode)
> -         *
> -         * On anything else, we behave as if LPES0 is 1
> -         * (externals don't alter MSR:HV)
> -         */
> -#if defined(TARGET_PPC64)
> -        if (excp_model == POWERPC_EXCP_POWER7 ||
> -            excp_model == POWERPC_EXCP_POWER8 ||
> -            excp_model == POWERPC_EXCP_POWER9 ||
> -            excp_model == POWERPC_EXCP_POWER10) {
> -            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> -        } else
> -#endif /* defined(TARGET_PPC64) */
> -        {
> -            lpes0 = true;
> -        }
> -
> -        if (!lpes0) {
> -            new_msr |= (target_ulong)MSR_HVB;
> -            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -            srr0 = SPR_HSRR0;
> -            srr1 = SPR_HSRR1;
> -        }
> -        if (env->mpic_proxy) {
> -            /* IACK the IRQ on delivery */
> -            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> -        }
>           break;
> -    }

Bare break?  Should this be reachable at all?
Should it in fact be g_assert_not_reached()?


r~

Re: [PATCH v2 07/14] target/ppc: 405: External exception cleanup

Posted by Fabiano Rosas 4 years ago

Richard Henderson <richard.henderson@linaro.org> writes:

> On 1/19/22 5:44 AM, Fabiano Rosas wrote:
>> 405 has no MSR_HV and EPR is BookE only so we can remove it all.
>> 
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>>   target/ppc/excp_helper.c | 37 -------------------------------------
>>   1 file changed, 37 deletions(-)
>> 
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index e98d783ecd..8fae8aa0be 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>>           msr |= env->error_code;
>>           break;
>>       case POWERPC_EXCP_EXTERNAL:  /* External input                           */
>> -    {
>> -        bool lpes0;
>> -
>> -        cs = CPU(cpu);
>> -
>> -        /*
>> -         * Exception targeting modifiers
>> -         *
>> -         * LPES0 is supported on POWER7/8/9
>> -         * LPES1 is not supported (old iSeries mode)
>> -         *
>> -         * On anything else, we behave as if LPES0 is 1
>> -         * (externals don't alter MSR:HV)
>> -         */
>> -#if defined(TARGET_PPC64)
>> -        if (excp_model == POWERPC_EXCP_POWER7 ||
>> -            excp_model == POWERPC_EXCP_POWER8 ||
>> -            excp_model == POWERPC_EXCP_POWER9 ||
>> -            excp_model == POWERPC_EXCP_POWER10) {
>> -            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
>> -        } else
>> -#endif /* defined(TARGET_PPC64) */
>> -        {
>> -            lpes0 = true;
>> -        }
>> -
>> -        if (!lpes0) {
>> -            new_msr |= (target_ulong)MSR_HVB;
>> -            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
>> -            srr0 = SPR_HSRR0;
>> -            srr1 = SPR_HSRR1;
>> -        }
>> -        if (env->mpic_proxy) {
>> -            /* IACK the IRQ on delivery */
>> -            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
>> -        }
>>           break;
>> -    }
>
> Bare break?  Should this be reachable at all?
> Should it in fact be g_assert_not_reached()?

It should be reachable. It is a valid exception for this CPU. We just
don't have anything else to do to dispatch it aside from what is done in
the generic code outside the switch statement.