[PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit

Fabiano Rosas posted 14 patches 4 years ago
Maintainers: "Cédric Le Goater" <clg@kaod.org>, Greg Kurz <groug@kaod.org>, Daniel Henrique Barboza <danielhb413@gmail.com>, David Gibson <david@gibson.dropbear.id.au>
[PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit
Posted by Fabiano Rosas 4 years ago
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e63705b1c6..23a13036b2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
                     (1ull << MSR_EE) |
                     (1ull << MSR_PR) |
                     (1ull << MSR_FP) |
+                    (1ull << MSR_ME) |
                     (1ull << MSR_DWE) |
                     (1ull << MSR_DE) |
                     (1ull << MSR_IR) |
-- 
2.33.1


Re: [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit
Posted by Cédric Le Goater 4 years ago
On 1/18/22 19:44, Fabiano Rosas wrote:
> The 405 MSR has the Machine Check Enable bit. We're making use of it
> when dispatching Machine Check, so add the bit to the msr_mask.
> 
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   target/ppc/cpu_init.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e63705b1c6..23a13036b2 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
>                       (1ull << MSR_EE) |
>                       (1ull << MSR_PR) |
>                       (1ull << MSR_FP) |
> +                    (1ull << MSR_ME) |
>                       (1ull << MSR_DWE) |
>                       (1ull << MSR_DE) |
>                       (1ull << MSR_IR) |
>