1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
Pretty small still, but there are two patches that ought
2
to get backported to stable, so no point in delaying.
2
3
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
4
r~
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
8
13
9
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
10
15
11
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
Fix for safe_syscall_base.
19
tcg: Reset free_temps before tcg_optimize
15
Fix for folding of vector add/sub.
20
tcg/riscv: Fix StoreStore barrier generation
16
Fix build on loongarch64 with gcc 8.
21
include/exec: Introduce fpst alias in helper-head.h.inc
17
Remove decl for qemu_run_machine_init_done_notifiers.
22
target/sparc: Use memcpy() and remove memcpy32()
18
23
19
----------------------------------------------------------------
24
----------------------------------------------------------------
20
Philippe Mathieu-Daudé (1):
25
Philippe Mathieu-Daudé (1):
21
linux-user: Fix trivial build error on loongarch64 hosts
26
target/sparc: Use memcpy() and remove memcpy32()
22
27
23
Richard Henderson (2):
28
Richard Henderson (2):
24
tcg/optimize: Fix folding of vector ops
29
tcg: Reset free_temps before tcg_optimize
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
30
include/exec: Introduce fpst alias in helper-head.h.inc
26
31
27
Xiaoyao Li (1):
32
Roman Artemev (1):
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
33
tcg/riscv: Fix StoreStore barrier generation
29
34
30
include/sysemu/sysemu.h | 1 -
35
include/tcg/tcg-temp-internal.h | 6 ++++++
31
linux-user/host/loongarch64/host-signal.h | 4 +--
36
accel/tcg/plugin-gen.c | 2 +-
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
37
target/sparc/win_helper.c | 26 ++++++++------------------
33
common-user/host/i386/safe-syscall.inc.S | 1 +
38
tcg/tcg.c | 5 ++++-
34
common-user/host/mips/safe-syscall.inc.S | 1 +
39
include/exec/helper-head.h.inc | 3 +++
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
40
tcg/riscv/tcg-target.c.inc | 2 +-
36
6 files changed, 42 insertions(+), 15 deletions(-)
41
6 files changed, 23 insertions(+), 21 deletions(-)
37
42
diff view generated by jsdifflib
1
For the ABIs in which the syscall return register is not
1
When allocating new temps during tcg_optmize, do not re-use
2
also the first function argument register, move the errno
2
any EBB temps that were used within the TB. We do not have
3
value into the correct place.
3
any idea what span of the TB in which the temp was live.
4
4
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
6
as well as replacing the equivalent in plugin_gen_inject and
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
7
tcg_func_start.
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
---
16
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
17
include/tcg/tcg-temp-internal.h | 6 ++++++
13
common-user/host/mips/safe-syscall.inc.S | 1 +
18
accel/tcg/plugin-gen.c | 2 +-
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
19
tcg/tcg.c | 5 ++++-
15
3 files changed, 3 insertions(+)
20
3 files changed, 11 insertions(+), 2 deletions(-)
16
21
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
18
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
24
--- a/include/tcg/tcg-temp-internal.h
20
+++ b/common-user/host/i386/safe-syscall.inc.S
25
+++ b/include/tcg/tcg-temp-internal.h
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
22
pop %ebp
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
23
.cfi_adjust_cfa_offset -4
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
24
.cfi_restore ebp
29
25
+ mov %eax, (%esp)
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
26
jmp safe_syscall_set_errno_tail
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
27
32
+{
28
.cfi_endproc
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
30
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
39
--- a/accel/tcg/plugin-gen.c
32
+++ b/common-user/host/mips/safe-syscall.inc.S
40
+++ b/accel/tcg/plugin-gen.c
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
34
1: USE_ALT_CP(t0)
42
* that might be live within the existing opcode stream.
35
SETUP_GPX(t1)
43
* The simplest solution is to release them all and create new.
36
SETUP_GPX64(t0, t1)
44
*/
37
+ move a0, v0
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
38
PTR_LA t9, safe_syscall_set_errno_tail
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
39
jr t9
47
40
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
42
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
52
--- a/tcg/tcg.c
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
53
+++ b/tcg/tcg.c
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
46
1: pop %rbp
55
s->nb_temps = s->nb_globals;
47
.cfi_def_cfa_offset 8
56
48
.cfi_restore rbp
57
/* No temps have been previously allocated for size or locality. */
49
+ mov %eax, %edi
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
50
jmp safe_syscall_set_errno_tail
59
+ tcg_temp_ebb_reset_freed(s);
51
.cfi_endproc
60
52
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
53
--
73
--
54
2.25.1
74
2.43.0
55
75
56
76
diff view generated by jsdifflib
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
2
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
3
On RISC-V to StoreStore barrier corresponds
4
and user.
4
`fence w, w` not `fence r, r`
5
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
6
Cc: qemu-stable@nongnu.org
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
13
---
12
include/sysemu/sysemu.h | 1 -
14
tcg/riscv/tcg-target.c.inc | 2 +-
13
1 file changed, 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
14
16
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
19
--- a/tcg/riscv/tcg-target.c.inc
18
+++ b/include/sysemu/sysemu.h
20
+++ b/tcg/riscv/tcg-target.c.inc
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
20
void qemu_add_exit_notifier(Notifier *notify);
22
insn |= 0x02100000;
21
void qemu_remove_exit_notifier(Notifier *notify);
23
}
22
24
if (a0 & TCG_MO_ST_ST) {
23
-void qemu_run_machine_init_done_notifiers(void);
25
- insn |= 0x02200000;
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
26
+ insn |= 0x01100000;
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
27
}
26
28
tcg_out32(s, insn);
29
}
27
--
30
--
28
2.25.1
31
2.43.0
29
30
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
2
3
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
6
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
7
include/exec/helper-head.h.inc | 3 +++
30
1 file changed, 1 insertion(+), 3 deletions(-)
8
1 file changed, 3 insertions(+)
31
9
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
33
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
12
--- a/include/exec/helper-head.h.inc
35
+++ b/linux-user/host/loongarch64/host-signal.h
13
+++ b/include/exec/helper-head.h.inc
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
14
@@ -XXX,XX +XXX,XX @@
37
}
15
#define dh_alias_ptr ptr
38
break;
16
#define dh_alias_cptr ptr
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
17
#define dh_alias_env ptr
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
18
+#define dh_alias_fpst ptr
41
-
19
#define dh_alias_void void
42
- switch (sel) {
20
#define dh_alias_noreturn noreturn
43
+ switch ((insn >> 15) & 0b11111111111) {
21
#define dh_alias(t) glue(dh_alias_, t)
44
case 0b00000100000: /* stx.b */
22
@@ -XXX,XX +XXX,XX @@
45
case 0b00000101000: /* stx.h */
23
#define dh_ctype_ptr void *
46
case 0b00000110000: /* stx.w */
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
47
--
38
--
48
2.25.1
39
2.43.0
49
40
50
41
diff view generated by jsdifflib
1
Bitwise operations are easy to fold, because the operation is
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
identical regardless of element size. But add and sub need
3
extra element size info that is not currently propagated.
4
2
5
Fixes: 2f9f08ba43d
3
Rather than manually copying each register, use
6
Cc: qemu-stable@nongnu.org
4
the libc memcpy(), which is well optimized nowadays.
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
5
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
12
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
13
target/sparc/win_helper.c | 26 ++++++++------------------
12
1 file changed, 38 insertions(+), 11 deletions(-)
14
1 file changed, 8 insertions(+), 18 deletions(-)
13
15
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
18
--- a/target/sparc/win_helper.c
17
+++ b/tcg/optimize.c
19
+++ b/target/sparc/win_helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
20
@@ -XXX,XX +XXX,XX @@
19
CASE_OP_32_64(mul):
21
#include "exec/helper-proto.h"
20
return x * y;
22
#include "trace.h"
21
23
22
- CASE_OP_32_64(and):
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
23
+ CASE_OP_32_64_VEC(and):
25
-{
24
return x & y;
26
- dst[0] = src[0];
25
27
- dst[1] = src[1];
26
- CASE_OP_32_64(or):
28
- dst[2] = src[2];
27
+ CASE_OP_32_64_VEC(or):
29
- dst[3] = src[3];
28
return x | y;
30
- dst[4] = src[4];
29
31
- dst[5] = src[5];
30
- CASE_OP_32_64(xor):
32
- dst[6] = src[6];
31
+ CASE_OP_32_64_VEC(xor):
33
- dst[7] = src[7];
32
return x ^ y;
34
-}
33
35
-
34
case INDEX_op_shl_i32:
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
37
{
36
case INDEX_op_rotl_i64:
38
/* put the modified wrap registers at their proper location */
37
return rol64(x, y & 63);
39
if (env->cwp == env->nwindows - 1) {
38
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
39
- CASE_OP_32_64(not):
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
40
+ CASE_OP_32_64_VEC(not):
42
+ sizeof(env->gregs));
41
return ~x;
43
}
42
44
env->cwp = new_cwp;
43
CASE_OP_32_64(neg):
45
44
return -x;
46
/* put the wrap registers at their temporary location */
45
47
if (new_cwp == env->nwindows - 1) {
46
- CASE_OP_32_64(andc):
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
47
+ CASE_OP_32_64_VEC(andc):
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
48
return x & ~y;
50
+ sizeof(env->gregs));
49
51
}
50
- CASE_OP_32_64(orc):
52
env->regwptr = env->regbase + (new_cwp * 16);
51
+ CASE_OP_32_64_VEC(orc):
52
return x | ~y;
53
54
CASE_OP_32_64(eqv):
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
56
return false;
57
}
53
}
58
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
55
dst = get_gl_gregset(env, env->gl);
60
+{
56
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
57
if (src != dst) {
62
+ return false;
58
- memcpy32(dst, env->gregs);
63
+}
59
- memcpy32(env->gregs, src);
64
+
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
66
{
62
}
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
69
return false;
70
}
63
}
71
64
72
+/* We cannot as yet do_constant_folding with vectors. */
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
66
/* Switch global register bank */
74
+{
67
src = get_gregset(env, new_pstate_regs);
75
+ if (fold_commutative(ctx, op) ||
68
dst = get_gregset(env, pstate_regs);
76
+ fold_xi_to_x(ctx, op, 0)) {
69
- memcpy32(dst, env->gregs);
77
+ return true;
70
- memcpy32(env->gregs, src);
78
+ }
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
79
+ return false;
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
80
+}
73
} else {
81
+
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
75
}
83
{
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
86
return false;
87
}
88
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
90
+/* We cannot as yet do_constant_folding with vectors. */
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
92
{
93
- if (fold_const2(ctx, op) ||
94
- fold_xx_to_i(ctx, op, 0) ||
95
+ if (fold_xx_to_i(ctx, op, 0) ||
96
fold_xi_to_x(ctx, op, 0) ||
97
fold_sub_to_neg(ctx, op)) {
98
return true;
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
100
return false;
101
}
102
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
104
+{
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
106
+}
107
+
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
109
{
110
return fold_addsub2(ctx, op, false);
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
* Sorted alphabetically by opcode as much as possible.
113
*/
114
switch (opc) {
115
- CASE_OP_32_64_VEC(add):
116
+ CASE_OP_32_64(add):
117
done = fold_add(&ctx, op);
118
break;
119
+ case INDEX_op_add_vec:
120
+ done = fold_add_vec(&ctx, op);
121
+ break;
122
CASE_OP_32_64(add2):
123
done = fold_add2(&ctx, op);
124
break;
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
126
CASE_OP_32_64(sextract):
127
done = fold_sextract(&ctx, op);
128
break;
129
- CASE_OP_32_64_VEC(sub):
130
+ CASE_OP_32_64(sub):
131
done = fold_sub(&ctx, op);
132
break;
133
+ case INDEX_op_sub_vec:
134
+ done = fold_sub_vec(&ctx, op);
135
+ break;
136
CASE_OP_32_64(sub2):
137
done = fold_sub2(&ctx, op);
138
break;
139
--
76
--
140
2.25.1
77
2.43.0
141
78
142
79
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