1 | The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea: | 1 | v2: Fix bsd-user signal.c Werror. |
---|---|---|---|
2 | 2 | I've conformed that it merges well with Warner's bsd-user pull. | |
3 | Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800) | 3 | |
4 | |||
5 | r~ | ||
6 | |||
7 | |||
8 | The following changes since commit da1034094d375afe9e3d8ec8980550ea0f06f7e0: | ||
9 | |||
10 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-10-03 07:43:44 -0400) | ||
4 | 11 | ||
5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
6 | 13 | ||
7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104 | 14 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231004 |
8 | 15 | ||
9 | for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4: | 16 | for you to fetch changes up to 79de3960ae1e322835112755d99187ee9b63a270: |
10 | 17 | ||
11 | common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800) | 18 | tcg/loongarch64: Fix buid error (2023-10-04 11:03:54 -0700) |
12 | 19 | ||
13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
14 | Fix for safe_syscall_base. | 21 | accel: Introduce AccelClass::cpu_common_[un]realize |
15 | Fix for folding of vector add/sub. | 22 | accel: Target agnostic code movement |
16 | Fix build on loongarch64 with gcc 8. | 23 | accel/tcg: Cleanups to use CPUState instead of CPUArchState |
17 | Remove decl for qemu_run_machine_init_done_notifiers. | 24 | accel/tcg: Move CPUNegativeOffsetState into CPUState |
25 | tcg: Split out tcg init functions to tcg/startup.h | ||
26 | linux-user/hppa: Fix struct target_sigcontext layout | ||
27 | build: Remove --enable-gprof | ||
18 | 28 | ||
19 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
20 | Philippe Mathieu-Daudé (1): | 30 | Anton Johansson (9): |
21 | linux-user: Fix trivial build error on loongarch64 hosts | 31 | target/arm: Replace TARGET_PAGE_ENTRY_EXTRA |
22 | 32 | accel/tcg: Modify tlb_*() to use CPUState | |
23 | Richard Henderson (2): | 33 | accel/tcg: Modify probe_access_internal() to use CPUState |
24 | tcg/optimize: Fix folding of vector ops | 34 | accel/tcg: Modify memory access functions to use CPUState |
25 | common-user: Fix tail calls to safe_syscall_set_errno_tail | 35 | accel/tcg: Modify atomic_mmu_lookup() to use CPUState |
26 | 36 | accel/tcg: Use CPUState in atomicity helpers | |
27 | Xiaoyao Li (1): | 37 | accel/tcg: Remove env_tlb() |
28 | sysemu: Cleanup qemu_run_machine_init_done_notifiers() | 38 | accel/tcg: Unify user and softmmu do_[st|ld]*_mmu() |
29 | 39 | accel/tcg: move ld/st helpers to ldst_common.c.inc | |
30 | include/sysemu/sysemu.h | 1 - | 40 | |
31 | linux-user/host/loongarch64/host-signal.h | 4 +-- | 41 | Philippe Mathieu-Daudé (19): |
32 | tcg/optimize.c | 49 +++++++++++++++++++++++------- | 42 | accel: Rename accel_cpu_realizefn() -> accel_cpu_realize() |
33 | common-user/host/i386/safe-syscall.inc.S | 1 + | 43 | accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize() |
34 | common-user/host/mips/safe-syscall.inc.S | 1 + | 44 | accel: Rename accel_cpu_realize() -> accel_cpu_common_realize() |
35 | common-user/host/x86_64/safe-syscall.inc.S | 1 + | 45 | accel: Introduce accel_cpu_common_unrealize() stub |
36 | 6 files changed, 42 insertions(+), 15 deletions(-) | 46 | accel: Declare AccelClass::cpu_common_[un]realize() handlers |
37 | 47 | accel/tcg: Have tcg_exec_realizefn() return a boolean | |
48 | accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG | ||
49 | exec: Make EXCP_FOO definitions target agnostic | ||
50 | exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h' | ||
51 | accel/tcg: Restrict dump_exec_info() declaration | ||
52 | accel: Make accel-blocker.o target agnostic | ||
53 | accel: Rename accel-common.c -> accel-target.c | ||
54 | exec: Rename cpu.c -> cpu-target.c | ||
55 | exec: Rename target specific page-vary.c -> page-vary-target.c | ||
56 | accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h' | ||
57 | accel/tcg: Make monitor.c a target-agnostic unit | ||
58 | accel/tcg: Make icount.o a target agnostic unit | ||
59 | accel/tcg: Make cpu-exec-common.c a target agnostic unit | ||
60 | tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed) | ||
61 | |||
62 | Richard Henderson (18): | ||
63 | accel/tcg: Move CPUTLB definitions from cpu-defs.h | ||
64 | qom: Propagate alignment through type system | ||
65 | target/arm: Remove size and alignment for cpu subclasses | ||
66 | target/*: Add instance_align to all cpu base classes | ||
67 | accel/tcg: Validate placement of CPUNegativeOffsetState | ||
68 | accel/tcg: Move CPUNegativeOffsetState into CPUState | ||
69 | accel/tcg: Remove CPUState.icount_decr_ptr | ||
70 | accel/tcg: Move can_do_io to CPUNegativeOffsetState | ||
71 | accel/tcg: Remove cpu_neg() | ||
72 | tcg: Rename cpu_env to tcg_env | ||
73 | accel/tcg: Replace CPUState.env_ptr with cpu_env() | ||
74 | accel/tcg: Remove cpu_set_cpustate_pointers | ||
75 | accel/tcg: Remove env_neg() | ||
76 | tcg: Remove TCGContext.tlb_fast_offset | ||
77 | tcg: Remove argument to tcg_prologue_init | ||
78 | tcg: Split out tcg init functions to tcg/startup.h | ||
79 | linux-user/hppa: Fix struct target_sigcontext layout | ||
80 | build: Remove --enable-gprof | ||
81 | |||
82 | gaosong (1): | ||
83 | tcg/loongarch64: Fix buid error | ||
84 | |||
85 | MAINTAINERS | 7 +- | ||
86 | docs/about/deprecated.rst | 14 - | ||
87 | meson.build | 18 +- | ||
88 | accel/tcg/atomic_template.h | 20 +- | ||
89 | accel/tcg/internal-common.h | 28 + | ||
90 | accel/tcg/{internal.h => internal-target.h} | 21 +- | ||
91 | bsd-user/bsd-proc.h | 3 - | ||
92 | include/exec/cpu-all.h | 67 +- | ||
93 | include/exec/cpu-common.h | 39 + | ||
94 | include/exec/cpu-defs.h | 138 --- | ||
95 | include/exec/cpu_ldst.h | 8 +- | ||
96 | include/exec/exec-all.h | 32 +- | ||
97 | include/hw/core/accel-cpu.h | 2 +- | ||
98 | include/hw/core/cpu.h | 171 ++- | ||
99 | include/qemu/accel.h | 12 +- | ||
100 | include/tcg/startup.h | 58 + | ||
101 | include/tcg/tcg.h | 6 +- | ||
102 | target/alpha/cpu.h | 1 - | ||
103 | target/arm/common-semi-target.h | 2 +- | ||
104 | target/arm/cpu-param.h | 12 - | ||
105 | target/arm/cpu.h | 1 - | ||
106 | target/arm/tcg/translate-a32.h | 2 +- | ||
107 | target/arm/tcg/translate-a64.h | 4 +- | ||
108 | target/arm/tcg/translate.h | 16 +- | ||
109 | target/avr/cpu.h | 1 - | ||
110 | target/cris/cpu.h | 1 - | ||
111 | target/hexagon/cpu.h | 2 +- | ||
112 | target/hexagon/gen_tcg.h | 120 +- | ||
113 | target/hexagon/gen_tcg_hvx.h | 20 +- | ||
114 | target/hexagon/macros.h | 8 +- | ||
115 | target/hppa/cpu.h | 1 - | ||
116 | target/i386/cpu.h | 1 - | ||
117 | target/loongarch/cpu.h | 1 - | ||
118 | target/m68k/cpu.h | 1 - | ||
119 | target/microblaze/cpu.h | 6 +- | ||
120 | target/mips/cpu.h | 4 +- | ||
121 | target/mips/tcg/translate.h | 6 +- | ||
122 | target/nios2/cpu.h | 1 - | ||
123 | target/openrisc/cpu.h | 1 - | ||
124 | target/ppc/cpu.h | 1 - | ||
125 | target/riscv/cpu.h | 2 +- | ||
126 | target/rx/cpu.h | 1 - | ||
127 | target/s390x/cpu.h | 1 - | ||
128 | target/sh4/cpu.h | 1 - | ||
129 | target/sparc/cpu.h | 1 - | ||
130 | target/tricore/cpu.h | 1 - | ||
131 | target/xtensa/cpu.h | 3 +- | ||
132 | accel/{accel-common.c => accel-target.c} | 27 +- | ||
133 | accel/dummy-cpus.c | 2 +- | ||
134 | accel/hvf/hvf-accel-ops.c | 2 +- | ||
135 | accel/kvm/kvm-accel-ops.c | 2 +- | ||
136 | accel/tcg/cpu-exec-common.c | 5 +- | ||
137 | accel/tcg/cpu-exec.c | 31 +- | ||
138 | accel/tcg/cputlb.c | 787 +++++------- | ||
139 | softmmu/icount.c => accel/tcg/icount-common.c | 7 +- | ||
140 | accel/tcg/monitor.c | 2 +- | ||
141 | accel/tcg/plugin-gen.c | 10 +- | ||
142 | accel/tcg/tb-maint.c | 3 +- | ||
143 | accel/tcg/tcg-accel-ops-icount.c | 8 +- | ||
144 | accel/tcg/tcg-accel-ops-mttcg.c | 4 +- | ||
145 | accel/tcg/tcg-accel-ops-rr.c | 6 +- | ||
146 | accel/tcg/tcg-accel-ops.c | 2 +- | ||
147 | accel/tcg/tcg-all.c | 8 +- | ||
148 | accel/tcg/translate-all.c | 15 +- | ||
149 | accel/tcg/translator.c | 24 +- | ||
150 | accel/tcg/user-exec.c | 279 +---- | ||
151 | bsd-user/main.c | 6 +- | ||
152 | bsd-user/signal.c | 14 +- | ||
153 | cpus-common.c => cpu-common.c | 0 | ||
154 | cpu.c => cpu-target.c | 13 +- | ||
155 | gdbstub/gdbstub.c | 4 +- | ||
156 | gdbstub/user-target.c | 2 +- | ||
157 | hw/core/cpu-common.c | 6 +- | ||
158 | hw/i386/kvm/clock.c | 2 +- | ||
159 | hw/intc/mips_gic.c | 2 +- | ||
160 | hw/intc/riscv_aclint.c | 12 +- | ||
161 | hw/intc/riscv_imsic.c | 2 +- | ||
162 | hw/ppc/e500.c | 4 +- | ||
163 | hw/ppc/spapr.c | 2 +- | ||
164 | linux-user/elfload.c | 4 +- | ||
165 | linux-user/exit.c | 6 - | ||
166 | linux-user/hppa/signal.c | 2 +- | ||
167 | linux-user/i386/cpu_loop.c | 2 +- | ||
168 | linux-user/main.c | 8 +- | ||
169 | linux-user/signal.c | 20 +- | ||
170 | linux-user/syscall.c | 2 +- | ||
171 | monitor/hmp-cmds-target.c | 2 +- | ||
172 | page-vary.c => page-vary-target.c | 0 | ||
173 | qom/object.c | 14 + | ||
174 | semihosting/arm-compat-semi.c | 6 +- | ||
175 | semihosting/syscalls.c | 28 +- | ||
176 | softmmu/watchpoint.c | 2 +- | ||
177 | target/alpha/cpu.c | 3 +- | ||
178 | target/alpha/translate.c | 146 +-- | ||
179 | target/arm/cpu.c | 12 +- | ||
180 | target/arm/cpu64.c | 4 - | ||
181 | target/arm/helper.c | 2 +- | ||
182 | target/arm/ptw.c | 4 +- | ||
183 | target/arm/tcg/mte_helper.c | 2 +- | ||
184 | target/arm/tcg/sve_helper.c | 2 +- | ||
185 | target/arm/tcg/tlb_helper.c | 4 +- | ||
186 | target/arm/tcg/translate-a64.c | 384 +++--- | ||
187 | target/arm/tcg/translate-m-nocp.c | 24 +- | ||
188 | target/arm/tcg/translate-mve.c | 52 +- | ||
189 | target/arm/tcg/translate-neon.c | 78 +- | ||
190 | target/arm/tcg/translate-sme.c | 8 +- | ||
191 | target/arm/tcg/translate-sve.c | 172 +-- | ||
192 | target/arm/tcg/translate-vfp.c | 56 +- | ||
193 | target/arm/tcg/translate.c | 234 ++-- | ||
194 | target/avr/cpu.c | 3 +- | ||
195 | target/avr/translate.c | 66 +- | ||
196 | target/cris/cpu.c | 3 +- | ||
197 | target/cris/translate.c | 72 +- | ||
198 | target/hexagon/cpu.c | 4 +- | ||
199 | target/hexagon/genptr.c | 36 +- | ||
200 | target/hexagon/idef-parser/parser-helpers.c | 2 +- | ||
201 | target/hexagon/translate.c | 52 +- | ||
202 | target/hppa/cpu.c | 2 +- | ||
203 | target/hppa/mem_helper.c | 2 +- | ||
204 | target/hppa/translate.c | 161 ++- | ||
205 | target/i386/cpu.c | 2 +- | ||
206 | target/i386/hvf/hvf-cpu.c | 2 +- | ||
207 | target/i386/kvm/kvm-cpu.c | 4 +- | ||
208 | target/i386/nvmm/nvmm-all.c | 14 +- | ||
209 | target/i386/tcg/sysemu/excp_helper.c | 2 +- | ||
210 | target/i386/tcg/tcg-cpu.c | 4 +- | ||
211 | target/i386/tcg/translate.c | 584 ++++----- | ||
212 | target/i386/whpx/whpx-all.c | 26 +- | ||
213 | target/loongarch/cpu.c | 9 +- | ||
214 | target/loongarch/translate.c | 22 +- | ||
215 | target/m68k/cpu.c | 9 +- | ||
216 | target/m68k/translate.c | 306 ++--- | ||
217 | target/microblaze/cpu.c | 2 +- | ||
218 | target/microblaze/translate.c | 52 +- | ||
219 | target/mips/cpu.c | 2 +- | ||
220 | target/mips/tcg/lcsr_translate.c | 6 +- | ||
221 | target/mips/tcg/msa_translate.c | 34 +- | ||
222 | target/mips/tcg/mxu_translate.c | 4 +- | ||
223 | target/mips/tcg/sysemu/mips-semi.c | 4 +- | ||
224 | target/mips/tcg/translate.c | 1288 ++++++++++---------- | ||
225 | target/mips/tcg/vr54xx_translate.c | 2 +- | ||
226 | target/nios2/cpu.c | 5 +- | ||
227 | target/nios2/translate.c | 52 +- | ||
228 | target/openrisc/cpu.c | 7 +- | ||
229 | target/openrisc/translate.c | 86 +- | ||
230 | target/ppc/cpu_init.c | 1 - | ||
231 | target/ppc/excp_helper.c | 10 +- | ||
232 | target/ppc/translate.c | 366 +++--- | ||
233 | target/riscv/cpu.c | 8 +- | ||
234 | target/riscv/translate.c | 56 +- | ||
235 | target/rx/cpu.c | 5 +- | ||
236 | target/rx/translate.c | 58 +- | ||
237 | target/s390x/cpu.c | 2 - | ||
238 | target/s390x/tcg/translate.c | 426 +++---- | ||
239 | target/sh4/cpu.c | 3 +- | ||
240 | target/sh4/op_helper.c | 2 +- | ||
241 | target/sh4/translate.c | 128 +- | ||
242 | target/sparc/cpu.c | 3 +- | ||
243 | target/sparc/translate.c | 332 ++--- | ||
244 | target/tricore/cpu.c | 10 +- | ||
245 | target/tricore/translate.c | 230 ++-- | ||
246 | target/xtensa/cpu.c | 2 +- | ||
247 | target/xtensa/translate.c | 192 +-- | ||
248 | tcg/tcg-op-gvec.c | 300 ++--- | ||
249 | tcg/tcg-op-ldst.c | 22 +- | ||
250 | tcg/tcg-op.c | 2 +- | ||
251 | tcg/tcg.c | 23 +- | ||
252 | accel/tcg/ldst_atomicity.c.inc | 88 +- | ||
253 | accel/tcg/ldst_common.c.inc | 225 ++++ | ||
254 | target/cris/translate_v10.c.inc | 28 +- | ||
255 | target/i386/tcg/decode-new.c.inc | 4 +- | ||
256 | target/i386/tcg/emit.c.inc | 262 ++-- | ||
257 | target/loongarch/insn_trans/trans_atomic.c.inc | 4 +- | ||
258 | target/loongarch/insn_trans/trans_branch.c.inc | 2 +- | ||
259 | target/loongarch/insn_trans/trans_extra.c.inc | 10 +- | ||
260 | target/loongarch/insn_trans/trans_farith.c.inc | 6 +- | ||
261 | target/loongarch/insn_trans/trans_fcmp.c.inc | 8 +- | ||
262 | target/loongarch/insn_trans/trans_fmemory.c.inc | 8 +- | ||
263 | target/loongarch/insn_trans/trans_fmov.c.inc | 20 +- | ||
264 | target/loongarch/insn_trans/trans_memory.c.inc | 8 +- | ||
265 | target/loongarch/insn_trans/trans_privileged.c.inc | 52 +- | ||
266 | target/loongarch/insn_trans/trans_vec.c.inc | 24 +- | ||
267 | target/mips/tcg/micromips_translate.c.inc | 12 +- | ||
268 | target/mips/tcg/nanomips_translate.c.inc | 200 +-- | ||
269 | target/ppc/power8-pmu-regs.c.inc | 8 +- | ||
270 | target/ppc/translate/branch-impl.c.inc | 2 +- | ||
271 | target/ppc/translate/dfp-impl.c.inc | 22 +- | ||
272 | target/ppc/translate/fixedpoint-impl.c.inc | 2 +- | ||
273 | target/ppc/translate/fp-impl.c.inc | 50 +- | ||
274 | target/ppc/translate/processor-ctrl-impl.c.inc | 8 +- | ||
275 | target/ppc/translate/spe-impl.c.inc | 30 +- | ||
276 | target/ppc/translate/storage-ctrl-impl.c.inc | 26 +- | ||
277 | target/ppc/translate/vmx-impl.c.inc | 34 +- | ||
278 | target/ppc/translate/vsx-impl.c.inc | 54 +- | ||
279 | target/riscv/insn_trans/trans_privileged.c.inc | 8 +- | ||
280 | target/riscv/insn_trans/trans_rvbf16.c.inc | 10 +- | ||
281 | target/riscv/insn_trans/trans_rvd.c.inc | 48 +- | ||
282 | target/riscv/insn_trans/trans_rvf.c.inc | 46 +- | ||
283 | target/riscv/insn_trans/trans_rvh.c.inc | 8 +- | ||
284 | target/riscv/insn_trans/trans_rvi.c.inc | 16 +- | ||
285 | target/riscv/insn_trans/trans_rvm.c.inc | 16 +- | ||
286 | target/riscv/insn_trans/trans_rvv.c.inc | 130 +- | ||
287 | target/riscv/insn_trans/trans_rvvk.c.inc | 30 +- | ||
288 | target/riscv/insn_trans/trans_rvzce.c.inc | 2 +- | ||
289 | target/riscv/insn_trans/trans_rvzfa.c.inc | 38 +- | ||
290 | target/riscv/insn_trans/trans_rvzfh.c.inc | 54 +- | ||
291 | target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 +- | ||
292 | target/riscv/insn_trans/trans_svinval.c.inc | 6 +- | ||
293 | target/riscv/insn_trans/trans_xthead.c.inc | 2 +- | ||
294 | target/s390x/tcg/translate_vx.c.inc | 104 +- | ||
295 | tcg/aarch64/tcg-target.c.inc | 2 +- | ||
296 | tcg/arm/tcg-target.c.inc | 2 +- | ||
297 | tcg/loongarch64/tcg-target.c.inc | 68 +- | ||
298 | accel/meson.build | 4 +- | ||
299 | accel/tcg/meson.build | 8 +- | ||
300 | meson_options.txt | 3 - | ||
301 | scripts/meson-buildoptions.sh | 3 - | ||
302 | softmmu/meson.build | 4 - | ||
303 | target/hexagon/README | 10 +- | ||
304 | target/hexagon/gen_tcg_funcs.py | 16 +- | ||
305 | tests/avocado/boot_linux_console.py | 7 - | ||
306 | tests/avocado/machine_mips_malta.py | 6 - | ||
307 | tests/avocado/replay_kernel.py | 7 - | ||
308 | tests/avocado/tuxrun_baselines.py | 4 - | ||
309 | tests/qemu-iotests/meson.build | 2 +- | ||
310 | 225 files changed, 5101 insertions(+), 5323 deletions(-) | ||
311 | create mode 100644 accel/tcg/internal-common.h | ||
312 | rename accel/tcg/{internal.h => internal-target.h} (89%) | ||
313 | create mode 100644 include/tcg/startup.h | ||
314 | rename accel/{accel-common.c => accel-target.c} (86%) | ||
315 | rename softmmu/icount.c => accel/tcg/icount-common.c (99%) | ||
316 | rename cpus-common.c => cpu-common.c (100%) | ||
317 | rename cpu.c => cpu-target.c (97%) | ||
318 | rename page-vary.c => page-vary-target.c (100%) | ||
319 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Bitwise operations are easy to fold, because the operation is | ||
2 | identical regardless of element size. But add and sub need | ||
3 | extra element size info that is not currently propagated. | ||
4 | 1 | ||
5 | Fixes: 2f9f08ba43d | ||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799 | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++----------- | ||
12 | 1 file changed, 38 insertions(+), 11 deletions(-) | ||
13 | |||
14 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tcg/optimize.c | ||
17 | +++ b/tcg/optimize.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | ||
19 | CASE_OP_32_64(mul): | ||
20 | return x * y; | ||
21 | |||
22 | - CASE_OP_32_64(and): | ||
23 | + CASE_OP_32_64_VEC(and): | ||
24 | return x & y; | ||
25 | |||
26 | - CASE_OP_32_64(or): | ||
27 | + CASE_OP_32_64_VEC(or): | ||
28 | return x | y; | ||
29 | |||
30 | - CASE_OP_32_64(xor): | ||
31 | + CASE_OP_32_64_VEC(xor): | ||
32 | return x ^ y; | ||
33 | |||
34 | case INDEX_op_shl_i32: | ||
35 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | ||
36 | case INDEX_op_rotl_i64: | ||
37 | return rol64(x, y & 63); | ||
38 | |||
39 | - CASE_OP_32_64(not): | ||
40 | + CASE_OP_32_64_VEC(not): | ||
41 | return ~x; | ||
42 | |||
43 | CASE_OP_32_64(neg): | ||
44 | return -x; | ||
45 | |||
46 | - CASE_OP_32_64(andc): | ||
47 | + CASE_OP_32_64_VEC(andc): | ||
48 | return x & ~y; | ||
49 | |||
50 | - CASE_OP_32_64(orc): | ||
51 | + CASE_OP_32_64_VEC(orc): | ||
52 | return x | ~y; | ||
53 | |||
54 | CASE_OP_32_64(eqv): | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op) | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | +static bool fold_commutative(OptContext *ctx, TCGOp *op) | ||
60 | +{ | ||
61 | + swap_commutative(op->args[0], &op->args[1], &op->args[2]); | ||
62 | + return false; | ||
63 | +} | ||
64 | + | ||
65 | static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) | ||
66 | { | ||
67 | swap_commutative(op->args[0], &op->args[1], &op->args[2]); | ||
68 | @@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op) | ||
69 | return false; | ||
70 | } | ||
71 | |||
72 | +/* We cannot as yet do_constant_folding with vectors. */ | ||
73 | +static bool fold_add_vec(OptContext *ctx, TCGOp *op) | ||
74 | +{ | ||
75 | + if (fold_commutative(ctx, op) || | ||
76 | + fold_xi_to_x(ctx, op, 0)) { | ||
77 | + return true; | ||
78 | + } | ||
79 | + return false; | ||
80 | +} | ||
81 | + | ||
82 | static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) | ||
83 | { | ||
84 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) && | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) | ||
86 | return false; | ||
87 | } | ||
88 | |||
89 | -static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
90 | +/* We cannot as yet do_constant_folding with vectors. */ | ||
91 | +static bool fold_sub_vec(OptContext *ctx, TCGOp *op) | ||
92 | { | ||
93 | - if (fold_const2(ctx, op) || | ||
94 | - fold_xx_to_i(ctx, op, 0) || | ||
95 | + if (fold_xx_to_i(ctx, op, 0) || | ||
96 | fold_xi_to_x(ctx, op, 0) || | ||
97 | fold_sub_to_neg(ctx, op)) { | ||
98 | return true; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
100 | return false; | ||
101 | } | ||
102 | |||
103 | +static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
104 | +{ | ||
105 | + return fold_const2(ctx, op) || fold_sub_vec(ctx, op); | ||
106 | +} | ||
107 | + | ||
108 | static bool fold_sub2(OptContext *ctx, TCGOp *op) | ||
109 | { | ||
110 | return fold_addsub2(ctx, op, false); | ||
111 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
112 | * Sorted alphabetically by opcode as much as possible. | ||
113 | */ | ||
114 | switch (opc) { | ||
115 | - CASE_OP_32_64_VEC(add): | ||
116 | + CASE_OP_32_64(add): | ||
117 | done = fold_add(&ctx, op); | ||
118 | break; | ||
119 | + case INDEX_op_add_vec: | ||
120 | + done = fold_add_vec(&ctx, op); | ||
121 | + break; | ||
122 | CASE_OP_32_64(add2): | ||
123 | done = fold_add2(&ctx, op); | ||
124 | break; | ||
125 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
126 | CASE_OP_32_64(sextract): | ||
127 | done = fold_sextract(&ctx, op); | ||
128 | break; | ||
129 | - CASE_OP_32_64_VEC(sub): | ||
130 | + CASE_OP_32_64(sub): | ||
131 | done = fold_sub(&ctx, op); | ||
132 | break; | ||
133 | + case INDEX_op_sub_vec: | ||
134 | + done = fold_sub_vec(&ctx, op); | ||
135 | + break; | ||
136 | CASE_OP_32_64(sub2): | ||
137 | done = fold_sub2(&ctx, op); | ||
138 | break; | ||
139 | -- | ||
140 | 2.25.1 | ||
141 | |||
142 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | When building using GCC 8.3.0 on loongarch64 (Loongnix) we get: | ||
4 | |||
5 | In file included from ../linux-user/signal.c:33: | ||
6 | ../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’: | ||
7 | ../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement | ||
8 | uint32_t sel = (insn >> 15) & 0b11111111111; | ||
9 | ^~~~~~~~ | ||
10 | |||
11 | We don't use the 'sel' variable more than once, so drop it. | ||
12 | |||
13 | Meson output for the record: | ||
14 | |||
15 | Host machine cpu family: loongarch64 | ||
16 | Host machine cpu: loongarch64 | ||
17 | C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0") | ||
18 | C linker for the host machine: cc ld.bfd 2.31.1-system | ||
19 | |||
20 | Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts") | ||
21 | Reported-by: Song Gao <gaosong@loongson.cn> | ||
22 | Suggested-by: Song Gao <gaosong@loongson.cn> | ||
23 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
24 | Reviewed-by: WANG Xuerui <git@xen0n.name> | ||
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-Id: <20220104215027.2180972-1-f4bug@amsat.org> | ||
27 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
28 | --- | ||
29 | linux-user/host/loongarch64/host-signal.h | 4 +--- | ||
30 | 1 file changed, 1 insertion(+), 3 deletions(-) | ||
31 | |||
32 | diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/linux-user/host/loongarch64/host-signal.h | ||
35 | +++ b/linux-user/host/loongarch64/host-signal.h | ||
36 | @@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) | ||
37 | } | ||
38 | break; | ||
39 | case 0b001110: /* indexed, atomic, bounds-checking memory operations */ | ||
40 | - uint32_t sel = (insn >> 15) & 0b11111111111; | ||
41 | - | ||
42 | - switch (sel) { | ||
43 | + switch ((insn >> 15) & 0b11111111111) { | ||
44 | case 0b00000100000: /* stx.b */ | ||
45 | case 0b00000101000: /* stx.h */ | ||
46 | case 0b00000110000: /* stx.w */ | ||
47 | -- | ||
48 | 2.25.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Xiaoyao Li <xiaoyao.li@intel.com> | ||
2 | 1 | ||
3 | Remove qemu_run_machine_init_done_notifiers() since no implementation | ||
4 | and user. | ||
5 | |||
6 | Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c") | ||
7 | Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | include/sysemu/sysemu.h | 1 - | ||
13 | 1 file changed, 1 deletion(-) | ||
14 | |||
15 | diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/sysemu/sysemu.h | ||
18 | +++ b/include/sysemu/sysemu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set; | ||
20 | void qemu_add_exit_notifier(Notifier *notify); | ||
21 | void qemu_remove_exit_notifier(Notifier *notify); | ||
22 | |||
23 | -void qemu_run_machine_init_done_notifiers(void); | ||
24 | void qemu_add_machine_init_done_notifier(Notifier *notify); | ||
25 | void qemu_remove_machine_init_done_notifier(Notifier *notify); | ||
26 | |||
27 | -- | ||
28 | 2.25.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For the ABIs in which the syscall return register is not | ||
2 | also the first function argument register, move the errno | ||
3 | value into the correct place. | ||
4 | 1 | ||
5 | Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base") | ||
6 | Reported-by: Laurent Vivier <laurent@vivier.eu> | ||
7 | Tested-by: Laurent Vivier <laurent@vivier.eu> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org> | ||
11 | --- | ||
12 | common-user/host/i386/safe-syscall.inc.S | 1 + | ||
13 | common-user/host/mips/safe-syscall.inc.S | 1 + | ||
14 | common-user/host/x86_64/safe-syscall.inc.S | 1 + | ||
15 | 3 files changed, 3 insertions(+) | ||
16 | |||
17 | diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/common-user/host/i386/safe-syscall.inc.S | ||
20 | +++ b/common-user/host/i386/safe-syscall.inc.S | ||
21 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
22 | pop %ebp | ||
23 | .cfi_adjust_cfa_offset -4 | ||
24 | .cfi_restore ebp | ||
25 | + mov %eax, (%esp) | ||
26 | jmp safe_syscall_set_errno_tail | ||
27 | |||
28 | .cfi_endproc | ||
29 | diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/common-user/host/mips/safe-syscall.inc.S | ||
32 | +++ b/common-user/host/mips/safe-syscall.inc.S | ||
33 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
34 | 1: USE_ALT_CP(t0) | ||
35 | SETUP_GPX(t1) | ||
36 | SETUP_GPX64(t0, t1) | ||
37 | + move a0, v0 | ||
38 | PTR_LA t9, safe_syscall_set_errno_tail | ||
39 | jr t9 | ||
40 | |||
41 | diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/common-user/host/x86_64/safe-syscall.inc.S | ||
44 | +++ b/common-user/host/x86_64/safe-syscall.inc.S | ||
45 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
46 | 1: pop %rbp | ||
47 | .cfi_def_cfa_offset 8 | ||
48 | .cfi_restore rbp | ||
49 | + mov %eax, %edi | ||
50 | jmp safe_syscall_set_errno_tail | ||
51 | .cfi_endproc | ||
52 | |||
53 | -- | ||
54 | 2.25.1 | ||
55 | |||
56 | diff view generated by jsdifflib |