[PULL 0/4] tcg patch queue
[PULL v2 00/53] tcg patch queue
1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
v2: Remove poisoned symbol CONFIG_RISCV_DIS from disas.c.
2
Wasn't visible from x86 with gcc or clang;
3
was visible from macos clang;
4
was visible from native riscv clang.
2
5
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
6
7
r~
8
9
10
The following changes since commit fff86d48a2cdcdfa75f845cac3e0d3cdd848d9e4:
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12
Merge tag 'migration-20230509-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-05-11 05:55:12 +0100)
4
13
5
are available in the Git repository at:
14
are available in the Git repository at:
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15
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
16
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230511-2
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17
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for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
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for you to fetch changes up to 335dfd253fc242b009a1b9b5d4fffbf4ea52928d:
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common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
20
target/loongarch: Do not include tcg-ldst.h (2023-05-11 09:53:41 +0100)
12
21
13
----------------------------------------------------------------
22
----------------------------------------------------------------
14
Fix for safe_syscall_base.
23
target/m68k: Fix gen_load_fp regression
15
Fix for folding of vector add/sub.
24
accel/tcg: Ensure fairness with icount
16
Fix build on loongarch64 with gcc 8.
25
disas: Move disas.c into the target-independent source sets
17
Remove decl for qemu_run_machine_init_done_notifiers.
26
tcg: Use common routines for calling slow path helpers
27
tcg/*: Cleanups to qemu_ld/st constraints
28
tcg: Remove TARGET_ALIGNED_ONLY
29
accel/tcg: Reorg system mode load/store helpers
18
30
19
----------------------------------------------------------------
31
----------------------------------------------------------------
20
Philippe Mathieu-Daudé (1):
32
Jamie Iles (2):
21
linux-user: Fix trivial build error on loongarch64 hosts
33
cpu: expose qemu_cpu_list_lock for lock-guard use
34
accel/tcg/tcg-accel-ops-rr: ensure fairness with icount
22
35
23
Richard Henderson (2):
36
Richard Henderson (49):
24
tcg/optimize: Fix folding of vector ops
37
target/m68k: Fix gen_load_fp for OS_LONG
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
38
accel/tcg: Fix atomic_mmu_lookup for reads
39
disas: Fix tabs and braces in disas.c
40
disas: Move disas.c to disas/
41
disas: Remove target_ulong from the interface
42
disas: Remove target-specific headers
43
tcg/i386: Introduce prepare_host_addr
44
tcg/i386: Use indexed addressing for softmmu fast path
45
tcg/aarch64: Introduce prepare_host_addr
46
tcg/arm: Introduce prepare_host_addr
47
tcg/loongarch64: Introduce prepare_host_addr
48
tcg/mips: Introduce prepare_host_addr
49
tcg/ppc: Introduce prepare_host_addr
50
tcg/riscv: Introduce prepare_host_addr
51
tcg/s390x: Introduce prepare_host_addr
52
tcg: Add routines for calling slow-path helpers
53
tcg/i386: Convert tcg_out_qemu_ld_slow_path
54
tcg/i386: Convert tcg_out_qemu_st_slow_path
55
tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path
56
tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path
57
tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path
58
tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path
59
tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path
60
tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path
61
tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path
62
tcg/loongarch64: Simplify constraints on qemu_ld/st
63
tcg/mips: Remove MO_BSWAP handling
64
tcg/mips: Reorg tlb load within prepare_host_addr
65
tcg/mips: Simplify constraints on qemu_ld/st
66
tcg/ppc: Reorg tcg_out_tlb_read
67
tcg/ppc: Adjust constraints on qemu_ld/st
68
tcg/ppc: Remove unused constraints A, B, C, D
69
tcg/ppc: Remove unused constraint J
70
tcg/riscv: Simplify constraints on qemu_ld/st
71
tcg/s390x: Use ALGFR in constructing softmmu host address
72
tcg/s390x: Simplify constraints on qemu_ld/st
73
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
74
target/mips: Add missing default_tcg_memop_mask
75
target/mips: Use MO_ALIGN instead of 0
76
target/mips: Remove TARGET_ALIGNED_ONLY
77
target/nios2: Remove TARGET_ALIGNED_ONLY
78
target/sh4: Use MO_ALIGN where required
79
target/sh4: Remove TARGET_ALIGNED_ONLY
80
tcg: Remove TARGET_ALIGNED_ONLY
81
accel/tcg: Add cpu_in_serial_context
82
accel/tcg: Introduce tlb_read_idx
83
accel/tcg: Reorg system mode load helpers
84
accel/tcg: Reorg system mode store helpers
85
target/loongarch: Do not include tcg-ldst.h
26
86
27
Xiaoyao Li (1):
87
Thomas Huth (2):
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
88
disas: Move softmmu specific code to separate file
89
disas: Move disas.c into the target-independent source set
29
90
30
include/sysemu/sysemu.h | 1 -
91
configs/targets/mips-linux-user.mak | 1 -
31
linux-user/host/loongarch64/host-signal.h | 4 +--
92
configs/targets/mips-softmmu.mak | 1 -
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
93
configs/targets/mips64-linux-user.mak | 1 -
33
common-user/host/i386/safe-syscall.inc.S | 1 +
94
configs/targets/mips64-softmmu.mak | 1 -
34
common-user/host/mips/safe-syscall.inc.S | 1 +
95
configs/targets/mips64el-linux-user.mak | 1 -
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
96
configs/targets/mips64el-softmmu.mak | 1 -
36
6 files changed, 42 insertions(+), 15 deletions(-)
97
configs/targets/mipsel-linux-user.mak | 1 -
37
98
configs/targets/mipsel-softmmu.mak | 1 -
99
configs/targets/mipsn32-linux-user.mak | 1 -
100
configs/targets/mipsn32el-linux-user.mak | 1 -
101
configs/targets/nios2-softmmu.mak | 1 -
102
configs/targets/sh4-linux-user.mak | 1 -
103
configs/targets/sh4-softmmu.mak | 1 -
104
configs/targets/sh4eb-linux-user.mak | 1 -
105
configs/targets/sh4eb-softmmu.mak | 1 -
106
meson.build | 3 -
107
accel/tcg/internal.h | 9 +
108
accel/tcg/tcg-accel-ops-icount.h | 3 +-
109
disas/disas-internal.h | 21 +
110
include/disas/disas.h | 23 +-
111
include/exec/cpu-common.h | 1 +
112
include/exec/cpu-defs.h | 7 +-
113
include/exec/cpu_ldst.h | 26 +-
114
include/exec/memop.h | 13 +-
115
include/exec/poison.h | 1 -
116
tcg/loongarch64/tcg-target-con-set.h | 2 -
117
tcg/loongarch64/tcg-target-con-str.h | 1 -
118
tcg/mips/tcg-target-con-set.h | 13 +-
119
tcg/mips/tcg-target-con-str.h | 2 -
120
tcg/mips/tcg-target.h | 4 +-
121
tcg/ppc/tcg-target-con-set.h | 11 +-
122
tcg/ppc/tcg-target-con-str.h | 7 -
123
tcg/riscv/tcg-target-con-set.h | 2 -
124
tcg/riscv/tcg-target-con-str.h | 1 -
125
tcg/s390x/tcg-target-con-set.h | 2 -
126
tcg/s390x/tcg-target-con-str.h | 1 -
127
accel/tcg/cpu-exec-common.c | 3 +
128
accel/tcg/cputlb.c | 1113 ++++++++++++++++-------------
129
accel/tcg/tb-maint.c | 2 +-
130
accel/tcg/tcg-accel-ops-icount.c | 21 +-
131
accel/tcg/tcg-accel-ops-rr.c | 37 +-
132
bsd-user/elfload.c | 5 +-
133
cpus-common.c | 2 +-
134
disas/disas-mon.c | 65 ++
135
disas.c => disas/disas.c | 111 +--
136
linux-user/elfload.c | 18 +-
137
migration/dirtyrate.c | 26 +-
138
replay/replay.c | 3 +-
139
target/loongarch/csr_helper.c | 1 -
140
target/loongarch/iocsr_helper.c | 1 -
141
target/m68k/translate.c | 1 +
142
target/mips/tcg/mxu_translate.c | 3 +-
143
target/nios2/translate.c | 10 +
144
target/sh4/translate.c | 102 ++-
145
tcg/tcg.c | 480 ++++++++++++-
146
trace/control-target.c | 9 +-
147
target/mips/tcg/micromips_translate.c.inc | 24 +-
148
target/mips/tcg/mips16e_translate.c.inc | 18 +-
149
target/mips/tcg/nanomips_translate.c.inc | 32 +-
150
tcg/aarch64/tcg-target.c.inc | 347 ++++-----
151
tcg/arm/tcg-target.c.inc | 455 +++++-------
152
tcg/i386/tcg-target.c.inc | 453 +++++-------
153
tcg/loongarch64/tcg-target.c.inc | 313 +++-----
154
tcg/mips/tcg-target.c.inc | 870 +++++++---------------
155
tcg/ppc/tcg-target.c.inc | 512 ++++++-------
156
tcg/riscv/tcg-target.c.inc | 304 ++++----
157
tcg/s390x/tcg-target.c.inc | 314 ++++----
158
disas/meson.build | 6 +-
159
68 files changed, 2789 insertions(+), 3040 deletions(-)
160
create mode 100644 disas/disas-internal.h
161
create mode 100644 disas/disas-mon.c
162
rename disas.c => disas/disas.c (78%)
diff view generated by jsdifflib
[PULL 1/4] tcg/optimize: Fix folding of vector ops
[PULL v2 08/53] disas: Move disas.c into the target-independent source set
1
Bitwise operations are easy to fold, because the operation is
1
From: Thomas Huth <thuth@redhat.com>
2
identical regardless of element size. But add and sub need
3
extra element size info that is not currently propagated.
4
2
5
Fixes: 2f9f08ba43d
3
Use target_words_bigendian() instead of an ifdef.
6
Cc: qemu-stable@nongnu.org
4
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
5
Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
a poisoned identifier, and anyway will always be set by meson.build
7
when building on a riscv host.
8
9
Signed-off-by: Thomas Huth <thuth@redhat.com>
10
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
11
[rth: Type change done in a separate patch]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
13
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
14
disas/disas.c | 12 ++++++------
12
1 file changed, 38 insertions(+), 11 deletions(-)
15
disas/meson.build | 3 ++-
16
2 files changed, 8 insertions(+), 7 deletions(-)
13
17
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
18
diff --git a/disas/disas.c b/disas/disas.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
20
--- a/disas/disas.c
17
+++ b/tcg/optimize.c
21
+++ b/disas/disas.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
22
@@ -XXX,XX +XXX,XX @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
19
CASE_OP_32_64(mul):
23
s->cpu = cpu;
20
return x * y;
24
s->info.read_memory_func = target_read_memory;
21
25
s->info.print_address_func = print_address;
22
- CASE_OP_32_64(and):
26
-#if TARGET_BIG_ENDIAN
23
+ CASE_OP_32_64_VEC(and):
27
- s->info.endian = BFD_ENDIAN_BIG;
24
return x & y;
28
-#else
25
29
- s->info.endian = BFD_ENDIAN_LITTLE;
26
- CASE_OP_32_64(or):
30
-#endif
27
+ CASE_OP_32_64_VEC(or):
31
+ if (target_words_bigendian()) {
28
return x | y;
32
+ s->info.endian = BFD_ENDIAN_BIG;
29
33
+ } else {
30
- CASE_OP_32_64(xor):
34
+ s->info.endian = BFD_ENDIAN_LITTLE;
31
+ CASE_OP_32_64_VEC(xor):
32
return x ^ y;
33
34
case INDEX_op_shl_i32:
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
36
case INDEX_op_rotl_i64:
37
return rol64(x, y & 63);
38
39
- CASE_OP_32_64(not):
40
+ CASE_OP_32_64_VEC(not):
41
return ~x;
42
43
CASE_OP_32_64(neg):
44
return -x;
45
46
- CASE_OP_32_64(andc):
47
+ CASE_OP_32_64_VEC(andc):
48
return x & ~y;
49
50
- CASE_OP_32_64(orc):
51
+ CASE_OP_32_64_VEC(orc):
52
return x | ~y;
53
54
CASE_OP_32_64(eqv):
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
56
return false;
57
}
58
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
60
+{
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
62
+ return false;
63
+}
64
+
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
66
{
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
69
return false;
70
}
71
72
+/* We cannot as yet do_constant_folding with vectors. */
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
74
+{
75
+ if (fold_commutative(ctx, op) ||
76
+ fold_xi_to_x(ctx, op, 0)) {
77
+ return true;
78
+ }
35
+ }
79
+ return false;
36
80
+}
37
CPUClass *cc = CPU_GET_CLASS(cpu);
81
+
38
if (cc->disas_set_info) {
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
39
@@ -XXX,XX +XXX,XX @@ static void initialize_debug_host(CPUDebug *s)
83
{
40
# ifdef _ARCH_PPC64
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
41
s->info.cap_mode = CS_MODE_64;
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
42
# endif
86
return false;
43
-#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
87
}
44
+#elif defined(__riscv)
88
45
#if defined(_ILP32) || (__riscv_xlen == 32)
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
46
s->info.print_insn = print_insn_riscv32;
90
+/* We cannot as yet do_constant_folding with vectors. */
47
#elif defined(_LP64)
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
48
diff --git a/disas/meson.build b/disas/meson.build
92
{
49
index XXXXXXX..XXXXXXX 100644
93
- if (fold_const2(ctx, op) ||
50
--- a/disas/meson.build
94
- fold_xx_to_i(ctx, op, 0) ||
51
+++ b/disas/meson.build
95
+ if (fold_xx_to_i(ctx, op, 0) ||
52
@@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
96
fold_xi_to_x(ctx, op, 0) ||
53
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
97
fold_sub_to_neg(ctx, op)) {
54
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
98
return true;
55
common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
56
+common_ss.add(files('disas.c'))
100
return false;
57
101
}
58
softmmu_ss.add(files('disas-mon.c'))
102
59
-specific_ss.add(files('disas.c'), capstone)
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
60
+specific_ss.add(capstone)
104
+{
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
106
+}
107
+
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
109
{
110
return fold_addsub2(ctx, op, false);
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
* Sorted alphabetically by opcode as much as possible.
113
*/
114
switch (opc) {
115
- CASE_OP_32_64_VEC(add):
116
+ CASE_OP_32_64(add):
117
done = fold_add(&ctx, op);
118
break;
119
+ case INDEX_op_add_vec:
120
+ done = fold_add_vec(&ctx, op);
121
+ break;
122
CASE_OP_32_64(add2):
123
done = fold_add2(&ctx, op);
124
break;
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
126
CASE_OP_32_64(sextract):
127
done = fold_sextract(&ctx, op);
128
break;
129
- CASE_OP_32_64_VEC(sub):
130
+ CASE_OP_32_64(sub):
131
done = fold_sub(&ctx, op);
132
break;
133
+ case INDEX_op_sub_vec:
134
+ done = fold_sub_vec(&ctx, op);
135
+ break;
136
CASE_OP_32_64(sub2):
137
done = fold_sub2(&ctx, op);
138
break;
139
--
61
--
140
2.25.1
62
2.34.1
141
142
diff view generated by jsdifflib
[PULL 2/4] linux-user: Fix trivial build error on loongarch64 hosts
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
30
1 file changed, 1 insertion(+), 3 deletions(-)
31
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
35
+++ b/linux-user/host/loongarch64/host-signal.h
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
37
}
38
break;
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
41
-
42
- switch (sel) {
43
+ switch ((insn >> 15) & 0b11111111111) {
44
case 0b00000100000: /* stx.b */
45
case 0b00000101000: /* stx.h */
46
case 0b00000110000: /* stx.w */
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
[PULL 3/4] sysemu: Cleanup qemu_run_machine_init_done_notifiers()
Deleted patch
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
2
1
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
4
and user.
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/sysemu/sysemu.h | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
18
+++ b/include/sysemu/sysemu.h
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
20
void qemu_add_exit_notifier(Notifier *notify);
21
void qemu_remove_exit_notifier(Notifier *notify);
22
23
-void qemu_run_machine_init_done_notifiers(void);
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
[PULL 4/4] common-user: Fix tail calls to safe_syscall_set_errno_tail
Deleted patch
1
For the ABIs in which the syscall return register is not
2
also the first function argument register, move the errno
3
value into the correct place.
4
1
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
11
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
13
common-user/host/mips/safe-syscall.inc.S | 1 +
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
18
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
20
+++ b/common-user/host/i386/safe-syscall.inc.S
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
22
pop %ebp
23
.cfi_adjust_cfa_offset -4
24
.cfi_restore ebp
25
+ mov %eax, (%esp)
26
jmp safe_syscall_set_errno_tail
27
28
.cfi_endproc
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
30
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
32
+++ b/common-user/host/mips/safe-syscall.inc.S
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
34
1: USE_ALT_CP(t0)
35
SETUP_GPX(t1)
36
SETUP_GPX64(t0, t1)
37
+ move a0, v0
38
PTR_LA t9, safe_syscall_set_errno_tail
39
jr t9
40
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
42
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
46
1: pop %rbp
47
.cfi_def_cfa_offset 8
48
.cfi_restore rbp
49
+ mov %eax, %edi
50
jmp safe_syscall_set_errno_tail
51
.cfi_endproc
52
53
--
54
2.25.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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