[PULL 0/4] tcg patch queue
[PULL v2 00/12] tcg patch queue
1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
2
2
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
3
Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
8
8
9
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
9
for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
10
10
11
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
11
tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Fix for safe_syscall_base.
14
Misc tcg-related patch queue.
15
Fix for folding of vector add/sub.
15
16
Fix build on loongarch64 with gcc 8.
16
v2: Update bitops.h rotate patch.
17
Remove decl for qemu_run_machine_init_done_notifiers.
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
Philippe Mathieu-Daudé (1):
19
Dickon Hood (1):
21
linux-user: Fix trivial build error on loongarch64 hosts
20
qemu/bitops.h: Limit rotate amounts
22
21
23
Richard Henderson (2):
22
Kiran Ostrolenk (1):
24
tcg/optimize: Fix folding of vector ops
23
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
26
24
27
Xiaoyao Li (1):
25
Nazar Kazakov (2):
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
26
tcg: Add tcg_gen_gvec_andcs
27
tcg: Add tcg_gen_gvec_rotrs
29
28
30
include/sysemu/sysemu.h | 1 -
29
Richard Henderson (7):
31
linux-user/host/loongarch64/host-signal.h | 4 +--
30
softmmu: Tidy dirtylimit_dirty_ring_full_time
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
31
qemu/int128: Re-shuffle Int128Alias members
33
common-user/host/i386/safe-syscall.inc.S | 1 +
32
migration/xbzrle: Use __attribute__((target)) for avx512
34
common-user/host/mips/safe-syscall.inc.S | 1 +
33
accel/tcg: Add cpu_ld*_code_mmu
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
34
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
36
6 files changed, 42 insertions(+), 15 deletions(-)
35
tcg/mips: Conditionalize tcg_out_exts_i32_i64
36
tcg: Introduce tcg_out_movext2
37
37
38
Weiwei Li (1):
39
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
40
41
meson.build | 5 +--
42
accel/tcg/tcg-runtime.h | 1 +
43
include/exec/cpu_ldst.h | 9 ++++++
44
include/qemu/bitops.h | 16 +++++-----
45
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++
46
include/qemu/int128.h | 4 +--
47
include/tcg/tcg-op-gvec.h | 4 +++
48
accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++
49
accel/tcg/tcg-runtime-gvec.c | 11 +++++++
50
accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++
51
migration/xbzrle.c | 9 +++---
52
softmmu/dirtylimit.c | 15 ++++++---
53
tcg/tcg-op-gvec.c | 28 ++++++++++++++++
54
tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++---
55
tcg/arm/tcg-target.c.inc | 44 +++++++++++--------------
56
tcg/i386/tcg-target.c.inc | 19 +++++------
57
tcg/loongarch64/tcg-target.c.inc | 4 ++-
58
tcg/mips/tcg-target.c.inc | 4 ++-
59
18 files changed, 339 insertions(+), 68 deletions(-)
diff view generated by jsdifflib
[PULL 1/4] tcg/optimize: Fix folding of vector ops
[PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
1
Bitwise operations are easy to fold, because the operation is
1
From: Dickon Hood <dickon.hood@codethink.co.uk>
2
identical regardless of element size. But add and sub need
3
extra element size info that is not currently propagated.
4
2
5
Fixes: 2f9f08ba43d
3
Rotates have been fixed up to only allow for reasonable rotate amounts
6
Cc: qemu-stable@nongnu.org
4
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
5
vector rotate instructions.
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
7
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
10
[rth: Mask shifts in both directions.]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
12
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
13
include/qemu/bitops.h | 16 ++++++++--------
12
1 file changed, 38 insertions(+), 11 deletions(-)
14
1 file changed, 8 insertions(+), 8 deletions(-)
13
15
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
18
--- a/include/qemu/bitops.h
17
+++ b/tcg/optimize.c
19
+++ b/include/qemu/bitops.h
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
20
@@ -XXX,XX +XXX,XX @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
19
CASE_OP_32_64(mul):
21
*/
20
return x * y;
22
static inline uint8_t rol8(uint8_t word, unsigned int shift)
21
23
{
22
- CASE_OP_32_64(and):
24
- return (word << shift) | (word >> ((8 - shift) & 7));
23
+ CASE_OP_32_64_VEC(and):
25
+ return (word << (shift & 7)) | (word >> (-shift & 7));
24
return x & y;
25
26
- CASE_OP_32_64(or):
27
+ CASE_OP_32_64_VEC(or):
28
return x | y;
29
30
- CASE_OP_32_64(xor):
31
+ CASE_OP_32_64_VEC(xor):
32
return x ^ y;
33
34
case INDEX_op_shl_i32:
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
36
case INDEX_op_rotl_i64:
37
return rol64(x, y & 63);
38
39
- CASE_OP_32_64(not):
40
+ CASE_OP_32_64_VEC(not):
41
return ~x;
42
43
CASE_OP_32_64(neg):
44
return -x;
45
46
- CASE_OP_32_64(andc):
47
+ CASE_OP_32_64_VEC(andc):
48
return x & ~y;
49
50
- CASE_OP_32_64(orc):
51
+ CASE_OP_32_64_VEC(orc):
52
return x | ~y;
53
54
CASE_OP_32_64(eqv):
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
56
return false;
57
}
26
}
58
27
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
28
/**
60
+{
29
@@ -XXX,XX +XXX,XX @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
30
*/
62
+ return false;
31
static inline uint8_t ror8(uint8_t word, unsigned int shift)
63
+}
64
+
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
66
{
32
{
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
33
- return (word >> shift) | (word << ((8 - shift) & 7));
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
34
+ return (word >> (shift & 7)) | (word << (-shift & 7));
69
return false;
70
}
35
}
71
36
72
+/* We cannot as yet do_constant_folding with vectors. */
37
/**
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
38
@@ -XXX,XX +XXX,XX @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
74
+{
39
*/
75
+ if (fold_commutative(ctx, op) ||
40
static inline uint16_t rol16(uint16_t word, unsigned int shift)
76
+ fold_xi_to_x(ctx, op, 0)) {
77
+ return true;
78
+ }
79
+ return false;
80
+}
81
+
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
83
{
41
{
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
42
- return (word << shift) | (word >> ((16 - shift) & 15));
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
43
+ return (word << (shift & 15)) | (word >> (-shift & 15));
86
return false;
87
}
44
}
88
45
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
46
/**
90
+/* We cannot as yet do_constant_folding with vectors. */
47
@@ -XXX,XX +XXX,XX @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
48
*/
49
static inline uint16_t ror16(uint16_t word, unsigned int shift)
92
{
50
{
93
- if (fold_const2(ctx, op) ||
51
- return (word >> shift) | (word << ((16 - shift) & 15));
94
- fold_xx_to_i(ctx, op, 0) ||
52
+ return (word >> (shift & 15)) | (word << (-shift & 15));
95
+ if (fold_xx_to_i(ctx, op, 0) ||
96
fold_xi_to_x(ctx, op, 0) ||
97
fold_sub_to_neg(ctx, op)) {
98
return true;
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
100
return false;
101
}
53
}
102
54
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
55
/**
104
+{
56
@@ -XXX,XX +XXX,XX @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
57
*/
106
+}
58
static inline uint32_t rol32(uint32_t word, unsigned int shift)
107
+
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
109
{
59
{
110
return fold_addsub2(ctx, op, false);
60
- return (word << shift) | (word >> ((32 - shift) & 31));
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
61
+ return (word << (shift & 31)) | (word >> (-shift & 31));
112
* Sorted alphabetically by opcode as much as possible.
62
}
113
*/
63
114
switch (opc) {
64
/**
115
- CASE_OP_32_64_VEC(add):
65
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
116
+ CASE_OP_32_64(add):
66
*/
117
done = fold_add(&ctx, op);
67
static inline uint32_t ror32(uint32_t word, unsigned int shift)
118
break;
68
{
119
+ case INDEX_op_add_vec:
69
- return (word >> shift) | (word << ((32 - shift) & 31));
120
+ done = fold_add_vec(&ctx, op);
70
+ return (word >> (shift & 31)) | (word << (-shift & 31));
121
+ break;
71
}
122
CASE_OP_32_64(add2):
72
123
done = fold_add2(&ctx, op);
73
/**
124
break;
74
@@ -XXX,XX +XXX,XX @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
75
*/
126
CASE_OP_32_64(sextract):
76
static inline uint64_t rol64(uint64_t word, unsigned int shift)
127
done = fold_sextract(&ctx, op);
77
{
128
break;
78
- return (word << shift) | (word >> ((64 - shift) & 63));
129
- CASE_OP_32_64_VEC(sub):
79
+ return (word << (shift & 63)) | (word >> (-shift & 63));
130
+ CASE_OP_32_64(sub):
80
}
131
done = fold_sub(&ctx, op);
81
132
break;
82
/**
133
+ case INDEX_op_sub_vec:
83
@@ -XXX,XX +XXX,XX @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
134
+ done = fold_sub_vec(&ctx, op);
84
*/
135
+ break;
85
static inline uint64_t ror64(uint64_t word, unsigned int shift)
136
CASE_OP_32_64(sub2):
86
{
137
done = fold_sub2(&ctx, op);
87
- return (word >> shift) | (word << ((64 - shift) & 63));
138
break;
88
+ return (word >> (shift & 63)) | (word << (-shift & 63));
89
}
90
91
/**
139
--
92
--
140
2.25.1
93
2.34.1
141
142
diff view generated by jsdifflib
[PULL 2/4] linux-user: Fix trivial build error on loongarch64 hosts
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
30
1 file changed, 1 insertion(+), 3 deletions(-)
31
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
35
+++ b/linux-user/host/loongarch64/host-signal.h
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
37
}
38
break;
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
41
-
42
- switch (sel) {
43
+ switch ((insn >> 15) & 0b11111111111) {
44
case 0b00000100000: /* stx.b */
45
case 0b00000101000: /* stx.h */
46
case 0b00000110000: /* stx.w */
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
[PULL 3/4] sysemu: Cleanup qemu_run_machine_init_done_notifiers()
Deleted patch
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
2
1
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
4
and user.
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/sysemu/sysemu.h | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
18
+++ b/include/sysemu/sysemu.h
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
20
void qemu_add_exit_notifier(Notifier *notify);
21
void qemu_remove_exit_notifier(Notifier *notify);
22
23
-void qemu_run_machine_init_done_notifiers(void);
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
[PULL 4/4] common-user: Fix tail calls to safe_syscall_set_errno_tail
Deleted patch
1
For the ABIs in which the syscall return register is not
2
also the first function argument register, move the errno
3
value into the correct place.
4
1
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
11
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
13
common-user/host/mips/safe-syscall.inc.S | 1 +
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
18
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
20
+++ b/common-user/host/i386/safe-syscall.inc.S
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
22
pop %ebp
23
.cfi_adjust_cfa_offset -4
24
.cfi_restore ebp
25
+ mov %eax, (%esp)
26
jmp safe_syscall_set_errno_tail
27
28
.cfi_endproc
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
30
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
32
+++ b/common-user/host/mips/safe-syscall.inc.S
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
34
1: USE_ALT_CP(t0)
35
SETUP_GPX(t1)
36
SETUP_GPX64(t0, t1)
37
+ move a0, v0
38
PTR_LA t9, safe_syscall_set_errno_tail
39
jr t9
40
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
42
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
46
1: pop %rbp
47
.cfi_def_cfa_offset 8
48
.cfi_restore rbp
49
+ mov %eax, %edi
50
jmp safe_syscall_set_errno_tail
51
.cfi_endproc
52
53
--
54
2.25.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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