[PULL 0/4] tcg patch queue
[PULL v3 00/91] tcg patch queue
1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
2
2
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
3
4
r~
5
6
7
The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
8
9
Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
4
10
5
are available in the Git repository at:
11
are available in the Git repository at:
6
12
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
8
14
9
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
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for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
10
16
11
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
17
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
12
18
13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
Fix for safe_syscall_base.
20
accel/tcg: Fix NB_MMU_MODES to 16
15
Fix for folding of vector add/sub.
21
Balance of the target/ patchset which eliminates tcg_temp_free
16
Fix build on loongarch64 with gcc 8.
22
Balance of the target/ patchset which eliminates tcg_const
17
Remove decl for qemu_run_machine_init_done_notifiers.
18
23
19
----------------------------------------------------------------
24
----------------------------------------------------------------
20
Philippe Mathieu-Daudé (1):
25
Anton Johansson (23):
21
linux-user: Fix trivial build error on loongarch64 hosts
26
include/exec: Set default `NB_MMU_MODES` to 16
27
target/alpha: Remove `NB_MMU_MODES` define
28
target/arm: Remove `NB_MMU_MODES` define
29
target/avr: Remove `NB_MMU_MODES` define
30
target/cris: Remove `NB_MMU_MODES` define
31
target/hexagon: Remove `NB_MMU_MODES` define
32
target/hppa: Remove `NB_MMU_MODES` define
33
target/i386: Remove `NB_MMU_MODES` define
34
target/loongarch: Remove `NB_MMU_MODES` define
35
target/m68k: Remove `NB_MMU_MODES` define
36
target/microblaze: Remove `NB_MMU_MODES` define
37
target/mips: Remove `NB_MMU_MODES` define
38
target/nios2: Remove `NB_MMU_MODES` define
39
target/openrisc: Remove `NB_MMU_MODES` define
40
target/ppc: Remove `NB_MMU_MODES` define
41
target/riscv: Remove `NB_MMU_MODES` define
42
target/rx: Remove `NB_MMU_MODES` define
43
target/s390x: Remove `NB_MMU_MODES` define
44
target/sh4: Remove `NB_MMU_MODES` define
45
target/sparc: Remove `NB_MMU_MODES` define
46
target/tricore: Remove `NB_MMU_MODES` define
47
target/xtensa: Remove `NB_MMU_MODES` define
48
include/exec: Remove guards around `NB_MMU_MODES`
22
49
23
Richard Henderson (2):
50
Richard Henderson (68):
24
tcg/optimize: Fix folding of vector ops
51
target/mips: Drop tcg_temp_free from micromips_translate.c.inc
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
52
target/mips: Drop tcg_temp_free from msa_translate.c
53
target/mips: Drop tcg_temp_free from mxu_translate.c
54
target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
55
target/mips: Drop tcg_temp_free from octeon_translate.c
56
target/mips: Drop tcg_temp_free from translate_addr_const.c
57
target/mips: Drop tcg_temp_free from tx79_translate.c
58
target/mips: Drop tcg_temp_free from vr54xx_translate.c
59
target/mips: Drop tcg_temp_free from translate.c
60
target/s390x: Drop free_compare
61
target/s390x: Drop tcg_temp_free from translate_vx.c.inc
62
target/s390x: Drop tcg_temp_free from translate.c
63
target/s390x: Remove assert vs g_in2
64
target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
65
tcg: Create tcg/tcg-temp-internal.h
66
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
67
target/avr: Avoid use of tcg_const_i32 throughout
68
target/cris: Avoid use of tcg_const_i32 throughout
69
target/hppa: Avoid tcg_const_i64 in trans_fid_f
70
target/hppa: Avoid use of tcg_const_i32 throughout
71
target/i386: Avoid use of tcg_const_* throughout
72
target/m68k: Avoid tcg_const_i32 when modified
73
target/m68k: Avoid tcg_const_i32 in bfop_reg
74
target/m68k: Avoid tcg_const_* throughout
75
target/mips: Split out gen_lxl
76
target/mips: Split out gen_lxr
77
target/mips: Avoid tcg_const_tl in gen_r6_ld
78
target/mips: Avoid tcg_const_* throughout
79
target/ppc: Split out gen_vx_vmul10
80
target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
81
target/rx: Use tcg_gen_abs_i32
82
target/rx: Use cpu_psw_z as temp in flags computation
83
target/rx: Avoid tcg_const_i32 when new temp needed
84
target/rx: Avoid tcg_const_i32
85
target/s390x: Avoid tcg_const_i64
86
target/sh4: Avoid tcg_const_i32 for TAS.B
87
target/sh4: Avoid tcg_const_i32
88
tcg/sparc: Avoid tcg_const_tl in gen_edge
89
target/tricore: Split t_n as constant from temp as variable
90
target/tricore: Rename t_off10 and use tcg_constant_i32
91
target/tricore: Use setcondi instead of explicit allocation
92
target/tricore: Drop some temp initialization
93
target/tricore: Avoid tcg_const_i32
94
tcg: Replace tcg_const_i64 in tcg-op.c
95
target/arm: Use rmode >= 0 for need_rmode
96
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
97
target/arm: Improve arm_rmode_to_sf
98
target/arm: Consistently use ARMFPRounding during translation
99
target/arm: Create gen_set_rmode, gen_restore_rmode
100
target/arm: Improve trans_BFCI
101
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
102
target/arm: Avoid tcg_const_* in translate-mve.c
103
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
104
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
105
target/arm: Avoid tcg_const_ptr in handle_rev
106
target/m68k: Use tcg_constant_i32 in gen_ea_mode
107
target/ppc: Avoid tcg_const_i64 in do_vcntmb
108
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
109
target/ppc: Avoid tcg_const_* in xxeval
110
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
111
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
112
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
113
target/ppc: Rewrite trans_ADDG6S
114
target/ppc: Fix gen_tlbsx_booke206
115
target/ppc: Avoid tcg_const_* in translate.c
116
target/tricore: Use min/max for saturate
117
tcg: Drop tcg_const_*_vec
118
tcg: Drop tcg_const_*
26
119
27
Xiaoyao Li (1):
120
include/exec/cpu-defs.h | 9 +-
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
121
include/tcg/tcg-op.h | 4 -
29
122
include/tcg/tcg-temp-internal.h | 83 +++
30
include/sysemu/sysemu.h | 1 -
123
include/tcg/tcg.h | 64 ---
31
linux-user/host/loongarch64/host-signal.h | 4 +--
124
target/alpha/cpu-param.h | 2 -
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
125
target/arm/cpu-param.h | 2 -
33
common-user/host/i386/safe-syscall.inc.S | 1 +
126
target/arm/internals.h | 12 +-
34
common-user/host/mips/safe-syscall.inc.S | 1 +
127
target/arm/tcg/translate.h | 17 +
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
128
target/avr/cpu-param.h | 1 -
36
6 files changed, 42 insertions(+), 15 deletions(-)
129
target/cris/cpu-param.h | 1 -
37
130
target/hexagon/cpu-param.h | 2 -
131
target/hppa/cpu-param.h | 1 -
132
target/i386/cpu-param.h | 1 -
133
target/loongarch/cpu-param.h | 1 -
134
target/m68k/cpu-param.h | 1 -
135
target/microblaze/cpu-param.h | 1 -
136
target/microblaze/cpu.h | 2 +-
137
target/mips/cpu-param.h | 1 -
138
target/nios2/cpu-param.h | 1 -
139
target/openrisc/cpu-param.h | 1 -
140
target/ppc/cpu-param.h | 1 -
141
target/riscv/cpu-param.h | 1 -
142
target/rx/cpu-param.h | 2 -
143
target/s390x/cpu-param.h | 1 -
144
target/sh4/cpu-param.h | 1 -
145
target/sparc/cpu-param.h | 2 -
146
target/tricore/cpu-param.h | 1 -
147
target/xtensa/cpu-param.h | 1 -
148
accel/tcg/plugin-gen.c | 1 +
149
target/arm/tcg/translate-a64.c | 168 +++---
150
target/arm/tcg/translate-mve.c | 56 +-
151
target/arm/tcg/translate-sve.c | 28 +-
152
target/arm/tcg/translate-vfp.c | 26 +-
153
target/arm/tcg/translate.c | 14 +-
154
target/arm/vfp_helper.c | 35 +-
155
target/avr/translate.c | 48 +-
156
target/cris/translate.c | 46 +-
157
target/hppa/translate.c | 35 +-
158
target/i386/tcg/translate.c | 83 +--
159
target/m68k/translate.c | 231 ++++----
160
target/mips/tcg/msa_translate.c | 9 -
161
target/mips/tcg/mxu_translate.c | 55 +-
162
target/mips/tcg/octeon_translate.c | 23 -
163
target/mips/tcg/translate.c | 819 +++++------------------------
164
target/mips/tcg/translate_addr_const.c | 7 -
165
target/mips/tcg/tx79_translate.c | 45 +-
166
target/mips/tcg/vr54xx_translate.c | 4 -
167
target/ppc/translate.c | 148 +++---
168
target/rx/translate.c | 84 ++-
169
target/s390x/tcg/translate.c | 208 +-------
170
target/sh4/translate.c | 35 +-
171
target/sparc/translate.c | 14 +-
172
target/tricore/translate.c | 476 ++++++++---------
173
tcg/tcg-op-gvec.c | 1 +
174
tcg/tcg-op-vec.c | 35 +-
175
tcg/tcg-op.c | 13 +-
176
tcg/tcg.c | 17 +-
177
target/cris/translate_v10.c.inc | 26 +-
178
target/mips/tcg/micromips_translate.c.inc | 12 +-
179
target/mips/tcg/nanomips_translate.c.inc | 143 +----
180
target/ppc/power8-pmu-regs.c.inc | 4 +-
181
target/ppc/translate/fixedpoint-impl.c.inc | 44 +-
182
target/ppc/translate/fp-impl.c.inc | 26 +-
183
target/ppc/translate/vmx-impl.c.inc | 130 ++---
184
target/ppc/translate/vsx-impl.c.inc | 36 +-
185
target/s390x/tcg/translate_vx.c.inc | 143 -----
186
tcg/i386/tcg-target.c.inc | 9 +-
187
67 files changed, 1166 insertions(+), 2388 deletions(-)
188
create mode 100644 include/tcg/tcg-temp-internal.h
diff view generated by jsdifflib
[PULL 1/4] tcg/optimize: Fix folding of vector ops
[PULL v3 73/91] target/arm: Improve trans_BFCI
1
Bitwise operations are easy to fold, because the operation is
1
Reorg temporary usage so that we can use tcg_constant_i32.
2
identical regardless of element size. But add and sub need
2
tcg_gen_deposit_i32 already has a width == 32 special case,
3
extra element size info that is not currently propagated.
3
so remove the check here.
4
4
5
Fixes: 2f9f08ba43d
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Cc: qemu-stable@nongnu.org
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
7
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
8
target/arm/tcg/translate.c | 14 ++++++--------
12
1 file changed, 38 insertions(+), 11 deletions(-)
9
1 file changed, 6 insertions(+), 8 deletions(-)
13
10
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
13
--- a/target/arm/tcg/translate.c
17
+++ b/tcg/optimize.c
14
+++ b/target/arm/tcg/translate.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
15
@@ -XXX,XX +XXX,XX @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
19
CASE_OP_32_64(mul):
16
20
return x * y;
17
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
21
18
{
22
- CASE_OP_32_64(and):
19
- TCGv_i32 tmp;
23
+ CASE_OP_32_64_VEC(and):
20
int msb = a->msb, lsb = a->lsb;
24
return x & y;
21
+ TCGv_i32 t_in, t_rd;
25
22
int width;
26
- CASE_OP_32_64(or):
23
27
+ CASE_OP_32_64_VEC(or):
24
if (!ENABLE_ARCH_6T2) {
28
return x | y;
25
@@ -XXX,XX +XXX,XX @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
29
26
width = msb + 1 - lsb;
30
- CASE_OP_32_64(xor):
27
if (a->rn == 15) {
31
+ CASE_OP_32_64_VEC(xor):
28
/* BFC */
32
return x ^ y;
29
- tmp = tcg_const_i32(0);
33
30
+ t_in = tcg_constant_i32(0);
34
case INDEX_op_shl_i32:
31
} else {
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
32
/* BFI */
36
case INDEX_op_rotl_i64:
33
- tmp = load_reg(s, a->rn);
37
return rol64(x, y & 63);
34
+ t_in = load_reg(s, a->rn);
38
35
}
39
- CASE_OP_32_64(not):
36
- if (width != 32) {
40
+ CASE_OP_32_64_VEC(not):
37
- TCGv_i32 tmp2 = load_reg(s, a->rd);
41
return ~x;
38
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
42
39
- }
43
CASE_OP_32_64(neg):
40
- store_reg(s, a->rd, tmp);
44
return -x;
41
+ t_rd = load_reg(s, a->rd);
45
42
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
46
- CASE_OP_32_64(andc):
43
+ store_reg(s, a->rd, t_rd);
47
+ CASE_OP_32_64_VEC(andc):
44
return true;
48
return x & ~y;
49
50
- CASE_OP_32_64(orc):
51
+ CASE_OP_32_64_VEC(orc):
52
return x | ~y;
53
54
CASE_OP_32_64(eqv):
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
56
return false;
57
}
45
}
58
46
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
60
+{
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
62
+ return false;
63
+}
64
+
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
66
{
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
69
return false;
70
}
71
72
+/* We cannot as yet do_constant_folding with vectors. */
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
74
+{
75
+ if (fold_commutative(ctx, op) ||
76
+ fold_xi_to_x(ctx, op, 0)) {
77
+ return true;
78
+ }
79
+ return false;
80
+}
81
+
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
83
{
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
86
return false;
87
}
88
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
90
+/* We cannot as yet do_constant_folding with vectors. */
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
92
{
93
- if (fold_const2(ctx, op) ||
94
- fold_xx_to_i(ctx, op, 0) ||
95
+ if (fold_xx_to_i(ctx, op, 0) ||
96
fold_xi_to_x(ctx, op, 0) ||
97
fold_sub_to_neg(ctx, op)) {
98
return true;
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
100
return false;
101
}
102
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
104
+{
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
106
+}
107
+
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
109
{
110
return fold_addsub2(ctx, op, false);
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
* Sorted alphabetically by opcode as much as possible.
113
*/
114
switch (opc) {
115
- CASE_OP_32_64_VEC(add):
116
+ CASE_OP_32_64(add):
117
done = fold_add(&ctx, op);
118
break;
119
+ case INDEX_op_add_vec:
120
+ done = fold_add_vec(&ctx, op);
121
+ break;
122
CASE_OP_32_64(add2):
123
done = fold_add2(&ctx, op);
124
break;
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
126
CASE_OP_32_64(sextract):
127
done = fold_sextract(&ctx, op);
128
break;
129
- CASE_OP_32_64_VEC(sub):
130
+ CASE_OP_32_64(sub):
131
done = fold_sub(&ctx, op);
132
break;
133
+ case INDEX_op_sub_vec:
134
+ done = fold_sub_vec(&ctx, op);
135
+ break;
136
CASE_OP_32_64(sub2):
137
done = fold_sub2(&ctx, op);
138
break;
139
--
47
--
140
2.25.1
48
2.34.1
141
49
142
50
diff view generated by jsdifflib
[PULL 2/4] linux-user: Fix trivial build error on loongarch64 hosts
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
30
1 file changed, 1 insertion(+), 3 deletions(-)
31
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
35
+++ b/linux-user/host/loongarch64/host-signal.h
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
37
}
38
break;
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
41
-
42
- switch (sel) {
43
+ switch ((insn >> 15) & 0b11111111111) {
44
case 0b00000100000: /* stx.b */
45
case 0b00000101000: /* stx.h */
46
case 0b00000110000: /* stx.w */
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
[PULL 3/4] sysemu: Cleanup qemu_run_machine_init_done_notifiers()
Deleted patch
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
2
1
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
4
and user.
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/sysemu/sysemu.h | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
18
+++ b/include/sysemu/sysemu.h
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
20
void qemu_add_exit_notifier(Notifier *notify);
21
void qemu_remove_exit_notifier(Notifier *notify);
22
23
-void qemu_run_machine_init_done_notifiers(void);
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
[PULL 4/4] common-user: Fix tail calls to safe_syscall_set_errno_tail
Deleted patch
1
For the ABIs in which the syscall return register is not
2
also the first function argument register, move the errno
3
value into the correct place.
4
1
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
11
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
13
common-user/host/mips/safe-syscall.inc.S | 1 +
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
18
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
20
+++ b/common-user/host/i386/safe-syscall.inc.S
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
22
pop %ebp
23
.cfi_adjust_cfa_offset -4
24
.cfi_restore ebp
25
+ mov %eax, (%esp)
26
jmp safe_syscall_set_errno_tail
27
28
.cfi_endproc
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
30
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
32
+++ b/common-user/host/mips/safe-syscall.inc.S
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
34
1: USE_ALT_CP(t0)
35
SETUP_GPX(t1)
36
SETUP_GPX64(t0, t1)
37
+ move a0, v0
38
PTR_LA t9, safe_syscall_set_errno_tail
39
jr t9
40
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
42
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
46
1: pop %rbp
47
.cfi_def_cfa_offset 8
48
.cfi_restore rbp
49
+ mov %eax, %edi
50
jmp safe_syscall_set_errno_tail
51
.cfi_endproc
52
53
--
54
2.25.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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