1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
v2: Fix mis-attributed --author.
2
2
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
3
4
r~
5
6
7
The following changes since commit 627634031092e1514f363fd8659a579398de0f0e:
8
9
Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +0000)
4
10
5
are available in the Git repository at:
11
are available in the Git repository at:
6
12
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230301
8
14
9
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
15
for you to fetch changes up to 9644e7142a2a2bb4b4743a3a4c940edbab16ca11:
10
16
11
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
17
tcg: Update docs/devel/tcg-ops.rst for temporary changes (2023-03-01 07:33:28 -1000)
12
18
13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
Fix for safe_syscall_base.
20
helper-head: Add fpu/softfloat-types.h
15
Fix for folding of vector add/sub.
21
softmmu: Use memmove in flatview_write_continue
16
Fix build on loongarch64 with gcc 8.
22
tcg: Add sign param to probe_access_flags, probe_access_full
17
Remove decl for qemu_run_machine_init_done_notifiers.
23
tcg: Convert TARGET_TB_PCREL to CF_PCREL
24
tcg: Simplify temporary lifetimes for translators
18
25
19
----------------------------------------------------------------
26
----------------------------------------------------------------
27
Akihiko Odaki (1):
28
softmmu: Use memmove in flatview_write_continue
29
30
Anton Johansson (27):
31
include/exec: Introduce `CF_PCREL`
32
target/i386: set `CF_PCREL` in `x86_cpu_realizefn`
33
target/arm: set `CF_PCREL` in `arm_cpu_realizefn`
34
accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL`
35
include/exec: Replace `TARGET_TB_PCREL` with `CF_PCREL`
36
target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`
37
target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`
38
include/exec: Remove `TARGET_TB_PCREL` define
39
target/arm: Remove `TARGET_TB_PCREL` define
40
target/i386: Remove `TARGET_TB_PCREL` define
41
accel/tcg: Move jmp-cache `CF_PCREL` checks to caller
42
accel/tcg: Replace `tb_pc()` with `tb->pc`
43
target/tricore: Replace `tb_pc()` with `tb->pc`
44
target/sparc: Replace `tb_pc()` with `tb->pc`
45
target/sh4: Replace `tb_pc()` with `tb->pc`
46
target/rx: Replace `tb_pc()` with `tb->pc`
47
target/riscv: Replace `tb_pc()` with `tb->pc`
48
target/openrisc: Replace `tb_pc()` with `tb->pc`
49
target/mips: Replace `tb_pc()` with `tb->pc`
50
target/microblaze: Replace `tb_pc()` with `tb->pc`
51
target/loongarch: Replace `tb_pc()` with `tb->pc`
52
target/i386: Replace `tb_pc()` with `tb->pc`
53
target/hppa: Replace `tb_pc()` with `tb->pc`
54
target/hexagon: Replace `tb_pc()` with `tb->pc`
55
target/avr: Replace `tb_pc()` with `tb->pc`
56
target/arm: Replace `tb_pc()` with `tb->pc`
57
include/exec: Remove `tb_pc()`
58
59
Daniel Henrique Barboza (1):
60
accel/tcg: Add 'size' param to probe_access_flags()
61
20
Philippe Mathieu-Daudé (1):
62
Philippe Mathieu-Daudé (1):
21
linux-user: Fix trivial build error on loongarch64 hosts
63
exec/helper-head: Include missing "fpu/softfloat-types.h" header
22
64
23
Richard Henderson (2):
65
Richard Henderson (32):
24
tcg/optimize: Fix folding of vector ops
66
accel/tcg: Add 'size' param to probe_access_full
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
67
tcg: Adjust TCGContext.temps_in_use check
68
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
69
accel/tcg: Use more accurate max_insns for tb_overflow
70
tcg: Remove branch-to-next regardless of reference count
71
tcg: Rename TEMP_LOCAL to TEMP_TB
72
tcg: Use noinline for major tcg_gen_code subroutines
73
tcg: Add liveness_pass_0
74
tcg: Remove TEMP_NORMAL
75
tcg: Pass TCGTempKind to tcg_temp_new_internal
76
tcg: Use tcg_constant_i32 in tcg_gen_io_start
77
tcg: Add tcg_gen_movi_ptr
78
tcg: Add tcg_temp_ebb_new_{i32,i64,ptr}
79
tcg: Use tcg_temp_ebb_new_* in tcg/
80
tcg: Use tcg_constant_ptr in do_dup
81
accel/tcg/plugin: Use tcg_temp_ebb_*
82
accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers
83
tcg: Don't re-use TEMP_TB temporaries
84
tcg: Change default temp lifetime to TEMP_TB
85
target/arm: Drop copies in gen_sve_{ldr,str}
86
target/arm: Don't use tcg_temp_local_new_*
87
target/cris: Don't use tcg_temp_local_new
88
target/hexagon: Don't use tcg_temp_local_new_*
89
target/hexagon/idef-parser: Drop gen_tmp_local
90
target/hppa: Don't use tcg_temp_local_new
91
target/i386: Don't use tcg_temp_local_new
92
target/mips: Don't use tcg_temp_local_new
93
target/ppc: Don't use tcg_temp_local_new
94
target/xtensa: Don't use tcg_temp_local_new_*
95
exec/gen-icount: Don't use tcg_temp_local_new_i32
96
tcg: Remove tcg_temp_local_new_*, tcg_const_local_*
97
tcg: Update docs/devel/tcg-ops.rst for temporary changes
26
98
27
Xiaoyao Li (1):
99
docs/devel/tcg-ops.rst | 230 +++++++++++++----------
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
100
target/hexagon/idef-parser/README.rst | 4 +-
101
accel/tcg/internal.h | 10 +-
102
accel/tcg/tb-jmp-cache.h | 42 +----
103
include/exec/cpu-defs.h | 3 -
104
include/exec/exec-all.h | 26 +--
105
include/exec/gen-icount.h | 12 +-
106
include/exec/helper-head.h | 2 +
107
include/exec/translator.h | 4 +-
108
include/tcg/tcg-op.h | 7 +-
109
include/tcg/tcg.h | 64 ++++---
110
target/arm/cpu-param.h | 2 -
111
target/arm/tcg/translate-a64.h | 1 -
112
target/arm/tcg/translate.h | 2 +-
113
target/hexagon/gen_tcg.h | 4 +-
114
target/i386/cpu-param.h | 4 -
115
accel/stubs/tcg-stub.c | 2 +-
116
accel/tcg/cpu-exec.c | 62 ++++--
117
accel/tcg/cputlb.c | 21 ++-
118
accel/tcg/perf.c | 2 +-
119
accel/tcg/plugin-gen.c | 32 ++--
120
accel/tcg/tb-maint.c | 10 +-
121
accel/tcg/translate-all.c | 18 +-
122
accel/tcg/translator.c | 6 +-
123
accel/tcg/user-exec.c | 5 +-
124
semihosting/uaccess.c | 2 +-
125
softmmu/physmem.c | 2 +-
126
target/alpha/translate.c | 2 +-
127
target/arm/cpu.c | 17 +-
128
target/arm/ptw.c | 4 +-
129
target/arm/tcg/mte_helper.c | 4 +-
130
target/arm/tcg/sve_helper.c | 4 +-
131
target/arm/tcg/translate-a64.c | 16 +-
132
target/arm/tcg/translate-sve.c | 38 +---
133
target/arm/tcg/translate.c | 14 +-
134
target/avr/cpu.c | 3 +-
135
target/avr/translate.c | 2 +-
136
target/cris/translate.c | 8 +-
137
target/hexagon/cpu.c | 4 +-
138
target/hexagon/genptr.c | 16 +-
139
target/hexagon/idef-parser/parser-helpers.c | 26 +--
140
target/hexagon/translate.c | 4 +-
141
target/hppa/cpu.c | 8 +-
142
target/hppa/translate.c | 5 +-
143
target/i386/cpu.c | 5 +
144
target/i386/helper.c | 2 +-
145
target/i386/tcg/sysemu/excp_helper.c | 4 +-
146
target/i386/tcg/tcg-cpu.c | 8 +-
147
target/i386/tcg/translate.c | 55 +++---
148
target/loongarch/cpu.c | 6 +-
149
target/loongarch/translate.c | 2 +-
150
target/m68k/translate.c | 2 +-
151
target/microblaze/cpu.c | 4 +-
152
target/microblaze/translate.c | 2 +-
153
target/mips/tcg/exception.c | 3 +-
154
target/mips/tcg/sysemu/special_helper.c | 2 +-
155
target/mips/tcg/translate.c | 59 ++----
156
target/nios2/translate.c | 2 +-
157
target/openrisc/cpu.c | 4 +-
158
target/openrisc/translate.c | 2 +-
159
target/ppc/translate.c | 8 +-
160
target/riscv/cpu.c | 7 +-
161
target/riscv/translate.c | 2 +-
162
target/rx/cpu.c | 3 +-
163
target/rx/translate.c | 2 +-
164
target/s390x/tcg/mem_helper.c | 2 +-
165
target/s390x/tcg/translate.c | 2 +-
166
target/sh4/cpu.c | 6 +-
167
target/sh4/translate.c | 2 +-
168
target/sparc/cpu.c | 4 +-
169
target/sparc/translate.c | 2 +-
170
target/tricore/cpu.c | 3 +-
171
target/tricore/translate.c | 2 +-
172
target/xtensa/translate.c | 18 +-
173
tcg/optimize.c | 2 +-
174
tcg/tcg-op-gvec.c | 189 ++++++++++---------
175
tcg/tcg-op.c | 258 ++++++++++++-------------
176
tcg/tcg.c | 280 ++++++++++++++++------------
177
target/cris/translate_v10.c.inc | 10 +-
178
target/mips/tcg/nanomips_translate.c.inc | 4 +-
179
target/ppc/translate/spe-impl.c.inc | 8 +-
180
target/ppc/translate/vmx-impl.c.inc | 4 +-
181
target/hexagon/README | 8 +-
182
target/hexagon/gen_tcg_funcs.py | 18 +-
183
84 files changed, 870 insertions(+), 890 deletions(-)
29
184
30
include/sysemu/sysemu.h | 1 -
31
linux-user/host/loongarch64/host-signal.h | 4 +--
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
33
common-user/host/i386/safe-syscall.inc.S | 1 +
34
common-user/host/mips/safe-syscall.inc.S | 1 +
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
36
6 files changed, 42 insertions(+), 15 deletions(-)
37
diff view generated by jsdifflib
Deleted patch
1
Bitwise operations are easy to fold, because the operation is
2
identical regardless of element size. But add and sub need
3
extra element size info that is not currently propagated.
4
1
5
Fixes: 2f9f08ba43d
6
Cc: qemu-stable@nongnu.org
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
12
1 file changed, 38 insertions(+), 11 deletions(-)
13
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
17
+++ b/tcg/optimize.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
19
CASE_OP_32_64(mul):
20
return x * y;
21
22
- CASE_OP_32_64(and):
23
+ CASE_OP_32_64_VEC(and):
24
return x & y;
25
26
- CASE_OP_32_64(or):
27
+ CASE_OP_32_64_VEC(or):
28
return x | y;
29
30
- CASE_OP_32_64(xor):
31
+ CASE_OP_32_64_VEC(xor):
32
return x ^ y;
33
34
case INDEX_op_shl_i32:
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
36
case INDEX_op_rotl_i64:
37
return rol64(x, y & 63);
38
39
- CASE_OP_32_64(not):
40
+ CASE_OP_32_64_VEC(not):
41
return ~x;
42
43
CASE_OP_32_64(neg):
44
return -x;
45
46
- CASE_OP_32_64(andc):
47
+ CASE_OP_32_64_VEC(andc):
48
return x & ~y;
49
50
- CASE_OP_32_64(orc):
51
+ CASE_OP_32_64_VEC(orc):
52
return x | ~y;
53
54
CASE_OP_32_64(eqv):
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
56
return false;
57
}
58
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
60
+{
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
62
+ return false;
63
+}
64
+
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
66
{
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
69
return false;
70
}
71
72
+/* We cannot as yet do_constant_folding with vectors. */
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
74
+{
75
+ if (fold_commutative(ctx, op) ||
76
+ fold_xi_to_x(ctx, op, 0)) {
77
+ return true;
78
+ }
79
+ return false;
80
+}
81
+
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
83
{
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
86
return false;
87
}
88
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
90
+/* We cannot as yet do_constant_folding with vectors. */
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
92
{
93
- if (fold_const2(ctx, op) ||
94
- fold_xx_to_i(ctx, op, 0) ||
95
+ if (fold_xx_to_i(ctx, op, 0) ||
96
fold_xi_to_x(ctx, op, 0) ||
97
fold_sub_to_neg(ctx, op)) {
98
return true;
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
100
return false;
101
}
102
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
104
+{
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
106
+}
107
+
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
109
{
110
return fold_addsub2(ctx, op, false);
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
* Sorted alphabetically by opcode as much as possible.
113
*/
114
switch (opc) {
115
- CASE_OP_32_64_VEC(add):
116
+ CASE_OP_32_64(add):
117
done = fold_add(&ctx, op);
118
break;
119
+ case INDEX_op_add_vec:
120
+ done = fold_add_vec(&ctx, op);
121
+ break;
122
CASE_OP_32_64(add2):
123
done = fold_add2(&ctx, op);
124
break;
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
126
CASE_OP_32_64(sextract):
127
done = fold_sextract(&ctx, op);
128
break;
129
- CASE_OP_32_64_VEC(sub):
130
+ CASE_OP_32_64(sub):
131
done = fold_sub(&ctx, op);
132
break;
133
+ case INDEX_op_sub_vec:
134
+ done = fold_sub_vec(&ctx, op);
135
+ break;
136
CASE_OP_32_64(sub2):
137
done = fold_sub2(&ctx, op);
138
break;
139
--
140
2.25.1
141
142
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
30
1 file changed, 1 insertion(+), 3 deletions(-)
31
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
35
+++ b/linux-user/host/loongarch64/host-signal.h
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
37
}
38
break;
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
41
-
42
- switch (sel) {
43
+ switch ((insn >> 15) & 0b11111111111) {
44
case 0b00000100000: /* stx.b */
45
case 0b00000101000: /* stx.h */
46
case 0b00000110000: /* stx.w */
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
Deleted patch
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
2
1
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
4
and user.
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/sysemu/sysemu.h | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
18
+++ b/include/sysemu/sysemu.h
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
20
void qemu_add_exit_notifier(Notifier *notify);
21
void qemu_remove_exit_notifier(Notifier *notify);
22
23
-void qemu_run_machine_init_done_notifiers(void);
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
Deleted patch
1
For the ABIs in which the syscall return register is not
2
also the first function argument register, move the errno
3
value into the correct place.
4
1
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
11
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
13
common-user/host/mips/safe-syscall.inc.S | 1 +
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
18
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
20
+++ b/common-user/host/i386/safe-syscall.inc.S
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
22
pop %ebp
23
.cfi_adjust_cfa_offset -4
24
.cfi_restore ebp
25
+ mov %eax, (%esp)
26
jmp safe_syscall_set_errno_tail
27
28
.cfi_endproc
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
30
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
32
+++ b/common-user/host/mips/safe-syscall.inc.S
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
34
1: USE_ALT_CP(t0)
35
SETUP_GPX(t1)
36
SETUP_GPX64(t0, t1)
37
+ move a0, v0
38
PTR_LA t9, safe_syscall_set_errno_tail
39
jr t9
40
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
42
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
46
1: pop %rbp
47
.cfi_def_cfa_offset 8
48
.cfi_restore rbp
49
+ mov %eax, %edi
50
jmp safe_syscall_set_errno_tail
51
.cfi_endproc
52
53
--
54
2.25.1
55
56
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