[PULL 0/4] tcg patch queue
[PULL v2 00/20] tcg patch queue
1
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
1
v2: Fix incorretly resolved rebase conflict in patch 16.
2
2
3
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
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4
r~
5
6
7
The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60:
8
9
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-09-02 13:24:28 -0400)
4
10
5
are available in the Git repository at:
11
are available in the Git repository at:
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12
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220904
8
14
9
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
15
for you to fetch changes up to cc64de1fdeb81bc1ab8bb6c7c24bfd4fc9b28ef2:
10
16
11
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
17
target/riscv: Make translator stop before the end of a page (2022-09-03 09:27:05 +0100)
12
18
13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
Fix for safe_syscall_base.
20
Respect PROT_EXEC in user-only mode.
15
Fix for folding of vector add/sub.
21
Fix s390x, i386 and riscv for translations crossing a page.
16
Fix build on loongarch64 with gcc 8.
17
Remove decl for qemu_run_machine_init_done_notifiers.
18
22
19
----------------------------------------------------------------
23
----------------------------------------------------------------
20
Philippe Mathieu-Daudé (1):
24
Ilya Leoshkevich (4):
21
linux-user: Fix trivial build error on loongarch64 hosts
25
linux-user: Clear translations on mprotect()
26
accel/tcg: Introduce is_same_page()
27
target/s390x: Make translator stop before the end of a page
28
target/i386: Make translator stop before the end of a page
22
29
23
Richard Henderson (2):
30
Richard Henderson (16):
24
tcg/optimize: Fix folding of vector ops
31
linux-user/arm: Mark the commpage executable
25
common-user: Fix tail calls to safe_syscall_set_errno_tail
32
linux-user/hppa: Allocate page zero as a commpage
33
linux-user/x86_64: Allocate vsyscall page as a commpage
34
linux-user: Honor PT_GNU_STACK
35
tests/tcg/i386: Move smc_code2 to an executable section
36
accel/tcg: Properly implement get_page_addr_code for user-only
37
accel/tcg: Unlock mmap_lock after longjmp
38
accel/tcg: Make tb_htable_lookup static
39
accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
40
accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp
41
accel/tcg: Document the faulting lookup in tb_lookup_cmp
42
accel/tcg: Remove translator_ldsw
43
accel/tcg: Add pc and host_pc params to gen_intermediate_code
44
accel/tcg: Add fast path for translator_ld*
45
target/riscv: Add MAX_INSN_LEN and insn_len
46
target/riscv: Make translator stop before the end of a page
26
47
27
Xiaoyao Li (1):
48
include/elf.h | 1 +
28
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
49
include/exec/cpu-common.h | 1 +
29
50
include/exec/exec-all.h | 89 ++++++++----------------
30
include/sysemu/sysemu.h | 1 -
51
include/exec/translator.h | 96 ++++++++++++++++---------
31
linux-user/host/loongarch64/host-signal.h | 4 +--
52
linux-user/arm/target_cpu.h | 4 +-
32
tcg/optimize.c | 49 +++++++++++++++++++++++-------
53
linux-user/qemu.h | 1 +
33
common-user/host/i386/safe-syscall.inc.S | 1 +
54
accel/tcg/cpu-exec.c | 143 ++++++++++++++++++++------------------
34
common-user/host/mips/safe-syscall.inc.S | 1 +
55
accel/tcg/cputlb.c | 93 +++++++------------------
35
common-user/host/x86_64/safe-syscall.inc.S | 1 +
56
accel/tcg/translate-all.c | 29 ++++----
36
6 files changed, 42 insertions(+), 15 deletions(-)
57
accel/tcg/translator.c | 135 ++++++++++++++++++++++++++---------
37
58
accel/tcg/user-exec.c | 17 ++++-
59
linux-user/elfload.c | 82 ++++++++++++++++++++--
60
linux-user/mmap.c | 6 +-
61
softmmu/physmem.c | 12 ++++
62
target/alpha/translate.c | 5 +-
63
target/arm/translate.c | 5 +-
64
target/avr/translate.c | 5 +-
65
target/cris/translate.c | 5 +-
66
target/hexagon/translate.c | 6 +-
67
target/hppa/translate.c | 5 +-
68
target/i386/tcg/translate.c | 71 +++++++++++--------
69
target/loongarch/translate.c | 6 +-
70
target/m68k/translate.c | 5 +-
71
target/microblaze/translate.c | 5 +-
72
target/mips/tcg/translate.c | 5 +-
73
target/nios2/translate.c | 5 +-
74
target/openrisc/translate.c | 6 +-
75
target/ppc/translate.c | 5 +-
76
target/riscv/translate.c | 32 +++++++--
77
target/rx/translate.c | 5 +-
78
target/s390x/tcg/translate.c | 20 ++++--
79
target/sh4/translate.c | 5 +-
80
target/sparc/translate.c | 5 +-
81
target/tricore/translate.c | 6 +-
82
target/xtensa/translate.c | 6 +-
83
tests/tcg/i386/test-i386.c | 2 +-
84
tests/tcg/riscv64/noexec.c | 79 +++++++++++++++++++++
85
tests/tcg/s390x/noexec.c | 106 ++++++++++++++++++++++++++++
86
tests/tcg/x86_64/noexec.c | 75 ++++++++++++++++++++
87
tests/tcg/multiarch/noexec.c.inc | 139 ++++++++++++++++++++++++++++++++++++
88
tests/tcg/riscv64/Makefile.target | 1 +
89
tests/tcg/s390x/Makefile.target | 1 +
90
tests/tcg/x86_64/Makefile.target | 3 +-
91
43 files changed, 966 insertions(+), 367 deletions(-)
92
create mode 100644 tests/tcg/riscv64/noexec.c
93
create mode 100644 tests/tcg/s390x/noexec.c
94
create mode 100644 tests/tcg/x86_64/noexec.c
95
create mode 100644 tests/tcg/multiarch/noexec.c.inc
diff view generated by jsdifflib
[PULL 1/4] tcg/optimize: Fix folding of vector ops
[PULL v2 16/20] accel/tcg: Add fast path for translator_ld*
1
Bitwise operations are easy to fold, because the operation is
1
Cache the translation from guest to host address, so we may
2
identical regardless of element size. But add and sub need
2
use direct loads when we hit on the primary translation page.
3
extra element size info that is not currently propagated.
4
3
5
Fixes: 2f9f08ba43d
4
Look up the second translation page only once, during translation.
6
Cc: qemu-stable@nongnu.org
5
This obviates another lookup of the second page within tb_gen_code
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
6
after translation.
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
8
Fixes a bug in that plugin_insn_append should be passed the bytes
9
in the original memory order, not bswapped by pieces.
10
11
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
12
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
14
---
11
tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++-----------
15
include/exec/translator.h | 63 +++++++++++--------
12
1 file changed, 38 insertions(+), 11 deletions(-)
16
accel/tcg/translate-all.c | 23 +++----
17
accel/tcg/translator.c | 126 +++++++++++++++++++++++++++++---------
18
3 files changed, 141 insertions(+), 71 deletions(-)
13
19
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
20
diff --git a/include/exec/translator.h b/include/exec/translator.h
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
22
--- a/include/exec/translator.h
17
+++ b/tcg/optimize.c
23
+++ b/include/exec/translator.h
18
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
24
@@ -XXX,XX +XXX,XX @@ typedef enum DisasJumpType {
19
CASE_OP_32_64(mul):
25
* Architecture-agnostic disassembly context.
20
return x * y;
26
*/
21
27
typedef struct DisasContextBase {
22
- CASE_OP_32_64(and):
28
- const TranslationBlock *tb;
23
+ CASE_OP_32_64_VEC(and):
29
+ TranslationBlock *tb;
24
return x & y;
30
target_ulong pc_first;
25
31
target_ulong pc_next;
26
- CASE_OP_32_64(or):
32
DisasJumpType is_jmp;
27
+ CASE_OP_32_64_VEC(or):
33
int num_insns;
28
return x | y;
34
int max_insns;
29
35
bool singlestep_enabled;
30
- CASE_OP_32_64(xor):
36
-#ifdef CONFIG_USER_ONLY
31
+ CASE_OP_32_64_VEC(xor):
37
- /*
32
return x ^ y;
38
- * Guest address of the last byte of the last protected page.
33
39
- *
34
case INDEX_op_shl_i32:
40
- * Pages containing the translated instructions are made non-writable in
35
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
41
- * order to achieve consistency in case another thread is modifying the
36
case INDEX_op_rotl_i64:
42
- * code while translate_insn() fetches the instruction bytes piecemeal.
37
return rol64(x, y & 63);
43
- * Such writer threads are blocked on mmap_lock() in page_unprotect().
38
44
- */
39
- CASE_OP_32_64(not):
45
- target_ulong page_protect_end;
40
+ CASE_OP_32_64_VEC(not):
46
-#endif
41
return ~x;
47
+ void *host_addr[2];
42
48
} DisasContextBase;
43
CASE_OP_32_64(neg):
49
44
return -x;
50
/**
45
51
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
46
- CASE_OP_32_64(andc):
52
* the relevant information at translation time.
47
+ CASE_OP_32_64_VEC(andc):
53
*/
48
return x & ~y;
54
49
55
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
50
- CASE_OP_32_64(orc):
56
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
51
+ CASE_OP_32_64_VEC(orc):
57
- abi_ptr pc, bool do_swap); \
52
return x | ~y;
58
- static inline type fullname(CPUArchState *env, \
53
59
- DisasContextBase *dcbase, abi_ptr pc) \
54
CASE_OP_32_64(eqv):
60
- { \
55
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
61
- return fullname ## _swap(env, dcbase, pc, false); \
56
return false;
62
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
63
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
64
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
65
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
66
+
67
+static inline uint16_t
68
+translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
69
+ abi_ptr pc, bool do_swap)
70
+{
71
+ uint16_t ret = translator_lduw(env, db, pc);
72
+ if (do_swap) {
73
+ ret = bswap16(ret);
74
}
75
+ return ret;
76
+}
77
78
-#define FOR_EACH_TRANSLATOR_LD(F) \
79
- F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
80
- F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
81
- F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
82
- F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
83
+static inline uint32_t
84
+translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
85
+ abi_ptr pc, bool do_swap)
86
+{
87
+ uint32_t ret = translator_ldl(env, db, pc);
88
+ if (do_swap) {
89
+ ret = bswap32(ret);
90
+ }
91
+ return ret;
92
+}
93
94
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
95
-
96
-#undef GEN_TRANSLATOR_LD
97
+static inline uint64_t
98
+translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
99
+ abi_ptr pc, bool do_swap)
100
+{
101
+ uint64_t ret = translator_ldq(env, db, pc);
102
+ if (do_swap) {
103
+ ret = bswap64(ret);
104
+ }
105
+ return ret;
106
+}
107
108
/*
109
* Return whether addr is on the same page as where disassembly started.
110
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/accel/tcg/translate-all.c
113
+++ b/accel/tcg/translate-all.c
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
115
{
116
CPUArchState *env = cpu->env_ptr;
117
TranslationBlock *tb, *existing_tb;
118
- tb_page_addr_t phys_pc, phys_page2;
119
- target_ulong virt_page2;
120
+ tb_page_addr_t phys_pc;
121
tcg_insn_unit *gen_code_buf;
122
int gen_code_size, search_size, max_insns;
123
#ifdef CONFIG_PROFILER
124
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
125
tb->flags = flags;
126
tb->cflags = cflags;
127
tb->trace_vcpu_dstate = *cpu->trace_dstate;
128
+ tb->page_addr[0] = phys_pc;
129
+ tb->page_addr[1] = -1;
130
tcg_ctx->tb_cflags = cflags;
131
tb_overflow:
132
133
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
134
}
135
136
/*
137
- * If the TB is not associated with a physical RAM page then
138
- * it must be a temporary one-insn TB, and we have nothing to do
139
- * except fill in the page_addr[] fields. Return early before
140
- * attempting to link to other TBs or add to the lookup table.
141
+ * If the TB is not associated with a physical RAM page then it must be
142
+ * a temporary one-insn TB, and we have nothing left to do. Return early
143
+ * before attempting to link to other TBs or add to the lookup table.
144
*/
145
- if (phys_pc == -1) {
146
- tb->page_addr[0] = tb->page_addr[1] = -1;
147
+ if (tb->page_addr[0] == -1) {
148
return tb;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
152
*/
153
tcg_tb_insert(tb);
154
155
- /* check next page if needed */
156
- virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
157
- phys_page2 = -1;
158
- if ((pc & TARGET_PAGE_MASK) != virt_page2) {
159
- phys_page2 = get_page_addr_code(env, virt_page2);
160
- }
161
/*
162
* No explicit memory barrier is required -- tb_link_page() makes the
163
* TB visible in a consistent state.
164
*/
165
- existing_tb = tb_link_page(tb, phys_pc, phys_page2);
166
+ existing_tb = tb_link_page(tb, tb->page_addr[0], tb->page_addr[1]);
167
/* if the TB already exists, discard what we just translated */
168
if (unlikely(existing_tb != tb)) {
169
uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
170
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/accel/tcg/translator.c
173
+++ b/accel/tcg/translator.c
174
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
175
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
57
}
176
}
58
177
59
+static bool fold_commutative(OptContext *ctx, TCGOp *op)
178
-static inline void translator_page_protect(DisasContextBase *dcbase,
60
+{
179
- target_ulong pc)
61
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
180
-{
62
+ return false;
181
-#ifdef CONFIG_USER_ONLY
63
+}
182
- dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
64
+
183
- page_protect(pc);
65
static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
184
-#endif
185
-}
186
-
187
void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
188
target_ulong pc, void *host_pc,
189
const TranslatorOps *ops, DisasContextBase *db)
190
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
191
db->num_insns = 0;
192
db->max_insns = max_insns;
193
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
194
- translator_page_protect(db, db->pc_next);
195
+ db->host_addr[0] = host_pc;
196
+ db->host_addr[1] = NULL;
197
+
198
+#ifdef CONFIG_USER_ONLY
199
+ page_protect(pc);
200
+#endif
201
202
ops->init_disas_context(db, cpu);
203
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
204
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
205
#endif
206
}
207
208
-static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
209
- target_ulong pc, size_t len)
210
+static void *translator_access(CPUArchState *env, DisasContextBase *db,
211
+ target_ulong pc, size_t len)
66
{
212
{
67
swap_commutative(op->args[0], &op->args[1], &op->args[2]);
213
-#ifdef CONFIG_USER_ONLY
68
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
214
- target_ulong end = pc + len - 1;
69
return false;
215
+ void *host;
216
+ target_ulong base, end;
217
+ TranslationBlock *tb;
218
219
- if (end > dcbase->page_protect_end) {
220
- translator_page_protect(dcbase, end);
221
+ tb = db->tb;
222
+
223
+ /* Use slow path if first page is MMIO. */
224
+ if (unlikely(tb->page_addr[0] == -1)) {
225
+ return NULL;
226
}
227
+
228
+ end = pc + len - 1;
229
+ if (likely(is_same_page(db, end))) {
230
+ host = db->host_addr[0];
231
+ base = db->pc_first;
232
+ } else {
233
+ host = db->host_addr[1];
234
+ base = TARGET_PAGE_ALIGN(db->pc_first);
235
+ if (host == NULL) {
236
+ tb->page_addr[1] =
237
+ get_page_addr_code_hostp(env, base, &db->host_addr[1]);
238
+#ifdef CONFIG_USER_ONLY
239
+ page_protect(end);
240
#endif
241
+ /* We cannot handle MMIO as second page. */
242
+ assert(tb->page_addr[1] != -1);
243
+ host = db->host_addr[1];
244
+ }
245
+
246
+ /* Use slow path when crossing pages. */
247
+ if (is_same_page(db, pc)) {
248
+ return NULL;
249
+ }
250
+ }
251
+
252
+ tcg_debug_assert(pc >= base);
253
+ return host + (pc - base);
70
}
254
}
71
255
72
+/* We cannot as yet do_constant_folding with vectors. */
256
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
73
+static bool fold_add_vec(OptContext *ctx, TCGOp *op)
257
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
74
+{
258
- abi_ptr pc, bool do_swap) \
75
+ if (fold_commutative(ctx, op) ||
259
- { \
76
+ fold_xi_to_x(ctx, op, 0)) {
260
- translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
77
+ return true;
261
- type ret = load_fn(env, pc); \
78
+ }
262
- if (do_swap) { \
79
+ return false;
263
- ret = swap_fn(ret); \
80
+}
264
- } \
81
+
265
- plugin_insn_append(pc, &ret, sizeof(ret)); \
82
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
266
- return ret; \
83
{
267
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
84
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
268
+{
85
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
269
+ uint8_t ret;
86
return false;
270
+ void *p = translator_access(env, db, pc, sizeof(ret));
87
}
271
+
88
272
+ if (p) {
89
-static bool fold_sub(OptContext *ctx, TCGOp *op)
273
+ plugin_insn_append(pc, p, sizeof(ret));
90
+/* We cannot as yet do_constant_folding with vectors. */
274
+ return ldub_p(p);
91
+static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
275
}
92
{
276
+ ret = cpu_ldub_code(env, pc);
93
- if (fold_const2(ctx, op) ||
277
+ plugin_insn_append(pc, &ret, sizeof(ret));
94
- fold_xx_to_i(ctx, op, 0) ||
278
+ return ret;
95
+ if (fold_xx_to_i(ctx, op, 0) ||
279
+}
96
fold_xi_to_x(ctx, op, 0) ||
280
97
fold_sub_to_neg(ctx, op)) {
281
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
98
return true;
282
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
283
+{
100
return false;
284
+ uint16_t ret, plug;
101
}
285
+ void *p = translator_access(env, db, pc, sizeof(ret));
102
286
103
+static bool fold_sub(OptContext *ctx, TCGOp *op)
287
-#undef GEN_TRANSLATOR_LD
104
+{
288
+ if (p) {
105
+ return fold_const2(ctx, op) || fold_sub_vec(ctx, op);
289
+ plugin_insn_append(pc, p, sizeof(ret));
106
+}
290
+ return lduw_p(p);
107
+
291
+ }
108
static bool fold_sub2(OptContext *ctx, TCGOp *op)
292
+ ret = cpu_lduw_code(env, pc);
109
{
293
+ plug = tswap16(ret);
110
return fold_addsub2(ctx, op, false);
294
+ plugin_insn_append(pc, &plug, sizeof(ret));
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
295
+ return ret;
112
* Sorted alphabetically by opcode as much as possible.
296
+}
113
*/
297
+
114
switch (opc) {
298
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
115
- CASE_OP_32_64_VEC(add):
299
+{
116
+ CASE_OP_32_64(add):
300
+ uint32_t ret, plug;
117
done = fold_add(&ctx, op);
301
+ void *p = translator_access(env, db, pc, sizeof(ret));
118
break;
302
+
119
+ case INDEX_op_add_vec:
303
+ if (p) {
120
+ done = fold_add_vec(&ctx, op);
304
+ plugin_insn_append(pc, p, sizeof(ret));
121
+ break;
305
+ return ldl_p(p);
122
CASE_OP_32_64(add2):
306
+ }
123
done = fold_add2(&ctx, op);
307
+ ret = cpu_ldl_code(env, pc);
124
break;
308
+ plug = tswap32(ret);
125
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
309
+ plugin_insn_append(pc, &plug, sizeof(ret));
126
CASE_OP_32_64(sextract):
310
+ return ret;
127
done = fold_sextract(&ctx, op);
311
+}
128
break;
312
+
129
- CASE_OP_32_64_VEC(sub):
313
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
130
+ CASE_OP_32_64(sub):
314
+{
131
done = fold_sub(&ctx, op);
315
+ uint64_t ret, plug;
132
break;
316
+ void *p = translator_access(env, db, pc, sizeof(ret));
133
+ case INDEX_op_sub_vec:
317
+
134
+ done = fold_sub_vec(&ctx, op);
318
+ if (p) {
135
+ break;
319
+ plugin_insn_append(pc, p, sizeof(ret));
136
CASE_OP_32_64(sub2):
320
+ return ldq_p(p);
137
done = fold_sub2(&ctx, op);
321
+ }
138
break;
322
+ ret = cpu_ldq_code(env, pc);
323
+ plug = tswap64(ret);
324
+ plugin_insn_append(pc, &plug, sizeof(ret));
325
+ return ret;
326
+}
139
--
327
--
140
2.25.1
328
2.34.1
141
142
diff view generated by jsdifflib
[PULL 2/4] linux-user: Fix trivial build error on loongarch64 hosts
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
4
5
In file included from ../linux-user/signal.c:33:
6
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
7
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement
8
uint32_t sel = (insn >> 15) & 0b11111111111;
9
^~~~~~~~
10
11
We don't use the 'sel' variable more than once, so drop it.
12
13
Meson output for the record:
14
15
Host machine cpu family: loongarch64
16
Host machine cpu: loongarch64
17
C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0")
18
C linker for the host machine: cc ld.bfd 2.31.1-system
19
20
Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts")
21
Reported-by: Song Gao <gaosong@loongson.cn>
22
Suggested-by: Song Gao <gaosong@loongson.cn>
23
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: WANG Xuerui <git@xen0n.name>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20220104215027.2180972-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
linux-user/host/loongarch64/host-signal.h | 4 +---
30
1 file changed, 1 insertion(+), 3 deletions(-)
31
32
diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/host/loongarch64/host-signal.h
35
+++ b/linux-user/host/loongarch64/host-signal.h
36
@@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
37
}
38
break;
39
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
40
- uint32_t sel = (insn >> 15) & 0b11111111111;
41
-
42
- switch (sel) {
43
+ switch ((insn >> 15) & 0b11111111111) {
44
case 0b00000100000: /* stx.b */
45
case 0b00000101000: /* stx.h */
46
case 0b00000110000: /* stx.w */
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
[PULL 3/4] sysemu: Cleanup qemu_run_machine_init_done_notifiers()
Deleted patch
1
From: Xiaoyao Li <xiaoyao.li@intel.com>
2
1
3
Remove qemu_run_machine_init_done_notifiers() since no implementation
4
and user.
5
6
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
7
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/sysemu/sysemu.h | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/sysemu/sysemu.h
18
+++ b/include/sysemu/sysemu.h
19
@@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set;
20
void qemu_add_exit_notifier(Notifier *notify);
21
void qemu_remove_exit_notifier(Notifier *notify);
22
23
-void qemu_run_machine_init_done_notifiers(void);
24
void qemu_add_machine_init_done_notifier(Notifier *notify);
25
void qemu_remove_machine_init_done_notifier(Notifier *notify);
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
[PULL 4/4] common-user: Fix tail calls to safe_syscall_set_errno_tail
Deleted patch
1
For the ABIs in which the syscall return register is not
2
also the first function argument register, move the errno
3
value into the correct place.
4
1
5
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base")
6
Reported-by: Laurent Vivier <laurent@vivier.eu>
7
Tested-by: Laurent Vivier <laurent@vivier.eu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org>
11
---
12
common-user/host/i386/safe-syscall.inc.S | 1 +
13
common-user/host/mips/safe-syscall.inc.S | 1 +
14
common-user/host/x86_64/safe-syscall.inc.S | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S
18
index XXXXXXX..XXXXXXX 100644
19
--- a/common-user/host/i386/safe-syscall.inc.S
20
+++ b/common-user/host/i386/safe-syscall.inc.S
21
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
22
pop %ebp
23
.cfi_adjust_cfa_offset -4
24
.cfi_restore ebp
25
+ mov %eax, (%esp)
26
jmp safe_syscall_set_errno_tail
27
28
.cfi_endproc
29
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
30
index XXXXXXX..XXXXXXX 100644
31
--- a/common-user/host/mips/safe-syscall.inc.S
32
+++ b/common-user/host/mips/safe-syscall.inc.S
33
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
34
1: USE_ALT_CP(t0)
35
SETUP_GPX(t1)
36
SETUP_GPX64(t0, t1)
37
+ move a0, v0
38
PTR_LA t9, safe_syscall_set_errno_tail
39
jr t9
40
41
diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S
42
index XXXXXXX..XXXXXXX 100644
43
--- a/common-user/host/x86_64/safe-syscall.inc.S
44
+++ b/common-user/host/x86_64/safe-syscall.inc.S
45
@@ -XXX,XX +XXX,XX @@ safe_syscall_end:
46
1: pop %rbp
47
.cfi_def_cfa_offset 8
48
.cfi_restore rbp
49
+ mov %eax, %edi
50
jmp safe_syscall_set_errno_tail
51
.cfi_endproc
52
53
--
54
2.25.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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