1 | The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea: | 1 | Version 4: Drop the cpu_loop noreturn patch. |
---|---|---|---|
2 | 2 | ||
3 | Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800) | 3 | |
4 | r~ | ||
5 | |||
6 | |||
7 | The following changes since commit 4c9af1ea1457782cf0adb293179335ef6de942aa: | ||
8 | |||
9 | gitlab-ci: Make more custom runner jobs manual, and don't allow failure (2021-09-14 17:03:03 +0100) | ||
4 | 10 | ||
5 | are available in the Git repository at: | 11 | are available in the Git repository at: |
6 | 12 | ||
7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104 | 13 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914-4 |
8 | 14 | ||
9 | for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4: | 15 | for you to fetch changes up to e028eada62dbfcba134ac5afdefc3aa343ae202f: |
10 | 16 | ||
11 | common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800) | 17 | tcg/arm: More use of the TCGReg enum (2021-09-14 12:00:21 -0700) |
12 | 18 | ||
13 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
14 | Fix for safe_syscall_base. | 20 | Fix translation race condition for user-only. |
15 | Fix for folding of vector add/sub. | 21 | Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ. |
16 | Fix build on loongarch64 with gcc 8. | 22 | Fix tcg/arm tcg_out_vec_op signature. |
17 | Remove decl for qemu_run_machine_init_done_notifiers. | 23 | Fix tcg/ppc (32bit) build with clang. |
24 | Remove dupluate TCG_KICK_PERIOD definition. | ||
25 | Remove unused tcg_global_reg_new. | ||
26 | Restrict cpu_exec_interrupt and its callees to sysemu. | ||
27 | Cleanups for tcg/arm. | ||
18 | 28 | ||
19 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
20 | Philippe Mathieu-Daudé (1): | 30 | Bin Meng (1): |
21 | linux-user: Fix trivial build error on loongarch64 hosts | 31 | tcg: Remove tcg_global_reg_new defines |
22 | 32 | ||
23 | Richard Henderson (2): | 33 | Ilya Leoshkevich (3): |
24 | tcg/optimize: Fix folding of vector ops | 34 | accel/tcg: Add DisasContextBase argument to translator_ld* |
25 | common-user: Fix tail calls to safe_syscall_set_errno_tail | 35 | accel/tcg: Clear PAGE_WRITE before translation |
36 | accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts | ||
26 | 37 | ||
27 | Xiaoyao Li (1): | 38 | Jose R. Ziviani (1): |
28 | sysemu: Cleanup qemu_run_machine_init_done_notifiers() | 39 | tcg/arm: Fix tcg_out_vec_op function signature |
29 | 40 | ||
30 | include/sysemu/sysemu.h | 1 - | 41 | Luc Michel (1): |
31 | linux-user/host/loongarch64/host-signal.h | 4 +-- | 42 | accel/tcg: remove redundant TCG_KICK_PERIOD define |
32 | tcg/optimize.c | 49 +++++++++++++++++++++++------- | ||
33 | common-user/host/i386/safe-syscall.inc.S | 1 + | ||
34 | common-user/host/mips/safe-syscall.inc.S | 1 + | ||
35 | common-user/host/x86_64/safe-syscall.inc.S | 1 + | ||
36 | 6 files changed, 42 insertions(+), 15 deletions(-) | ||
37 | 43 | ||
44 | Philippe Mathieu-Daudé (24): | ||
45 | target/avr: Remove pointless use of CONFIG_USER_ONLY definition | ||
46 | target/i386: Restrict sysemu-only fpu_helper helpers | ||
47 | target/i386: Simplify TARGET_X86_64 #ifdef'ry | ||
48 | target/xtensa: Restrict do_transaction_failed() to sysemu | ||
49 | accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt | ||
50 | target/alpha: Restrict cpu_exec_interrupt() handler to sysemu | ||
51 | target/arm: Restrict cpu_exec_interrupt() handler to sysemu | ||
52 | target/cris: Restrict cpu_exec_interrupt() handler to sysemu | ||
53 | target/hppa: Restrict cpu_exec_interrupt() handler to sysemu | ||
54 | target/i386: Restrict cpu_exec_interrupt() handler to sysemu | ||
55 | target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder | ||
56 | target/m68k: Restrict cpu_exec_interrupt() handler to sysemu | ||
57 | target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu | ||
58 | target/mips: Restrict cpu_exec_interrupt() handler to sysemu | ||
59 | target/nios2: Restrict cpu_exec_interrupt() handler to sysemu | ||
60 | target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu | ||
61 | target/ppc: Restrict cpu_exec_interrupt() handler to sysemu | ||
62 | target/riscv: Restrict cpu_exec_interrupt() handler to sysemu | ||
63 | target/sh4: Restrict cpu_exec_interrupt() handler to sysemu | ||
64 | target/sparc: Restrict cpu_exec_interrupt() handler to sysemu | ||
65 | target/rx: Restrict cpu_exec_interrupt() handler to sysemu | ||
66 | target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu | ||
67 | accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu | ||
68 | user: Remove cpu_get_pic_interrupt() stubs | ||
69 | |||
70 | Richard Henderson (13): | ||
71 | tcg/i386: Split P_VEXW from P_REXW | ||
72 | tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN | ||
73 | tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF | ||
74 | tcg/arm: Remove fallback definition of __ARM_ARCH | ||
75 | tcg/arm: Standardize on tcg_out_<branch>_{reg,imm} | ||
76 | tcg/arm: Simplify use_armv5t_instructions | ||
77 | tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call | ||
78 | tcg/arm: Split out tcg_out_ldstm | ||
79 | tcg/arm: Simplify usage of encode_imm | ||
80 | tcg/arm: Drop inline markers | ||
81 | tcg/arm: Give enum arm_cond_code_e a typedef and use it | ||
82 | tcg/arm: More use of the ARMInsn enum | ||
83 | tcg/arm: More use of the TCGReg enum | ||
84 | |||
85 | include/exec/translate-all.h | 1 + | ||
86 | include/exec/translator.h | 44 +-- | ||
87 | include/hw/core/tcg-cpu-ops.h | 26 +- | ||
88 | include/tcg/tcg-op.h | 2 - | ||
89 | target/alpha/cpu.h | 2 +- | ||
90 | target/arm/arm_ldst.h | 12 +- | ||
91 | target/arm/cpu.h | 3 +- | ||
92 | target/cris/cpu.h | 2 +- | ||
93 | target/hppa/cpu.h | 4 +- | ||
94 | target/i386/cpu.h | 3 + | ||
95 | target/i386/tcg/helper-tcg.h | 2 + | ||
96 | target/m68k/cpu.h | 2 + | ||
97 | target/microblaze/cpu.h | 2 + | ||
98 | target/mips/tcg/tcg-internal.h | 5 +- | ||
99 | target/openrisc/cpu.h | 5 +- | ||
100 | target/ppc/cpu.h | 4 +- | ||
101 | target/riscv/cpu.h | 2 +- | ||
102 | target/rx/cpu.h | 2 + | ||
103 | target/sh4/cpu.h | 4 +- | ||
104 | target/xtensa/cpu.h | 2 + | ||
105 | tcg/arm/tcg-target.h | 27 +- | ||
106 | accel/tcg/cpu-exec.c | 14 +- | ||
107 | accel/tcg/tcg-accel-ops-rr.c | 2 - | ||
108 | accel/tcg/translate-all.c | 59 ++-- | ||
109 | accel/tcg/translator.c | 39 +++ | ||
110 | accel/tcg/user-exec.c | 48 ++- | ||
111 | bsd-user/i386/target_arch_cpu.c | 5 - | ||
112 | bsd-user/x86_64/target_arch_cpu.c | 5 - | ||
113 | linux-user/main.c | 7 - | ||
114 | target/alpha/cpu.c | 2 +- | ||
115 | target/alpha/helper.c | 5 +- | ||
116 | target/alpha/translate.c | 2 +- | ||
117 | target/arm/cpu.c | 7 +- | ||
118 | target/arm/cpu_tcg.c | 6 +- | ||
119 | target/arm/translate-a64.c | 2 +- | ||
120 | target/arm/translate.c | 9 +- | ||
121 | target/avr/cpu.c | 3 - | ||
122 | target/cris/cpu.c | 4 +- | ||
123 | target/cris/helper.c | 17 +- | ||
124 | target/hexagon/translate.c | 3 +- | ||
125 | target/hppa/cpu.c | 2 +- | ||
126 | target/hppa/int_helper.c | 7 +- | ||
127 | target/hppa/translate.c | 5 +- | ||
128 | target/i386/tcg/seg_helper.c | 74 +---- | ||
129 | target/i386/tcg/sysemu/seg_helper.c | 62 ++++ | ||
130 | target/i386/tcg/tcg-cpu.c | 8 +- | ||
131 | target/i386/tcg/translate.c | 10 +- | ||
132 | target/m68k/cpu.c | 2 +- | ||
133 | target/m68k/op_helper.c | 16 +- | ||
134 | target/m68k/translate.c | 2 +- | ||
135 | target/microblaze/cpu.c | 2 +- | ||
136 | target/microblaze/helper.c | 13 +- | ||
137 | target/mips/cpu.c | 2 +- | ||
138 | target/mips/tcg/exception.c | 18 -- | ||
139 | target/mips/tcg/sysemu/tlb_helper.c | 18 ++ | ||
140 | target/mips/tcg/translate.c | 8 +- | ||
141 | target/mips/tcg/user/tlb_helper.c | 5 - | ||
142 | target/nios2/cpu.c | 5 +- | ||
143 | target/openrisc/cpu.c | 2 +- | ||
144 | target/openrisc/interrupt.c | 2 - | ||
145 | target/openrisc/translate.c | 2 +- | ||
146 | target/ppc/cpu_init.c | 2 +- | ||
147 | target/ppc/excp_helper.c | 21 +- | ||
148 | target/ppc/translate.c | 5 +- | ||
149 | target/riscv/cpu.c | 2 +- | ||
150 | target/riscv/cpu_helper.c | 5 - | ||
151 | target/riscv/translate.c | 5 +- | ||
152 | target/rx/cpu.c | 2 +- | ||
153 | target/rx/helper.c | 4 + | ||
154 | target/s390x/tcg/translate.c | 16 +- | ||
155 | target/sh4/cpu.c | 2 +- | ||
156 | target/sh4/helper.c | 9 +- | ||
157 | target/sh4/translate.c | 4 +- | ||
158 | target/sparc/cpu.c | 4 +- | ||
159 | target/sparc/translate.c | 2 +- | ||
160 | target/xtensa/cpu.c | 2 +- | ||
161 | target/xtensa/exc_helper.c | 7 +- | ||
162 | target/xtensa/translate.c | 5 +- | ||
163 | target/mips/tcg/micromips_translate.c.inc | 2 +- | ||
164 | target/mips/tcg/mips16e_translate.c.inc | 4 +- | ||
165 | target/mips/tcg/nanomips_translate.c.inc | 4 +- | ||
166 | tcg/arm/tcg-target.c.inc | 517 ++++++++++++++++-------------- | ||
167 | tcg/i386/tcg-target.c.inc | 13 +- | ||
168 | tcg/ppc/tcg-target.c.inc | 25 +- | ||
169 | target/openrisc/meson.build | 6 +- | ||
170 | 85 files changed, 700 insertions(+), 628 deletions(-) | ||
171 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Bitwise operations are easy to fold, because the operation is | ||
2 | identical regardless of element size. But add and sub need | ||
3 | extra element size info that is not currently propagated. | ||
4 | 1 | ||
5 | Fixes: 2f9f08ba43d | ||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799 | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | tcg/optimize.c | 49 ++++++++++++++++++++++++++++++++++++++----------- | ||
12 | 1 file changed, 38 insertions(+), 11 deletions(-) | ||
13 | |||
14 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tcg/optimize.c | ||
17 | +++ b/tcg/optimize.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | ||
19 | CASE_OP_32_64(mul): | ||
20 | return x * y; | ||
21 | |||
22 | - CASE_OP_32_64(and): | ||
23 | + CASE_OP_32_64_VEC(and): | ||
24 | return x & y; | ||
25 | |||
26 | - CASE_OP_32_64(or): | ||
27 | + CASE_OP_32_64_VEC(or): | ||
28 | return x | y; | ||
29 | |||
30 | - CASE_OP_32_64(xor): | ||
31 | + CASE_OP_32_64_VEC(xor): | ||
32 | return x ^ y; | ||
33 | |||
34 | case INDEX_op_shl_i32: | ||
35 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | ||
36 | case INDEX_op_rotl_i64: | ||
37 | return rol64(x, y & 63); | ||
38 | |||
39 | - CASE_OP_32_64(not): | ||
40 | + CASE_OP_32_64_VEC(not): | ||
41 | return ~x; | ||
42 | |||
43 | CASE_OP_32_64(neg): | ||
44 | return -x; | ||
45 | |||
46 | - CASE_OP_32_64(andc): | ||
47 | + CASE_OP_32_64_VEC(andc): | ||
48 | return x & ~y; | ||
49 | |||
50 | - CASE_OP_32_64(orc): | ||
51 | + CASE_OP_32_64_VEC(orc): | ||
52 | return x | ~y; | ||
53 | |||
54 | CASE_OP_32_64(eqv): | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op) | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | +static bool fold_commutative(OptContext *ctx, TCGOp *op) | ||
60 | +{ | ||
61 | + swap_commutative(op->args[0], &op->args[1], &op->args[2]); | ||
62 | + return false; | ||
63 | +} | ||
64 | + | ||
65 | static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) | ||
66 | { | ||
67 | swap_commutative(op->args[0], &op->args[1], &op->args[2]); | ||
68 | @@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op) | ||
69 | return false; | ||
70 | } | ||
71 | |||
72 | +/* We cannot as yet do_constant_folding with vectors. */ | ||
73 | +static bool fold_add_vec(OptContext *ctx, TCGOp *op) | ||
74 | +{ | ||
75 | + if (fold_commutative(ctx, op) || | ||
76 | + fold_xi_to_x(ctx, op, 0)) { | ||
77 | + return true; | ||
78 | + } | ||
79 | + return false; | ||
80 | +} | ||
81 | + | ||
82 | static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) | ||
83 | { | ||
84 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) && | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) | ||
86 | return false; | ||
87 | } | ||
88 | |||
89 | -static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
90 | +/* We cannot as yet do_constant_folding with vectors. */ | ||
91 | +static bool fold_sub_vec(OptContext *ctx, TCGOp *op) | ||
92 | { | ||
93 | - if (fold_const2(ctx, op) || | ||
94 | - fold_xx_to_i(ctx, op, 0) || | ||
95 | + if (fold_xx_to_i(ctx, op, 0) || | ||
96 | fold_xi_to_x(ctx, op, 0) || | ||
97 | fold_sub_to_neg(ctx, op)) { | ||
98 | return true; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
100 | return false; | ||
101 | } | ||
102 | |||
103 | +static bool fold_sub(OptContext *ctx, TCGOp *op) | ||
104 | +{ | ||
105 | + return fold_const2(ctx, op) || fold_sub_vec(ctx, op); | ||
106 | +} | ||
107 | + | ||
108 | static bool fold_sub2(OptContext *ctx, TCGOp *op) | ||
109 | { | ||
110 | return fold_addsub2(ctx, op, false); | ||
111 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
112 | * Sorted alphabetically by opcode as much as possible. | ||
113 | */ | ||
114 | switch (opc) { | ||
115 | - CASE_OP_32_64_VEC(add): | ||
116 | + CASE_OP_32_64(add): | ||
117 | done = fold_add(&ctx, op); | ||
118 | break; | ||
119 | + case INDEX_op_add_vec: | ||
120 | + done = fold_add_vec(&ctx, op); | ||
121 | + break; | ||
122 | CASE_OP_32_64(add2): | ||
123 | done = fold_add2(&ctx, op); | ||
124 | break; | ||
125 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
126 | CASE_OP_32_64(sextract): | ||
127 | done = fold_sextract(&ctx, op); | ||
128 | break; | ||
129 | - CASE_OP_32_64_VEC(sub): | ||
130 | + CASE_OP_32_64(sub): | ||
131 | done = fold_sub(&ctx, op); | ||
132 | break; | ||
133 | + case INDEX_op_sub_vec: | ||
134 | + done = fold_sub_vec(&ctx, op); | ||
135 | + break; | ||
136 | CASE_OP_32_64(sub2): | ||
137 | done = fold_sub2(&ctx, op); | ||
138 | break; | ||
139 | -- | ||
140 | 2.25.1 | ||
141 | |||
142 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | When building using GCC 8.3.0 on loongarch64 (Loongnix) we get: | ||
4 | |||
5 | In file included from ../linux-user/signal.c:33: | ||
6 | ../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’: | ||
7 | ../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be part of a statement and a declaration is not a statement | ||
8 | uint32_t sel = (insn >> 15) & 0b11111111111; | ||
9 | ^~~~~~~~ | ||
10 | |||
11 | We don't use the 'sel' variable more than once, so drop it. | ||
12 | |||
13 | Meson output for the record: | ||
14 | |||
15 | Host machine cpu family: loongarch64 | ||
16 | Host machine cpu: loongarch64 | ||
17 | C compiler for the host machine: cc (gcc 8.3.0 "cc (Loongnix 8.3.0-6.lnd.vec.27) 8.3.0") | ||
18 | C linker for the host machine: cc ld.bfd 2.31.1-system | ||
19 | |||
20 | Fixes: ad812c3bd65 ("linux-user: Implement CPU-specific signal handler for loongarch64 hosts") | ||
21 | Reported-by: Song Gao <gaosong@loongson.cn> | ||
22 | Suggested-by: Song Gao <gaosong@loongson.cn> | ||
23 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
24 | Reviewed-by: WANG Xuerui <git@xen0n.name> | ||
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-Id: <20220104215027.2180972-1-f4bug@amsat.org> | ||
27 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
28 | --- | ||
29 | linux-user/host/loongarch64/host-signal.h | 4 +--- | ||
30 | 1 file changed, 1 insertion(+), 3 deletions(-) | ||
31 | |||
32 | diff --git a/linux-user/host/loongarch64/host-signal.h b/linux-user/host/loongarch64/host-signal.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/linux-user/host/loongarch64/host-signal.h | ||
35 | +++ b/linux-user/host/loongarch64/host-signal.h | ||
36 | @@ -XXX,XX +XXX,XX @@ static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) | ||
37 | } | ||
38 | break; | ||
39 | case 0b001110: /* indexed, atomic, bounds-checking memory operations */ | ||
40 | - uint32_t sel = (insn >> 15) & 0b11111111111; | ||
41 | - | ||
42 | - switch (sel) { | ||
43 | + switch ((insn >> 15) & 0b11111111111) { | ||
44 | case 0b00000100000: /* stx.b */ | ||
45 | case 0b00000101000: /* stx.h */ | ||
46 | case 0b00000110000: /* stx.w */ | ||
47 | -- | ||
48 | 2.25.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Xiaoyao Li <xiaoyao.li@intel.com> | ||
2 | 1 | ||
3 | Remove qemu_run_machine_init_done_notifiers() since no implementation | ||
4 | and user. | ||
5 | |||
6 | Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c") | ||
7 | Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-Id: <20220104024136.1433545-1-xiaoyao.li@intel.com> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | include/sysemu/sysemu.h | 1 - | ||
13 | 1 file changed, 1 deletion(-) | ||
14 | |||
15 | diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/sysemu/sysemu.h | ||
18 | +++ b/include/sysemu/sysemu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ extern bool qemu_uuid_set; | ||
20 | void qemu_add_exit_notifier(Notifier *notify); | ||
21 | void qemu_remove_exit_notifier(Notifier *notify); | ||
22 | |||
23 | -void qemu_run_machine_init_done_notifiers(void); | ||
24 | void qemu_add_machine_init_done_notifier(Notifier *notify); | ||
25 | void qemu_remove_machine_init_done_notifier(Notifier *notify); | ||
26 | |||
27 | -- | ||
28 | 2.25.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For the ABIs in which the syscall return register is not | ||
2 | also the first function argument register, move the errno | ||
3 | value into the correct place. | ||
4 | 1 | ||
5 | Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into safe_syscall_base") | ||
6 | Reported-by: Laurent Vivier <laurent@vivier.eu> | ||
7 | Tested-by: Laurent Vivier <laurent@vivier.eu> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-Id: <20220104190454.542225-1-richard.henderson@linaro.org> | ||
11 | --- | ||
12 | common-user/host/i386/safe-syscall.inc.S | 1 + | ||
13 | common-user/host/mips/safe-syscall.inc.S | 1 + | ||
14 | common-user/host/x86_64/safe-syscall.inc.S | 1 + | ||
15 | 3 files changed, 3 insertions(+) | ||
16 | |||
17 | diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/common-user/host/i386/safe-syscall.inc.S | ||
20 | +++ b/common-user/host/i386/safe-syscall.inc.S | ||
21 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
22 | pop %ebp | ||
23 | .cfi_adjust_cfa_offset -4 | ||
24 | .cfi_restore ebp | ||
25 | + mov %eax, (%esp) | ||
26 | jmp safe_syscall_set_errno_tail | ||
27 | |||
28 | .cfi_endproc | ||
29 | diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/common-user/host/mips/safe-syscall.inc.S | ||
32 | +++ b/common-user/host/mips/safe-syscall.inc.S | ||
33 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
34 | 1: USE_ALT_CP(t0) | ||
35 | SETUP_GPX(t1) | ||
36 | SETUP_GPX64(t0, t1) | ||
37 | + move a0, v0 | ||
38 | PTR_LA t9, safe_syscall_set_errno_tail | ||
39 | jr t9 | ||
40 | |||
41 | diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/common-user/host/x86_64/safe-syscall.inc.S | ||
44 | +++ b/common-user/host/x86_64/safe-syscall.inc.S | ||
45 | @@ -XXX,XX +XXX,XX @@ safe_syscall_end: | ||
46 | 1: pop %rbp | ||
47 | .cfi_def_cfa_offset 8 | ||
48 | .cfi_restore rbp | ||
49 | + mov %eax, %edi | ||
50 | jmp safe_syscall_set_errno_tail | ||
51 | .cfi_endproc | ||
52 | |||
53 | -- | ||
54 | 2.25.1 | ||
55 | |||
56 | diff view generated by jsdifflib |