[PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties

liweiwei posted 7 patches 4 years, 1 month ago
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, "Daniel P. Berrangé" <berrange@redhat.com>
There is a newer version of this series
[PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
Posted by liweiwei 4 years, 1 month ago
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 961c5f4334..6575ec8cfa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,19 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
+    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
+    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
+    DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
+    DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
+    DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
+    DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
+    DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
+    DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
+    DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
+    DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
+    DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
+    DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     /* ePMP 0.9.3 */
-- 
2.17.1


Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
Posted by Alistair Francis 4 years, 1 month ago
On Fri, Dec 31, 2021 at 12:32 AM liweiwei <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
> Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 961c5f4334..6575ec8cfa 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,19 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>      DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>      DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
> +    DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
> +    DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
> +    DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
> +    DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
> +    DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
> +    DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
> +    DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
> +    DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
> +    DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
> +    DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),

These are ratified specs, so these don't need to be marked as
experimental, you can drop the "x-".

Alistair

>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>      /* ePMP 0.9.3 */
> --
> 2.17.1
>
>

Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
Posted by Weiwei Li 4 years, 1 month ago
在 2022/1/10 下午3:06, Alistair Francis 写道:
> On Fri, Dec 31, 2021 at 12:32 AM liweiwei <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
>> Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/cpu.c | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 961c5f4334..6575ec8cfa 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -668,6 +668,19 @@ static Property riscv_cpu_properties[] = {
>>       DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>>       DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>>       DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
>> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
>> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
>> +    DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
>> +    DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
>> +    DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
>> +    DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
>> +    DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
>> +    DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
>> +    DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
>> +    DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
>> +    DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
>> +    DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),
> These are ratified specs, so these don't need to be marked as
> experimental, you can drop the "x-".
>
> Alistair
>
OK. I'll update them. Thanks.
>>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>>       DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>>       /* ePMP 0.9.3 */
>> --
>> 2.17.1
>>
>>