From: Frank Chang <frank.chang@sifive.com>
In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
This patchset implements Zve32f and Zve64f extensions.
The port is available at:
https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream
Zve32f can be enabled with -cpu option: Zve32f=true and
Zve64f can be enabled with -cpu option: Zve64f=true.
V is not required to be enabled explicitly.
Quote from the inclusion diagram for the six standard vector extensions
from Nick Knight <nick.knight@sifive.com>:
V
|
Zve64d
|
Zve64f
/ \
Zve64x Zve32f
\ /
Zve32x
Note: This patchset depends on other patchsets listed in Based-on
section below so it is not able to be built unless those patchsets
are applied.
Based-on: <20211229021250.29804-1-frank.chang@sifive.com>
Frank Chang (17):
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx
insns
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
target/riscv: rvv-1.0: Add Zve64f support for single-width fp
reduction insns
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert
insns
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert
insns
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
target/riscv: rvv-1.0: Add Zve32f support for single-width fp
reduction insns
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert
insns
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert
insns
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
target/riscv/cpu.c | 6 +
target/riscv/cpu.h | 2 +
target/riscv/cpu_helper.c | 5 +-
target/riscv/csr.c | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc | 217 ++++++++++++++++++++----
target/riscv/translate.c | 4 +
6 files changed, 203 insertions(+), 37 deletions(-)
--
2.31.1