[PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang <frank.chang@sifive.com>

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-12-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5d1eec1ea0..3dfbc17738 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
     if (env->misa_ext & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+#endif
         return RISCV_EXCP_NONE;
     }
     return RISCV_EXCP_ILLEGAL_INST;
-- 
2.31.1

• [PULL 01/88] target/riscv: zfh: half-precision load and store
• [PULL 02/88] target/riscv: zfh: half-precision computational
• [PULL 03/88] target/riscv: zfh: half-precision convert and move
• [PULL 04/88] target/riscv: zfh: half-precision floating-point compare
• [PULL 05/88] target/riscv: zfh: half-precision floating-point classify
• [PULL 06/88] target/riscv: zfh: add Zfh cpu property
• [PULL 07/88] target/riscv: zfh: implement zfhmin extension
• [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property
• [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support
• [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field
• [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field
• [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
• [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field
• [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field
• [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status
• [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
• [PULL 17/88] target/riscv: rvv-1.0: add vcsr register
• [PULL 18/88] target/riscv: rvv-1.0: add vlenb register
• [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
• [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations
• [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL
• [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA
• [PULL 23/88] target/riscv: rvv-1.0: update check functions
• [PULL 24/88] target/riscv: introduce more imm value modes in translator functions
• [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function
• [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions
• [PULL 27/88] target/riscv: rvv-1.0: configure instructions
• [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions
• [PULL 29/88] target/riscv: rvv-1.0: index load and store instructions
• [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load
• [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions
• [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
• [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
• [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction
• [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions
• [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction
• [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction
• [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions
• [PULL 40/88] target/riscv: rvv-1.0: iota instruction
• [PULL 41/88] target/riscv: rvv-1.0: element index instruction
• [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended
• [PULL 43/88] target/riscv: rvv-1.0: register gather instructions
• [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions
• [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction
• [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions
• [PULL 47/88] target/riscv: rvv-1.0: whole register move instructions
• [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions
• [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
• [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions
• [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
• [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions
• [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions
• [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
• [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions
• [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions
• [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions
• [PULL 58/88] target/riscv: rvv-1.0: slide instructions
• [PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions
• [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
• [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction
• [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions
• [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions
• [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
• [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
• [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction
• [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions
• [PULL 68/88] target/riscv: introduce floating-point rounding mode enum
• [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
• [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert
• [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function
• [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
• [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
• [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR
• [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
• [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32
• [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
• [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
• [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
• [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction
• [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
• [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
• [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
• [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment
• [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
• [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32
• [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions
• [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr