1
Hi; here's the first target-arm pullreq for the 7.0 cycle.
1
The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:
2
2
3
thanks
3
Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)
4
-- PMM
5
6
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
7
8
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203
13
8
14
for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:
9
for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:
15
10
16
tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)
11
target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* ITS: error reporting cleanup
15
* Fix physical address resolution for Stage2
21
* aspeed: improve documentation
16
* pl011: refactoring, implement reset method
22
* Fix STM32F2XX USART data register readout
17
* Support GICv3 with hvf acceleration
23
* allow emulated GICv3 to be disabled in non-TCG builds
18
* sbsa-ref: remove cortex-a76 from list of supported cpus
24
* fix exception priority for singlestep, misaligned PC, bp, etc
19
* Correct syndrome for ATS12NSO* traps at Secure EL1
25
* Correct calculation of tlb range invalidate length
20
* Fix priority of HSTR_EL2 traps vs UNDEFs
26
* npcm7xx_emc: fix missing queue_flush
21
* Implement FEAT_FGT for '-cpu max'
27
* virt: Add VIOT ACPI table for virtio-iommu
28
* target/i386: Use assert() to sanity-check b1 in SSE decode
29
* Don't include qemu-common unnecessarily
30
22
31
----------------------------------------------------------------
23
----------------------------------------------------------------
32
Alex Bennée (1):
24
Alexander Graf (3):
33
hw/intc: clean-up error reporting for failed ITS cmd
25
hvf: arm: Add support for GICv3
26
hw/arm/virt: Consolidate GIC finalize logic
27
hw/arm/virt: Make accels in GIC finalize logic explicit
34
28
35
Jean-Philippe Brucker (8):
29
Evgeny Iakovlev (4):
36
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
30
hw/char/pl011: refactor FIFO depth handling code
37
hw/arm/virt: Remove device tree restriction for virtio-iommu
31
hw/char/pl011: add post_load hook for backwards-compatibility
38
hw/arm/virt: Reject instantiation of multiple IOMMUs
32
hw/char/pl011: implement a reset method
39
hw/arm/virt: Use object_property_set instead of qdev_prop_set
33
hw/char/pl011: better handling of FIFO flags on LCR reset
40
tests/acpi: allow updates of VIOT expected data files
41
tests/acpi: add test case for VIOT
42
tests/acpi: add expected blobs for VIOT test on q35 machine
43
tests/acpi: add expected blob for VIOT test on virt machine
44
34
45
Joel Stanley (4):
35
Marcin Juszkiewicz (1):
46
docs: aspeed: Add new boards
36
sbsa-ref: remove cortex-a76 from list of supported cpus
47
docs: aspeed: Update OpenBMC image URL
48
docs: aspeed: Give an example of booting a kernel
49
docs: aspeed: ADC is now modelled
50
37
51
Olivier Hériveaux (1):
38
Peter Maydell (23):
52
Fix STM32F2XX USART data register readout
39
target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
40
target/arm: Correct syndrome for ATS12NSO* at Secure EL1
41
target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
42
target/arm: Move do_coproc_insn() syndrome calculation earlier
43
target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
44
target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
45
target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
46
target/arm: Define the FEAT_FGT registers
47
target/arm: Implement FGT trapping infrastructure
48
target/arm: Mark up sysregs for HFGRTR bits 0..11
49
target/arm: Mark up sysregs for HFGRTR bits 12..23
50
target/arm: Mark up sysregs for HFGRTR bits 24..35
51
target/arm: Mark up sysregs for HFGRTR bits 36..63
52
target/arm: Mark up sysregs for HDFGRTR bits 0..11
53
target/arm: Mark up sysregs for HDFGRTR bits 12..63
54
target/arm: Mark up sysregs for HFGITR bits 0..11
55
target/arm: Mark up sysregs for HFGITR bits 12..17
56
target/arm: Mark up sysregs for HFGITR bits 18..47
57
target/arm: Mark up sysregs for HFGITR bits 48..63
58
target/arm: Implement the HFGITR_EL2.ERET trap
59
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
60
target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
61
target/arm: Enable FEAT_FGT on '-cpu max'
53
62
54
Patrick Venture (1):
63
Richard Henderson (2):
55
hw/net: npcm7xx_emc fix missing queue_flush
64
hw/arm: Use TYPE_ARM_SMMUV3
65
target/arm: Fix physical address resolution for Stage2
56
66
57
Peter Maydell (6):
67
docs/system/arm/emulation.rst | 1 +
58
target/i386: Use assert() to sanity-check b1 in SSE decode
68
include/hw/arm/virt.h | 15 +-
59
include/hw/i386: Don't include qemu-common.h in .h files
69
include/hw/char/pl011.h | 5 +-
60
target/hexagon/cpu.h: don't include qemu-common.h
70
target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++++++++++-
61
target/rx/cpu.h: Don't include qemu-common.h
71
target/arm/cpu.h | 18 ++
62
hw/arm: Don't include qemu-common.h unnecessarily
72
target/arm/internals.h | 20 ++
63
target/arm: Correct calculation of tlb range invalidate length
73
target/arm/syndrome.h | 10 +
64
74
target/arm/translate.h | 6 +
65
Philippe Mathieu-Daudé (2):
75
hw/arm/sbsa-ref.c | 4 +-
66
hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
76
hw/arm/virt.c | 203 +++++++++---------
67
hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
77
hw/char/pl011.c | 93 ++++++--
68
78
hw/intc/arm_gicv3_cpuif.c | 18 +-
69
Richard Henderson (10):
79
target/arm/cpu64.c | 1 +
70
target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
80
target/arm/debug_helper.c | 46 +++-
71
target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
81
target/arm/helper.c | 245 ++++++++++++++++++++-
72
target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
82
target/arm/hvf/hvf.c | 151 +++++++++++++
73
target/arm: Split arm_pre_translate_insn
83
target/arm/op_helper.c | 58 ++++-
74
target/arm: Advance pc for arch single-step exception
84
target/arm/ptw.c | 2 +-
75
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
85
target/arm/translate-a64.c | 22 +-
76
target/arm: Take an exception if PC is misaligned
86
target/arm/translate.c | 125 +++++++----
77
target/arm: Assert thumb pc is aligned
87
target/arm/hvf/trace-events | 2 +
78
target/arm: Suppress bp for exceptions with more priority
88
21 files changed, 1340 insertions(+), 189 deletions(-)
79
tests/tcg: Add arm and aarch64 pc alignment tests
80
81
docs/system/arm/aspeed.rst | 26 ++++++++++++----
82
include/hw/i386/microvm.h | 1 -
83
include/hw/i386/x86.h | 1 -
84
target/arm/helper.h | 1 +
85
target/arm/syndrome.h | 5 +++
86
target/hexagon/cpu.h | 1 -
87
target/rx/cpu.h | 1 -
88
hw/arm/boot.c | 1 -
89
hw/arm/digic_boards.c | 1 -
90
hw/arm/highbank.c | 1 -
91
hw/arm/npcm7xx_boards.c | 1 -
92
hw/arm/sbsa-ref.c | 1 -
93
hw/arm/stm32f405_soc.c | 1 -
94
hw/arm/vexpress.c | 1 -
95
hw/arm/virt-acpi-build.c | 7 +++++
96
hw/arm/virt.c | 21 ++++++-------
97
hw/char/stm32f2xx_usart.c | 3 +-
98
hw/intc/arm_gicv3.c | 2 +-
99
hw/intc/arm_gicv3_cpuif.c | 10 +-----
100
hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++
101
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++--------
102
hw/net/npcm7xx_emc.c | 18 +++++------
103
hw/virtio/virtio-iommu-pci.c | 12 ++------
104
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------
105
linux-user/hexagon/cpu_loop.c | 1 +
106
target/arm/debug_helper.c | 23 ++++++++++++++
107
target/arm/gdbstub.c | 9 ++++--
108
target/arm/helper.c | 6 ++--
109
target/arm/machine.c | 10 ++++++
110
target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++----------
111
target/arm/translate-a64.c | 23 ++++++++++++--
112
target/arm/translate.c | 58 ++++++++++++++++++++++++++---------
113
target/i386/tcg/translate.c | 12 ++------
114
tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++
115
tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++
116
tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++
117
hw/arm/Kconfig | 1 +
118
hw/intc/Kconfig | 5 +++
119
hw/intc/meson.build | 11 ++++---
120
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
121
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
122
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
123
tests/tcg/aarch64/Makefile.target | 4 +--
124
tests/tcg/arm/Makefile.target | 4 +++
125
44 files changed, 429 insertions(+), 145 deletions(-)
126
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
127
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
128
create mode 100644 tests/tcg/arm/pcalign-a32.c
129
create mode 100644 tests/data/acpi/q35/DSDT.viot
130
create mode 100644 tests/data/acpi/q35/VIOT.viot
131
create mode 100644 tests/data/acpi/virt/VIOT
132
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The size of the code covered by a TranslationBlock cannot be 0;
3
Use the macro instead of two explicit string literals.
4
this is checked via assert in tb_gen_code.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/translate-a64.c | 1 +
11
hw/arm/sbsa-ref.c | 3 ++-
11
1 file changed, 1 insertion(+)
12
hw/arm/virt.c | 2 +-
13
2 files changed, 3 insertions(+), 2 deletions(-)
12
14
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
17
--- a/hw/arm/sbsa-ref.c
16
+++ b/target/arm/translate-a64.c
18
+++ b/hw/arm/sbsa-ref.c
17
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
19
@@ -XXX,XX +XXX,XX @@
18
assert(s->base.num_insns == 1);
20
#include "exec/hwaddr.h"
19
gen_swstep_exception(s, 0, 0);
21
#include "kvm_arm.h"
20
s->base.is_jmp = DISAS_NORETURN;
22
#include "hw/arm/boot.h"
21
+ s->base.pc_next = pc + 4;
23
+#include "hw/arm/smmuv3.h"
24
#include "hw/block/flash.h"
25
#include "hw/boards.h"
26
#include "hw/ide/internal.h"
27
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
28
DeviceState *dev;
29
int i;
30
31
- dev = qdev_new("arm-smmuv3");
32
+ dev = qdev_new(TYPE_ARM_SMMUV3);
33
34
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
35
&error_abort);
36
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/virt.c
39
+++ b/hw/arm/virt.c
40
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
22
return;
41
return;
23
}
42
}
24
43
44
- dev = qdev_new("arm-smmuv3");
45
+ dev = qdev_new(TYPE_ARM_SMMUV3);
46
47
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
48
&error_abort);
25
--
49
--
26
2.25.1
50
2.34.1
27
51
28
52
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Conversion to probe_access_full missed applying the page offset.
4
5
Cc: qemu-stable@nongnu.org
6
Reported-by: Sid Manning <sidneym@quicinc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
10
Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
13
---
7
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
14
target/arm/ptw.c | 2 +-
8
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
15
1 file changed, 1 insertion(+), 1 deletion(-)
9
tests/tcg/aarch64/Makefile.target | 4 +--
10
tests/tcg/arm/Makefile.target | 4 +++
11
4 files changed, 89 insertions(+), 2 deletions(-)
12
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
13
create mode 100644 tests/tcg/arm/pcalign-a32.c
14
16
15
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/tests/tcg/aarch64/pcalign-a64.c
20
@@ -XXX,XX +XXX,XX @@
21
+/* Test PC misalignment exception */
22
+
23
+#include <assert.h>
24
+#include <signal.h>
25
+#include <stdlib.h>
26
+#include <stdio.h>
27
+
28
+static void *expected;
29
+
30
+static void sigbus(int sig, siginfo_t *info, void *vuc)
31
+{
32
+ assert(info->si_code == BUS_ADRALN);
33
+ assert(info->si_addr == expected);
34
+ exit(EXIT_SUCCESS);
35
+}
36
+
37
+int main()
38
+{
39
+ void *tmp;
40
+
41
+ struct sigaction sa = {
42
+ .sa_sigaction = sigbus,
43
+ .sa_flags = SA_SIGINFO
44
+ };
45
+
46
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
47
+ perror("sigaction");
48
+ return EXIT_FAILURE;
49
+ }
50
+
51
+ asm volatile("adr %0, 1f + 1\n\t"
52
+ "str %0, %1\n\t"
53
+ "br %0\n"
54
+ "1:"
55
+ : "=&r"(tmp), "=m"(expected));
56
+ abort();
57
+}
58
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/tests/tcg/arm/pcalign-a32.c
63
@@ -XXX,XX +XXX,XX @@
64
+/* Test PC misalignment exception */
65
+
66
+#ifdef __thumb__
67
+#error "This test must be compiled for ARM"
68
+#endif
69
+
70
+#include <assert.h>
71
+#include <signal.h>
72
+#include <stdlib.h>
73
+#include <stdio.h>
74
+
75
+static void *expected;
76
+
77
+static void sigbus(int sig, siginfo_t *info, void *vuc)
78
+{
79
+ assert(info->si_code == BUS_ADRALN);
80
+ assert(info->si_addr == expected);
81
+ exit(EXIT_SUCCESS);
82
+}
83
+
84
+int main()
85
+{
86
+ void *tmp;
87
+
88
+ struct sigaction sa = {
89
+ .sa_sigaction = sigbus,
90
+ .sa_flags = SA_SIGINFO
91
+ };
92
+
93
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
94
+ perror("sigaction");
95
+ return EXIT_FAILURE;
96
+ }
97
+
98
+ asm volatile("adr %0, 1f + 2\n\t"
99
+ "str %0, %1\n\t"
100
+ "bx %0\n"
101
+ "1:"
102
+ : "=&r"(tmp), "=m"(expected));
103
+
104
+ /*
105
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
106
+ * the address or not. If so, we can legitimately fall through.
107
+ */
108
+ return EXIT_SUCCESS;
109
+}
110
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
111
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/tcg/aarch64/Makefile.target
19
--- a/target/arm/ptw.c
113
+++ b/tests/tcg/aarch64/Makefile.target
20
+++ b/target/arm/ptw.c
114
@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
21
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
115
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
22
if (unlikely(flags & TLB_INVALID_MASK)) {
116
VPATH         += $(AARCH64_SRC)
23
goto fail;
117
24
}
118
-# Float-convert Tests
25
- ptw->out_phys = full->phys_addr;
119
-AARCH64_TESTS=fcvt
26
+ ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
120
+# Base architecture tests
27
ptw->out_rw = full->prot & PAGE_WRITE;
121
+AARCH64_TESTS=fcvt pcalign-a64
28
pte_attrs = full->pte_attrs;
122
29
pte_secure = full->attrs.secure;
123
fcvt: LDFLAGS+=-lm
124
125
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
126
index XXXXXXX..XXXXXXX 100644
127
--- a/tests/tcg/arm/Makefile.target
128
+++ b/tests/tcg/arm/Makefile.target
129
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
130
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
131
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
132
133
+# PC alignment test
134
+ARM_TESTS += pcalign-a32
135
+pcalign-a32: CFLAGS+=-marm
136
+
137
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
138
139
# Semihosting smoke test for linux-user
140
--
30
--
141
2.25.1
31
2.34.1
142
32
143
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
We will reuse this section of arm_deliver_fault for
3
PL011 can be in either of 2 modes depending guest config: FIFO and
4
raising pc alignment faults.
4
single register. The last mode could be viewed as a 1-element-deep FIFO.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
7
depth handling code to isolate calculating current FIFO depth.
8
9
One functional (albeit guest-invisible) side-effect of this change is
10
that previously we would always increment s->read_pos in UARTDR read
11
handler even if FIFO was disabled, now we are limiting read_pos to not
12
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
13
14
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
19
---
10
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
20
include/hw/char/pl011.h | 5 ++++-
11
1 file changed, 28 insertions(+), 17 deletions(-)
21
hw/char/pl011.c | 30 ++++++++++++++++++------------
22
2 files changed, 22 insertions(+), 13 deletions(-)
12
23
13
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
24
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tlb_helper.c
26
--- a/include/hw/char/pl011.h
16
+++ b/target/arm/tlb_helper.c
27
+++ b/include/hw/char/pl011.h
17
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
28
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
18
return syn;
29
/* This shares the same struct (and cast macro) as the base pl011 device */
30
#define TYPE_PL011_LUMINARY "pl011_luminary"
31
32
+/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
33
+#define PL011_FIFO_DEPTH 16
34
+
35
struct PL011State {
36
SysBusDevice parent_obj;
37
38
@@ -XXX,XX +XXX,XX @@ struct PL011State {
39
uint32_t dmacr;
40
uint32_t int_enabled;
41
uint32_t int_level;
42
- uint32_t read_fifo[16];
43
+ uint32_t read_fifo[PL011_FIFO_DEPTH];
44
uint32_t ilpr;
45
uint32_t ibrd;
46
uint32_t fbrd;
47
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/char/pl011.c
50
+++ b/hw/char/pl011.c
51
@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
52
}
19
}
53
}
20
54
21
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
55
+static bool pl011_is_fifo_enabled(PL011State *s)
22
- MMUAccessType access_type,
56
+{
23
- int mmu_idx, ARMMMUFaultInfo *fi)
57
+ return (s->lcr & 0x10) != 0;
24
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
25
+ int target_el, int mmu_idx, uint32_t *ret_fsc)
26
{
27
- CPUARMState *env = &cpu->env;
28
- int target_el;
29
- bool same_el;
30
- uint32_t syn, exc, fsr, fsc;
31
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
32
-
33
- target_el = exception_target_el(env);
34
- if (fi->stage2) {
35
- target_el = 2;
36
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
37
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
38
- env->cp15.hpfar_el2 |= HPFAR_NS;
39
- }
40
- }
41
- same_el = (arm_current_el(env) == target_el);
42
+ uint32_t fsr, fsc;
43
44
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
45
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
46
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
47
fsc = 0x3f;
48
}
49
50
+ *ret_fsc = fsc;
51
+ return fsr;
52
+}
58
+}
53
+
59
+
54
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
60
+static inline unsigned pl011_get_fifo_depth(PL011State *s)
55
+ MMUAccessType access_type,
56
+ int mmu_idx, ARMMMUFaultInfo *fi)
57
+{
61
+{
58
+ CPUARMState *env = &cpu->env;
62
+ /* Note: FIFO depth is expected to be power-of-2 */
59
+ int target_el;
63
+ return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
60
+ bool same_el;
64
+}
61
+ uint32_t syn, exc, fsr, fsc;
62
+
65
+
63
+ target_el = exception_target_el(env);
66
static uint64_t pl011_read(void *opaque, hwaddr offset,
64
+ if (fi->stage2) {
67
unsigned size)
65
+ target_el = 2;
68
{
66
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
69
@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
67
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
70
c = s->read_fifo[s->read_pos];
68
+ env->cp15.hpfar_el2 |= HPFAR_NS;
71
if (s->read_count > 0) {
69
+ }
72
s->read_count--;
70
+ }
73
- if (++s->read_pos == 16)
71
+ same_el = (arm_current_el(env) == target_el);
74
- s->read_pos = 0;
72
+
75
+ s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
73
+ fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
76
}
74
+
77
if (s->read_count == 0) {
75
if (access_type == MMU_INST_FETCH) {
78
s->flags |= PL011_FLAG_RXFE;
76
syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
79
@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
77
exc = EXCP_PREFETCH_ABORT;
80
PL011State *s = (PL011State *)opaque;
81
int r;
82
83
- if (s->lcr & 0x10) {
84
- r = s->read_count < 16;
85
- } else {
86
- r = s->read_count < 1;
87
- }
88
+ r = s->read_count < pl011_get_fifo_depth(s);
89
trace_pl011_can_receive(s->lcr, s->read_count, r);
90
return r;
91
}
92
@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
93
{
94
PL011State *s = (PL011State *)opaque;
95
int slot;
96
+ unsigned pipe_depth;
97
98
- slot = s->read_pos + s->read_count;
99
- if (slot >= 16)
100
- slot -= 16;
101
+ pipe_depth = pl011_get_fifo_depth(s);
102
+ slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
103
s->read_fifo[slot] = value;
104
s->read_count++;
105
s->flags &= ~PL011_FLAG_RXFE;
106
trace_pl011_put_fifo(value, s->read_count);
107
- if (!(s->lcr & 0x10) || s->read_count == 16) {
108
+ if (s->read_count == pipe_depth) {
109
trace_pl011_put_fifo_full();
110
s->flags |= PL011_FLAG_RXFF;
111
}
112
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
113
VMSTATE_UINT32(dmacr, PL011State),
114
VMSTATE_UINT32(int_enabled, PL011State),
115
VMSTATE_UINT32(int_level, PL011State),
116
- VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
117
+ VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
118
VMSTATE_UINT32(ilpr, PL011State),
119
VMSTATE_UINT32(ibrd, PL011State),
120
VMSTATE_UINT32(fbrd, PL011State),
78
--
121
--
79
2.25.1
122
2.34.1
80
123
81
124
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
Misaligned thumb PC is architecturally impossible.
3
Previous change slightly modified the way we handle data writes when
4
Assert is better than proceeding, in case we've missed
4
FIFO is disabled. Previously we kept incrementing read_pos and were
5
something somewhere.
5
storing data at that position, although we only have a
6
single-register-deep FIFO now. Then we changed it to always store data
7
at pos 0.
6
8
7
Expand a comment about aligning the pc in gdbstub.
9
If guest disables FIFO and the proceeds to read data, it will work out
8
Fail an incoming migrate if a thumb pc is misaligned.
10
fine, because we still read from current read_pos before setting it to
11
0.
9
12
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
However, to make code less fragile, introduce a post_load hook for
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
PL011State and move fixup read FIFO state when FIFO is disabled. Since
15
we are introducing a post_load hook, also do some sanity checking on
16
untrusted incoming input state.
17
18
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
19
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
21
---
14
target/arm/gdbstub.c | 9 +++++++--
22
hw/char/pl011.c | 25 +++++++++++++++++++++++++
15
target/arm/machine.c | 10 ++++++++++
23
1 file changed, 25 insertions(+)
16
target/arm/translate.c | 3 +++
17
3 files changed, 20 insertions(+), 2 deletions(-)
18
24
19
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
25
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
20
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/gdbstub.c
27
--- a/hw/char/pl011.c
22
+++ b/target/arm/gdbstub.c
28
+++ b/hw/char/pl011.c
23
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
29
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
24
25
tmp = ldl_p(mem_buf);
26
27
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
28
- cause problems if we ever implement the Jazelle DBX extensions. */
29
+ /*
30
+ * Mask out low bits of PC to workaround gdb bugs.
31
+ * This avoids an assert in thumb_tr_translate_insn, because it is
32
+ * architecturally impossible to misalign the pc.
33
+ * This will probably cause problems if we ever implement the
34
+ * Jazelle DBX extensions.
35
+ */
36
if (n == 15) {
37
tmp &= ~1;
38
}
30
}
39
diff --git a/target/arm/machine.c b/target/arm/machine.c
31
};
40
index XXXXXXX..XXXXXXX 100644
32
41
--- a/target/arm/machine.c
33
+static int pl011_post_load(void *opaque, int version_id)
42
+++ b/target/arm/machine.c
34
+{
43
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
35
+ PL011State* s = opaque;
44
return -1;
45
}
46
}
47
+
36
+
48
+ /*
37
+ /* Sanity-check input state */
49
+ * Misaligned thumb pc is architecturally impossible.
38
+ if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
50
+ * We have an assert in thumb_tr_translate_insn to verify this.
39
+ s->read_count > ARRAY_SIZE(s->read_fifo)) {
51
+ * Fail an incoming migrate to avoid this assert.
52
+ */
53
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
54
+ return -1;
40
+ return -1;
55
+ }
41
+ }
56
+
42
+
57
if (!kvm_enabled()) {
43
+ if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
58
pmu_op_finish(&cpu->env);
44
+ /*
59
}
45
+ * Older versions of PL011 didn't ensure that the single
60
diff --git a/target/arm/translate.c b/target/arm/translate.c
46
+ * character in the FIFO in FIFO-disabled mode is in
61
index XXXXXXX..XXXXXXX 100644
47
+ * element 0 of the array; convert to follow the current
62
--- a/target/arm/translate.c
48
+ * code's assumptions.
63
+++ b/target/arm/translate.c
49
+ */
64
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
50
+ s->read_fifo[0] = s->read_fifo[s->read_pos];
65
uint32_t insn;
51
+ s->read_pos = 0;
66
bool is_16bit;
52
+ }
67
68
+ /* Misaligned thumb PC is architecturally impossible. */
69
+ assert((dc->base.pc_next & 1) == 0);
70
+
53
+
71
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
54
+ return 0;
72
dc->base.pc_next = pc + 2;
55
+}
73
return;
56
+
57
static const VMStateDescription vmstate_pl011 = {
58
.name = "pl011",
59
.version_id = 2,
60
.minimum_version_id = 2,
61
+ .post_load = pl011_post_load,
62
.fields = (VMStateField[]) {
63
VMSTATE_UINT32(readbuff, PL011State),
64
VMSTATE_UINT32(flags, PL011State),
74
--
65
--
75
2.25.1
66
2.34.1
76
77
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
To propagate errors to the caller of the pre_plug callback, use the
3
PL011 currently lacks a reset method. Implement it.
4
object_poperty_set*() functions directly instead of the qdev_prop_set*()
5
helpers.
6
4
7
Suggested-by: Igor Mammedov <imammedo@redhat.com>
5
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
11
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/virt.c | 5 +++--
11
hw/char/pl011.c | 26 +++++++++++++++++++++-----
15
1 file changed, 3 insertions(+), 2 deletions(-)
12
1 file changed, 21 insertions(+), 5 deletions(-)
16
13
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
16
--- a/hw/char/pl011.c
20
+++ b/hw/arm/virt.c
17
+++ b/hw/char/pl011.c
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
18
@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
22
db_start, db_end,
19
s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
23
VIRTIO_IOMMU_RESV_MEM_T_MSI);
20
ClockUpdate);
24
21
25
- qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
22
- s->read_trigger = 1;
26
- qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
23
- s->ifl = 0x12;
27
+ object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
24
- s->cr = 0x300;
28
+ object_property_set_str(OBJECT(dev), "reserved-regions[0]",
25
- s->flags = 0x90;
29
+ resv_prop_str, errp);
26
-
30
g_free(resv_prop_str);
27
s->id = pl011_id_arm;
31
}
28
}
29
30
@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
31
pl011_event, NULL, s, NULL, true);
32
}
33
34
+static void pl011_reset(DeviceState *dev)
35
+{
36
+ PL011State *s = PL011(dev);
37
+
38
+ s->lcr = 0;
39
+ s->rsr = 0;
40
+ s->dmacr = 0;
41
+ s->int_enabled = 0;
42
+ s->int_level = 0;
43
+ s->ilpr = 0;
44
+ s->ibrd = 0;
45
+ s->fbrd = 0;
46
+ s->read_pos = 0;
47
+ s->read_count = 0;
48
+ s->read_trigger = 1;
49
+ s->ifl = 0x12;
50
+ s->cr = 0x300;
51
+ s->flags = 0x90;
52
+}
53
+
54
static void pl011_class_init(ObjectClass *oc, void *data)
55
{
56
DeviceClass *dc = DEVICE_CLASS(oc);
57
58
dc->realize = pl011_realize;
59
+ dc->reset = pl011_reset;
60
dc->vmsd = &vmstate_pl011;
61
device_class_set_props(dc, pl011_properties);
32
}
62
}
33
--
63
--
34
2.25.1
64
2.34.1
35
65
36
66
diff view generated by jsdifflib
1
From: Patrick Venture <venture@google.com>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
The rx_active boolean change to true should always trigger a try_read
3
Current FIFO handling code does not reset RXFE/RXFF flags when guest
4
call that flushes the queue.
4
resets FIFO by writing to UARTLCR register, although internal FIFO state
5
is reset to 0 read count. Actual guest-visible flag update will happen
6
only on next data read or write attempt. As a result of that any guest
7
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
8
FIFO will never see that happen.
5
9
6
Signed-off-by: Patrick Venture <venture@google.com>
10
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20211203221002.1719306-1-venture@google.com
12
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
hw/net/npcm7xx_emc.c | 18 ++++++++----------
15
hw/char/pl011.c | 18 +++++++++++++-----
12
1 file changed, 8 insertions(+), 10 deletions(-)
16
1 file changed, 13 insertions(+), 5 deletions(-)
13
17
14
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
18
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/npcm7xx_emc.c
20
--- a/hw/char/pl011.c
17
+++ b/hw/net/npcm7xx_emc.c
21
+++ b/hw/char/pl011.c
18
@@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
22
@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
19
emc_set_mista(emc, mista_flag);
23
return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
20
}
24
}
21
25
22
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
26
+static inline void pl011_reset_fifo(PL011State *s)
23
+{
27
+{
24
+ emc->rx_active = true;
28
+ s->read_count = 0;
25
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
29
+ s->read_pos = 0;
30
+
31
+ /* Reset FIFO flags */
32
+ s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
33
+ s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
26
+}
34
+}
27
+
35
+
28
static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
36
static uint64_t pl011_read(void *opaque, hwaddr offset,
29
const NPCM7xxEMCTxDesc *tx_desc,
37
unsigned size)
30
uint32_t desc_addr)
38
{
31
@@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
39
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
32
return len;
40
case 11: /* UARTLCR_H */
41
/* Reset the FIFO state on FIFO enable or disable */
42
if ((s->lcr ^ value) & 0x10) {
43
- s->read_count = 0;
44
- s->read_pos = 0;
45
+ pl011_reset_fifo(s);
46
}
47
if ((s->lcr ^ value) & 0x1) {
48
int break_enable = value & 0x1;
49
@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
50
s->ilpr = 0;
51
s->ibrd = 0;
52
s->fbrd = 0;
53
- s->read_pos = 0;
54
- s->read_count = 0;
55
s->read_trigger = 1;
56
s->ifl = 0x12;
57
s->cr = 0x300;
58
- s->flags = 0x90;
59
+ s->flags = 0;
60
+ pl011_reset_fifo(s);
33
}
61
}
34
62
35
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
63
static void pl011_class_init(ObjectClass *oc, void *data)
36
-{
37
- if (emc_can_receive(qemu_get_queue(emc->nic))) {
38
- qemu_flush_queued_packets(qemu_get_queue(emc->nic));
39
- }
40
-}
41
-
42
static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
43
{
44
NPCM7xxEMCState *emc = opaque;
45
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
46
emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
47
}
48
if (value & REG_MCMDR_RXON) {
49
- emc->rx_active = true;
50
+ emc_enable_rx_and_flush(emc);
51
} else {
52
emc_halt_rx(emc, 0);
53
}
54
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
55
break;
56
case REG_RSDR:
57
if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
58
- emc->rx_active = true;
59
- emc_try_receive_next_packet(emc);
60
+ emc_enable_rx_and_flush(emc);
61
}
62
break;
63
case REG_MIIDA:
64
--
64
--
65
2.25.1
65
2.34.1
66
67
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
3
We currently only support GICv2 emulation. To also support GICv3, we will
4
arm_gicv3_common_realize(). Since we want to restrict
4
need to pass a few system registers into their respective handler functions.
5
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
5
6
to a new file. Add this file to the meson 'specific'
6
This patch adds support for HVF to call into the TCG callbacks for GICv3
7
source set, since it needs access to "cpu.h".
7
system register handlers. This is safe because the GICv3 TCG code is generic
8
8
as long as we limit ourselves to EL0 and EL1 - which are the only modes
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
supported by HVF.
10
11
To make sure nobody trips over that, we also annotate callbacks that don't
12
work in HVF mode, such as EL state change hooks.
13
14
With GICv3 support in place, we can run with more than 8 vCPUs.
15
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
17
Message-id: 20230128224459.70676-1-agraf@csgraf.de
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20211115223619.2599282-2-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
20
---
14
hw/intc/arm_gicv3_cpuif.c | 10 +---------
21
hw/intc/arm_gicv3_cpuif.c | 16 +++-
15
hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
22
target/arm/hvf/hvf.c | 151 ++++++++++++++++++++++++++++++++++++
16
hw/intc/meson.build | 1 +
23
target/arm/hvf/trace-events | 2 +
17
3 files changed, 24 insertions(+), 9 deletions(-)
24
3 files changed, 168 insertions(+), 1 deletion(-)
18
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
19
25
20
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
26
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
21
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_cpuif.c
28
--- a/hw/intc/arm_gicv3_cpuif.c
23
+++ b/hw/intc/arm_gicv3_cpuif.c
29
+++ b/hw/intc/arm_gicv3_cpuif.c
24
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@
25
/*
26
- * ARM Generic Interrupt Controller v3
27
+ * ARM Generic Interrupt Controller v3 (emulation)
28
*
29
* Copyright (c) 2016 Linaro Limited
30
* Written by Peter Maydell
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/irq.h"
31
#include "hw/irq.h"
33
#include "cpu.h"
32
#include "cpu.h"
34
33
#include "target/arm/cpregs.h"
35
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
34
+#include "sysemu/tcg.h"
36
-{
35
+#include "sysemu/qtest.h"
37
- ARMCPU *arm_cpu = ARM_CPU(cpu);
36
38
- CPUARMState *env = &arm_cpu->env;
37
/*
39
-
38
* Special case return value from hppvi_index(); must be larger than
40
- env->gicv3state = (void *)s;
39
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
41
-};
40
* which case we'd get the wrong value.
42
-
41
* So instead we define the regs with no ri->opaque info, and
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
42
* get back to the GICv3CPUState from the CPUARMState.
44
{
43
+ *
45
return env->gicv3state;
44
+ * These CP regs callbacks can be called from either TCG or HVF code.
46
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c
45
*/
47
new file mode 100644
46
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
48
index XXXXXXX..XXXXXXX
47
49
--- /dev/null
48
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
50
+++ b/hw/intc/arm_gicv3_cpuif_common.c
49
define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
50
}
51
}
52
- arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
53
+ if (tcg_enabled() || qtest_enabled()) {
54
+ /*
55
+ * We can only trap EL changes with TCG. However the GIC interrupt
56
+ * state only changes on EL changes involving EL2 or EL3, so for
57
+ * the non-TCG case this is OK, as EL2 and EL3 can't exist.
58
+ */
59
+ arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
60
+ } else {
61
+ assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
62
+ assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
63
+ }
64
}
65
}
66
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/hvf/hvf.c
69
+++ b/target/arm/hvf/hvf.c
51
@@ -XXX,XX +XXX,XX @@
70
@@ -XXX,XX +XXX,XX @@
52
+/* SPDX-License-Identifier: GPL-2.0-or-later */
71
#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
53
+/*
72
#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
54
+ * ARM Generic Interrupt Controller v3
73
55
+ *
74
+#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
56
+ * Copyright (c) 2016 Linaro Limited
75
+#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5)
57
+ * Written by Peter Maydell
76
+#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6)
58
+ *
77
+#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7)
59
+ * This code is licensed under the GPL, version 2 or (at your option)
78
+#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0)
60
+ * any later version.
79
+#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1)
61
+ */
80
+#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)
62
+
81
+#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3)
63
+#include "qemu/osdep.h"
82
+#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6)
64
+#include "gicv3_internal.h"
83
+#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3)
65
+#include "cpu.h"
84
+#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3)
66
+
85
+#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
86
+#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1)
87
+#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1)
88
+#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1)
89
+#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)
90
+#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)
91
+#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0)
92
+#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0)
93
+#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6)
94
+#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7)
95
+#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)
96
+#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3)
97
+#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7)
98
+#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5)
99
+#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5)
100
+
101
#define WFX_IS_WFE (1 << 0)
102
103
#define TMR_CTL_ENABLE (1 << 0)
104
@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
105
SYSREG_CRM(reg) < 8;
106
}
107
108
+static uint32_t hvf_reg2cp_reg(uint32_t reg)
109
+{
110
+ return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
111
+ (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
112
+ (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
113
+ (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
114
+ (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
115
+ (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
116
+}
117
+
118
+static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
68
+{
119
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
120
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
121
+ CPUARMState *env = &arm_cpu->env;
71
+
122
+ const ARMCPRegInfo *ri;
72
+ env->gicv3state = (void *)s;
123
+
73
+};
124
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
74
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
125
+ if (ri) {
126
+ if (ri->accessfn) {
127
+ if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
128
+ return false;
129
+ }
130
+ }
131
+ if (ri->type & ARM_CP_CONST) {
132
+ *val = ri->resetvalue;
133
+ } else if (ri->readfn) {
134
+ *val = ri->readfn(env, ri);
135
+ } else {
136
+ *val = CPREG_FIELD64(env, ri);
137
+ }
138
+ trace_hvf_vgic_read(ri->name, *val);
139
+ return true;
140
+ }
141
+
142
+ return false;
143
+}
144
+
145
static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
146
{
147
ARMCPU *arm_cpu = ARM_CPU(cpu);
148
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
149
case SYSREG_OSDLR_EL1:
150
/* Dummy register */
151
break;
152
+ case SYSREG_ICC_AP0R0_EL1:
153
+ case SYSREG_ICC_AP0R1_EL1:
154
+ case SYSREG_ICC_AP0R2_EL1:
155
+ case SYSREG_ICC_AP0R3_EL1:
156
+ case SYSREG_ICC_AP1R0_EL1:
157
+ case SYSREG_ICC_AP1R1_EL1:
158
+ case SYSREG_ICC_AP1R2_EL1:
159
+ case SYSREG_ICC_AP1R3_EL1:
160
+ case SYSREG_ICC_ASGI1R_EL1:
161
+ case SYSREG_ICC_BPR0_EL1:
162
+ case SYSREG_ICC_BPR1_EL1:
163
+ case SYSREG_ICC_DIR_EL1:
164
+ case SYSREG_ICC_EOIR0_EL1:
165
+ case SYSREG_ICC_EOIR1_EL1:
166
+ case SYSREG_ICC_HPPIR0_EL1:
167
+ case SYSREG_ICC_HPPIR1_EL1:
168
+ case SYSREG_ICC_IAR0_EL1:
169
+ case SYSREG_ICC_IAR1_EL1:
170
+ case SYSREG_ICC_IGRPEN0_EL1:
171
+ case SYSREG_ICC_IGRPEN1_EL1:
172
+ case SYSREG_ICC_PMR_EL1:
173
+ case SYSREG_ICC_SGI0R_EL1:
174
+ case SYSREG_ICC_SGI1R_EL1:
175
+ case SYSREG_ICC_SRE_EL1:
176
+ case SYSREG_ICC_CTLR_EL1:
177
+ /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
178
+ if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
179
+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
180
+ }
181
+ break;
182
default:
183
if (is_id_sysreg(reg)) {
184
/* ID system registers read as RES0 */
185
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
186
}
187
}
188
189
+static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
190
+{
191
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
192
+ CPUARMState *env = &arm_cpu->env;
193
+ const ARMCPRegInfo *ri;
194
+
195
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
196
+
197
+ if (ri) {
198
+ if (ri->accessfn) {
199
+ if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
200
+ return false;
201
+ }
202
+ }
203
+ if (ri->writefn) {
204
+ ri->writefn(env, ri, val);
205
+ } else {
206
+ CPREG_FIELD64(env, ri) = val;
207
+ }
208
+
209
+ trace_hvf_vgic_write(ri->name, val);
210
+ return true;
211
+ }
212
+
213
+ return false;
214
+}
215
+
216
static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
217
{
218
ARMCPU *arm_cpu = ARM_CPU(cpu);
219
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
220
case SYSREG_OSDLR_EL1:
221
/* Dummy register */
222
break;
223
+ case SYSREG_ICC_AP0R0_EL1:
224
+ case SYSREG_ICC_AP0R1_EL1:
225
+ case SYSREG_ICC_AP0R2_EL1:
226
+ case SYSREG_ICC_AP0R3_EL1:
227
+ case SYSREG_ICC_AP1R0_EL1:
228
+ case SYSREG_ICC_AP1R1_EL1:
229
+ case SYSREG_ICC_AP1R2_EL1:
230
+ case SYSREG_ICC_AP1R3_EL1:
231
+ case SYSREG_ICC_ASGI1R_EL1:
232
+ case SYSREG_ICC_BPR0_EL1:
233
+ case SYSREG_ICC_BPR1_EL1:
234
+ case SYSREG_ICC_CTLR_EL1:
235
+ case SYSREG_ICC_DIR_EL1:
236
+ case SYSREG_ICC_EOIR0_EL1:
237
+ case SYSREG_ICC_EOIR1_EL1:
238
+ case SYSREG_ICC_HPPIR0_EL1:
239
+ case SYSREG_ICC_HPPIR1_EL1:
240
+ case SYSREG_ICC_IAR0_EL1:
241
+ case SYSREG_ICC_IAR1_EL1:
242
+ case SYSREG_ICC_IGRPEN0_EL1:
243
+ case SYSREG_ICC_IGRPEN1_EL1:
244
+ case SYSREG_ICC_PMR_EL1:
245
+ case SYSREG_ICC_SGI0R_EL1:
246
+ case SYSREG_ICC_SGI1R_EL1:
247
+ case SYSREG_ICC_SRE_EL1:
248
+ /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
249
+ if (!hvf_sysreg_write_cp(cpu, reg, val)) {
250
+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
251
+ }
252
+ break;
253
default:
254
cpu_synchronize_state(cpu);
255
trace_hvf_unhandled_sysreg_write(env->pc, reg,
256
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
75
index XXXXXXX..XXXXXXX 100644
257
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/intc/meson.build
258
--- a/target/arm/hvf/trace-events
77
+++ b/hw/intc/meson.build
259
+++ b/target/arm/hvf/trace-events
78
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
260
@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
79
261
hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
80
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
262
hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
81
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
263
hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
82
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
264
+hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
83
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
265
+hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
84
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
85
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
86
--
266
--
87
2.25.1
267
2.34.1
88
89
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
virtio-iommu is now supported with ACPI VIOT as well as device tree.
3
Up to now, the finalize_gic_version() code open coded what is essentially
4
Remove the restriction that prevents from instantiating a virtio-iommu
4
a support bitmap match between host/emulation environment and desired
5
device under ACPI.
5
target GIC type.
6
6
7
Acked-by: Igor Mammedov <imammedo@redhat.com>
7
This open coding leads to undesirable side effects. For example, a VM with
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
KVM and -smp 10 will automatically choose GICv3 while the same command
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
line with TCG will stay on GICv2 and fail the launch.
10
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
10
11
This patch combines the TCG and KVM matching code paths by making
12
everything a 2 pass process. First, we determine which GIC versions the
13
current environment is able to support, then we go through a single
14
state machine to determine which target GIC mode that means for us.
15
16
After this patch, the only user noticable changes should be consolidated
17
error messages as well as TCG -M virt supporting -smp > 8 automatically.
18
19
Signed-off-by: Alexander Graf <agraf@csgraf.de>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
22
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
23
Message-id: 20221223090107.98888-2-agraf@csgraf.de
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
25
---
13
hw/arm/virt.c | 10 ++--------
26
include/hw/arm/virt.h | 15 ++--
14
hw/virtio/virtio-iommu-pci.c | 12 ++----------
27
hw/arm/virt.c | 198 ++++++++++++++++++++++--------------------
15
2 files changed, 4 insertions(+), 18 deletions(-)
28
2 files changed, 112 insertions(+), 101 deletions(-)
16
29
30
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/arm/virt.h
33
+++ b/include/hw/arm/virt.h
34
@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
35
} VirtMSIControllerType;
36
37
typedef enum VirtGICType {
38
- VIRT_GIC_VERSION_MAX,
39
- VIRT_GIC_VERSION_HOST,
40
- VIRT_GIC_VERSION_2,
41
- VIRT_GIC_VERSION_3,
42
- VIRT_GIC_VERSION_4,
43
+ VIRT_GIC_VERSION_MAX = 0,
44
+ VIRT_GIC_VERSION_HOST = 1,
45
+ /* The concrete GIC values have to match the GIC version number */
46
+ VIRT_GIC_VERSION_2 = 2,
47
+ VIRT_GIC_VERSION_3 = 3,
48
+ VIRT_GIC_VERSION_4 = 4,
49
VIRT_GIC_VERSION_NOSEL,
50
} VirtGICType;
51
52
+#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
53
+#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
54
+#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
55
+
56
struct VirtMachineClass {
57
MachineClass parent;
58
bool disallow_affinity_adjustment;
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
59
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
61
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
62
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
63
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
22
MachineClass *mc = MACHINE_GET_CLASS(machine);
23
24
if (device_is_dynamic_sysbus(mc, dev) ||
25
- (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
26
+ object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
27
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
28
return HOTPLUG_HANDLER(machine);
29
}
64
}
30
- if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
65
}
31
- VirtMachineState *vms = VIRT_MACHINE(machine);
66
67
+static VirtGICType finalize_gic_version_do(const char *accel_name,
68
+ VirtGICType gic_version,
69
+ int gics_supported,
70
+ unsigned int max_cpus)
71
+{
72
+ /* Convert host/max/nosel to GIC version number */
73
+ switch (gic_version) {
74
+ case VIRT_GIC_VERSION_HOST:
75
+ if (!kvm_enabled()) {
76
+ error_report("gic-version=host requires KVM");
77
+ exit(1);
78
+ }
79
+
80
+ /* For KVM, gic-version=host means gic-version=max */
81
+ return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
82
+ gics_supported, max_cpus);
83
+ case VIRT_GIC_VERSION_MAX:
84
+ if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
85
+ gic_version = VIRT_GIC_VERSION_4;
86
+ } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
87
+ gic_version = VIRT_GIC_VERSION_3;
88
+ } else {
89
+ gic_version = VIRT_GIC_VERSION_2;
90
+ }
91
+ break;
92
+ case VIRT_GIC_VERSION_NOSEL:
93
+ if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
94
+ max_cpus <= GIC_NCPU) {
95
+ gic_version = VIRT_GIC_VERSION_2;
96
+ } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
97
+ /*
98
+ * in case the host does not support v2 emulation or
99
+ * the end-user requested more than 8 VCPUs we now default
100
+ * to v3. In any case defaulting to v2 would be broken.
101
+ */
102
+ gic_version = VIRT_GIC_VERSION_3;
103
+ } else if (max_cpus > GIC_NCPU) {
104
+ error_report("%s only supports GICv2 emulation but more than 8 "
105
+ "vcpus are requested", accel_name);
106
+ exit(1);
107
+ }
108
+ break;
109
+ case VIRT_GIC_VERSION_2:
110
+ case VIRT_GIC_VERSION_3:
111
+ case VIRT_GIC_VERSION_4:
112
+ break;
113
+ }
114
+
115
+ /* Check chosen version is effectively supported */
116
+ switch (gic_version) {
117
+ case VIRT_GIC_VERSION_2:
118
+ if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
119
+ error_report("%s does not support GICv2 emulation", accel_name);
120
+ exit(1);
121
+ }
122
+ break;
123
+ case VIRT_GIC_VERSION_3:
124
+ if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
125
+ error_report("%s does not support GICv3 emulation", accel_name);
126
+ exit(1);
127
+ }
128
+ break;
129
+ case VIRT_GIC_VERSION_4:
130
+ if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
131
+ error_report("%s does not support GICv4 emulation, is virtualization=on?",
132
+ accel_name);
133
+ exit(1);
134
+ }
135
+ break;
136
+ default:
137
+ error_report("logic error in finalize_gic_version");
138
+ exit(1);
139
+ break;
140
+ }
141
+
142
+ return gic_version;
143
+}
144
+
145
/*
146
* finalize_gic_version - Determines the final gic_version
147
* according to the gic-version property
148
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
149
*/
150
static void finalize_gic_version(VirtMachineState *vms)
151
{
152
+ const char *accel_name = current_accel_name();
153
unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
154
+ int gics_supported = 0;
155
156
- if (kvm_enabled()) {
157
- int probe_bitmap;
158
+ /* Determine which GIC versions the current environment supports */
159
+ if (kvm_enabled() && kvm_irqchip_in_kernel()) {
160
+ int probe_bitmap = kvm_arm_vgic_probe();
161
162
- if (!kvm_irqchip_in_kernel()) {
163
- switch (vms->gic_version) {
164
- case VIRT_GIC_VERSION_HOST:
165
- warn_report(
166
- "gic-version=host not relevant with kernel-irqchip=off "
167
- "as only userspace GICv2 is supported. Using v2 ...");
168
- return;
169
- case VIRT_GIC_VERSION_MAX:
170
- case VIRT_GIC_VERSION_NOSEL:
171
- vms->gic_version = VIRT_GIC_VERSION_2;
172
- return;
173
- case VIRT_GIC_VERSION_2:
174
- return;
175
- case VIRT_GIC_VERSION_3:
176
- error_report(
177
- "gic-version=3 is not supported with kernel-irqchip=off");
178
- exit(1);
179
- case VIRT_GIC_VERSION_4:
180
- error_report(
181
- "gic-version=4 is not supported with kernel-irqchip=off");
182
- exit(1);
183
- }
184
- }
32
-
185
-
33
- if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
186
- probe_bitmap = kvm_arm_vgic_probe();
34
- return HOTPLUG_HANDLER(machine);
187
if (!probe_bitmap) {
188
error_report("Unable to determine GIC version supported by host");
189
exit(1);
190
}
191
192
- switch (vms->gic_version) {
193
- case VIRT_GIC_VERSION_HOST:
194
- case VIRT_GIC_VERSION_MAX:
195
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
196
- vms->gic_version = VIRT_GIC_VERSION_3;
197
- } else {
198
- vms->gic_version = VIRT_GIC_VERSION_2;
199
- }
200
- return;
201
- case VIRT_GIC_VERSION_NOSEL:
202
- if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
203
- vms->gic_version = VIRT_GIC_VERSION_2;
204
- } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
205
- /*
206
- * in case the host does not support v2 in-kernel emulation or
207
- * the end-user requested more than 8 VCPUs we now default
208
- * to v3. In any case defaulting to v2 would be broken.
209
- */
210
- vms->gic_version = VIRT_GIC_VERSION_3;
211
- } else if (max_cpus > GIC_NCPU) {
212
- error_report("host only supports in-kernel GICv2 emulation "
213
- "but more than 8 vcpus are requested");
214
- exit(1);
215
- }
216
- break;
217
- case VIRT_GIC_VERSION_2:
218
- case VIRT_GIC_VERSION_3:
219
- break;
220
- case VIRT_GIC_VERSION_4:
221
- error_report("gic-version=4 is not supported with KVM");
222
- exit(1);
223
+ if (probe_bitmap & KVM_ARM_VGIC_V2) {
224
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
225
}
226
-
227
- /* Check chosen version is effectively supported by the host */
228
- if (vms->gic_version == VIRT_GIC_VERSION_2 &&
229
- !(probe_bitmap & KVM_ARM_VGIC_V2)) {
230
- error_report("host does not support in-kernel GICv2 emulation");
231
- exit(1);
232
- } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
233
- !(probe_bitmap & KVM_ARM_VGIC_V3)) {
234
- error_report("host does not support in-kernel GICv3 emulation");
235
- exit(1);
236
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
237
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
238
}
239
- return;
240
- }
241
-
242
- /* TCG mode */
243
- switch (vms->gic_version) {
244
- case VIRT_GIC_VERSION_NOSEL:
245
- vms->gic_version = VIRT_GIC_VERSION_2;
246
- break;
247
- case VIRT_GIC_VERSION_MAX:
248
+ } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
249
+ /* KVM w/o kernel irqchip can only deal with GICv2 */
250
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
251
+ accel_name = "KVM with kernel-irqchip=off";
252
+ } else {
253
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
254
if (module_object_class_by_name("arm-gicv3")) {
255
- /* CONFIG_ARM_GICV3_TCG was set */
256
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
257
if (vms->virt) {
258
/* GICv4 only makes sense if CPU has EL2 */
259
- vms->gic_version = VIRT_GIC_VERSION_4;
260
- } else {
261
- vms->gic_version = VIRT_GIC_VERSION_3;
262
+ gics_supported |= VIRT_GIC_VERSION_4_MASK;
263
}
264
- } else {
265
- vms->gic_version = VIRT_GIC_VERSION_2;
266
}
267
- break;
268
- case VIRT_GIC_VERSION_HOST:
269
- error_report("gic-version=host requires KVM");
270
- exit(1);
271
- case VIRT_GIC_VERSION_4:
272
- if (!vms->virt) {
273
- error_report("gic-version=4 requires virtualization enabled");
274
- exit(1);
35
- }
275
- }
36
- }
276
- break;
37
return NULL;
277
- case VIRT_GIC_VERSION_2:
278
- case VIRT_GIC_VERSION_3:
279
- break;
280
}
281
+
282
+ /*
283
+ * Then convert helpers like host/max to concrete GIC versions and ensure
284
+ * the desired version is supported
285
+ */
286
+ vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
287
+ gics_supported, max_cpus);
38
}
288
}
39
289
40
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
290
/*
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/virtio-iommu-pci.c
43
+++ b/hw/virtio/virtio-iommu-pci.c
44
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
45
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
46
47
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
48
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
49
-
50
- error_setg(errp,
51
- "%s machine fails to create iommu-map device tree bindings",
52
- mc->name);
53
- error_append_hint(errp,
54
- "Check your machine implements a hotplug handler "
55
- "for the virtio-iommu-pci device\n");
56
- error_append_hint(errp, "Check the guest is booted without FW or with "
57
- "-no-acpi\n");
58
+ error_setg(errp, "Check your machine implements a hotplug handler "
59
+ "for the virtio-iommu-pci device");
60
return;
61
}
62
for (int i = 0; i < s->nb_reserved_regions; i++) {
63
--
291
--
64
2.25.1
292
2.34.1
65
66
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
We do not support instantiating multiple IOMMUs. Before adding a
3
Let's explicitly list out all accelerators that we support when trying to
4
virtio-iommu, check that no other IOMMU is present. This will detect
4
determine the supported set of GIC versions. KVM was already separate, so
5
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
5
the only missing one is HVF which simply reuses all of TCG's emulation
6
code and thus has the same compatibility matrix.
6
7
7
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
8
Signed-off-by: Alexander Graf <agraf@csgraf.de>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
10
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
11
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20221223090107.98888-3-agraf@csgraf.de
14
[PMM: Added qtest to the list of accelerators]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
16
---
14
hw/arm/virt.c | 5 +++++
17
hw/arm/virt.c | 7 ++++++-
15
1 file changed, 5 insertions(+)
18
1 file changed, 6 insertions(+), 1 deletion(-)
16
19
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
22
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
23
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
24
@@ -XXX,XX +XXX,XX @@
22
hwaddr db_start = 0, db_end = 0;
25
#include "sysemu/numa.h"
23
char *resv_prop_str;
26
#include "sysemu/runstate.h"
24
27
#include "sysemu/tpm.h"
25
+ if (vms->iommu != VIRT_IOMMU_NONE) {
28
+#include "sysemu/tcg.h"
26
+ error_setg(errp, "virt machine does not support multiple IOMMUs");
29
#include "sysemu/kvm.h"
27
+ return;
30
#include "sysemu/hvf.h"
28
+ }
31
+#include "sysemu/qtest.h"
29
+
32
#include "hw/loader.h"
30
switch (vms->msi_controller) {
33
#include "qapi/error.h"
31
case VIRT_MSI_CTRL_NONE:
34
#include "qemu/bitops.h"
32
return;
35
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
36
/* KVM w/o kernel irqchip can only deal with GICv2 */
37
gics_supported |= VIRT_GIC_VERSION_2_MASK;
38
accel_name = "KVM with kernel-irqchip=off";
39
- } else {
40
+ } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
41
gics_supported |= VIRT_GIC_VERSION_2_MASK;
42
if (module_object_class_by_name("arm-gicv3")) {
43
gics_supported |= VIRT_GIC_VERSION_3_MASK;
44
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
45
gics_supported |= VIRT_GIC_VERSION_4_MASK;
46
}
47
}
48
+ } else {
49
+ error_report("Unsupported accelerator, can not determine GIC support");
50
+ exit(1);
51
}
52
53
/*
33
--
54
--
34
2.25.1
55
2.34.1
35
56
36
57
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
The VIOT blob contains the following:
3
Cortex-A76 supports 40bits of address space. sbsa-ref's memory
4
starts above this limit.
4
5
5
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
6
[004h 0004 4] Table Length : 00000058
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
[008h 0008 1] Revision : 00
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
[009h 0009 1] Checksum : 66
9
Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org
9
[00Ah 0010 6] Oem ID : "BOCHS "
10
[010h 0016 8] Oem Table ID : "BXPC "
11
[018h 0024 4] Oem Revision : 00000001
12
[01Ch 0028 4] Asl Compiler ID : "BXPC"
13
[020h 0032 4] Asl Compiler Revision : 00000001
14
15
[024h 0036 2] Node count : 0002
16
[026h 0038 2] Node offset : 0030
17
[028h 0040 8] Reserved : 0000000000000000
18
19
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
20
[031h 0049 1] Reserved : 00
21
[032h 0050 2] Length : 0010
22
23
[034h 0052 2] PCI Segment : 0000
24
[036h 0054 2] PCI BDF number : 0008
25
[038h 0056 8] Reserved : 0000000000000000
26
27
[040h 0064 1] Type : 01 [PCI Range]
28
[041h 0065 1] Reserved : 00
29
[042h 0066 2] Length : 0018
30
31
[044h 0068 4] Endpoint start : 00000000
32
[048h 0072 2] PCI Segment start : 0000
33
[04Ah 0074 2] PCI Segment end : 0000
34
[04Ch 0076 2] PCI BDF start : 0000
35
[04Eh 0078 2] PCI BDF end : 00FF
36
[050h 0080 2] Output node : 0030
37
[052h 0082 6] Reserved : 000000000000
38
39
Acked-by: Ani Sinha <ani@anisinha.ca>
40
Reviewed-by: Eric Auger <eric.auger@redhat.com>
41
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
42
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
---
11
---
45
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
12
hw/arm/sbsa-ref.c | 1 -
46
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
13
1 file changed, 1 deletion(-)
47
2 files changed, 1 deletion(-)
48
14
49
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
50
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
51
--- a/tests/qtest/bios-tables-test-allowed-diff.h
17
--- a/hw/arm/sbsa-ref.c
52
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
18
+++ b/hw/arm/sbsa-ref.c
53
@@ -1,2 +1 @@
19
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
54
/* List of comma-separated changed AML files to ignore */
20
static const char * const valid_cpus[] = {
55
-"tests/data/acpi/virt/VIOT",
21
ARM_CPU_TYPE_NAME("cortex-a57"),
56
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
22
ARM_CPU_TYPE_NAME("cortex-a72"),
57
index XXXXXXX..XXXXXXX 100644
23
- ARM_CPU_TYPE_NAME("cortex-a76"),
58
GIT binary patch
24
ARM_CPU_TYPE_NAME("neoverse-n1"),
59
literal 88
25
ARM_CPU_TYPE_NAME("max"),
60
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
26
};
61
I{D-Rq0Q5fy0RR91
62
63
literal 0
64
HcmV?d00001
65
66
--
27
--
67
2.25.1
28
2.34.1
68
29
69
30
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
2
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
3
them AT S1E1R and AT S1E1W (which are entirely different
4
instructions). Fix the names.
2
5
3
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
6
(This has no guest-visible effect as the names are for debug purposes
4
q35 machine.
7
only.)
5
8
6
Since the test instantiates a virtio device and two PCIe expander
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
bridges, DSDT.viot has more blocks than the base DSDT.
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Fuad Tabba <tabba@google.com>
12
Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org
13
Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org
14
---
15
target/arm/helper.c | 4 ++--
16
1 file changed, 2 insertions(+), 2 deletions(-)
8
17
9
The VIOT table generated for the q35 test is:
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
10
11
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
12
[004h 0004 4] Table Length : 00000070
13
[008h 0008 1] Revision : 00
14
[009h 0009 1] Checksum : 3D
15
[00Ah 0010 6] Oem ID : "BOCHS "
16
[010h 0016 8] Oem Table ID : "BXPC "
17
[018h 0024 4] Oem Revision : 00000001
18
[01Ch 0028 4] Asl Compiler ID : "BXPC"
19
[020h 0032 4] Asl Compiler Revision : 00000001
20
21
[024h 0036 2] Node count : 0003
22
[026h 0038 2] Node offset : 0030
23
[028h 0040 8] Reserved : 0000000000000000
24
25
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
26
[031h 0049 1] Reserved : 00
27
[032h 0050 2] Length : 0010
28
29
[034h 0052 2] PCI Segment : 0000
30
[036h 0054 2] PCI BDF number : 0010
31
[038h 0056 8] Reserved : 0000000000000000
32
33
[040h 0064 1] Type : 01 [PCI Range]
34
[041h 0065 1] Reserved : 00
35
[042h 0066 2] Length : 0018
36
37
[044h 0068 4] Endpoint start : 00003000
38
[048h 0072 2] PCI Segment start : 0000
39
[04Ah 0074 2] PCI Segment end : 0000
40
[04Ch 0076 2] PCI BDF start : 3000
41
[04Eh 0078 2] PCI BDF end : 30FF
42
[050h 0080 2] Output node : 0030
43
[052h 0082 6] Reserved : 000000000000
44
45
[058h 0088 1] Type : 01 [PCI Range]
46
[059h 0089 1] Reserved : 00
47
[05Ah 0090 2] Length : 0018
48
49
[05Ch 0092 4] Endpoint start : 00001000
50
[060h 0096 2] PCI Segment start : 0000
51
[062h 0098 2] PCI Segment end : 0000
52
[064h 0100 2] PCI BDF start : 1000
53
[066h 0102 2] PCI BDF end : 10FF
54
[068h 0104 2] Output node : 0030
55
[06Ah 0106 6] Reserved : 000000000000
56
57
And the DSDT diff is:
58
59
@@ -XXX,XX +XXX,XX @@
60
*
61
* Disassembling to symbolic ASL+ operators
62
*
63
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
64
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
65
*
66
* Original Table Header:
67
* Signature "DSDT"
68
- * Length 0x00002061 (8289)
69
+ * Length 0x000024B6 (9398)
70
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
71
- * Checksum 0xFA
72
+ * Checksum 0xA7
73
* OEM ID "BOCHS "
74
* OEM Table ID "BXPC "
75
* OEM Revision 0x00000001 (1)
76
@@ -XXX,XX +XXX,XX @@
77
}
78
}
79
80
+ Scope (\_SB)
81
+ {
82
+ Device (PC30)
83
+ {
84
+ Name (_UID, 0x30) // _UID: Unique ID
85
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
86
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
87
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
88
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
89
+ {
90
+ CreateDWordField (Arg3, Zero, CDW1)
91
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
92
+ {
93
+ CreateDWordField (Arg3, 0x04, CDW2)
94
+ CreateDWordField (Arg3, 0x08, CDW3)
95
+ Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
96
+ Local0 &= 0x1F
97
+ If ((Arg1 != One))
98
+ {
99
+ CDW1 |= 0x08
100
+ }
101
+
102
+ If ((CDW3 != Local0))
103
+ {
104
+ CDW1 |= 0x10
105
+ }
106
+
107
+ CDW3 = Local0
108
+ }
109
+ Else
110
+ {
111
+ CDW1 |= 0x04
112
+ }
113
+
114
+ Return (Arg3)
115
+ }
116
+
117
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
118
+ {
119
+ Local0 = Package (0x80){}
120
+ Local1 = Zero
121
+ While ((Local1 < 0x80))
122
+ {
123
+ Local2 = (Local1 >> 0x02)
124
+ Local3 = ((Local1 + Local2) & 0x03)
125
+ If ((Local3 == Zero))
126
+ {
127
+ Local4 = Package (0x04)
128
+ {
129
+ Zero,
130
+ Zero,
131
+ LNKD,
132
+ Zero
133
+ }
134
+ }
135
+
136
+ If ((Local3 == One))
137
+ {
138
+ Local4 = Package (0x04)
139
+ {
140
+ Zero,
141
+ Zero,
142
+ LNKA,
143
+ Zero
144
+ }
145
+ }
146
+
147
+ If ((Local3 == 0x02))
148
+ {
149
+ Local4 = Package (0x04)
150
+ {
151
+ Zero,
152
+ Zero,
153
+ LNKB,
154
+ Zero
155
+ }
156
+ }
157
+
158
+ If ((Local3 == 0x03))
159
+ {
160
+ Local4 = Package (0x04)
161
+ {
162
+ Zero,
163
+ Zero,
164
+ LNKC,
165
+ Zero
166
+ }
167
+ }
168
+
169
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
170
+ Local4 [One] = (Local1 & 0x03)
171
+ Local0 [Local1] = Local4
172
+ Local1++
173
+ }
174
+
175
+ Return (Local0)
176
+ }
177
+
178
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
179
+ {
180
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
181
+ 0x0000, // Granularity
182
+ 0x0030, // Range Minimum
183
+ 0x0030, // Range Maximum
184
+ 0x0000, // Translation Offset
185
+ 0x0001, // Length
186
+ ,, )
187
+ })
188
+ }
189
+ }
190
+
191
+ Scope (\_SB)
192
+ {
193
+ Device (PC20)
194
+ {
195
+ Name (_UID, 0x20) // _UID: Unique ID
196
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
197
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
198
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
199
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
200
+ {
201
+ CreateDWordField (Arg3, Zero, CDW1)
202
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
203
+ {
204
+ CreateDWordField (Arg3, 0x04, CDW2)
205
+ CreateDWordField (Arg3, 0x08, CDW3)
206
+ Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
207
+ Local0 &= 0x1F
208
+ If ((Arg1 != One))
209
+ {
210
+ CDW1 |= 0x08
211
+ }
212
+
213
+ If ((CDW3 != Local0))
214
+ {
215
+ CDW1 |= 0x10
216
+ }
217
+
218
+ CDW3 = Local0
219
+ }
220
+ Else
221
+ {
222
+ CDW1 |= 0x04
223
+ }
224
+
225
+ Return (Arg3)
226
+ }
227
+
228
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
229
+ {
230
+ Local0 = Package (0x80){}
231
+ Local1 = Zero
232
+ While ((Local1 < 0x80))
233
+ {
234
+ Local2 = (Local1 >> 0x02)
235
+ Local3 = ((Local1 + Local2) & 0x03)
236
+ If ((Local3 == Zero))
237
+ {
238
+ Local4 = Package (0x04)
239
+ {
240
+ Zero,
241
+ Zero,
242
+ LNKD,
243
+ Zero
244
+ }
245
+ }
246
+
247
+ If ((Local3 == One))
248
+ {
249
+ Local4 = Package (0x04)
250
+ {
251
+ Zero,
252
+ Zero,
253
+ LNKA,
254
+ Zero
255
+ }
256
+ }
257
+
258
+ If ((Local3 == 0x02))
259
+ {
260
+ Local4 = Package (0x04)
261
+ {
262
+ Zero,
263
+ Zero,
264
+ LNKB,
265
+ Zero
266
+ }
267
+ }
268
+
269
+ If ((Local3 == 0x03))
270
+ {
271
+ Local4 = Package (0x04)
272
+ {
273
+ Zero,
274
+ Zero,
275
+ LNKC,
276
+ Zero
277
+ }
278
+ }
279
+
280
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
281
+ Local4 [One] = (Local1 & 0x03)
282
+ Local0 [Local1] = Local4
283
+ Local1++
284
+ }
285
+
286
+ Return (Local0)
287
+ }
288
+
289
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
290
+ {
291
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
292
+ 0x0000, // Granularity
293
+ 0x0020, // Range Minimum
294
+ 0x0020, // Range Maximum
295
+ 0x0000, // Translation Offset
296
+ 0x0001, // Length
297
+ ,, )
298
+ })
299
+ }
300
+ }
301
+
302
+ Scope (\_SB)
303
+ {
304
+ Device (PC10)
305
+ {
306
+ Name (_UID, 0x10) // _UID: Unique ID
307
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
308
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
309
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
310
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
311
+ {
312
+ CreateDWordField (Arg3, Zero, CDW1)
313
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
314
+ {
315
+ CreateDWordField (Arg3, 0x04, CDW2)
316
+ CreateDWordField (Arg3, 0x08, CDW3)
317
+ Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
318
+ Local0 &= 0x1F
319
+ If ((Arg1 != One))
320
+ {
321
+ CDW1 |= 0x08
322
+ }
323
+
324
+ If ((CDW3 != Local0))
325
+ {
326
+ CDW1 |= 0x10
327
+ }
328
+
329
+ CDW3 = Local0
330
+ }
331
+ Else
332
+ {
333
+ CDW1 |= 0x04
334
+ }
335
+
336
+ Return (Arg3)
337
+ }
338
+
339
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
340
+ {
341
+ Local0 = Package (0x80){}
342
+ Local1 = Zero
343
+ While ((Local1 < 0x80))
344
+ {
345
+ Local2 = (Local1 >> 0x02)
346
+ Local3 = ((Local1 + Local2) & 0x03)
347
+ If ((Local3 == Zero))
348
+ {
349
+ Local4 = Package (0x04)
350
+ {
351
+ Zero,
352
+ Zero,
353
+ LNKD,
354
+ Zero
355
+ }
356
+ }
357
+
358
+ If ((Local3 == One))
359
+ {
360
+ Local4 = Package (0x04)
361
+ {
362
+ Zero,
363
+ Zero,
364
+ LNKA,
365
+ Zero
366
+ }
367
+ }
368
+
369
+ If ((Local3 == 0x02))
370
+ {
371
+ Local4 = Package (0x04)
372
+ {
373
+ Zero,
374
+ Zero,
375
+ LNKB,
376
+ Zero
377
+ }
378
+ }
379
+
380
+ If ((Local3 == 0x03))
381
+ {
382
+ Local4 = Package (0x04)
383
+ {
384
+ Zero,
385
+ Zero,
386
+ LNKC,
387
+ Zero
388
+ }
389
+ }
390
+
391
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
392
+ Local4 [One] = (Local1 & 0x03)
393
+ Local0 [Local1] = Local4
394
+ Local1++
395
+ }
396
+
397
+ Return (Local0)
398
+ }
399
+
400
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
401
+ {
402
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
403
+ 0x0000, // Granularity
404
+ 0x0010, // Range Minimum
405
+ 0x0010, // Range Maximum
406
+ 0x0000, // Translation Offset
407
+ 0x0001, // Length
408
+ ,, )
409
+ })
410
+ }
411
+ }
412
+
413
Scope (\_SB.PCI0)
414
{
415
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
416
@@ -XXX,XX +XXX,XX @@
417
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
418
0x0000, // Granularity
419
0x0000, // Range Minimum
420
- 0x00FF, // Range Maximum
421
+ 0x000F, // Range Maximum
422
0x0000, // Translation Offset
423
- 0x0100, // Length
424
+ 0x0010, // Length
425
,, )
426
IO (Decode16,
427
0x0CF8, // Range Minimum
428
@@ -XXX,XX +XXX,XX @@
429
}
430
}
431
432
+ Device (S10)
433
+ {
434
+ Name (_ADR, 0x00020000) // _ADR: Address
435
+ }
436
+
437
+ Device (S18)
438
+ {
439
+ Name (_ADR, 0x00030000) // _ADR: Address
440
+ }
441
+
442
+ Device (S20)
443
+ {
444
+ Name (_ADR, 0x00040000) // _ADR: Address
445
+ }
446
+
447
+ Device (S28)
448
+ {
449
+ Name (_ADR, 0x00050000) // _ADR: Address
450
+ }
451
+
452
Method (PCNT, 0, NotSerialized)
453
{
454
}
455
456
Reviewed-by: Eric Auger <eric.auger@redhat.com>
457
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
458
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
459
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
460
---
461
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
462
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
463
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
464
3 files changed, 2 deletions(-)
465
466
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
467
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
468
--- a/tests/qtest/bios-tables-test-allowed-diff.h
20
--- a/target/arm/helper.c
469
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
21
+++ b/target/arm/helper.c
470
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
471
/* List of comma-separated changed AML files to ignore */
23
472
"tests/data/acpi/virt/VIOT",
24
#ifndef CONFIG_USER_ONLY
473
-"tests/data/acpi/q35/DSDT.viot",
25
static const ARMCPRegInfo ats1e1_reginfo[] = {
474
-"tests/data/acpi/q35/VIOT.viot",
26
- { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
475
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
27
+ { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
476
index XXXXXXX..XXXXXXX 100644
28
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
477
GIT binary patch
29
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
478
literal 9398
30
.writefn = ats_write64 },
479
zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_
31
- { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
480
z5(9Az1F`}niVsB-)<KW7p`g9Br(A2Gm-gmc1N78GFS!;)e2V(MnH_0{q<{#yMgn&C
32
+ { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
481
zn|*J-d9yqFhO_H6z19~`FlPL*u<DkZ*}|)JH;X@mF-FI<cPg<fti9tEN*yB^i5czN
33
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
482
zNq&q?!OZ;BE3B7{KWzJ-`Tn~f`9?Qj8~2^N8{Oc8J%57{==w%rS#;nOCp*nTr@iZ1
34
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
483
zb+?i;JLQUJ=O0?8*>S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS
35
.writefn = ats_write64 },
484
zeLZ*n<<Bm^n}6`jfBx#u8&(W}1?)}iF9o#mZ~E2+zwdn7yK3AbIzKnxpZ>JRPm3~#
485
z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW%
486
z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^
487
z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-<Qe4p)GQ=)AtYx2VcwdLVAEXEjG
488
z^Mj|UHPqkj-LsWuzQem1>F3atdZn=zv3$#RmZzSHN+6-yyU#8cJb=YDilX&sl}vNm
489
znkgAR^O<3kj4if>{ly5fwRfMWuC5=lrlvKPX~i#654Cp}R_d*JS$9laZ$ra6)<ns8
490
zFZy28G%xP(nit&F>LDi%G<tIc=TY=gl$jSD&Uv!Yat~XR46h%rI$!}a%!|xG7u8Zn
491
zeY8_|n=K>xz_v_W8VX$W-Fg-qFWcT}7MCyz{%%{ia7hZ>Law-k6NOr}VI&_48U=2l
492
zwqDKFE8eTwwozDdms#e?x?5a|v>&JF;2_v0L~z5n%BYU^52<*cWuD4|GYUm@1+?))
493
zte^45>Rz)t*<T5V#={r>@t@{%?^i#W{i=HAZ*Dc9y59Va-+#P!jrGs;u38a{fLr`N
494
zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-<
495
z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%<lrgAHSpd^DRf-*}_#Ly0mB!LSfVgWcQ
496
z&T$@~G9)JI=hz5m0vkrel+Xy{Oh7pkAu-V!j*W7rY(bO}Q$nMH2`FbGB&N)QaV4<4
497
zo)~9JXiP9=;}NPl<C@MmXG&;XFlFNrsyfFsonxFSp<}vEgsRSQP3O3#b6nSnP}ON_
498
zI!#Tdsp~|j>ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^=
499
zt?NXn>YUJYPG~wObe#xQos*i*NloXZt`niEb4t@WrRki~bs|)CI+{*L)9L6s5vn><
500
zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w}
501
zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t
502
zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3
503
zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`&
504
zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V
505
zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq|
506
zK*>M_l;<P^MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO<
507
zGhv_#lnhirIg<<&q0|Wj6<E%MfhtfkPyyvkGEjt4Ck#|zITHq|K*>M_lrzad5lWpf
508
zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb}
509
zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOc<yFB?A>u&LjgxD0RX>1(q{mpbC@>R6seC
510
z3>2Z%2?G^a&V+#~P%=;f<xDbAgi<FARA4z12C6{GKn0XD$v_cGoiI>=<xCi;0wn_#
511
zP|hR+MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4
512
z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0
513
zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T
514
zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4<vU_xO+1efmLq
515
zZ;W>N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp
516
zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a
517
zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD
518
zGDYiA3<$Tu<JnHL(KPOChi#zrR32t83}naR$+ym4P_h?z_5#|cW-nw$XD_sOtE62l
519
zrD3@*)NVyiklt0&yF9%+klsBey&I<Y2E<!f(E8TuJte)z(|ZHyy<^gQVfx}=`q&B5
520
z7nSryp1wGczIaUfVwiq$Fn#<4=@*ssi#+|}K>EdF(l3VTOM~ghPLRH&q%ZOGrGfON
521
zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|*<gA{q?Zp5Oe-+l#rmyYmKozi9y=P>
522
zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s
523
zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q
524
z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ<p0O%rZ?JzIY3-QdmZ
525
zzs|n>`a5r3e|z)wcUaqS>nqFQ-8x}eCF4u`OWUxqst-@1rSmUs%WmKP5e0dcb?e2N
526
z;Z|x*!);VwF|Yuhqs^khqOM!@u*jY!WYldISF(V6`BoNd&6Qfk3>X#SuD^7J>p_D=
527
zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|<i!a=ELS@)%a{^NIH3SDuN<R~sah1km#P
528
zU@?*f%<rG=4W1wgfi;C?_n|W@%lm$&8YfvNOJodIg&IcIpIJQRHr<+ej11GQ6)&eF
529
z2Lam*jIH}#y0>KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4
530
z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a<?}h$zLoj}4;PP!+(O{@!a1y-hoAhF_7!z+6
531
zslpAmNtYbjHrw-~#SPVk_FUf>-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG
532
z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi
533
zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr
534
zx_b#v9Xv-Y><Wb%?S^0Xe&<)bbKl_=Z|3C$tf|F<bYzE*mfHB;uC)`q-?buaBe?l?
535
zcLTpK*k<49Z32`K?|nSBMFqxTK^_IE-li2fEGdK~(ZdoKBl6ab4a;Hler#`xvEXJG
536
zb?<E%EZExfX>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a
537
zyVen1i{1BKd%~`D7|m$;U0a<I*3I7%^N%N%lGYdU_GS!gaR8T$NA@GzFi~z`l7hdl
538
zarZy6590|88pi(1zq;V(>38zM0sT&<zX;R5$1w3;`_JMG`;&I&0Y23DMx1%@(w(R9
539
z4M$j;D5J+Gy%fijRQsctzFKf&cv|BAz#YLq3CZJWDdtL4u1u1|mkdcUp7|sxJC+?Y
540
z_@@s`v3j}Q7*z>6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0
541
zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROf<M%qC6lgVdpFt4<-|uM
542
z=#rl_b1#YjSIl6Toj2z_hOZcKupkdE(LozC(fN=FY(x|sk)ym|;Rq2E1xJWD%Z!ol
543
Gu>S+TT-130
544
545
literal 0
546
HcmV?d00001
547
548
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
549
index XXXXXXX..XXXXXXX 100644
550
GIT binary patch
551
literal 112
552
zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj
553
Q0Zb)W9Hva*zW_`e0M!8s0RR91
554
555
literal 0
556
HcmV?d00001
557
558
--
36
--
559
2.25.1
37
2.34.1
560
561
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
The AArch32 ATS12NSO* address translation operations are supposed to
2
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
3
can only happen if EL3 is AArch64). We implement this, but we got
4
the syndrome value wrong: like other traps to EL2 or EL3 on an
5
AArch32 cpreg access, they should report the 0x3 syndrome, not the
6
0x0 'uncategorized' syndrome. This is clear in the access pseudocode
7
for these instructions.
2
8
3
Create empty data files and allow updates for the upcoming VIOT tests.
9
Fix the syndrome value for these operations by correcting the
10
returned value from the ats_access() function.
4
11
5
Acked-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
10
---
17
---
11
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
18
target/arm/helper.c | 4 ++--
12
tests/data/acpi/q35/DSDT.viot | 0
19
1 file changed, 2 insertions(+), 2 deletions(-)
13
tests/data/acpi/q35/VIOT.viot | 0
14
tests/data/acpi/virt/VIOT | 0
15
4 files changed, 3 insertions(+)
16
create mode 100644 tests/data/acpi/q35/DSDT.viot
17
create mode 100644 tests/data/acpi/q35/VIOT.viot
18
create mode 100644 tests/data/acpi/virt/VIOT
19
20
20
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/tests/qtest/bios-tables-test-allowed-diff.h
23
--- a/target/arm/helper.c
23
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
24
+++ b/target/arm/helper.c
24
@@ -1 +1,4 @@
25
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
25
/* List of comma-separated changed AML files to ignore */
26
if (arm_current_el(env) == 1) {
26
+"tests/data/acpi/virt/VIOT",
27
if (arm_is_secure_below_el3(env)) {
27
+"tests/data/acpi/q35/DSDT.viot",
28
if (env->cp15.scr_el3 & SCR_EEL2) {
28
+"tests/data/acpi/q35/VIOT.viot",
29
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
29
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
30
+ return CP_ACCESS_TRAP_EL2;
30
new file mode 100644
31
}
31
index XXXXXXX..XXXXXXX
32
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
32
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
33
+ return CP_ACCESS_TRAP_EL3;
33
new file mode 100644
34
}
34
index XXXXXXX..XXXXXXX
35
return CP_ACCESS_TRAP_UNCATEGORIZED;
35
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
36
}
36
new file mode 100644
37
index XXXXXXX..XXXXXXX
38
--
37
--
39
2.25.1
38
2.34.1
40
41
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
3
the ats_access() function, but doing so was incorrect (a bug fixed in
4
a previous commit). There aren't any cases where we want an access
5
function to be able to request a trap to EL2 or EL3 with a zero
6
syndrome value, so remove these enum values.
2
7
3
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
8
As well as cleaning up dead code, the motivation here is that
4
table.
9
we'd like to implement fine-grained-trap handling in
10
helper_access_check_cp_reg(). Although the fine-grained traps
11
to EL2 are always lower priority than trap-to-same-EL and
12
higher priority than trap-to-EL3, they are in the middle of
13
various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
14
must always for us have the same syndrome (ie that an access
15
function will return CP_ACCESS_TRAP_EL2 and there is no other
16
kind of trap-to-EL2 enum value) means we don't have to try
17
to choose which of the two syndrome values to report if the
18
access would trap to EL2 both for the fine-grained-trap and
19
because the access function requires it.
5
20
6
Acked-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Tested-by: Fuad Tabba <tabba@google.com>
24
Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org
25
Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
11
---
26
---
12
hw/arm/virt-acpi-build.c | 7 +++++++
27
target/arm/cpregs.h | 4 ++--
13
hw/arm/Kconfig | 1 +
28
target/arm/op_helper.c | 2 ++
14
2 files changed, 8 insertions(+)
29
2 files changed, 4 insertions(+), 2 deletions(-)
15
30
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
31
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
17
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
33
--- a/target/arm/cpregs.h
19
+++ b/hw/arm/virt-acpi-build.c
34
+++ b/target/arm/cpregs.h
20
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
21
#include "kvm_arm.h"
36
* Access fails and results in an exception syndrome 0x0 ("uncategorized").
22
#include "migration/vmstate.h"
37
* Note that this is not a catch-all case -- the set of cases which may
23
#include "hw/acpi/ghes.h"
38
* result in this failure is specifically defined by the architecture.
24
+#include "hw/acpi/viot.h"
39
+ * This trap is always to the usual target EL, never directly to a
25
40
+ * specified target EL.
26
#define ARM_SPI_BASE 32
41
*/
27
42
CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
28
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
43
- CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
29
}
44
- CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
30
#endif
45
} CPAccessResult;
31
46
32
+ if (vms->iommu == VIRT_IOMMU_VIRTIO) {
47
typedef struct ARMCPRegInfo ARMCPRegInfo;
33
+ acpi_add_table(table_offsets, tables_blob);
48
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
34
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
35
+ vms->oem_id, vms->oem_table_id);
36
+ }
37
+
38
/* XSDT is pointed to by RSDP */
39
xsdt = tables_blob->len;
40
build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
41
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
42
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/Kconfig
50
--- a/target/arm/op_helper.c
44
+++ b/hw/arm/Kconfig
51
+++ b/target/arm/op_helper.c
45
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
52
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
46
select DIMM
53
case CP_ACCESS_TRAP:
47
select ACPI_HW_REDUCED
54
break;
48
select ACPI_APEI
55
case CP_ACCESS_TRAP_UNCATEGORIZED:
49
+ select ACPI_VIOT
56
+ /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
50
57
+ assert((res & CP_ACCESS_EL_MASK) == 0);
51
config CHEETAH
58
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
52
bool
59
arm_cpreg_in_idspace(ri)) {
60
/*
53
--
61
--
54
2.25.1
62
2.34.1
55
56
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Rearrange the code in do_coproc_insn() so that we calculate the
2
syndrome value for a potential trap early; we're about to add a
3
second check that wants this value earlier than where it is currently
4
determined.
2
5
3
Create arm_check_ss_active and arm_check_kernelpage.
6
(Specifically, a trap to EL2 because of HSTR_EL2 should take
7
priority over an UNDEF to EL1, even when the UNDEF is because
8
the register does not exist at all or because its ri->access
9
bits non-configurably fail the access. So the check we put in
10
for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
11
going to have to be done before the check "is the ARMCPRegInfo
12
pointer NULL".)
4
13
5
Reverse the order of the tests. While it doesn't matter in practice,
14
This commit is just code motion; the change to HSTR_EL2
6
because only user-only has a kernel page and user-only never sets
15
handling that will use the 'syndrome' variable is in a
7
ss_active, ss_active has priority over execution exceptions and it
16
subsequent commit.
8
is best to keep them in the proper order.
9
17
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Tested-by: Fuad Tabba <tabba@google.com>
21
Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org
22
Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org
13
---
23
---
14
target/arm/translate.c | 10 +++++++---
24
target/arm/translate.c | 83 +++++++++++++++++++++---------------------
15
1 file changed, 7 insertions(+), 3 deletions(-)
25
1 file changed, 41 insertions(+), 42 deletions(-)
16
26
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
27
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
29
--- a/target/arm/translate.c
20
+++ b/target/arm/translate.c
30
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
31
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
22
dc->insn_start = tcg_last_op();
32
const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
23
}
33
TCGv_ptr tcg_ri = NULL;
24
34
bool need_exit_tb;
25
-static bool arm_pre_translate_insn(DisasContext *dc)
35
+ uint32_t syndrome;
26
+static bool arm_check_kernelpage(DisasContext *dc)
36
+
27
{
37
+ /*
28
#ifdef CONFIG_USER_ONLY
38
+ * Note that since we are an implementation which takes an
29
/* Intercept jump to the magic kernel page. */
39
+ * exception on a trapped conditional instruction only if the
30
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
40
+ * instruction passes its condition code check, we can take
31
return true;
41
+ * advantage of the clause in the ARM ARM that allows us to set
32
}
42
+ * the COND field in the instruction to 0xE in all cases.
33
#endif
43
+ * We could fish the actual condition out of the insn (ARM)
34
+ return false;
44
+ * or the condexec bits (Thumb) but it isn't necessary.
35
+}
45
+ */
36
46
+ switch (cpnum) {
37
+static bool arm_check_ss_active(DisasContext *dc)
47
+ case 14:
38
+{
48
+ if (is64) {
39
if (dc->ss_active && !dc->pstate_ss) {
49
+ syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
40
/* Singlestep state is Active-pending.
50
+ isread, false);
41
* If we're in this state at the start of a TB then either
51
+ } else {
42
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
52
+ syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
43
uint32_t pc = dc->base.pc_next;
53
+ rt, isread, false);
44
unsigned int insn;
54
+ }
45
55
+ break;
46
- if (arm_pre_translate_insn(dc)) {
56
+ case 15:
47
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
57
+ if (is64) {
48
dc->base.pc_next = pc + 4;
58
+ syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
49
return;
59
+ isread, false);
50
}
60
+ } else {
51
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
61
+ syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
52
uint32_t insn;
62
+ rt, isread, false);
53
bool is_16bit;
63
+ }
54
64
+ break;
55
- if (arm_pre_translate_insn(dc)) {
65
+ default:
56
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
66
+ /*
57
dc->base.pc_next = pc + 2;
67
+ * ARMv8 defines that only coprocessors 14 and 15 exist,
58
return;
68
+ * so this can only happen if this is an ARMv7 or earlier CPU,
59
}
69
+ * in which case the syndrome information won't actually be
70
+ * guest visible.
71
+ */
72
+ assert(!arm_dc_feature(s, ARM_FEATURE_V8));
73
+ syndrome = syn_uncategorized();
74
+ break;
75
+ }
76
77
if (!ri) {
78
/*
79
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
80
* Note that on XScale all cp0..c13 registers do an access check
81
* call in order to handle c15_cpar.
82
*/
83
- uint32_t syndrome;
84
-
85
- /*
86
- * Note that since we are an implementation which takes an
87
- * exception on a trapped conditional instruction only if the
88
- * instruction passes its condition code check, we can take
89
- * advantage of the clause in the ARM ARM that allows us to set
90
- * the COND field in the instruction to 0xE in all cases.
91
- * We could fish the actual condition out of the insn (ARM)
92
- * or the condexec bits (Thumb) but it isn't necessary.
93
- */
94
- switch (cpnum) {
95
- case 14:
96
- if (is64) {
97
- syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
98
- isread, false);
99
- } else {
100
- syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
101
- rt, isread, false);
102
- }
103
- break;
104
- case 15:
105
- if (is64) {
106
- syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
107
- isread, false);
108
- } else {
109
- syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
110
- rt, isread, false);
111
- }
112
- break;
113
- default:
114
- /*
115
- * ARMv8 defines that only coprocessors 14 and 15 exist,
116
- * so this can only happen if this is an ARMv7 or earlier CPU,
117
- * in which case the syndrome information won't actually be
118
- * guest visible.
119
- */
120
- assert(!arm_dc_feature(s, ARM_FEATURE_V8));
121
- syndrome = syn_uncategorized();
122
- break;
123
- }
124
-
125
gen_set_condexec(s);
126
gen_update_pc(s, 0);
127
tcg_ri = tcg_temp_new_ptr();
60
--
128
--
61
2.25.1
129
2.34.1
62
63
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The HSTR_EL2 register has a collection of trap bits which allow
2
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
3
registers. The specification of these bits is that when the bit is
4
set we should trap
5
* EL1 accesses
6
* EL0 accesses, if the access is not UNDEFINED when the
7
trap bit is 0
2
8
3
While trying to debug a GIC ITS failure I saw some guest errors that
9
In other words, all UNDEF traps from EL0 to EL1 take precedence over
4
had poor formatting as well as leaving me confused as to what failed.
10
the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind
5
As most of the checks aren't possible without a valid dte split that
11
of trap-to-EL1 is the UNDEF.)
6
check apart and then check the other conditions in steps. This avoids
7
us relying on undefined data.
8
12
9
I still get a failure with the current kvm-unit-tests but at least I
13
Our implementation doesn't quite get this right -- we check for traps
10
know (partially) why now:
14
in the order:
15
* no such register
16
* ARMCPRegInfo::access bits
17
* HSTR_EL2 trap bits
18
* ARMCPRegInfo::accessfn
11
19
12
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
20
So UNDEFs that happen because of the access bits or because the
13
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
21
register doesn't exist at all correctly take priority over the
14
ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
22
HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
15
INT dev_id=2 event_id=20
23
accessfn we are incorrectly always taking the HSTR_EL2 trap. There
16
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
24
aren't many of these, but one example is the PMCR; if you look at the
17
PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
25
access pseudocode for this register you can see that UNDEFs taken
18
SUMMARY: 6 tests, 1 unexpected failures
26
because of the value of PMUSERENR.EN are checked before the HSTR_EL2
27
bit.
19
28
20
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
29
Rearrange helper_access_check_cp_reg() so that we always call the
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
accessfn, and use its return value if it indicates that the access
22
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
31
traps to EL0 rather than continuing to do the HSTR_EL2 check.
23
Cc: Shashi Mallela <shashi.mallela@linaro.org>
32
24
Cc: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
35
Tested-by: Fuad Tabba <tabba@google.com>
36
Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org
37
Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org
26
---
38
---
27
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
39
target/arm/op_helper.c | 21 ++++++++++++++++-----
28
1 file changed, 27 insertions(+), 12 deletions(-)
40
1 file changed, 16 insertions(+), 5 deletions(-)
29
41
30
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
42
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
31
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_its.c
44
--- a/target/arm/op_helper.c
33
+++ b/hw/intc/arm_gicv3_its.c
45
+++ b/target/arm/op_helper.c
34
@@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
46
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
35
if (res != MEMTX_OK) {
47
goto fail;
36
return result;
48
}
49
50
+ if (ri->accessfn) {
51
+ res = ri->accessfn(env, ri, isread);
52
+ }
53
+
54
/*
55
- * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
56
- * to sysregs non accessible at EL0 to have UNDEF-ed already.
57
+ * If the access function indicates a trap from EL0 to EL1 then
58
+ * that always takes priority over the HSTR_EL2 trap. (If it indicates
59
+ * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates
60
+ * a trap to EL2, then the syndrome is the same either way so we don't
61
+ * care whether technically the architecture says that HSTR_EL2 trap or
62
+ * the other trap takes priority. So we take the "check HSTR_EL2" path
63
+ * for all of those cases.)
64
*/
65
+ if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
66
+ arm_current_el(env) == 0) {
67
+ goto fail;
68
+ }
69
+
70
if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
71
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
72
uint32_t mask = 1 << ri->crn;
73
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
37
}
74
}
38
+ } else {
39
+ qemu_log_mask(LOG_GUEST_ERROR,
40
+ "%s: invalid command attributes: "
41
+ "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
42
+ __func__, dte, devid, res);
43
+ return result;
44
}
75
}
45
76
46
- if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
77
- if (ri->accessfn) {
47
- !cte_valid || (eventid > max_eventid)) {
78
- res = ri->accessfn(env, ri, isread);
48
+
79
- }
49
+ /*
80
if (likely(res == CP_ACCESS_OK)) {
50
+ * In this implementation, in case of guest errors we ignore the
81
return ri;
51
+ * command and move onto the next command in the queue.
82
}
52
+ */
53
+ if (devid > s->dt.maxids.max_devids) {
54
qemu_log_mask(LOG_GUEST_ERROR,
55
- "%s: invalid command attributes "
56
- "devid %d or eventid %d or invalid dte %d or"
57
- "invalid cte %d or invalid ite %d\n",
58
- __func__, devid, eventid, dte_valid, cte_valid,
59
- ite_valid);
60
- /*
61
- * in this implementation, in case of error
62
- * we ignore this command and move onto the next
63
- * command in the queue
64
- */
65
+ "%s: invalid command attributes: devid %d>%d",
66
+ __func__, devid, s->dt.maxids.max_devids);
67
+
68
+ } else if (!dte_valid || !ite_valid || !cte_valid) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "%s: invalid command attributes: "
71
+ "dte: %s, ite: %s, cte: %s\n",
72
+ __func__,
73
+ dte_valid ? "valid" : "invalid",
74
+ ite_valid ? "valid" : "invalid",
75
+ cte_valid ? "valid" : "invalid");
76
+ } else if (eventid > max_eventid) {
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "%s: invalid command attributes: eventid %d > %d\n",
79
+ __func__, eventid, max_eventid);
80
} else {
81
/*
82
* Current implementation only supports rdbase == procnum
83
--
83
--
84
2.25.1
84
2.34.1
85
86
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The semantics of HSTR_EL2 require that it traps cpreg accesses
2
to EL2 for:
3
* EL1 accesses
4
* EL0 accesses, if the access is not UNDEFINED when the
5
trap bit is 0
2
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
9
HSTR_EL2 traps from EL0 are priority 15.)
10
11
However, we don't get this right for EL1 accesses which UNDEF because
12
the register doesn't exist at all or because its ri->access bits
13
non-configurably forbid the access. At EL1, check for the HSTR_EL2
14
trap early, before either of these UNDEF reasons.
15
16
We have to retain the HSTR_EL2 check in access_check_cp_reg(),
17
because at EL0 any kind of UNDEF-to-EL1 (including "no such
18
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
19
takes precedence over the trap to EL2. But we only need to do that
20
check for EL0 now.
21
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Tested-by: Fuad Tabba <tabba@google.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
26
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
6
---
27
---
7
target/arm/translate.c | 16 ++++++++--------
28
target/arm/op_helper.c | 6 +++++-
8
1 file changed, 8 insertions(+), 8 deletions(-)
29
target/arm/translate.c | 28 +++++++++++++++++++++++++++-
30
2 files changed, 32 insertions(+), 2 deletions(-)
9
31
32
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/op_helper.c
35
+++ b/target/arm/op_helper.c
36
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
37
goto fail;
38
}
39
40
- if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
41
+ /*
42
+ * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
43
+ * we only need to check here for traps from EL0.
44
+ */
45
+ if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
46
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
47
uint32_t mask = 1 << ri->crn;
48
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
49
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate.c
51
--- a/target/arm/translate.c
13
+++ b/target/arm/translate.c
52
+++ b/target/arm/translate.c
14
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
53
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
15
{
54
break;
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
55
}
17
CPUARMState *env = cpu->env_ptr;
56
18
+ uint32_t pc = dc->base.pc_next;
57
+ if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
19
uint32_t insn;
58
+ /*
20
bool is_16bit;
59
+ * At EL1, check for a HSTR_EL2 trap, which must take precedence
21
60
+ * over the UNDEF for "no such register" or the UNDEF for "access
22
if (arm_pre_translate_insn(dc)) {
61
+ * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
23
- dc->base.pc_next += 2;
62
+ * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
24
+ dc->base.pc_next = pc + 2;
63
+ * access_check_cp_reg(), after the checks for whether the access
64
+ * configurably trapped to EL1.
65
+ */
66
+ uint32_t maskbit = is64 ? crm : crn;
67
+
68
+ if (maskbit != 4 && maskbit != 14) {
69
+ /* T4 and T14 are RES0 so never cause traps */
70
+ TCGv_i32 t;
71
+ DisasLabel over = gen_disas_label(s);
72
+
73
+ t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
74
+ tcg_gen_andi_i32(t, t, 1u << maskbit);
75
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
76
+ tcg_temp_free_i32(t);
77
+
78
+ gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
79
+ set_disas_label(s, over);
80
+ }
81
+ }
82
+
83
if (!ri) {
84
/*
85
* Unknown register; this might be a guest error or a QEMU
86
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
25
return;
87
return;
26
}
88
}
27
89
28
- dc->pc_curr = dc->base.pc_next;
90
- if (s->hstr_active || ri->accessfn ||
29
- insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
91
+ if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
30
+ dc->pc_curr = pc;
92
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
31
+ insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
93
/*
32
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
94
* Emit code to perform further access permissions checks at
33
- dc->base.pc_next += 2;
34
+ pc += 2;
35
if (!is_16bit) {
36
- uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
37
- dc->sctlr_b);
38
-
39
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
40
insn = insn << 16 | insn2;
41
- dc->base.pc_next += 2;
42
+ pc += 2;
43
}
44
+ dc->base.pc_next = pc;
45
dc->insn = insn;
46
47
if (dc->pstate_il) {
48
--
95
--
49
2.25.1
96
2.34.1
50
51
diff view generated by jsdifflib
1
The calculation of the length of TLB range invalidate operations
1
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
2
in tlbi_aa64_range_get_length() is incorrect in two ways:
2
enabled in the current security state. We weren't checking for this,
3
* the NUM field is 5 bits, but we read only 4 bits
3
which meant that if the guest set up the HSTR_EL2 register we would
4
* we miscalculate the page_shift value, because of an
4
incorrectly trap even for accesses from Secure EL0 and EL1.
5
off-by-one error:
6
TG 0b00 is invalid
7
TG 0b01 is 4K granule size == 4096 == 2^12
8
TG 0b10 is 16K granule size == 16384 == 2^14
9
TG 0b11 is 64K granule size == 65536 == 2^16
10
so page_shift should be (TG - 1) * 2 + 12
11
5
12
Thanks to the bug report submitter Cha HyunSoo for identifying
6
Add the missing checks. (Other places where we look at HSTR_EL2
13
both these errors.
7
for the not-in-v8A bits TTEE and TJDBX are already checking that
8
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
14
9
15
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Tested-by: Fuad Tabba <tabba@google.com>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
21
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
14
Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
22
---
15
---
23
target/arm/helper.c | 6 +++---
16
target/arm/helper.c | 2 +-
24
1 file changed, 3 insertions(+), 3 deletions(-)
17
target/arm/op_helper.c | 1 +
18
2 files changed, 2 insertions(+), 1 deletion(-)
25
19
26
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
27
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/helper.c
22
--- a/target/arm/helper.c
29
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper.c
30
@@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
24
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
31
uint64_t exponent;
25
DP_TBFLAG_A32(flags, VFPEN, 1);
32
uint64_t length;
33
34
- num = extract64(value, 39, 4);
35
+ num = extract64(value, 39, 5);
36
scale = extract64(value, 44, 2);
37
page_size_granule = extract64(value, 46, 2);
38
39
- page_shift = page_size_granule * 2 + 12;
40
-
41
if (page_size_granule == 0) {
42
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
43
page_size_granule);
44
return 0;
45
}
26
}
46
27
47
+ page_shift = (page_size_granule - 1) * 2 + 12;
28
- if (el < 2 && env->cp15.hstr_el2 &&
48
+
29
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
49
exponent = (5 * scale) + 1;
30
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
50
length = (num + 1) << (exponent + page_shift);
31
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
32
}
33
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/op_helper.c
36
+++ b/target/arm/op_helper.c
37
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
38
* we only need to check here for traps from EL0.
39
*/
40
if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
41
+ arm_is_el2_enabled(env) &&
42
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
43
uint32_t mask = 1 << ri->crn;
51
44
52
--
45
--
53
2.25.1
46
2.34.1
54
55
diff view generated by jsdifflib
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
Define the system registers which are provided by the
2
2
FEAT_FGT fine-grained trap architectural feature:
3
Add two test cases for VIOT, one on the q35 machine and the other on
3
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
4
virt. To test complex topologies the q35 test has two PCIe buses that
4
5
bypass the IOMMU (and are therefore not described by VIOT), and two
5
All these registers are a set of bit fields, where each bit is set
6
buses that are translated by virtio-iommu.
6
for a trap and clear to not trap on a particular system register
7
7
access. The R and W register pairs are for system registers,
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
allowing trapping to be done separately for reads and writes; the I
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
9
register is for system instructions where trapping is on instruction
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
execution.
11
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
11
12
The data storage in the CPU state struct is arranged as a set of
13
arrays rather than separate fields so that when we're looking up the
14
bits for a system register access we can just index into the array
15
rather than having to use a switch to select a named struct member.
16
The later FEAT_FGT2 will add extra elements to these arrays.
17
18
The field definitions for the new registers are in cpregs.h because
19
in practice the code that needs them is code that also needs
20
the cpregs information; cpu.h is included in a lot more files.
21
We're also going to add some FGT-specific definitions to cpregs.h
22
in the next commit.
23
24
We do not implement HAFGRTR_EL2, because we don't implement
25
FEAT_AMUv1.
26
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Tested-by: Fuad Tabba <tabba@google.com>
30
Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org
31
Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
13
---
32
---
14
tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
33
target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 38 insertions(+)
34
target/arm/cpu.h | 15 +++
16
35
target/arm/helper.c | 40 +++++++
17
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
36
3 files changed, 340 insertions(+)
37
38
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
18
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/qtest/bios-tables-test.c
40
--- a/target/arm/cpregs.h
20
+++ b/tests/qtest/bios-tables-test.c
41
+++ b/target/arm/cpregs.h
21
@@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void)
42
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
22
free_test_data(&data);
43
CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
44
} CPAccessResult;
45
46
+/* Indexes into fgt_read[] */
47
+#define FGTREG_HFGRTR 0
48
+#define FGTREG_HDFGRTR 1
49
+/* Indexes into fgt_write[] */
50
+#define FGTREG_HFGWTR 0
51
+#define FGTREG_HDFGWTR 1
52
+/* Indexes into fgt_exec[] */
53
+#define FGTREG_HFGITR 0
54
+
55
+FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
56
+FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
57
+FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
58
+FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
59
+FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
60
+FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
61
+FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
62
+FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
63
+FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
64
+FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
65
+FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
66
+FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
67
+FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
68
+FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
69
+FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
70
+FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
71
+FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
72
+FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
73
+FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
74
+FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
75
+FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
76
+FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
77
+FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
78
+FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
79
+FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
80
+FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
81
+FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
82
+FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
83
+FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
84
+FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
85
+FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
86
+FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
87
+FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
88
+FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
89
+FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
90
+FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
91
+FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
92
+FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
93
+FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
94
+FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
95
+FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
96
+FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
97
+FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
98
+FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
99
+FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
100
+FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
101
+FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
102
+FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
103
+FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
104
+FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
105
+FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
106
+/* 51-53: RES0 */
107
+FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
108
+FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
109
+/* 56-63: RES0 */
110
+
111
+/* These match HFGRTR but bits for RO registers are RES0 */
112
+FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
113
+FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
114
+FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
115
+FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
116
+FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
117
+FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
118
+FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
119
+FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
120
+FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
121
+FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
122
+FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
123
+FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
124
+FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
125
+FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
126
+FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
127
+FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
128
+FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
129
+FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
130
+FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
131
+FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
132
+FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
133
+FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
134
+FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
135
+FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
136
+FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
137
+FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
138
+FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
139
+FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
140
+FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
141
+FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
142
+FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
143
+FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
144
+FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
145
+FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
146
+FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
147
+FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
148
+FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
149
+FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
150
+FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
151
+FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
152
+
153
+FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
154
+FIELD(HFGITR_EL2, ICIALLU, 1, 1)
155
+FIELD(HFGITR_EL2, ICIVAU, 2, 1)
156
+FIELD(HFGITR_EL2, DCIVAC, 3, 1)
157
+FIELD(HFGITR_EL2, DCISW, 4, 1)
158
+FIELD(HFGITR_EL2, DCCSW, 5, 1)
159
+FIELD(HFGITR_EL2, DCCISW, 6, 1)
160
+FIELD(HFGITR_EL2, DCCVAU, 7, 1)
161
+FIELD(HFGITR_EL2, DCCVAP, 8, 1)
162
+FIELD(HFGITR_EL2, DCCVADP, 9, 1)
163
+FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
164
+FIELD(HFGITR_EL2, DCZVA, 11, 1)
165
+FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
166
+FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
167
+FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
168
+FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
169
+FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
170
+FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
171
+FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
172
+FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
173
+FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
174
+FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
175
+FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
176
+FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
177
+FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
178
+FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
179
+FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
180
+FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
181
+FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
182
+FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
183
+FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
184
+FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
185
+FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
186
+FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
187
+FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
188
+FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
189
+FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
190
+FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
191
+FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
192
+FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
193
+FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
194
+FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
195
+FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
196
+FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
197
+FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
198
+FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
199
+FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
200
+FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
201
+FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
202
+FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
203
+FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
204
+FIELD(HFGITR_EL2, ERET, 51, 1)
205
+FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
206
+FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
207
+FIELD(HFGITR_EL2, DCCVAC, 54, 1)
208
+FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
209
+FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
210
+
211
+FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
212
+FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
213
+FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
214
+FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
215
+FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
216
+FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
217
+FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
218
+FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
219
+/* 8: RES0: OSLAR_EL1 is WO */
220
+FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
221
+FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
222
+FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
223
+FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
224
+FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
225
+FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
226
+FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
227
+FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
228
+FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
229
+FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
230
+FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
231
+/* 20: RES0: PMSWINC_EL0 is WO */
232
+/* 21: RES0: PMCR_EL0 is WO */
233
+FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
234
+FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
235
+FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
236
+FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
237
+FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
238
+FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
239
+FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
240
+FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
241
+FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
242
+FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
243
+FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
244
+FIELD(HDFGRTR_EL2, TRC, 33, 1)
245
+FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
246
+FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
247
+FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
248
+FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
249
+/* 38, 39: RES0 */
250
+FIELD(HDFGRTR_EL2, TRCID, 40, 1)
251
+FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
252
+/* 42: RES0: TRCOSLAR is WO */
253
+FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
254
+FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
255
+FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
256
+FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
257
+FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
258
+FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
259
+/* 49: RES0: TRFCR_EL1 is WO */
260
+FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
261
+FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
262
+FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
263
+FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
264
+FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
265
+FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
266
+FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
267
+FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
268
+FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
269
+FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
270
+FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
271
+FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
272
+FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
273
+FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
274
+
275
+/*
276
+ * These match HDFGRTR_EL2, but bits for RO registers are RES0.
277
+ * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
278
+ */
279
+FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
280
+FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
281
+FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
282
+FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
283
+FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
284
+FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
285
+FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
286
+FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
287
+FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
288
+FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
289
+FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
290
+FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
291
+FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
292
+FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
293
+FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
294
+FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
295
+FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
296
+FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
297
+FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
298
+FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
299
+FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
300
+FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
301
+FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
302
+FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
303
+FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
304
+FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
305
+FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
306
+FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
307
+FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
308
+FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
309
+FIELD(HDFGWTR_EL2, TRC, 33, 1)
310
+FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
311
+FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
312
+FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
313
+FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
314
+FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
315
+FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
316
+FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
317
+FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
318
+FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
319
+FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
320
+FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
321
+FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
322
+FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
323
+FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
324
+FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
325
+FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
326
+FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
327
+FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
328
+FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
329
+FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
330
+
331
typedef struct ARMCPRegInfo ARMCPRegInfo;
332
333
/*
334
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
335
index XXXXXXX..XXXXXXX 100644
336
--- a/target/arm/cpu.h
337
+++ b/target/arm/cpu.h
338
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
339
uint64_t disr_el1;
340
uint64_t vdisr_el2;
341
uint64_t vsesr_el2;
342
+
343
+ /*
344
+ * Fine-Grained Trap registers. We store these as arrays so the
345
+ * access checking code doesn't have to manually select
346
+ * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
347
+ * FEAT_FGT2 will add more elements to these arrays.
348
+ */
349
+ uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
350
+ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
351
+ uint64_t fgt_exec[1]; /* HFGITR */
352
} cp15;
353
354
struct {
355
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
356
return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
23
}
357
}
24
358
25
+static void test_acpi_q35_viot(void)
359
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
26
+{
360
+{
27
+ test_data data = {
361
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
28
+ .machine = MACHINE_Q35,
29
+ .variant = ".viot",
30
+ };
31
+
32
+ /*
33
+ * To keep things interesting, two buses bypass the IOMMU.
34
+ * VIOT should only describes the other two buses.
35
+ */
36
+ test_acpi_one("-machine default_bus_bypass_iommu=on "
37
+ "-device virtio-iommu-pci "
38
+ "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
39
+ "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
40
+ "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
41
+ &data);
42
+ free_test_data(&data);
43
+}
362
+}
44
+
363
+
45
+static void test_acpi_virt_viot(void)
364
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
365
{
366
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
367
diff --git a/target/arm/helper.c b/target/arm/helper.c
368
index XXXXXXX..XXXXXXX 100644
369
--- a/target/arm/helper.c
370
+++ b/target/arm/helper.c
371
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
372
if (cpu_isar_feature(aa64_hcx, cpu)) {
373
valid_mask |= SCR_HXEN;
374
}
375
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
376
+ valid_mask |= SCR_FGTEN;
377
+ }
378
} else {
379
valid_mask &= ~(SCR_RW | SCR_ST);
380
if (cpu_isar_feature(aa32_ras, cpu)) {
381
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
382
.access = PL3_RW,
383
.fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
384
};
385
+
386
+static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
387
+ bool isread)
46
+{
388
+{
47
+ test_data data = {
389
+ if (arm_current_el(env) == 2 &&
48
+ .machine = "virt",
390
+ arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
49
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
391
+ return CP_ACCESS_TRAP_EL3;
50
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
392
+ }
51
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
393
+ return CP_ACCESS_OK;
52
+ .ram_start = 0x40000000ULL,
53
+ .scan_len = 128ULL * 1024 * 1024,
54
+ };
55
+
56
+ test_acpi_one("-cpu cortex-a57 "
57
+ "-device virtio-iommu-pci", &data);
58
+ free_test_data(&data);
59
+}
394
+}
60
+
395
+
61
static void test_oem_fields(test_data *data)
396
+static const ARMCPRegInfo fgt_reginfo[] = {
62
{
397
+ { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
63
int i;
398
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
64
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
399
+ .access = PL2_RW, .accessfn = access_fgt,
65
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
400
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
66
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
401
+ { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
67
}
402
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
68
+ qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
403
+ .access = PL2_RW, .accessfn = access_fgt,
69
} else if (strcmp(arch, "aarch64") == 0) {
404
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
70
if (has_tcg) {
405
+ { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
71
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
406
+ .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
72
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
407
+ .access = PL2_RW, .accessfn = access_fgt,
73
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
408
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
74
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
409
+ { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
75
qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
410
+ .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
76
+ qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
411
+ .access = PL2_RW, .accessfn = access_fgt,
77
}
412
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
413
+ { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
414
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
415
+ .access = PL2_RW, .accessfn = access_fgt,
416
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
417
+};
418
#endif /* TARGET_AARCH64 */
419
420
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
421
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
422
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
423
define_arm_cp_regs(cpu, scxtnum_reginfo);
78
}
424
}
79
ret = g_test_run();
425
+
426
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
427
+ define_arm_cp_regs(cpu, fgt_reginfo);
428
+ }
429
#endif
430
431
if (cpu_isar_feature(any_predinv, cpu)) {
80
--
432
--
81
2.25.1
433
2.34.1
82
83
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the machinery for fine-grained traps on normal sysregs.
2
2
Any sysreg with a fine-grained trap will set the new field to
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
indicate which FGT register bit it should trap on.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
5
FGT traps only happen when an AArch64 EL2 enables them for
6
an AArch64 EL1. They therefore are only relevant for AArch32
7
cpregs when the cpreg can be accessed from EL0. The logic
8
in access_check_cp_reg() will check this, so it is safe to
9
add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.
10
11
The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
12
which can be used to specify the FGT bit, eg
13
.fgt = FGT_AFSR0_EL1
14
(We assume that there is no bit name duplication across the FGT
15
registers, for brevity's sake.)
16
17
Subsequent commits will add the .fgt fields to the relevant register
18
definitions and define the FGT_nnn values for them.
19
20
Note that some of the FGT traps are for instructions that we don't
21
handle via the cpregs mechanisms (mostly these are instruction traps).
22
Those we will have to handle separately.
23
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Tested-by: Fuad Tabba <tabba@google.com>
27
Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
28
Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
6
---
29
---
7
target/arm/translate-a64.c | 7 ++++---
30
target/arm/cpregs.h | 72 ++++++++++++++++++++++++++++++++++++++
8
1 file changed, 4 insertions(+), 3 deletions(-)
31
target/arm/cpu.h | 1 +
9
32
target/arm/internals.h | 20 +++++++++++
33
target/arm/translate.h | 2 ++
34
target/arm/helper.c | 9 +++++
35
target/arm/op_helper.c | 30 ++++++++++++++++
36
target/arm/translate-a64.c | 3 +-
37
target/arm/translate.c | 2 ++
38
8 files changed, 138 insertions(+), 1 deletion(-)
39
40
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpregs.h
43
+++ b/target/arm/cpregs.h
44
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
45
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
46
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
47
48
+/* Which fine-grained trap bit register to check, if any */
49
+FIELD(FGT, TYPE, 10, 3)
50
+FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
51
+FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
52
+FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
53
+
54
+/*
55
+ * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
56
+ * fields. We assume for brevity's sake that there are no duplicated
57
+ * bit names across the various FGT registers.
58
+ */
59
+#define DO_BIT(REG, BITNAME) \
60
+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
61
+
62
+/* Some bits have reversed sense, so 0 means trap and 1 means not */
63
+#define DO_REV_BIT(REG, BITNAME) \
64
+ FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
65
+
66
+typedef enum FGTBit {
67
+ /*
68
+ * These bits tell us which register arrays to use:
69
+ * if FGT_R is set then reads are checked against fgt_read[];
70
+ * if FGT_W is set then writes are checked against fgt_write[];
71
+ * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
72
+ *
73
+ * For almost all bits in the R/W register pairs, the bit exists in
74
+ * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
75
+ * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
76
+ * for a WO register. There are unfortunately a couple of exceptions
77
+ * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
78
+ * the FGT system only allows trapping of writes, not reads.
79
+ *
80
+ * Note that we arrange these bits so that a 0 FGTBit means "no trap".
81
+ */
82
+ FGT_R = 1 << R_FGT_TYPE_SHIFT,
83
+ FGT_W = 2 << R_FGT_TYPE_SHIFT,
84
+ FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
85
+ FGT_RW = FGT_R | FGT_W,
86
+ /* Bit to identify whether trap bit is reversed sense */
87
+ FGT_REV = R_FGT_REV_MASK,
88
+
89
+ /*
90
+ * If a bit exists in HFGRTR/HDFGRTR then either the register being
91
+ * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
92
+ * want to trap for both reads and writes or else it's harmless to mark
93
+ * it as trap-on-writes.
94
+ * If a bit exists only in HFGWTR/HDFGWTR then either the register being
95
+ * trapped is WO, or else it is one of the two oddball special cases
96
+ * which are RW but have only a write trap. We mark these as only
97
+ * FGT_W so we get the right behaviour for those special cases.
98
+ * (If a bit was added in future that provided only a read trap for an
99
+ * RW register we'd need to do something special to get the FGT_R bit
100
+ * only. But this seems unlikely to happen.)
101
+ *
102
+ * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
103
+ * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
104
+ */
105
+ FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
106
+ FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
107
+ FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
108
+ FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
109
+ FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
110
+} FGTBit;
111
+
112
+#undef DO_BIT
113
+#undef DO_REV_BIT
114
+
115
typedef struct ARMCPRegInfo ARMCPRegInfo;
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
119
CPAccessRights access;
120
/* Security state: ARM_CP_SECSTATE_* bits/values */
121
CPSecureState secure;
122
+ /*
123
+ * Which fine-grained trap register bit to check, if any. This
124
+ * value encodes both the trap register and bit within it.
125
+ */
126
+ FGTBit fgt;
127
/*
128
* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
129
* this register was defined: can be used to hand data through to the
130
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/arm/cpu.h
133
+++ b/target/arm/cpu.h
134
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
135
/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
136
FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
137
FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
138
+FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
139
140
/*
141
* Bit usage when in AArch32 state, both A- and M-profile.
142
diff --git a/target/arm/internals.h b/target/arm/internals.h
143
index XXXXXXX..XXXXXXX 100644
144
--- a/target/arm/internals.h
145
+++ b/target/arm/internals.h
146
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
147
((1 << (1 - 1)) | (1 << (2 - 1)) | \
148
(1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
149
150
+/*
151
+ * Return true if it is possible to take a fine-grained-trap to EL2.
152
+ */
153
+static inline bool arm_fgt_active(CPUARMState *env, int el)
154
+{
155
+ /*
156
+ * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
157
+ * that can affect EL0, but it is harmless to do the test also for
158
+ * traps on registers that are only accessible at EL1 because if the test
159
+ * returns true then we can't be executing at EL1 anyway.
160
+ * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
161
+ * traps from AArch32 only happen for the EL0 is AArch32 case.
162
+ */
163
+ return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
164
+ el < 2 && arm_is_el2_enabled(env) &&
165
+ arm_el_is_aa64(env, 1) &&
166
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
167
+ (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
168
+}
169
+
170
#endif
171
diff --git a/target/arm/translate.h b/target/arm/translate.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/target/arm/translate.h
174
+++ b/target/arm/translate.h
175
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
176
bool is_nonstreaming;
177
/* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
178
bool mve_no_pred;
179
+ /* True if fine-grained traps are active */
180
+ bool fgt_active;
181
/*
182
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
183
* < 0, set by the current instruction.
184
diff --git a/target/arm/helper.c b/target/arm/helper.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/target/arm/helper.c
187
+++ b/target/arm/helper.c
188
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
189
if (arm_singlestep_active(env)) {
190
DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
191
}
192
+
193
return flags;
194
}
195
196
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
197
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
198
}
199
200
+ if (arm_fgt_active(env, el)) {
201
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
202
+ }
203
+
204
if (env->uncached_cpsr & CPSR_IL) {
205
DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
206
}
207
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
208
DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
209
}
210
211
+ if (arm_fgt_active(env, el)) {
212
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
213
+ }
214
+
215
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
216
/*
217
* Set MTE_ACTIVE if any access may be Checked, and leave clear
218
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
219
index XXXXXXX..XXXXXXX 100644
220
--- a/target/arm/op_helper.c
221
+++ b/target/arm/op_helper.c
222
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
223
}
224
}
225
226
+ /*
227
+ * Fine-grained traps also are lower priority than undef-to-EL1,
228
+ * higher priority than trap-to-EL3, and we don't care about priority
229
+ * order with other EL2 traps because the syndrome value is the same.
230
+ */
231
+ if (arm_fgt_active(env, arm_current_el(env))) {
232
+ uint64_t trapword = 0;
233
+ unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
234
+ unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
235
+ bool rev = FIELD_EX32(ri->fgt, FGT, REV);
236
+ bool trapbit;
237
+
238
+ if (ri->fgt & FGT_EXEC) {
239
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
240
+ trapword = env->cp15.fgt_exec[idx];
241
+ } else if (isread && (ri->fgt & FGT_R)) {
242
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
243
+ trapword = env->cp15.fgt_read[idx];
244
+ } else if (!isread && (ri->fgt & FGT_W)) {
245
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
246
+ trapword = env->cp15.fgt_write[idx];
247
+ }
248
+
249
+ trapbit = extract64(trapword, bitpos, 1);
250
+ if (trapbit != rev) {
251
+ res = CP_ACCESS_TRAP_EL2;
252
+ goto fail;
253
+ }
254
+ }
255
+
256
if (likely(res == CP_ACCESS_OK)) {
257
return ri;
258
}
10
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
259
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
11
index XXXXXXX..XXXXXXX 100644
260
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate-a64.c
261
--- a/target/arm/translate-a64.c
13
+++ b/target/arm/translate-a64.c
262
+++ b/target/arm/translate-a64.c
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
263
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
15
{
16
DisasContext *s = container_of(dcbase, DisasContext, base);
17
CPUARMState *env = cpu->env_ptr;
18
+ uint64_t pc = s->base.pc_next;
19
uint32_t insn;
20
21
if (s->ss_active && !s->pstate_ss) {
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
23
return;
264
return;
24
}
265
}
25
266
26
- s->pc_curr = s->base.pc_next;
267
- if (ri->accessfn) {
27
- insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
268
+ if (ri->accessfn || (ri->fgt && s->fgt_active)) {
28
+ s->pc_curr = pc;
269
/* Emit code to perform further access permissions checks at
29
+ insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
270
* runtime; this may result in an exception.
30
s->insn = insn;
271
*/
31
- s->base.pc_next += 4;
272
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
32
+ s->base.pc_next = pc + 4;
273
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
33
274
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
34
s->fp_access_checked = false;
275
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
35
s->sve_access_checked = false;
276
+ dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
277
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
278
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
279
dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
280
diff --git a/target/arm/translate.c b/target/arm/translate.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/target/arm/translate.c
283
+++ b/target/arm/translate.c
284
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
285
}
286
287
if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
288
+ (ri->fgt && s->fgt_active) ||
289
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
290
/*
291
* Emit code to perform further access permissions checks at
292
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
293
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
294
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
295
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
296
+ dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
297
298
if (arm_feature(env, ARM_FEATURE_M)) {
299
dc->vfp_enabled = 1;
36
--
300
--
37
2.25.1
301
2.34.1
38
39
diff view generated by jsdifflib
1
A lot of C files in hw/arm include qemu-common.h when they don't
1
Mark up the sysreg definitions for the registers trapped
2
need anything from it. Drop the include lines.
2
by HFGRTR/HFGWTR bits 0..11.
3
4
omap1.c, pxa2xx.c and strongarm.c retain the include because they
5
use it for the prototype of qemu_get_timedate().
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Fuad Tabba <tabba@google.com>
10
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org
11
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
8
Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
12
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
13
---
9
---
14
hw/arm/boot.c | 1 -
10
target/arm/cpregs.h | 14 ++++++++++++++
15
hw/arm/digic_boards.c | 1 -
11
target/arm/helper.c | 17 +++++++++++++++++
16
hw/arm/highbank.c | 1 -
12
2 files changed, 31 insertions(+)
17
hw/arm/npcm7xx_boards.c | 1 -
18
hw/arm/sbsa-ref.c | 1 -
19
hw/arm/stm32f405_soc.c | 1 -
20
hw/arm/vexpress.c | 1 -
21
hw/arm/virt.c | 1 -
22
8 files changed, 8 deletions(-)
23
13
24
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/boot.c
16
--- a/target/arm/cpregs.h
27
+++ b/hw/arm/boot.c
17
+++ b/target/arm/cpregs.h
28
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
29
*/
19
FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
30
20
FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
31
#include "qemu/osdep.h"
21
FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
32
-#include "qemu-common.h"
22
+
33
#include "qemu/datadir.h"
23
+ /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
34
#include "qemu/error-report.h"
24
+ DO_BIT(HFGRTR, AFSR0_EL1),
35
#include "qapi/error.h"
25
+ DO_BIT(HFGRTR, AFSR1_EL1),
36
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
26
+ DO_BIT(HFGRTR, AIDR_EL1),
27
+ DO_BIT(HFGRTR, AMAIR_EL1),
28
+ DO_BIT(HFGRTR, APDAKEY),
29
+ DO_BIT(HFGRTR, APDBKEY),
30
+ DO_BIT(HFGRTR, APGAKEY),
31
+ DO_BIT(HFGRTR, APIAKEY),
32
+ DO_BIT(HFGRTR, APIBKEY),
33
+ DO_BIT(HFGRTR, CCSIDR_EL1),
34
+ DO_BIT(HFGRTR, CLIDR_EL1),
35
+ DO_BIT(HFGRTR, CONTEXTIDR_EL1),
36
} FGTBit;
37
38
#undef DO_BIT
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/digic_boards.c
41
--- a/target/arm/helper.c
39
+++ b/hw/arm/digic_boards.c
42
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
41
44
{ .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
42
#include "qemu/osdep.h"
45
.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
43
#include "qapi/error.h"
46
.access = PL1_RW, .accessfn = access_tvm_trvm,
44
-#include "qemu-common.h"
47
+ .fgt = FGT_CONTEXTIDR_EL1,
45
#include "qemu/datadir.h"
48
.secure = ARM_CP_SECSTATE_NS,
46
#include "hw/boards.h"
49
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
47
#include "qemu/error-report.h"
50
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
48
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
51
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
49
index XXXXXXX..XXXXXXX 100644
52
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
50
--- a/hw/arm/highbank.c
53
.access = PL1_R,
51
+++ b/hw/arm/highbank.c
54
.accessfn = access_tid4,
52
@@ -XXX,XX +XXX,XX @@
55
+ .fgt = FGT_CCSIDR_EL1,
53
*/
56
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
54
57
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
55
#include "qemu/osdep.h"
58
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
56
-#include "qemu-common.h"
59
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
57
#include "qemu/datadir.h"
60
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
58
#include "qapi/error.h"
61
.access = PL1_R, .type = ARM_CP_CONST,
59
#include "hw/sysbus.h"
62
.accessfn = access_aa64_tid1,
60
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
63
+ .fgt = FGT_AIDR_EL1,
61
index XXXXXXX..XXXXXXX 100644
64
.resetvalue = 0 },
62
--- a/hw/arm/npcm7xx_boards.c
65
/*
63
+++ b/hw/arm/npcm7xx_boards.c
66
* Auxiliary fault status registers: these also are IMPDEF, and we
64
@@ -XXX,XX +XXX,XX @@
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
65
#include "hw/qdev-core.h"
68
{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
66
#include "hw/qdev-properties.h"
69
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
67
#include "qapi/error.h"
70
.access = PL1_RW, .accessfn = access_tvm_trvm,
68
-#include "qemu-common.h"
71
+ .fgt = FGT_AFSR0_EL1,
69
#include "qemu/datadir.h"
72
.type = ARM_CP_CONST, .resetvalue = 0 },
70
#include "qemu/units.h"
73
{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
71
#include "sysemu/blockdev.h"
74
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
72
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
75
.access = PL1_RW, .accessfn = access_tvm_trvm,
73
index XXXXXXX..XXXXXXX 100644
76
+ .fgt = FGT_AFSR1_EL1,
74
--- a/hw/arm/sbsa-ref.c
77
.type = ARM_CP_CONST, .resetvalue = 0 },
75
+++ b/hw/arm/sbsa-ref.c
78
/*
76
@@ -XXX,XX +XXX,XX @@
79
* MAIR can just read-as-written because we don't implement caches
77
*/
80
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
78
81
{ .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
79
#include "qemu/osdep.h"
82
.opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
80
-#include "qemu-common.h"
83
.access = PL1_RW, .accessfn = access_tvm_trvm,
81
#include "qemu/datadir.h"
84
+ .fgt = FGT_AMAIR_EL1,
82
#include "qapi/error.h"
85
.type = ARM_CP_CONST, .resetvalue = 0 },
83
#include "qemu/error-report.h"
86
/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
84
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
87
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
85
index XXXXXXX..XXXXXXX 100644
88
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
86
--- a/hw/arm/stm32f405_soc.c
89
{ .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
87
+++ b/hw/arm/stm32f405_soc.c
90
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
88
@@ -XXX,XX +XXX,XX @@
91
.access = PL1_RW, .accessfn = access_pauth,
89
92
+ .fgt = FGT_APDAKEY,
90
#include "qemu/osdep.h"
93
.fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
91
#include "qapi/error.h"
94
{ .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
92
-#include "qemu-common.h"
95
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
93
#include "exec/address-spaces.h"
96
.access = PL1_RW, .accessfn = access_pauth,
94
#include "sysemu/sysemu.h"
97
+ .fgt = FGT_APDAKEY,
95
#include "hw/arm/stm32f405_soc.h"
98
.fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
96
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
99
{ .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
97
index XXXXXXX..XXXXXXX 100644
100
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
98
--- a/hw/arm/vexpress.c
101
.access = PL1_RW, .accessfn = access_pauth,
99
+++ b/hw/arm/vexpress.c
102
+ .fgt = FGT_APDBKEY,
100
@@ -XXX,XX +XXX,XX @@
103
.fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
101
104
{ .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
102
#include "qemu/osdep.h"
105
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
103
#include "qapi/error.h"
106
.access = PL1_RW, .accessfn = access_pauth,
104
-#include "qemu-common.h"
107
+ .fgt = FGT_APDBKEY,
105
#include "qemu/datadir.h"
108
.fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
106
#include "cpu.h"
109
{ .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
107
#include "hw/sysbus.h"
110
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
108
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
111
.access = PL1_RW, .accessfn = access_pauth,
109
index XXXXXXX..XXXXXXX 100644
112
+ .fgt = FGT_APGAKEY,
110
--- a/hw/arm/virt.c
113
.fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
111
+++ b/hw/arm/virt.c
114
{ .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
112
@@ -XXX,XX +XXX,XX @@
115
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
113
*/
116
.access = PL1_RW, .accessfn = access_pauth,
114
117
+ .fgt = FGT_APGAKEY,
115
#include "qemu/osdep.h"
118
.fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
116
-#include "qemu-common.h"
119
{ .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
117
#include "qemu/datadir.h"
120
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
118
#include "qemu/units.h"
121
.access = PL1_RW, .accessfn = access_pauth,
119
#include "qemu/option.h"
122
+ .fgt = FGT_APIAKEY,
123
.fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
124
{ .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
125
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
126
.access = PL1_RW, .accessfn = access_pauth,
127
+ .fgt = FGT_APIAKEY,
128
.fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
129
{ .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
130
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
131
.access = PL1_RW, .accessfn = access_pauth,
132
+ .fgt = FGT_APIBKEY,
133
.fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
134
{ .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
136
.access = PL1_RW, .accessfn = access_pauth,
137
+ .fgt = FGT_APIBKEY,
138
.fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
139
};
140
141
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
142
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
143
.access = PL1_R, .type = ARM_CP_CONST,
144
.accessfn = access_tid4,
145
+ .fgt = FGT_CLIDR_EL1,
146
.resetvalue = cpu->clidr
147
};
148
define_one_arm_cp_reg(cpu, &clidr);
120
--
149
--
121
2.25.1
150
2.34.1
122
123
diff view generated by jsdifflib
1
The qemu-common.h header is not supposed to be included from any
1
Mark up the sysreg definitions for the registers trapped
2
other header files, only from .c files (as documented in a comment at
2
by HFGRTR/HFGWTR bits 12..23.
3
the start of it).
4
5
Nothing actually relies on target/rx/cpu.h including it, so we can
6
just drop the include.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Fuad Tabba <tabba@google.com>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org
12
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
8
Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
13
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
14
---
9
---
15
target/rx/cpu.h | 1 -
10
target/arm/cpregs.h | 12 ++++++++++++
16
1 file changed, 1 deletion(-)
11
target/arm/helper.c | 12 ++++++++++++
12
2 files changed, 24 insertions(+)
17
13
18
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/rx/cpu.h
16
--- a/target/arm/cpregs.h
21
+++ b/target/rx/cpu.h
17
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
23
#define RX_CPU_H
19
DO_BIT(HFGRTR, CCSIDR_EL1),
24
20
DO_BIT(HFGRTR, CLIDR_EL1),
25
#include "qemu/bitops.h"
21
DO_BIT(HFGRTR, CONTEXTIDR_EL1),
26
-#include "qemu-common.h"
22
+ DO_BIT(HFGRTR, CPACR_EL1),
27
#include "hw/registerfields.h"
23
+ DO_BIT(HFGRTR, CSSELR_EL1),
28
#include "cpu-qom.h"
24
+ DO_BIT(HFGRTR, CTR_EL0),
29
25
+ DO_BIT(HFGRTR, DCZID_EL0),
26
+ DO_BIT(HFGRTR, ESR_EL1),
27
+ DO_BIT(HFGRTR, FAR_EL1),
28
+ DO_BIT(HFGRTR, ISR_EL1),
29
+ DO_BIT(HFGRTR, LORC_EL1),
30
+ DO_BIT(HFGRTR, LOREA_EL1),
31
+ DO_BIT(HFGRTR, LORID_EL1),
32
+ DO_BIT(HFGRTR, LORN_EL1),
33
+ DO_BIT(HFGRTR, LORSA_EL1),
34
} FGTBit;
35
36
#undef DO_BIT
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
42
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
43
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
44
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
45
+ .fgt = FGT_CPACR_EL1,
46
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
47
.resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
48
};
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
50
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
51
.access = PL1_RW,
52
.accessfn = access_tid4,
53
+ .fgt = FGT_CSSELR_EL1,
54
.writefn = csselr_write, .resetvalue = 0,
55
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
56
offsetof(CPUARMState, cp15.csselr_ns) } },
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
58
.resetfn = arm_cp_reset_ignore },
59
{ .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
60
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
61
+ .fgt = FGT_ISR_EL1,
62
.type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
63
/* 32 bit ITLB invalidates */
64
{ .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
66
{ .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
67
.opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
68
.access = PL1_RW, .accessfn = access_tvm_trvm,
69
+ .fgt = FGT_FAR_EL1,
70
.fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
71
.resetvalue = 0, },
72
};
73
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
74
{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
75
.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
76
.access = PL1_RW, .accessfn = access_tvm_trvm,
77
+ .fgt = FGT_ESR_EL1,
78
.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
79
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
81
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
82
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
83
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
84
.access = PL0_R, .type = ARM_CP_NO_RAW,
85
+ .fgt = FGT_DCZID_EL0,
86
.readfn = aa64_dczid_read },
87
{ .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
88
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
89
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
90
{ .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
91
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
92
.access = PL1_RW, .accessfn = access_lor_other,
93
+ .fgt = FGT_LORSA_EL1,
94
.type = ARM_CP_CONST, .resetvalue = 0 },
95
{ .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
97
.access = PL1_RW, .accessfn = access_lor_other,
98
+ .fgt = FGT_LOREA_EL1,
99
.type = ARM_CP_CONST, .resetvalue = 0 },
100
{ .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
101
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
102
.access = PL1_RW, .accessfn = access_lor_other,
103
+ .fgt = FGT_LORN_EL1,
104
.type = ARM_CP_CONST, .resetvalue = 0 },
105
{ .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
106
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
107
.access = PL1_RW, .accessfn = access_lor_other,
108
+ .fgt = FGT_LORC_EL1,
109
.type = ARM_CP_CONST, .resetvalue = 0 },
110
{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
111
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
112
.access = PL1_R, .accessfn = access_lor_ns,
113
+ .fgt = FGT_LORID_EL1,
114
.type = ARM_CP_CONST, .resetvalue = 0 },
115
};
116
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
{ .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
119
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
120
.access = PL0_R, .accessfn = ctr_el0_access,
121
+ .fgt = FGT_CTR_EL0,
122
.type = ARM_CP_CONST, .resetvalue = cpu->ctr },
123
/* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
124
{ .name = "TCMTR",
30
--
125
--
31
2.25.1
126
2.34.1
32
33
diff view generated by jsdifflib
1
The qemu-common.h header is not supposed to be included from any
1
Mark up the sysreg definitions for the registers trapped
2
other header files, only from .c files (as documented in a comment at
2
by HFGRTR/HFGWTR bits 24..35.
3
the start of it).
4
5
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
6
the declaration of cpu_exec_step_atomic().
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Fuad Tabba <tabba@google.com>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org
12
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
8
Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
13
---
9
---
14
target/hexagon/cpu.h | 1 -
10
target/arm/cpregs.h | 12 ++++++++++++
15
linux-user/hexagon/cpu_loop.c | 1 +
11
target/arm/helper.c | 14 ++++++++++++++
16
2 files changed, 1 insertion(+), 1 deletion(-)
12
2 files changed, 26 insertions(+)
17
13
18
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/hexagon/cpu.h
16
--- a/target/arm/cpregs.h
21
+++ b/target/hexagon/cpu.h
17
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState;
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
23
19
DO_BIT(HFGRTR, LORID_EL1),
24
#include "fpu/softfloat-types.h"
20
DO_BIT(HFGRTR, LORN_EL1),
25
21
DO_BIT(HFGRTR, LORSA_EL1),
26
-#include "qemu-common.h"
22
+ DO_BIT(HFGRTR, MAIR_EL1),
27
#include "exec/cpu-defs.h"
23
+ DO_BIT(HFGRTR, MIDR_EL1),
28
#include "hex_regs.h"
24
+ DO_BIT(HFGRTR, MPIDR_EL1),
29
#include "mmvec/mmvec.h"
25
+ DO_BIT(HFGRTR, PAR_EL1),
30
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
26
+ DO_BIT(HFGRTR, REVIDR_EL1),
27
+ DO_BIT(HFGRTR, SCTLR_EL1),
28
+ DO_BIT(HFGRTR, SCXTNUM_EL1),
29
+ DO_BIT(HFGRTR, SCXTNUM_EL0),
30
+ DO_BIT(HFGRTR, TCR_EL1),
31
+ DO_BIT(HFGRTR, TPIDR_EL1),
32
+ DO_BIT(HFGRTR, TPIDRRO_EL0),
33
+ DO_BIT(HFGRTR, TPIDR_EL0),
34
} FGTBit;
35
36
#undef DO_BIT
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
32
--- a/linux-user/hexagon/cpu_loop.c
39
--- a/target/arm/helper.c
33
+++ b/linux-user/hexagon/cpu_loop.c
40
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
35
*/
42
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
36
43
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
37
#include "qemu/osdep.h"
44
.access = PL1_RW, .accessfn = access_tvm_trvm,
38
+#include "qemu-common.h"
45
+ .fgt = FGT_MAIR_EL1,
39
#include "qemu.h"
46
.fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
40
#include "user-internals.h"
47
.resetvalue = 0 },
41
#include "cpu_loop-common.h"
48
{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
50
{ .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
51
.opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
52
.access = PL0_RW,
53
+ .fgt = FGT_TPIDR_EL0,
54
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
55
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
56
.access = PL0_RW,
57
+ .fgt = FGT_TPIDR_EL0,
58
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
59
offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
60
.resetfn = arm_cp_reset_ignore },
61
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
62
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
63
.access = PL0_R | PL1_W,
64
+ .fgt = FGT_TPIDRRO_EL0,
65
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
66
.resetvalue = 0},
67
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
68
.access = PL0_R | PL1_W,
69
+ .fgt = FGT_TPIDRRO_EL0,
70
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
71
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
72
.resetfn = arm_cp_reset_ignore },
73
{ .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
74
.opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
75
.access = PL1_RW,
76
+ .fgt = FGT_TPIDR_EL1,
77
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
78
{ .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
79
.access = PL1_RW,
80
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
81
{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
83
.access = PL1_RW, .accessfn = access_tvm_trvm,
84
+ .fgt = FGT_TCR_EL1,
85
.writefn = vmsa_tcr_el12_write,
86
.raw_writefn = raw_write,
87
.resetvalue = 0,
88
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
89
.type = ARM_CP_ALIAS,
90
.opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
91
.access = PL1_RW, .resetvalue = 0,
92
+ .fgt = FGT_PAR_EL1,
93
.fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
94
.writefn = par_write },
95
#endif
96
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
97
{ .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
98
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
99
.access = PL0_RW, .accessfn = access_scxtnum,
100
+ .fgt = FGT_SCXTNUM_EL0,
101
.fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
102
{ .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
103
.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
104
.access = PL1_RW, .accessfn = access_scxtnum,
105
+ .fgt = FGT_SCXTNUM_EL1,
106
.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
107
{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
108
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
109
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
110
{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
113
+ .fgt = FGT_MIDR_EL1,
114
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
115
.readfn = midr_read },
116
/* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
119
.access = PL1_R,
120
.accessfn = access_aa64_tid1,
121
+ .fgt = FGT_REVIDR_EL1,
122
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
123
};
124
ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
125
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
126
ARMCPRegInfo mpidr_cp_reginfo[] = {
127
{ .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
128
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
129
+ .fgt = FGT_MPIDR_EL1,
130
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
131
};
132
#ifdef CONFIG_USER_ONLY
133
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
134
.name = "SCTLR", .state = ARM_CP_STATE_BOTH,
135
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
136
.access = PL1_RW, .accessfn = access_tvm_trvm,
137
+ .fgt = FGT_SCTLR_EL1,
138
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
139
offsetof(CPUARMState, cp15.sctlr_ns) },
140
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
42
--
141
--
43
2.25.1
142
2.34.1
44
45
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Mark up the sysreg definitions for the registers trapped
2
by HFGRTR/HFGWTR bits 36..63.
2
3
3
The TYPE_ARM_GICV3 device is an emulated one. When using
4
Of these, some correspond to RAS registers which we implement as
4
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
5
always-UNDEF: these don't need any extra handling for FGT because the
5
(which uses in-kernel support).
6
UNDEF-to-EL1 always takes priority over any theoretical
7
FGT-trap-to-EL2.
6
8
7
When using --with-devices-FOO, it is possible to build a
9
Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
8
binary with a specific set of devices. When this binary is
10
of the FEAT_LS64_ACCDATA feature which we don't yet implement.
9
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
10
irrelevant, and it is desirable to remove it from the binary.
11
11
12
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
which select the files required to have the TYPE_ARM_GICV3
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
device, but also allowing to de-select this device.
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
17
---
18
target/arm/cpregs.h | 7 +++++++
19
hw/intc/arm_gicv3_cpuif.c | 2 ++
20
target/arm/helper.c | 10 ++++++++++
21
3 files changed, 19 insertions(+)
15
22
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20211115223619.2599282-3-philmd@redhat.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/intc/arm_gicv3.c | 2 +-
22
hw/intc/Kconfig | 5 +++++
23
hw/intc/meson.build | 10 ++++++----
24
3 files changed, 12 insertions(+), 5 deletions(-)
25
26
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
27
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/intc/arm_gicv3.c
25
--- a/target/arm/cpregs.h
29
+++ b/hw/intc/arm_gicv3.c
26
+++ b/target/arm/cpregs.h
30
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
31
/*
28
DO_BIT(HFGRTR, TPIDR_EL1),
32
- * ARM Generic Interrupt Controller v3
29
DO_BIT(HFGRTR, TPIDRRO_EL0),
33
+ * ARM Generic Interrupt Controller v3 (emulation)
30
DO_BIT(HFGRTR, TPIDR_EL0),
34
*
31
+ DO_BIT(HFGRTR, TTBR0_EL1),
35
* Copyright (c) 2015 Huawei.
32
+ DO_BIT(HFGRTR, TTBR1_EL1),
36
* Copyright (c) 2016 Linaro Limited
33
+ DO_BIT(HFGRTR, VBAR_EL1),
37
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
34
+ DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
35
+ DO_BIT(HFGRTR, ERRIDR_EL1),
36
+ DO_REV_BIT(HFGRTR, NSMPRI_EL1),
37
+ DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
38
} FGTBit;
39
40
#undef DO_BIT
41
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
38
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/intc/Kconfig
43
--- a/hw/intc/arm_gicv3_cpuif.c
40
+++ b/hw/intc/Kconfig
44
+++ b/hw/intc/arm_gicv3_cpuif.c
41
@@ -XXX,XX +XXX,XX @@ config APIC
45
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
42
select MSI_NONBROKEN
46
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
43
select I8259
47
.type = ARM_CP_IO | ARM_CP_NO_RAW,
44
48
.access = PL1_RW, .accessfn = gicv3_fiq_access,
45
+config ARM_GIC_TCG
49
+ .fgt = FGT_ICC_IGRPENN_EL1,
46
+ bool
50
.readfn = icc_igrpen_read,
47
+ default y
51
.writefn = icc_igrpen_write,
48
+ depends on ARM_GIC && TCG
52
},
49
+
53
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
50
config ARM_GIC_KVM
54
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
51
bool
55
.type = ARM_CP_IO | ARM_CP_NO_RAW,
52
default y
56
.access = PL1_RW, .accessfn = gicv3_irq_access,
53
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
57
+ .fgt = FGT_ICC_IGRPENN_EL1,
58
.readfn = icc_igrpen_read,
59
.writefn = icc_igrpen_write,
60
},
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
54
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/intc/meson.build
63
--- a/target/arm/helper.c
56
+++ b/hw/intc/meson.build
64
+++ b/target/arm/helper.c
57
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
58
'arm_gic.c',
66
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
59
'arm_gic_common.c',
67
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
60
'arm_gicv2m.c',
68
.access = PL1_RW, .accessfn = access_tvm_trvm,
61
- 'arm_gicv3.c',
69
+ .fgt = FGT_TTBR0_EL1,
62
'arm_gicv3_common.c',
70
.writefn = vmsa_ttbr_write, .resetvalue = 0,
63
- 'arm_gicv3_dist.c',
71
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
64
'arm_gicv3_its_common.c',
72
offsetof(CPUARMState, cp15.ttbr0_ns) } },
65
- 'arm_gicv3_redist.c',
73
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
66
+))
74
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
67
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
75
.access = PL1_RW, .accessfn = access_tvm_trvm,
68
+ 'arm_gicv3.c',
76
+ .fgt = FGT_TTBR1_EL1,
69
+ 'arm_gicv3_dist.c',
77
.writefn = vmsa_ttbr_write, .resetvalue = 0,
70
'arm_gicv3_its.c',
78
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
71
+ 'arm_gicv3_redist.c',
79
offsetof(CPUARMState, cp15.ttbr1_ns) } },
72
))
80
@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
73
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
81
* ERRSELR_EL1
74
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
82
* may generate UNDEFINED, which is the effect we get by not
75
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
83
* listing them at all.
76
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
84
+ *
77
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
85
+ * These registers have fine-grained trap bits, but UNDEF-to-EL1
78
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
86
+ * is higher priority than FGT-to-EL2 so we do not need to list them
79
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
87
+ * in order to check for an FGT.
80
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
88
*/
81
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
89
static const ARMCPRegInfo minimal_ras_reginfo[] = {
82
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
90
{ .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
83
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
91
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
92
{ .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
93
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
94
.access = PL1_R, .accessfn = access_terr,
95
+ .fgt = FGT_ERRIDR_EL1,
96
.type = ARM_CP_CONST, .resetvalue = 0 },
97
{ .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
98
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
100
{ .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
101
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
102
.access = PL0_RW, .accessfn = access_tpidr2,
103
+ .fgt = FGT_NTPIDR2_EL0,
104
.fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
105
{ .name = "SVCR", .state = ARM_CP_STATE_AA64,
106
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
107
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
108
{ .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
109
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
110
.access = PL1_RW, .accessfn = access_esm,
111
+ .fgt = FGT_NSMPRI_EL1,
112
.type = ARM_CP_CONST, .resetvalue = 0 },
113
{ .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
114
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
115
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
116
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
117
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
118
.access = PL1_RW, .writefn = vbar_write,
119
+ .fgt = FGT_VBAR_EL1,
120
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
121
offsetof(CPUARMState, cp15.vbar_ns) },
122
.resetvalue = 0 },
84
--
123
--
85
2.25.1
124
2.34.1
86
87
diff view generated by jsdifflib
1
From: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
1
Mark up the sysreg definitons for the registers trapped
2
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
3
related registers.
2
4
3
Fix issue where the data register may be overwritten by next character
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
reception before being read and returned.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Fuad Tabba <tabba@google.com>
8
Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org
10
---
11
target/arm/cpregs.h | 12 ++++++++++++
12
target/arm/debug_helper.c | 11 +++++++++++
13
2 files changed, 23 insertions(+)
5
14
6
Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/char/stm32f2xx_usart.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/stm32f2xx_usart.c
17
--- a/target/arm/cpregs.h
18
+++ b/hw/char/stm32f2xx_usart.c
18
+++ b/target/arm/cpregs.h
19
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
20
return retvalue;
20
DO_BIT(HFGRTR, ERRIDR_EL1),
21
case USART_DR:
21
DO_REV_BIT(HFGRTR, NSMPRI_EL1),
22
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
22
DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
23
+ retvalue = s->usart_dr & 0x3FF;
23
+
24
s->usart_sr &= ~USART_SR_RXNE;
24
+ /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
25
qemu_chr_fe_accept_input(&s->chr);
25
+ DO_BIT(HDFGRTR, DBGBCRN_EL1),
26
qemu_set_irq(s->irq, 0);
26
+ DO_BIT(HDFGRTR, DBGBVRN_EL1),
27
- return s->usart_dr & 0x3FF;
27
+ DO_BIT(HDFGRTR, DBGWCRN_EL1),
28
+ return retvalue;
28
+ DO_BIT(HDFGRTR, DBGWVRN_EL1),
29
case USART_BRR:
29
+ DO_BIT(HDFGRTR, MDSCR_EL1),
30
return s->usart_brr;
30
+ DO_BIT(HDFGRTR, DBGCLAIM),
31
case USART_CR1:
31
+ DO_BIT(HDFGWTR, OSLAR_EL1),
32
+ DO_BIT(HDFGRTR, OSLSR_EL1),
33
+ DO_BIT(HDFGRTR, OSECCR_EL1),
34
+ DO_BIT(HDFGRTR, OSDLR_EL1),
35
} FGTBit;
36
37
#undef DO_BIT
38
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/debug_helper.c
41
+++ b/target/arm/debug_helper.c
42
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
43
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
44
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
45
.access = PL1_RW, .accessfn = access_tda,
46
+ .fgt = FGT_MDSCR_EL1,
47
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
48
.resetvalue = 0 },
49
/*
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
51
{ .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
52
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
53
.access = PL1_RW, .accessfn = access_tda,
54
+ .fgt = FGT_OSECCR_EL1,
55
.type = ARM_CP_CONST, .resetvalue = 0 },
56
/*
57
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
59
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
60
.access = PL1_W, .type = ARM_CP_NO_RAW,
61
.accessfn = access_tdosa,
62
+ .fgt = FGT_OSLAR_EL1,
63
.writefn = oslar_write },
64
{ .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
65
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
66
.access = PL1_R, .resetvalue = 10,
67
.accessfn = access_tdosa,
68
+ .fgt = FGT_OSLSR_EL1,
69
.fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
70
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
71
{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
72
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
73
.access = PL1_RW, .accessfn = access_tdosa,
74
+ .fgt = FGT_OSDLR_EL1,
75
.writefn = osdlr_write,
76
.fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
77
/*
78
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
79
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
80
.type = ARM_CP_ALIAS,
81
.access = PL1_RW, .accessfn = access_tda,
82
+ .fgt = FGT_DBGCLAIM,
83
.writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
84
{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
85
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
86
.access = PL1_RW, .accessfn = access_tda,
87
+ .fgt = FGT_DBGCLAIM,
88
.writefn = dbgclaimclr_write, .raw_writefn = raw_write,
89
.fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
90
};
91
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
92
{ .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
93
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
94
.access = PL1_RW, .accessfn = access_tda,
95
+ .fgt = FGT_DBGBVRN_EL1,
96
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
97
.writefn = dbgbvr_write, .raw_writefn = raw_write
98
},
99
{ .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
100
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
101
.access = PL1_RW, .accessfn = access_tda,
102
+ .fgt = FGT_DBGBCRN_EL1,
103
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
104
.writefn = dbgbcr_write, .raw_writefn = raw_write
105
},
106
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
107
{ .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
108
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
109
.access = PL1_RW, .accessfn = access_tda,
110
+ .fgt = FGT_DBGWVRN_EL1,
111
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
112
.writefn = dbgwvr_write, .raw_writefn = raw_write
113
},
114
{ .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
115
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
116
.access = PL1_RW, .accessfn = access_tda,
117
+ .fgt = FGT_DBGWCRN_EL1,
118
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
119
.writefn = dbgwcr_write, .raw_writefn = raw_write
120
},
32
--
121
--
33
2.25.1
122
2.34.1
34
35
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Mark up the sysreg definitions for the registers trapped
2
2
by HDFGRTR/HDFGWTR bits 12..x.
3
Move it to the supported list.
3
4
4
Bits 12..22 and bit 58 are for PMU registers.
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
5
6
Message-id: 20211117065752.330632-5-joel@jms.id.au
6
The remaining bits in HDFGRTR/HDFGWTR are for traps on
7
registers that are part of features we don't implement:
8
9
Bits 23..32 and 63 : FEAT_SPE
10
Bits 33..48 : FEAT_ETE
11
Bits 50..56 : FEAT_TRBE
12
Bits 59..61 : FEAT_BRBE
13
Bit 62 : FEAT_SPEv1p2.
14
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Fuad Tabba <tabba@google.com>
18
Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org
19
Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org
8
---
20
---
9
docs/system/arm/aspeed.rst | 2 +-
21
target/arm/cpregs.h | 12 ++++++++++++
10
1 file changed, 1 insertion(+), 1 deletion(-)
22
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
11
23
2 files changed, 49 insertions(+)
12
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
24
25
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
13
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/aspeed.rst
27
--- a/target/arm/cpregs.h
15
+++ b/docs/system/arm/aspeed.rst
28
+++ b/target/arm/cpregs.h
16
@@ -XXX,XX +XXX,XX @@ Supported devices
29
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
17
* Front LEDs (PCA9552 on I2C bus)
30
DO_BIT(HDFGRTR, OSLSR_EL1),
18
* LPC Peripheral Controller (a subset of subdevices are supported)
31
DO_BIT(HDFGRTR, OSECCR_EL1),
19
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
32
DO_BIT(HDFGRTR, OSDLR_EL1),
20
+ * ADC
33
+ DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
21
34
+ DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
22
35
+ DO_BIT(HDFGRTR, PMCCFILTR_EL0),
23
Missing devices
36
+ DO_BIT(HDFGRTR, PMCCNTR_EL0),
24
---------------
37
+ DO_BIT(HDFGRTR, PMCNTEN),
25
38
+ DO_BIT(HDFGRTR, PMINTEN),
26
* Coprocessor support
39
+ DO_BIT(HDFGRTR, PMOVS),
27
- * ADC (out of tree implementation)
40
+ DO_BIT(HDFGRTR, PMSELR_EL0),
28
* PWM and Fan Controller
41
+ DO_BIT(HDFGWTR, PMSWINC_EL0),
29
* Slave GPIO Controller
42
+ DO_BIT(HDFGWTR, PMCR_EL0),
30
* Super I/O Controller
43
+ DO_BIT(HDFGRTR, PMMIR_EL1),
44
+ DO_BIT(HDFGRTR, PMCEIDN_EL0),
45
} FGTBit;
46
47
#undef DO_BIT
48
diff --git a/target/arm/helper.c b/target/arm/helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/helper.c
51
+++ b/target/arm/helper.c
52
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
53
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
54
.writefn = pmcntenset_write,
55
.accessfn = pmreg_access,
56
+ .fgt = FGT_PMCNTEN,
57
.raw_writefn = raw_write },
58
{ .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
59
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
60
.access = PL0_RW, .accessfn = pmreg_access,
61
+ .fgt = FGT_PMCNTEN,
62
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
63
.writefn = pmcntenset_write, .raw_writefn = raw_write },
64
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
65
.access = PL0_RW,
66
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
67
.accessfn = pmreg_access,
68
+ .fgt = FGT_PMCNTEN,
69
.writefn = pmcntenclr_write,
70
.type = ARM_CP_ALIAS | ARM_CP_IO },
71
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
72
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
73
.access = PL0_RW, .accessfn = pmreg_access,
74
+ .fgt = FGT_PMCNTEN,
75
.type = ARM_CP_ALIAS | ARM_CP_IO,
76
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
77
.writefn = pmcntenclr_write },
78
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
79
.access = PL0_RW, .type = ARM_CP_IO,
80
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
81
.accessfn = pmreg_access,
82
+ .fgt = FGT_PMOVS,
83
.writefn = pmovsr_write,
84
.raw_writefn = raw_write },
85
{ .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
86
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
87
.access = PL0_RW, .accessfn = pmreg_access,
88
+ .fgt = FGT_PMOVS,
89
.type = ARM_CP_ALIAS | ARM_CP_IO,
90
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
91
.writefn = pmovsr_write,
92
.raw_writefn = raw_write },
93
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
94
.access = PL0_W, .accessfn = pmreg_access_swinc,
95
+ .fgt = FGT_PMSWINC_EL0,
96
.type = ARM_CP_NO_RAW | ARM_CP_IO,
97
.writefn = pmswinc_write },
98
{ .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
99
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
100
.access = PL0_W, .accessfn = pmreg_access_swinc,
101
+ .fgt = FGT_PMSWINC_EL0,
102
.type = ARM_CP_NO_RAW | ARM_CP_IO,
103
.writefn = pmswinc_write },
104
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
105
.access = PL0_RW, .type = ARM_CP_ALIAS,
106
+ .fgt = FGT_PMSELR_EL0,
107
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
108
.accessfn = pmreg_access_selr, .writefn = pmselr_write,
109
.raw_writefn = raw_write},
110
{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
111
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
112
.access = PL0_RW, .accessfn = pmreg_access_selr,
113
+ .fgt = FGT_PMSELR_EL0,
114
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
115
.writefn = pmselr_write, .raw_writefn = raw_write, },
116
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
117
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
118
+ .fgt = FGT_PMCCNTR_EL0,
119
.readfn = pmccntr_read, .writefn = pmccntr_write32,
120
.accessfn = pmreg_access_ccntr },
121
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
122
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
123
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
124
+ .fgt = FGT_PMCCNTR_EL0,
125
.type = ARM_CP_IO,
126
.fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
127
.readfn = pmccntr_read, .writefn = pmccntr_write,
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
129
{ .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
130
.writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
131
.access = PL0_RW, .accessfn = pmreg_access,
132
+ .fgt = FGT_PMCCFILTR_EL0,
133
.type = ARM_CP_ALIAS | ARM_CP_IO,
134
.resetvalue = 0, },
135
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
136
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
137
.writefn = pmccfiltr_write, .raw_writefn = raw_write,
138
.access = PL0_RW, .accessfn = pmreg_access,
139
+ .fgt = FGT_PMCCFILTR_EL0,
140
.type = ARM_CP_IO,
141
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
142
.resetvalue = 0, },
143
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
144
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
145
.accessfn = pmreg_access,
146
+ .fgt = FGT_PMEVTYPERN_EL0,
147
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
148
{ .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
149
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
150
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
151
.accessfn = pmreg_access,
152
+ .fgt = FGT_PMEVTYPERN_EL0,
153
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
154
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
155
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
156
.accessfn = pmreg_access_xevcntr,
157
+ .fgt = FGT_PMEVCNTRN_EL0,
158
.writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
159
{ .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
161
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
162
.accessfn = pmreg_access_xevcntr,
163
+ .fgt = FGT_PMEVCNTRN_EL0,
164
.writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
165
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
166
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
167
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
168
.writefn = pmuserenr_write, .raw_writefn = raw_write },
169
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
170
.access = PL1_RW, .accessfn = access_tpm,
171
+ .fgt = FGT_PMINTEN,
172
.type = ARM_CP_ALIAS | ARM_CP_IO,
173
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
174
.resetvalue = 0,
175
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
176
{ .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
177
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
178
.access = PL1_RW, .accessfn = access_tpm,
179
+ .fgt = FGT_PMINTEN,
180
.type = ARM_CP_IO,
181
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
182
.writefn = pmintenset_write, .raw_writefn = raw_write,
183
.resetvalue = 0x0 },
184
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
185
.access = PL1_RW, .accessfn = access_tpm,
186
+ .fgt = FGT_PMINTEN,
187
.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
188
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
189
.writefn = pmintenclr_write, },
190
{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
192
.access = PL1_RW, .accessfn = access_tpm,
193
+ .fgt = FGT_PMINTEN,
194
.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
195
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
196
.writefn = pmintenclr_write },
197
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
198
/* PMOVSSET is not implemented in v7 before v7ve */
199
{ .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
200
.access = PL0_RW, .accessfn = pmreg_access,
201
+ .fgt = FGT_PMOVS,
202
.type = ARM_CP_ALIAS | ARM_CP_IO,
203
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
204
.writefn = pmovsset_write,
205
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
206
{ .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
207
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
208
.access = PL0_RW, .accessfn = pmreg_access,
209
+ .fgt = FGT_PMOVS,
210
.type = ARM_CP_ALIAS | ARM_CP_IO,
211
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
212
.writefn = pmovsset_write,
213
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
214
ARMCPRegInfo pmcr = {
215
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
216
.access = PL0_RW,
217
+ .fgt = FGT_PMCR_EL0,
218
.type = ARM_CP_IO | ARM_CP_ALIAS,
219
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
220
.accessfn = pmreg_access, .writefn = pmcr_write,
221
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
222
.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
223
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
224
.access = PL0_RW, .accessfn = pmreg_access,
225
+ .fgt = FGT_PMCR_EL0,
226
.type = ARM_CP_IO,
227
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
228
.resetvalue = cpu->isar.reset_pmcr_el0,
229
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
230
{ .name = pmevcntr_name, .cp = 15, .crn = 14,
231
.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
232
.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
233
+ .fgt = FGT_PMEVCNTRN_EL0,
234
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
235
.accessfn = pmreg_access_xevcntr },
236
{ .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
237
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
238
.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
239
.type = ARM_CP_IO,
240
+ .fgt = FGT_PMEVCNTRN_EL0,
241
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
242
.raw_readfn = pmevcntr_rawread,
243
.raw_writefn = pmevcntr_rawwrite },
244
{ .name = pmevtyper_name, .cp = 15, .crn = 14,
245
.crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
246
.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
247
+ .fgt = FGT_PMEVTYPERN_EL0,
248
.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
249
.accessfn = pmreg_access },
250
{ .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
252
.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
253
+ .fgt = FGT_PMEVTYPERN_EL0,
254
.type = ARM_CP_IO,
255
.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
256
.raw_writefn = pmevtyper_rawwrite },
257
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
258
{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
259
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
260
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
261
+ .fgt = FGT_PMCEIDN_EL0,
262
.resetvalue = extract64(cpu->pmceid0, 32, 32) },
263
{ .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
264
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
265
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
266
+ .fgt = FGT_PMCEIDN_EL0,
267
.resetvalue = extract64(cpu->pmceid1, 32, 32) },
268
};
269
define_arm_cp_regs(cpu, v81_pmu_regs);
270
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
271
.name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
272
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
273
.access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
274
+ .fgt = FGT_PMMIR_EL1,
275
.resetvalue = 0
276
};
277
define_one_arm_cp_reg(cpu, &v84_pmmir);
278
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
279
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
280
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
281
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
282
+ .fgt = FGT_PMCEIDN_EL0,
283
.resetvalue = extract64(cpu->pmceid0, 0, 32) },
284
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
285
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
286
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
287
+ .fgt = FGT_PMCEIDN_EL0,
288
.resetvalue = cpu->pmceid0 },
289
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
290
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
291
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
292
+ .fgt = FGT_PMCEIDN_EL0,
293
.resetvalue = extract64(cpu->pmceid1, 0, 32) },
294
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
295
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
296
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
297
+ .fgt = FGT_PMCEIDN_EL0,
298
.resetvalue = cpu->pmceid1 },
299
};
300
#ifdef CONFIG_USER_ONLY
31
--
301
--
32
2.25.1
302
2.34.1
33
34
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 0..11. These bits cover various
3
cache maintenance operations.
2
4
3
A common use case for the ASPEED machine is to boot a Linux kernel.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Provide a full example command line.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Fuad Tabba <tabba@google.com>
8
Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
10
---
11
target/arm/cpregs.h | 14 ++++++++++++++
12
target/arm/helper.c | 28 ++++++++++++++++++++++++++++
13
2 files changed, 42 insertions(+)
5
14
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-4-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 15 ++++++++++++---
12
1 file changed, 12 insertions(+), 3 deletions(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
--- a/target/arm/cpregs.h
17
+++ b/docs/system/arm/aspeed.rst
18
+++ b/target/arm/cpregs.h
18
@@ -XXX,XX +XXX,XX @@ Missing devices
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
19
Boot options
20
DO_BIT(HDFGWTR, PMCR_EL0),
20
------------
21
DO_BIT(HDFGRTR, PMMIR_EL1),
21
22
DO_BIT(HDFGRTR, PMCEIDN_EL0),
22
-The Aspeed machines can be started using the ``-kernel`` option to
23
-load a Linux kernel or from a firmware. Images can be downloaded from
24
-the OpenBMC jenkins :
25
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options
26
+to load a Linux kernel or from a firmware. Images can be downloaded from the
27
+OpenBMC jenkins :
28
29
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
30
31
@@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository :
32
33
https://github.com/openbmc/openbmc/releases
34
35
+To boot a kernel directly from a Linux build tree:
36
+
23
+
37
+.. code-block:: bash
24
+ /* Trap bits in HFGITR_EL2, starting from bit 0 */
38
+
25
+ DO_BIT(HFGITR, ICIALLUIS),
39
+ $ qemu-system-arm -M ast2600-evb -nographic \
26
+ DO_BIT(HFGITR, ICIALLU),
40
+ -kernel arch/arm/boot/zImage \
27
+ DO_BIT(HFGITR, ICIVAU),
41
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
28
+ DO_BIT(HFGITR, DCIVAC),
42
+ -initrd rootfs.cpio
29
+ DO_BIT(HFGITR, DCISW),
43
+
30
+ DO_BIT(HFGITR, DCCSW),
44
The image should be attached as an MTD drive. Run :
31
+ DO_BIT(HFGITR, DCCISW),
45
32
+ DO_BIT(HFGITR, DCCVAU),
46
.. code-block:: bash
33
+ DO_BIT(HFGITR, DCCVAP),
34
+ DO_BIT(HFGITR, DCCVADP),
35
+ DO_BIT(HFGITR, DCCIVAC),
36
+ DO_BIT(HFGITR, DCZVA),
37
} FGTBit;
38
39
#undef DO_BIT
40
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/helper.c
43
+++ b/target/arm/helper.c
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
45
#ifndef CONFIG_USER_ONLY
46
/* Avoid overhead of an access check that always passes in user-mode */
47
.accessfn = aa64_zva_access,
48
+ .fgt = FGT_DCZVA,
49
#endif
50
},
51
{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
52
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
53
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
54
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
55
.access = PL1_W, .type = ARM_CP_NOP,
56
+ .fgt = FGT_ICIALLUIS,
57
.accessfn = access_ticab },
58
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
59
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
60
.access = PL1_W, .type = ARM_CP_NOP,
61
+ .fgt = FGT_ICIALLU,
62
.accessfn = access_tocu },
63
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
64
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
65
.access = PL0_W, .type = ARM_CP_NOP,
66
+ .fgt = FGT_ICIVAU,
67
.accessfn = access_tocu },
68
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
69
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
70
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
71
+ .fgt = FGT_DCIVAC,
72
.type = ARM_CP_NOP },
73
{ .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
74
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
75
+ .fgt = FGT_DCISW,
76
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
77
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
78
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
80
.accessfn = aa64_cacheop_poc_access },
81
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
82
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
83
+ .fgt = FGT_DCCSW,
84
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
85
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
86
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
87
.access = PL0_W, .type = ARM_CP_NOP,
88
+ .fgt = FGT_DCCVAU,
89
.accessfn = access_tocu },
90
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
91
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
92
.access = PL0_W, .type = ARM_CP_NOP,
93
+ .fgt = FGT_DCCIVAC,
94
.accessfn = aa64_cacheop_poc_access },
95
{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
97
+ .fgt = FGT_DCCISW,
98
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
99
/* TLBI operations */
100
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
101
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
102
{ .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
103
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
104
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
105
+ .fgt = FGT_DCCVAP,
106
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
107
};
108
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
110
{ .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
111
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
112
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
113
+ .fgt = FGT_DCCVADP,
114
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
115
};
116
#endif /*CONFIG_USER_ONLY*/
117
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
118
{ .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
119
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
120
.type = ARM_CP_NOP, .access = PL1_W,
121
+ .fgt = FGT_DCIVAC,
122
.accessfn = aa64_cacheop_poc_access },
123
{ .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
124
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
125
+ .fgt = FGT_DCISW,
126
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
127
{ .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
128
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
129
.type = ARM_CP_NOP, .access = PL1_W,
130
+ .fgt = FGT_DCIVAC,
131
.accessfn = aa64_cacheop_poc_access },
132
{ .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
134
+ .fgt = FGT_DCISW,
135
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
136
{ .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
137
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
138
+ .fgt = FGT_DCCSW,
139
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
140
{ .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
141
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
142
+ .fgt = FGT_DCCSW,
143
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
144
{ .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
145
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
146
+ .fgt = FGT_DCCISW,
147
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
148
{ .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
149
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
150
+ .fgt = FGT_DCCISW,
151
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
152
};
153
154
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
155
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
156
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
157
.type = ARM_CP_NOP, .access = PL0_W,
158
+ .fgt = FGT_DCCVAP,
159
.accessfn = aa64_cacheop_poc_access },
160
{ .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
161
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
162
.type = ARM_CP_NOP, .access = PL0_W,
163
+ .fgt = FGT_DCCVAP,
164
.accessfn = aa64_cacheop_poc_access },
165
{ .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
166
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
167
.type = ARM_CP_NOP, .access = PL0_W,
168
+ .fgt = FGT_DCCVADP,
169
.accessfn = aa64_cacheop_poc_access },
170
{ .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
172
.type = ARM_CP_NOP, .access = PL0_W,
173
+ .fgt = FGT_DCCVADP,
174
.accessfn = aa64_cacheop_poc_access },
175
{ .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
177
.type = ARM_CP_NOP, .access = PL0_W,
178
+ .fgt = FGT_DCCIVAC,
179
.accessfn = aa64_cacheop_poc_access },
180
{ .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
182
.type = ARM_CP_NOP, .access = PL0_W,
183
+ .fgt = FGT_DCCIVAC,
184
.accessfn = aa64_cacheop_poc_access },
185
{ .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
186
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
187
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
188
#ifndef CONFIG_USER_ONLY
189
/* Avoid overhead of an access check that always passes in user-mode */
190
.accessfn = aa64_zva_access,
191
+ .fgt = FGT_DCZVA,
192
#endif
193
},
194
{ .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
195
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
196
#ifndef CONFIG_USER_ONLY
197
/* Avoid overhead of an access check that always passes in user-mode */
198
.accessfn = aa64_zva_access,
199
+ .fgt = FGT_DCZVA,
200
#endif
201
},
202
};
47
--
203
--
48
2.25.1
204
2.34.1
49
50
diff view generated by jsdifflib
1
The qemu-common.h header is not supposed to be included from any
1
Mark up the sysreg definitions for the system instructions
2
other header files, only from .c files (as documented in a comment at
2
trapped by HFGITR bits 12..17. These bits cover AT address
3
the start of it).
3
translation instructions.
4
5
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
6
In fact, the include is not required at all, so we can just drop it
7
from both files.
8
4
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Tested-by: Fuad Tabba <tabba@google.com>
12
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
8
Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
13
---
10
---
14
include/hw/i386/microvm.h | 1 -
11
target/arm/cpregs.h | 6 ++++++
15
include/hw/i386/x86.h | 1 -
12
target/arm/helper.c | 6 ++++++
16
2 files changed, 2 deletions(-)
13
2 files changed, 12 insertions(+)
17
14
18
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/i386/microvm.h
17
--- a/target/arm/cpregs.h
21
+++ b/include/hw/i386/microvm.h
18
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
23
#ifndef HW_I386_MICROVM_H
20
DO_BIT(HFGITR, DCCVADP),
24
#define HW_I386_MICROVM_H
21
DO_BIT(HFGITR, DCCIVAC),
25
22
DO_BIT(HFGITR, DCZVA),
26
-#include "qemu-common.h"
23
+ DO_BIT(HFGITR, ATS1E1R),
27
#include "exec/hwaddr.h"
24
+ DO_BIT(HFGITR, ATS1E1W),
28
#include "qemu/notify.h"
25
+ DO_BIT(HFGITR, ATS1E0R),
29
26
+ DO_BIT(HFGITR, ATS1E0W),
30
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
27
+ DO_BIT(HFGITR, ATS1E1RP),
28
+ DO_BIT(HFGITR, ATS1E1WP),
29
} FGTBit;
30
31
#undef DO_BIT
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/i386/x86.h
34
--- a/target/arm/helper.c
33
+++ b/include/hw/i386/x86.h
35
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
35
#ifndef HW_I386_X86_H
37
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
36
#define HW_I386_X86_H
38
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
37
39
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
38
-#include "qemu-common.h"
40
+ .fgt = FGT_ATS1E1R,
39
#include "exec/hwaddr.h"
41
.writefn = ats_write64 },
40
#include "qemu/notify.h"
42
{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
43
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
44
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
45
+ .fgt = FGT_ATS1E1W,
46
.writefn = ats_write64 },
47
{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
48
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
49
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
50
+ .fgt = FGT_ATS1E0R,
51
.writefn = ats_write64 },
52
{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
53
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
54
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
55
+ .fgt = FGT_ATS1E0W,
56
.writefn = ats_write64 },
57
{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
58
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
59
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
60
{ .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
62
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
63
+ .fgt = FGT_ATS1E1RP,
64
.writefn = ats_write64 },
65
{ .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
66
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
67
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
68
+ .fgt = FGT_ATS1E1WP,
69
.writefn = ats_write64 },
70
};
41
71
42
--
72
--
43
2.25.1
73
2.34.1
44
45
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 18..47. These bits cover TLBI
3
TLB maintenance instructions.
2
4
3
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
5
(If we implemented FEAT_XS we would need to trap some of the
4
removed in v7.0.
6
instructions added by that feature using these bits; but we don't
7
yet, so will need to add the .fgt markup when we do.)
5
8
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20211117065752.330632-2-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Fuad Tabba <tabba@google.com>
12
Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org
13
Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
10
---
14
---
11
docs/system/arm/aspeed.rst | 7 ++++++-
15
target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++
12
1 file changed, 6 insertions(+), 1 deletion(-)
16
target/arm/helper.c | 30 ++++++++++++++++++++++++++++++
17
2 files changed, 60 insertions(+)
13
18
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
19
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
21
--- a/target/arm/cpregs.h
17
+++ b/docs/system/arm/aspeed.rst
22
+++ b/target/arm/cpregs.h
18
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
23
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
19
24
DO_BIT(HFGITR, ATS1E0W),
20
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
25
DO_BIT(HFGITR, ATS1E1RP),
21
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
26
DO_BIT(HFGITR, ATS1E1WP),
22
+- ``supermicrox11-bmc`` Supermicro X11 BMC
27
+ DO_BIT(HFGITR, TLBIVMALLE1OS),
23
28
+ DO_BIT(HFGITR, TLBIVAE1OS),
24
AST2500 SoC based machines :
29
+ DO_BIT(HFGITR, TLBIASIDE1OS),
25
30
+ DO_BIT(HFGITR, TLBIVAAE1OS),
26
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
31
+ DO_BIT(HFGITR, TLBIVALE1OS),
27
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
32
+ DO_BIT(HFGITR, TLBIVAALE1OS),
28
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
33
+ DO_BIT(HFGITR, TLBIRVAE1OS),
29
- ``sonorapass-bmc`` OCP SonoraPass BMC
34
+ DO_BIT(HFGITR, TLBIRVAAE1OS),
30
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9
35
+ DO_BIT(HFGITR, TLBIRVALE1OS),
31
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
36
+ DO_BIT(HFGITR, TLBIRVAALE1OS),
32
+- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
37
+ DO_BIT(HFGITR, TLBIVMALLE1IS),
33
+- ``g220a-bmc`` Bytedance G220A BMC
38
+ DO_BIT(HFGITR, TLBIVAE1IS),
34
39
+ DO_BIT(HFGITR, TLBIASIDE1IS),
35
AST2600 SoC based machines :
40
+ DO_BIT(HFGITR, TLBIVAAE1IS),
36
41
+ DO_BIT(HFGITR, TLBIVALE1IS),
37
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
42
+ DO_BIT(HFGITR, TLBIVAALE1IS),
38
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
43
+ DO_BIT(HFGITR, TLBIRVAE1IS),
39
+- ``rainier-bmc`` IBM Rainier POWER10 BMC
44
+ DO_BIT(HFGITR, TLBIRVAAE1IS),
40
+- ``fuji-bmc`` Facebook Fuji BMC
45
+ DO_BIT(HFGITR, TLBIRVALE1IS),
41
46
+ DO_BIT(HFGITR, TLBIRVAALE1IS),
42
Supported devices
47
+ DO_BIT(HFGITR, TLBIRVAE1),
43
-----------------
48
+ DO_BIT(HFGITR, TLBIRVAAE1),
49
+ DO_BIT(HFGITR, TLBIRVALE1),
50
+ DO_BIT(HFGITR, TLBIRVAALE1),
51
+ DO_BIT(HFGITR, TLBIVMALLE1),
52
+ DO_BIT(HFGITR, TLBIVAE1),
53
+ DO_BIT(HFGITR, TLBIASIDE1),
54
+ DO_BIT(HFGITR, TLBIVAAE1),
55
+ DO_BIT(HFGITR, TLBIVALE1),
56
+ DO_BIT(HFGITR, TLBIVAALE1),
57
} FGTBit;
58
59
#undef DO_BIT
60
diff --git a/target/arm/helper.c b/target/arm/helper.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/helper.c
63
+++ b/target/arm/helper.c
64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
65
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
66
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
67
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
68
+ .fgt = FGT_TLBIVMALLE1IS,
69
.writefn = tlbi_aa64_vmalle1is_write },
70
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
71
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
72
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
73
+ .fgt = FGT_TLBIVAE1IS,
74
.writefn = tlbi_aa64_vae1is_write },
75
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
76
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
77
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
78
+ .fgt = FGT_TLBIASIDE1IS,
79
.writefn = tlbi_aa64_vmalle1is_write },
80
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
81
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
82
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
83
+ .fgt = FGT_TLBIVAAE1IS,
84
.writefn = tlbi_aa64_vae1is_write },
85
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
86
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
87
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
88
+ .fgt = FGT_TLBIVALE1IS,
89
.writefn = tlbi_aa64_vae1is_write },
90
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
91
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
92
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
93
+ .fgt = FGT_TLBIVAALE1IS,
94
.writefn = tlbi_aa64_vae1is_write },
95
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
97
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
98
+ .fgt = FGT_TLBIVMALLE1,
99
.writefn = tlbi_aa64_vmalle1_write },
100
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
101
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
102
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
103
+ .fgt = FGT_TLBIVAE1,
104
.writefn = tlbi_aa64_vae1_write },
105
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
106
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
107
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
108
+ .fgt = FGT_TLBIASIDE1,
109
.writefn = tlbi_aa64_vmalle1_write },
110
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
111
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
112
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
113
+ .fgt = FGT_TLBIVAAE1,
114
.writefn = tlbi_aa64_vae1_write },
115
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
116
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
117
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
118
+ .fgt = FGT_TLBIVALE1,
119
.writefn = tlbi_aa64_vae1_write },
120
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
121
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
122
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
123
+ .fgt = FGT_TLBIVAALE1,
124
.writefn = tlbi_aa64_vae1_write },
125
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
126
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
127
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
128
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
129
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
130
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
131
+ .fgt = FGT_TLBIRVAE1IS,
132
.writefn = tlbi_aa64_rvae1is_write },
133
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
134
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
135
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
136
+ .fgt = FGT_TLBIRVAAE1IS,
137
.writefn = tlbi_aa64_rvae1is_write },
138
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
139
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
140
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
141
+ .fgt = FGT_TLBIRVALE1IS,
142
.writefn = tlbi_aa64_rvae1is_write },
143
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
144
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
145
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
146
+ .fgt = FGT_TLBIRVAALE1IS,
147
.writefn = tlbi_aa64_rvae1is_write },
148
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
149
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
150
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
151
+ .fgt = FGT_TLBIRVAE1OS,
152
.writefn = tlbi_aa64_rvae1is_write },
153
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
154
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
155
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
156
+ .fgt = FGT_TLBIRVAAE1OS,
157
.writefn = tlbi_aa64_rvae1is_write },
158
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
159
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
160
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
161
+ .fgt = FGT_TLBIRVALE1OS,
162
.writefn = tlbi_aa64_rvae1is_write },
163
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
164
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
165
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
166
+ .fgt = FGT_TLBIRVAALE1OS,
167
.writefn = tlbi_aa64_rvae1is_write },
168
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
169
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
170
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
171
+ .fgt = FGT_TLBIRVAE1,
172
.writefn = tlbi_aa64_rvae1_write },
173
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
174
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
175
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
176
+ .fgt = FGT_TLBIRVAAE1,
177
.writefn = tlbi_aa64_rvae1_write },
178
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
179
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
180
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
181
+ .fgt = FGT_TLBIRVALE1,
182
.writefn = tlbi_aa64_rvae1_write },
183
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
184
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
185
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
186
+ .fgt = FGT_TLBIRVAALE1,
187
.writefn = tlbi_aa64_rvae1_write },
188
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
189
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
190
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
191
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
192
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
193
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
194
+ .fgt = FGT_TLBIVMALLE1OS,
195
.writefn = tlbi_aa64_vmalle1is_write },
196
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
197
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
198
+ .fgt = FGT_TLBIVAE1OS,
199
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
200
.writefn = tlbi_aa64_vae1is_write },
201
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
202
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
203
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
204
+ .fgt = FGT_TLBIASIDE1OS,
205
.writefn = tlbi_aa64_vmalle1is_write },
206
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
207
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
208
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
209
+ .fgt = FGT_TLBIVAAE1OS,
210
.writefn = tlbi_aa64_vae1is_write },
211
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
212
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
213
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
214
+ .fgt = FGT_TLBIVALE1OS,
215
.writefn = tlbi_aa64_vae1is_write },
216
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
217
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
218
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
219
+ .fgt = FGT_TLBIVAALE1OS,
220
.writefn = tlbi_aa64_vae1is_write },
221
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
222
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
44
--
223
--
45
2.25.1
224
2.34.1
46
47
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 48..63.
2
3
3
This is the latest URL for the OpenBMC CI. The old URL still works, but
4
Some of these bits are for trapping instructions which are
4
redirects.
5
not in the system instruction encoding (i.e. which are
6
not handled by the ARMCPRegInfo mechanism):
7
* ERET, ERETAA, ERETAB
8
* SVC
5
9
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
We will have to handle those separately and manually.
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
8
Message-id: 20211117065752.330632-3-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org
10
---
17
---
11
docs/system/arm/aspeed.rst | 2 +-
18
target/arm/cpregs.h | 4 ++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
19
target/arm/helper.c | 9 +++++++++
20
2 files changed, 13 insertions(+)
13
21
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
22
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
24
--- a/target/arm/cpregs.h
17
+++ b/docs/system/arm/aspeed.rst
25
+++ b/target/arm/cpregs.h
18
@@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to
26
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
19
load a Linux kernel or from a firmware. Images can be downloaded from
27
DO_BIT(HFGITR, TLBIVAAE1),
20
the OpenBMC jenkins :
28
DO_BIT(HFGITR, TLBIVALE1),
21
29
DO_BIT(HFGITR, TLBIVAALE1),
22
- https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
30
+ DO_BIT(HFGITR, CFPRCTX),
23
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
31
+ DO_BIT(HFGITR, DVPRCTX),
24
32
+ DO_BIT(HFGITR, CPPRCTX),
25
or directly from the OpenBMC GitHub release repository :
33
+ DO_BIT(HFGITR, DCCVAC),
34
} FGTBit;
35
36
#undef DO_BIT
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
42
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
43
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
44
.access = PL0_W, .type = ARM_CP_NOP,
45
+ .fgt = FGT_DCCVAC,
46
.accessfn = aa64_cacheop_poc_access },
47
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
48
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
50
{ .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
51
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
52
.type = ARM_CP_NOP, .access = PL0_W,
53
+ .fgt = FGT_DCCVAC,
54
.accessfn = aa64_cacheop_poc_access },
55
{ .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
56
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
57
.type = ARM_CP_NOP, .access = PL0_W,
58
+ .fgt = FGT_DCCVAC,
59
.accessfn = aa64_cacheop_poc_access },
60
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
62
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
63
static const ARMCPRegInfo predinv_reginfo[] = {
64
{ .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
65
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
66
+ .fgt = FGT_CFPRCTX,
67
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
68
{ .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
69
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
70
+ .fgt = FGT_DVPRCTX,
71
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
72
{ .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
73
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
74
+ .fgt = FGT_CPPRCTX,
75
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
76
/*
77
* Note the AArch32 opcodes have a different OPC1.
78
*/
79
{ .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
80
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
81
+ .fgt = FGT_CFPRCTX,
82
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
83
{ .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
84
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
85
+ .fgt = FGT_DVPRCTX,
86
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
87
{ .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
88
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
89
+ .fgt = FGT_CPPRCTX,
90
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
91
};
26
92
27
--
93
--
28
2.25.1
94
2.34.1
29
30
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the HFGITR_EL2.ERET fine-grained trap. This traps
2
execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is
3
reported with a syndrome value of 0x1a.
2
4
3
For A64, any input to an indirect branch can cause this.
5
The trap must take precedence over a possible pointer-authentication
6
trap for ERETAA and ERETAB.
4
7
5
For A32, many indirect branch paths force the branch to be aligned,
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
but BXWritePC does not. This includes the BX instruction but also
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
10
Tested-by: Fuad Tabba <tabba@google.com>
8
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
11
Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
9
exception or force align the PC.
12
Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
13
---
14
target/arm/cpu.h | 1 +
15
target/arm/syndrome.h | 10 ++++++++++
16
target/arm/translate.h | 2 ++
17
target/arm/helper.c | 3 +++
18
target/arm/translate-a64.c | 10 ++++++++++
19
5 files changed, 26 insertions(+)
10
20
11
We choose to raise an exception because we have the infrastructure,
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
it makes the generated code for gen_bx simpler, and it has the
13
possibility of catching more guest bugs.
14
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/helper.h | 1 +
20
target/arm/syndrome.h | 5 ++++
21
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
22
target/arm/tlb_helper.c | 18 ++++++++++++++
23
target/arm/translate-a64.c | 15 ++++++++++++
24
target/arm/translate.c | 22 ++++++++++++++++-
25
6 files changed, 87 insertions(+), 20 deletions(-)
26
27
diff --git a/target/arm/helper.h b/target/arm/helper.h
28
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.h
23
--- a/target/arm/cpu.h
30
+++ b/target/arm/helper.h
24
+++ b/target/arm/cpu.h
31
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
25
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
32
DEF_HELPER_2(exception_internal, void, env, i32)
26
FIELD(TBFLAG_A64, SVL, 24, 4)
33
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
27
/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
34
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
28
FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
35
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
29
+FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
36
DEF_HELPER_1(setend, void, env)
30
37
DEF_HELPER_2(wfi, void, env, i32)
31
/*
38
DEF_HELPER_1(wfe, void, env)
32
* Helpers for using the above.
39
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
33
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
40
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/syndrome.h
35
--- a/target/arm/syndrome.h
42
+++ b/target/arm/syndrome.h
36
+++ b/target/arm/syndrome.h
43
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void)
37
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
44
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
38
EC_AA64_SMC = 0x17,
39
EC_SYSTEMREGISTERTRAP = 0x18,
40
EC_SVEACCESSTRAP = 0x19,
41
+ EC_ERETTRAP = 0x1a,
42
EC_SMETRAP = 0x1d,
43
EC_INSNABORT = 0x20,
44
EC_INSNABORT_SAME_EL = 0x21,
45
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
46
return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
45
}
47
}
46
48
47
+static inline uint32_t syn_pcalignment(void)
49
+/*
50
+ * eret_op is bits [1:0] of the ERET instruction, so:
51
+ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
52
+ */
53
+static inline uint32_t syn_erettrap(int eret_op)
48
+{
54
+{
49
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
55
+ return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
50
+}
56
+}
51
+
57
+
52
#endif /* TARGET_ARM_SYNDROME_H */
58
static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
53
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
59
{
60
return (EC_SMETRAP << ARM_EL_EC_SHIFT)
61
diff --git a/target/arm/translate.h b/target/arm/translate.h
54
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
55
--- a/linux-user/aarch64/cpu_loop.c
63
--- a/target/arm/translate.h
56
+++ b/linux-user/aarch64/cpu_loop.c
64
+++ b/target/arm/translate.h
57
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
65
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
58
break;
66
bool mve_no_pred;
59
case EXCP_PREFETCH_ABORT:
67
/* True if fine-grained traps are active */
60
case EXCP_DATA_ABORT:
68
bool fgt_active;
61
- /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
69
+ /* True if fine-grained trap on ERET is enabled */
62
ec = syn_get_ec(env->exception.syndrome);
70
+ bool fgt_eret;
63
- assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
71
/*
64
-
72
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
65
- /* Both EC have the same format for FSC, or close enough. */
73
* < 0, set by the current instruction.
66
- fsc = extract32(env->exception.syndrome, 0, 6);
74
diff --git a/target/arm/helper.c b/target/arm/helper.c
67
- switch (fsc) {
68
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
69
- si_signo = TARGET_SIGSEGV;
70
- si_code = TARGET_SEGV_MAPERR;
71
+ switch (ec) {
72
+ case EC_DATAABORT:
73
+ case EC_INSNABORT:
74
+ /* Both EC have the same format for FSC, or close enough. */
75
+ fsc = extract32(env->exception.syndrome, 0, 6);
76
+ switch (fsc) {
77
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
78
+ si_signo = TARGET_SIGSEGV;
79
+ si_code = TARGET_SEGV_MAPERR;
80
+ break;
81
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
82
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
83
+ si_signo = TARGET_SIGSEGV;
84
+ si_code = TARGET_SEGV_ACCERR;
85
+ break;
86
+ case 0x11: /* Synchronous Tag Check Fault */
87
+ si_signo = TARGET_SIGSEGV;
88
+ si_code = TARGET_SEGV_MTESERR;
89
+ break;
90
+ case 0x21: /* Alignment fault */
91
+ si_signo = TARGET_SIGBUS;
92
+ si_code = TARGET_BUS_ADRALN;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
break;
98
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
99
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
100
- si_signo = TARGET_SIGSEGV;
101
- si_code = TARGET_SEGV_ACCERR;
102
- break;
103
- case 0x11: /* Synchronous Tag Check Fault */
104
- si_signo = TARGET_SIGSEGV;
105
- si_code = TARGET_SEGV_MTESERR;
106
- break;
107
- case 0x21: /* Alignment fault */
108
+ case EC_PCALIGNMENT:
109
si_signo = TARGET_SIGBUS;
110
si_code = TARGET_BUS_ADRALN;
111
break;
112
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
113
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/tlb_helper.c
76
--- a/target/arm/helper.c
115
+++ b/target/arm/tlb_helper.c
77
+++ b/target/arm/helper.c
116
@@ -XXX,XX +XXX,XX @@
78
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
117
#include "cpu.h"
79
118
#include "internals.h"
80
if (arm_fgt_active(env, el)) {
119
#include "exec/exec-all.h"
81
DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
120
+#include "exec/helper-proto.h"
82
+ if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
121
83
+ DP_TBFLAG_A64(flags, FGT_ERET, 1);
122
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
84
+ }
123
unsigned int target_el,
85
}
124
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
86
125
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
87
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
126
}
127
128
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
129
+{
130
+ ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
131
+ int target_el = exception_target_el(env);
132
+ int mmu_idx = cpu_mmu_index(env, true);
133
+ uint32_t fsc;
134
+
135
+ env->exception.vaddress = pc;
136
+
137
+ /*
138
+ * Note that the fsc is not applicable to this exception,
139
+ * since any syndrome is pcalignment not insn_abort.
140
+ */
141
+ env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc);
142
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el);
143
+}
144
+
145
#if !defined(CONFIG_USER_ONLY)
146
147
/*
148
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
88
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
149
index XXXXXXX..XXXXXXX 100644
89
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/translate-a64.c
90
--- a/target/arm/translate-a64.c
151
+++ b/target/arm/translate-a64.c
91
+++ b/target/arm/translate-a64.c
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
92
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
153
uint64_t pc = s->base.pc_next;
93
if (op4 != 0) {
154
uint32_t insn;
94
goto do_unallocated;
155
95
}
156
+ /* Singlestep exceptions have the highest priority. */
96
+ if (s->fgt_eret) {
157
if (s->ss_active && !s->pstate_ss) {
97
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
158
/* Singlestep state is Active-pending.
98
+ return;
159
* If we're in this state at the start of a TB then either
99
+ }
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
100
dst = tcg_temp_new_i64();
161
return;
101
tcg_gen_ld_i64(dst, cpu_env,
162
}
102
offsetof(CPUARMState, elr_el[s->current_el]));
163
103
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
164
+ if (pc & 3) {
104
if (rn != 0x1f || op4 != 0x1f) {
165
+ /*
105
goto do_unallocated;
166
+ * PC alignment fault. This has priority over the instruction abort
106
}
167
+ * that we would receive from a translation fault via arm_ldl_code.
107
+ /* The FGT trap takes precedence over an auth trap. */
168
+ * This should only be possible after an indirect branch, at the
108
+ if (s->fgt_eret) {
169
+ * start of the TB.
109
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
170
+ */
110
+ return;
171
+ assert(s->base.num_insns == 1);
111
+ }
172
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
112
dst = tcg_temp_new_i64();
173
+ s->base.is_jmp = DISAS_NORETURN;
113
tcg_gen_ld_i64(dst, cpu_env,
174
+ s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
114
offsetof(CPUARMState, elr_el[s->current_el]));
175
+ return;
115
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
176
+ }
116
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
177
+
117
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
178
s->pc_curr = pc;
118
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
179
insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
119
+ dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
180
s->insn = insn;
120
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
181
diff --git a/target/arm/translate.c b/target/arm/translate.c
121
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
182
index XXXXXXX..XXXXXXX 100644
122
dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
183
--- a/target/arm/translate.c
184
+++ b/target/arm/translate.c
185
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
186
uint32_t pc = dc->base.pc_next;
187
unsigned int insn;
188
189
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
190
+ /* Singlestep exceptions have the highest priority. */
191
+ if (arm_check_ss_active(dc)) {
192
+ dc->base.pc_next = pc + 4;
193
+ return;
194
+ }
195
+
196
+ if (pc & 3) {
197
+ /*
198
+ * PC alignment fault. This has priority over the instruction abort
199
+ * that we would receive from a translation fault via arm_ldl_code
200
+ * (or the execution of the kernelpage entrypoint). This should only
201
+ * be possible after an indirect branch, at the start of the TB.
202
+ */
203
+ assert(dc->base.num_insns == 1);
204
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
205
+ dc->base.is_jmp = DISAS_NORETURN;
206
+ dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
207
+ return;
208
+ }
209
+
210
+ if (arm_check_kernelpage(dc)) {
211
dc->base.pc_next = pc + 4;
212
return;
213
}
214
--
123
--
215
2.25.1
124
2.34.1
216
217
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
2
These trap execution of the SVC instruction from AArch32 and AArch64.
3
(As usual, AArch32 can only trap from EL0, as fine grained traps are
4
disabled with an AArch32 EL1.)
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Fuad Tabba <tabba@google.com>
9
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
10
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
6
---
11
---
7
target/arm/translate.c | 9 +++++----
12
target/arm/cpu.h | 1 +
8
1 file changed, 5 insertions(+), 4 deletions(-)
13
target/arm/translate.h | 2 ++
14
target/arm/helper.c | 20 ++++++++++++++++++++
15
target/arm/translate-a64.c | 9 ++++++++-
16
target/arm/translate.c | 12 +++++++++---
17
5 files changed, 40 insertions(+), 4 deletions(-)
9
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
24
FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
25
FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
26
FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
27
+FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
28
29
/*
30
* Bit usage when in AArch32 state, both A- and M-profile.
31
diff --git a/target/arm/translate.h b/target/arm/translate.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/translate.h
34
+++ b/target/arm/translate.h
35
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
36
bool fgt_active;
37
/* True if fine-grained trap on ERET is enabled */
38
bool fgt_eret;
39
+ /* True if fine-grained trap on SVC is enabled */
40
+ bool fgt_svc;
41
/*
42
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
43
* < 0, set by the current instruction.
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper.c
47
+++ b/target/arm/helper.c
48
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
49
return arm_mmu_idx_el(env, arm_current_el(env));
50
}
51
52
+static inline bool fgt_svc(CPUARMState *env, int el)
53
+{
54
+ /*
55
+ * Assuming fine-grained-traps are active, return true if we
56
+ * should be trapping on SVC instructions. Only AArch64 can
57
+ * trap on an SVC at EL1, but we don't need to special-case this
58
+ * because if this is AArch32 EL1 then arm_fgt_active() is false.
59
+ * We also know el is 0 or 1.
60
+ */
61
+ return el == 0 ?
62
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
63
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
64
+}
65
+
66
static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
67
ARMMMUIdx mmu_idx,
68
CPUARMTBFlags flags)
69
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
70
71
if (arm_fgt_active(env, el)) {
72
DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
73
+ if (fgt_svc(env, el)) {
74
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
75
+ }
76
}
77
78
if (env->uncached_cpsr & CPSR_IL) {
79
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
80
if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
81
DP_TBFLAG_A64(flags, FGT_ERET, 1);
82
}
83
+ if (fgt_svc(env, el)) {
84
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
85
+ }
86
}
87
88
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
89
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/translate-a64.c
92
+++ b/target/arm/translate-a64.c
93
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
94
int opc = extract32(insn, 21, 3);
95
int op2_ll = extract32(insn, 0, 5);
96
int imm16 = extract32(insn, 5, 16);
97
+ uint32_t syndrome;
98
99
switch (opc) {
100
case 0:
101
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
102
*/
103
switch (op2_ll) {
104
case 1: /* SVC */
105
+ syndrome = syn_aa64_svc(imm16);
106
+ if (s->fgt_svc) {
107
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
108
+ break;
109
+ }
110
gen_ss_advance(s);
111
- gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
112
+ gen_exception_insn(s, 4, EXCP_SWI, syndrome);
113
break;
114
case 2: /* HVC */
115
if (s->current_el == 0) {
116
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
117
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
118
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
119
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
120
+ dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
121
dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
122
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
123
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
124
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
index XXXXXXX..XXXXXXX 100644
125
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate.c
126
--- a/target/arm/translate.c
13
+++ b/target/arm/translate.c
127
+++ b/target/arm/translate.c
14
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
128
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
15
{
129
(a->imm == semihost_imm)) {
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
130
gen_exception_internal_insn(s, EXCP_SEMIHOST);
17
CPUARMState *env = cpu->env_ptr;
131
} else {
18
+ uint32_t pc = dc->base.pc_next;
132
- gen_update_pc(s, curr_insn_len(s));
19
unsigned int insn;
133
- s->svc_imm = a->imm;
20
134
- s->base.is_jmp = DISAS_SWI;
21
if (arm_pre_translate_insn(dc)) {
135
+ if (s->fgt_svc) {
22
- dc->base.pc_next += 4;
136
+ uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
23
+ dc->base.pc_next = pc + 4;
137
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
24
return;
138
+ } else {
139
+ gen_update_pc(s, curr_insn_len(s));
140
+ s->svc_imm = a->imm;
141
+ s->base.is_jmp = DISAS_SWI;
142
+ }
25
}
143
}
26
144
return true;
27
- dc->pc_curr = dc->base.pc_next;
145
}
28
- insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
146
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
29
+ dc->pc_curr = pc;
147
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
30
+ insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
148
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
31
dc->insn = insn;
149
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
32
- dc->base.pc_next += 4;
150
+ dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
33
+ dc->base.pc_next = pc + 4;
151
34
disas_arm_insn(dc, insn);
152
if (arm_feature(env, ARM_FEATURE_M)) {
35
153
dc->vfp_enabled = 1;
36
arm_post_translate_insn(dc);
37
--
154
--
38
2.25.1
155
2.34.1
39
40
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
2
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
3
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
4
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
5
AArch32 equivalents). This trapping is independent of whether
6
fine-grained traps are enabled or not.
2
7
3
Both single-step and pc alignment faults have priority over
8
Implement these extra traps. (We don't implement DBGDTR_EL0,
4
breakpoint exceptions.
9
DBGDTRRX_EL0 and DBGDTRTX_EL0.)
5
10
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Fuad Tabba <tabba@google.com>
14
Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
15
Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
9
---
16
---
10
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
17
target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++----
11
1 file changed, 23 insertions(+)
18
1 file changed, 31 insertions(+), 4 deletions(-)
12
19
13
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
20
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/debug_helper.c
22
--- a/target/arm/debug_helper.c
16
+++ b/target/arm/debug_helper.c
23
+++ b/target/arm/debug_helper.c
17
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
24
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
25
return CP_ACCESS_OK;
26
}
27
28
+/*
29
+ * Check for traps to Debug Comms Channel registers. If FEAT_FGT
30
+ * is implemented then these are controlled by MDCR_EL2.TDCC for
31
+ * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
32
+ * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
33
+ */
34
+static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
35
+ bool isread)
36
+{
37
+ int el = arm_current_el(env);
38
+ uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
39
+ bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
40
+ (arm_hcr_el2_eff(env) & HCR_TGE);
41
+ bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
42
+ (mdcr_el2 & MDCR_TDCC);
43
+ bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
44
+ (env->cp15.mdcr_el3 & MDCR_TDCC);
45
+
46
+ if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
47
+ return CP_ACCESS_TRAP_EL2;
48
+ }
49
+ if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
50
+ return CP_ACCESS_TRAP_EL3;
51
+ }
52
+ return CP_ACCESS_OK;
53
+}
54
+
55
static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
56
uint64_t value)
18
{
57
{
19
ARMCPU *cpu = ARM_CPU(cs);
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
20
CPUARMState *env = &cpu->env;
59
*/
21
+ target_ulong pc;
60
{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
22
int n;
61
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
23
62
- .access = PL0_R, .accessfn = access_tda,
63
+ .access = PL0_R, .accessfn = access_tdcc,
64
.type = ARM_CP_CONST, .resetvalue = 0 },
24
/*
65
/*
25
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
66
* OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
26
return false;
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
27
}
68
*/
28
69
{ .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
29
+ /*
70
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
30
+ * Single-step exceptions have priority over breakpoint exceptions.
71
- .access = PL1_RW, .accessfn = access_tda,
31
+ * If single-step state is active-pending, suppress the bp.
72
+ .access = PL1_RW, .accessfn = access_tdcc,
32
+ */
73
.type = ARM_CP_CONST, .resetvalue = 0 },
33
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
74
{ .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
34
+ return false;
75
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
35
+ }
76
- .access = PL1_RW, .accessfn = access_tda,
36
+
77
+ .access = PL1_RW, .accessfn = access_tdcc,
37
+ /*
78
.type = ARM_CP_CONST, .resetvalue = 0 },
38
+ * PC alignment faults have priority over breakpoint exceptions.
79
/*
39
+ */
80
* OSECCR_EL1 provides a mechanism for an operating system
40
+ pc = is_a64(env) ? env->pc : env->regs[15];
81
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
41
+ if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
82
*/
42
+ return false;
83
{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
43
+ }
84
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
44
+
85
- .access = PL1_RW, .accessfn = access_tda,
45
+ /*
86
+ .access = PL1_RW, .accessfn = access_tdcc,
46
+ * Instruction aborts have priority over breakpoint exceptions.
87
.type = ARM_CP_NOP },
47
+ * TODO: We would need to look up the page for PC and verify that
88
/*
48
+ * it is present and executable.
89
* Dummy DBGCLAIM registers.
49
+ */
50
+
51
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
52
if (bp_wp_matches(cpu, n, false)) {
53
return true;
54
--
90
--
55
2.25.1
91
2.34.1
56
57
diff view generated by jsdifflib
1
In the SSE decode function gen_sse(), we combine a byte
1
Update the ID registers for TCG's '-cpu max' to report the
2
'b' and a value 'b1' which can be [0..3], and switch on them:
2
presence of FEAT_FGT Fine-Grained Traps support.
3
b |= (b1 << 8);
4
switch (b) {
5
...
6
default:
7
unknown_op:
8
gen_unknown_opcode(env, s);
9
return;
10
}
11
3
12
In three cases inside this switch, we were then also checking for
13
"if (b1 >= 2) { goto unknown_op; }".
14
However, this can never happen, because the 'case' values in each place
15
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
16
cases to the default already.
17
18
This check was added in commit c045af25a52e9 in 2010; the added code
19
was unnecessary then as well, and was apparently intended only to
20
ensure that we never accidentally ended up indexing off the end
21
of an sse_op_table with only 2 entries as a result of future bugs
22
in the decode logic.
23
24
Change the checks to assert() instead, and make sure they're always
25
immediately before the array access they are protecting.
26
27
Fixes: Coverity CID 1460207
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Fuad Tabba <tabba@google.com>
7
Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
8
Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
30
---
9
---
31
target/i386/tcg/translate.c | 12 +++---------
10
docs/system/arm/emulation.rst | 1 +
32
1 file changed, 3 insertions(+), 9 deletions(-)
11
target/arm/cpu64.c | 1 +
12
2 files changed, 2 insertions(+)
33
13
34
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
14
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
35
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
36
--- a/target/i386/tcg/translate.c
16
--- a/docs/system/arm/emulation.rst
37
+++ b/target/i386/tcg/translate.c
17
+++ b/docs/system/arm/emulation.rst
38
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
18
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
39
case 0x171: /* shift xmm, im */
19
- FEAT_ETS (Enhanced Translation Synchronization)
40
case 0x172:
20
- FEAT_EVT (Enhanced Virtualization Traps)
41
case 0x173:
21
- FEAT_FCMA (Floating-point complex number instructions)
42
- if (b1 >= 2) {
22
+- FEAT_FGT (Fine-Grained Traps)
43
- goto unknown_op;
23
- FEAT_FHM (Floating-point half-precision multiplication instructions)
44
- }
24
- FEAT_FP16 (Half-precision floating-point data processing)
45
val = x86_ldub_code(env, s);
25
- FEAT_FRINTTS (Floating-point to integer instructions)
46
if (is_xmm) {
26
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
47
tcg_gen_movi_tl(s->T0, val);
27
index XXXXXXX..XXXXXXX 100644
48
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
28
--- a/target/arm/cpu64.c
49
offsetof(CPUX86State, mmx_t0.MMX_L(1)));
29
+++ b/target/arm/cpu64.c
50
op1_offset = offsetof(CPUX86State,mmx_t0);
30
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
51
}
31
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
52
+ assert(b1 < 2);
32
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
53
sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
33
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
54
(((modrm >> 3)) & 7)][b1];
34
+ t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
55
if (!sse_fn_epp) {
35
cpu->isar.id_aa64mmfr0 = t;
56
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
36
57
rm = modrm & 7;
37
t = cpu->isar.id_aa64mmfr1;
58
reg = ((modrm >> 3) & 7) | REX_R(s);
59
mod = (modrm >> 6) & 3;
60
- if (b1 >= 2) {
61
- goto unknown_op;
62
- }
63
64
+ assert(b1 < 2);
65
sse_fn_epp = sse_op_table6[b].op[b1];
66
if (!sse_fn_epp) {
67
goto unknown_op;
68
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
69
rm = modrm & 7;
70
reg = ((modrm >> 3) & 7) | REX_R(s);
71
mod = (modrm >> 6) & 3;
72
- if (b1 >= 2) {
73
- goto unknown_op;
74
- }
75
76
+ assert(b1 < 2);
77
sse_fn_eppi = sse_op_table7[b].op[b1];
78
if (!sse_fn_eppi) {
79
goto unknown_op;
80
--
38
--
81
2.25.1
39
2.34.1
82
83
diff view generated by jsdifflib