Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are
using the wrong registers, which yields the wrong result when using
them.

This patch series fixes this issue by correcting the registers used.
It also takes the opportunity to move these instructions to decodetree.

v2:
- Change ISA310 flag to ISA300 in xscvqpdp

Matheus Ferst (2):
  target/ppc: fix xscvqpdp register access
  target/ppc: move xscvqpdp to decodetree

Victor Colombo (2):
  target/ppc: Fix xs{max,min}[cj]dp to use VSX registers
  target/ppc: Move xs{max,min}[cj]dp to decodetree

 target/ppc/fpu_helper.c             | 14 +++-----
 target/ppc/helper.h                 | 10 +++---
 target/ppc/insn32.decode            | 21 +++++++++--
 target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++--------
 target/ppc/translate/vsx-ops.c.inc  |  5 ---
 5 files changed, 68 insertions(+), 37 deletions(-)

-- 
2.25.1

On 12/13/21 13:09, Victor Colombo wrote:
> Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are
> using the wrong registers, which yields the wrong result when using
> them.
> 
> This patch series fixes this issue by correcting the registers used.
> It also takes the opportunity to move these instructions to decodetree.


Applied to ppc-next.

Thanks,

C.