| 1 | Last minute pullreq with one patch, fixing the GICv3 ICH_MISR_EL2.LRENP | 1 | The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a: |
|---|---|---|---|
| 2 | calculation. I went back-and-forth on whether to put this in, but: | ||
| 3 | * it's an effective regression from 6.1 (the bug itself has been | ||
| 4 | present since before then, but it was previously masked by the | ||
| 5 | other bug which we fixed in 9cee1efe92) | ||
| 6 | * I just realized it could cause a screaming maintenance interrupt | ||
| 7 | even for hypervisors like KVM that don't set LRENPIE | ||
| 8 | 2 | ||
| 9 | On the other hand this is very late and we haven't seen it be a | 3 | Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000) |
| 10 | problem with any guest except Qualcomm's hypervisor. So if you want | ||
| 11 | to decide it's better not going in that's OK too. | ||
| 12 | |||
| 13 | Tested on the gitlab CI and with a local test of nested KVM. | ||
| 14 | |||
| 15 | -- PMM | ||
| 16 | |||
| 17 | The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82: | ||
| 18 | |||
| 19 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-06 11:18:06 -0800) | ||
| 20 | 4 | ||
| 21 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 22 | 6 | ||
| 23 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211207 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328 |
| 24 | 8 | ||
| 25 | for you to fetch changes up to 2958e5150dfa297dd5a51fe57a29156b8744f07f: | 9 | for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a: |
| 26 | 10 | ||
| 27 | gicv3: fix ICH_MISR's LRENP computation (2021-12-07 15:30:08 +0000) | 11 | target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100) |
| 28 | 12 | ||
| 29 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 30 | target-arm queue: | 14 | target-arm queue: |
| 31 | * Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation | 15 | * fix part of the "TCG-disabled builds are broken" issue |
| 32 | of maintenance interrupts | ||
| 33 | 16 | ||
| 34 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 35 | Damien Hedde (1): | 18 | Philippe Mathieu-Daudé (1): |
| 36 | gicv3: fix ICH_MISR's LRENP computation | 19 | target/arm/gdbstub: Only advertise M-profile features if TCG available |
| 37 | 20 | ||
| 38 | hw/intc/arm_gicv3_cpuif.c | 3 ++- | 21 | target/arm/gdbstub.c | 5 +++-- |
| 39 | 1 file changed, 2 insertions(+), 1 deletion(-) | 22 | 1 file changed, 3 insertions(+), 2 deletions(-) |
| 40 | 23 | diff view generated by jsdifflib |
| 1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | According to the "Arm Generic Interrupt Controller Architecture | 3 | Cortex-M profile is only emulable from TCG accelerator. Restrict |
| 4 | Specification GIC architecture version 3 and 4" (version G: page 345 | 4 | the GDBstub features to its availability in order to avoid a link |
| 5 | for aarch64 or 509 for aarch32): | 5 | error when TCG is not enabled: |
| 6 | LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and | ||
| 7 | ICH_HCR.EOIcount is non-zero. | ||
| 8 | 6 | ||
| 9 | When only LRENPIE was set (and EOI count was zero), the LRENP bit was | 7 | Undefined symbols for architecture arm64: |
| 10 | wrongly set and MISR value was wrong. | 8 | "_arm_v7m_get_sp_ptr", referenced from: |
| 9 | _m_sysreg_get in target_arm_gdbstub.c.o | ||
| 10 | "_arm_v7m_mrs_control", referenced from: | ||
| 11 | _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o | ||
| 12 | ld: symbol(s) not found for architecture arm64 | ||
| 13 | clang: error: linker command failed with exit code 1 (use -v to see invocation) | ||
| 11 | 14 | ||
| 12 | As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, | 15 | Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext") |
| 13 | the maintenance interrupt was constantly fired. It happens since patch | 16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 14 | 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") | 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 15 | which fixed another bug about maintenance interrupt (most significant | 18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 16 | bits of misr, including this one, were ignored in the interrupt trigger). | 19 | Message-id: 20230322142902.69511-3-philmd@linaro.org |
| 17 | 20 | [PMM: add #include since I cherry-picked this patch from the series] | |
| 18 | Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers") | ||
| 19 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
| 20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 21 | Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com | ||
| 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 23 | --- | 22 | --- |
| 24 | hw/intc/arm_gicv3_cpuif.c | 3 ++- | 23 | target/arm/gdbstub.c | 5 +++-- |
| 25 | 1 file changed, 2 insertions(+), 1 deletion(-) | 24 | 1 file changed, 3 insertions(+), 2 deletions(-) |
| 26 | 25 | ||
| 27 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | 26 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
| 28 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 29 | --- a/hw/intc/arm_gicv3_cpuif.c | 28 | --- a/target/arm/gdbstub.c |
| 30 | +++ b/hw/intc/arm_gicv3_cpuif.c | 29 | +++ b/target/arm/gdbstub.c |
| 31 | @@ -XXX,XX +XXX,XX @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) | 30 | @@ -XXX,XX +XXX,XX @@ |
| 32 | /* Scan list registers and fill in the U, NP and EOI bits */ | 31 | #include "cpu.h" |
| 33 | eoi_maintenance_interrupt_state(cs, &value); | 32 | #include "exec/gdbstub.h" |
| 34 | 33 | #include "gdbstub/helpers.h" | |
| 35 | - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { | 34 | +#include "sysemu/tcg.h" |
| 36 | + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && | 35 | #include "internals.h" |
| 37 | + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { | 36 | #include "cpregs.h" |
| 38 | value |= ICH_MISR_EL2_LRENP; | 37 | |
| 38 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
| 39 | 2, "arm-vfp-sysregs.xml", 0); | ||
| 40 | } | ||
| 39 | } | 41 | } |
| 40 | 42 | - if (cpu_isar_feature(aa32_mve, cpu)) { | |
| 43 | + if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { | ||
| 44 | gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, | ||
| 45 | 1, "arm-m-profile-mve.xml", 0); | ||
| 46 | } | ||
| 47 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
| 48 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
| 49 | "system-registers.xml", 0); | ||
| 50 | |||
| 51 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
| 52 | + if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { | ||
| 53 | gdb_register_coprocessor(cs, | ||
| 54 | arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
| 55 | arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
| 41 | -- | 56 | -- |
| 42 | 2.25.1 | 57 | 2.34.1 |
| 43 | 58 | ||
| 44 | 59 | diff view generated by jsdifflib |