[PULL for-6.2 0/1] target-arm queue
[PULL 0/3] target-arm queue
1
Last minute pullreq with one patch, fixing the GICv3 ICH_MISR_EL2.LRENP
1
Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
2
calculation. I went back-and-forth on whether to put this in, but:
3
* it's an effective regression from 6.1 (the bug itself has been
4
present since before then, but it was previously masked by the
5
other bug which we fixed in 9cee1efe92)
6
* I just realized it could cause a screaming maintenance interrupt
7
even for hypervisors like KVM that don't set LRENPIE
8
9
On the other hand this is very late and we haven't seen it be a
10
problem with any guest except Qualcomm's hypervisor. So if you want
11
to decide it's better not going in that's OK too.
12
13
Tested on the gitlab CI and with a local test of nested KVM.
14
2
15
-- PMM
3
-- PMM
16
4
17
The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82:
5
The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
18
6
19
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-06 11:18:06 -0800)
7
Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
20
8
21
are available in the Git repository at:
9
are available in the Git repository at:
22
10
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211207
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
24
12
25
for you to fetch changes up to 2958e5150dfa297dd5a51fe57a29156b8744f07f:
13
for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
26
14
27
gicv3: fix ICH_MISR's LRENP computation (2021-12-07 15:30:08 +0000)
15
target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
28
16
29
----------------------------------------------------------------
17
----------------------------------------------------------------
30
target-arm queue:
18
target-arm queue:
31
* Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
19
* Fix KVM SVE ID register probe code
32
of maintenance interrupts
33
20
34
----------------------------------------------------------------
21
----------------------------------------------------------------
35
Damien Hedde (1):
22
Richard Henderson (3):
36
gicv3: fix ICH_MISR's LRENP computation
23
target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
24
target/arm: Set KVM_ARM_VCPU_SVE while probing the host
25
target/arm: Move sve probe inside kvm >= 4.15 branch
37
26
38
hw/intc/arm_gicv3_cpuif.c | 3 ++-
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
39
1 file changed, 2 insertions(+), 1 deletion(-)
28
1 file changed, 22 insertions(+), 23 deletions(-)
40
diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
28
2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
was always returning zero. This also obviates the adjustment
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
7
The effects of the bug are not visible, because the only thing that
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/kvm64.c | 27 +++++++++++++--------------
18
1 file changed, 13 insertions(+), 14 deletions(-)
19
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/kvm64.c
23
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
25
bool sve_supported;
26
bool pmu_supported = false;
27
uint64_t features = 0;
28
- uint64_t t;
29
int err;
30
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
struct kvm_vcpu_init init = { .target = -1, };
34
35
/*
36
- * Ask for Pointer Authentication if supported. We can't play the
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
38
- * whether we have the architected or IMPDEF version of PAuth, so
39
- * we have to use the actual ID regs.
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
41
+ * which is otherwise RAZ.
42
+ */
43
+ sve_supported = kvm_arm_sve_supported();
44
+ if (sve_supported) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
46
+ }
47
+
48
+ /*
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
*/
52
if (kvm_arm_pauth_supported()) {
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
}
56
}
57
58
- sve_supported = kvm_arm_sve_supported();
59
-
60
- /* Add feature bits that can't appear until after VCPU init. */
61
if (sve_supported) {
62
- t = ahcf->isar.id_aa64pfr0;
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
- ahcf->isar.id_aa64pfr0 = t;
65
-
66
/*
67
* There is a range of kernels between kernel commit 73433762fcae
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
- * SVE support, so we only read it here, rather than together with all
71
- * the other ID registers earlier.
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
*/
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
77
--
78
2.25.1
diff view generated by jsdifflib
[PULL 1/1] gicv3: fix ICH_MISR's LRENP computation
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
According to the "Arm Generic Interrupt Controller Architecture
3
The test for the IF block indicates no ID registers are exposed, much
4
Specification GIC architecture version 3 and 4" (version G: page 345
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
for aarch64 or 509 for aarch32):
6
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
7
ICH_HCR.EOIcount is non-zero.
8
5
9
When only LRENPIE was set (and EOI count was zero), the LRENP bit was
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
wrongly set and MISR value was wrong.
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
11
12
As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
13
the maintenance interrupt was constantly fired. It happens since patch
14
9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
15
which fixed another bug about maintenance interrupt (most significant
16
bits of misr, including this one, were ignored in the interrupt trigger).
17
18
Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
19
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
10
---
24
hw/intc/arm_gicv3_cpuif.c | 3 ++-
11
target/arm/kvm64.c | 22 +++++++++++-----------
25
1 file changed, 2 insertions(+), 1 deletion(-)
12
1 file changed, 11 insertions(+), 11 deletions(-)
26
13
27
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
28
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/intc/arm_gicv3_cpuif.c
16
--- a/target/arm/kvm64.c
30
+++ b/hw/intc/arm_gicv3_cpuif.c
17
+++ b/target/arm/kvm64.c
31
@@ -XXX,XX +XXX,XX @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
32
/* Scan list registers and fill in the U, NP and EOI bits */
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
33
eoi_maintenance_interrupt_state(cs, &value);
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
34
21
}
35
- if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
22
- }
36
+ if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
23
37
+ (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
24
- if (sve_supported) {
38
value |= ICH_MISR_EL2_LRENP;
25
- /*
26
- * There is a range of kernels between kernel commit 73433762fcae
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
29
- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
31
- */
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
34
+ if (sve_supported) {
35
+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
39
}
45
}
40
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
41
--
48
--
42
2.25.1
49
2.25.1
43
44
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.