Series comparison

-[PULL for-6.2 0/1] target-arm queue
+[PULL v2 00/11] target-arm queue
-Last minute pullreq with one patch, fixing the GICv3 ICH_MISR_EL2.LRENP
+Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
-calculation. I went back-and-forth on whether to put this in, but:
+ethernet device failed 'make check' on big-endian hosts.
  * it's an effective regression from 6.1 (the bug itself has been
    present since before then, but it was previously masked by the
    other bug which we fixed in 9cee1efe92)
  * I just realized it could cause a screaming maintenance interrupt
    even for hypervisors like KVM that don't set LRENPIE
 On the other hand this is very late and we haven't seen it be a
 problem with any guest except Qualcomm's hypervisor. So if you want
 to decide it's better not going in that's OK too.
 Tested on the gitlab CI and with a local test of nested KVM.
 -- PMM
-The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82:
+The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
-  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-06 11:18:06 -0800)
+  Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211207
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
-for you to fetch changes up to 2958e5150dfa297dd5a51fe57a29156b8744f07f:
+for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
-  gicv3: fix ICH_MISR's LRENP computation (2021-12-07 15:30:08 +0000)
+  target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
+ * Correctly initialize MDCR_EL2.HPMN
-   of maintenance interrupts
+ * versal: Use nr_apu_cpus in favor of hard coding 2
  * accel/tcg: Add URL of clang bug to comment about our workaround
  * Add support for FEAT_DIT, Data Independent Timing
  * Remove GPIO from unimplemented NPCM7XX
  * Fix SCR RES1 handling
  * Don't migrate CPUARMState.features
 ----------------------------------------------------------------
-Damien Hedde (1):
+Aaron Lindsay (1):
-      gicv3: fix ICH_MISR's LRENP computation
+      target/arm: Don't migrate CPUARMState.features
- hw/intc/arm_gicv3_cpuif.c | 3 ++-
+Daniel Müller (1):
-file changed, 2 insertions(+), 1 deletion(-)
+      target/arm: Correctly initialize MDCR_EL2.HPMN
+Edgar E. Iglesias (1):
+      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
+Hao Wu (1):
+      hw/arm: Remove GPIO from unimplemented NPCM7XX
+Mike Nawrocki (1):
+      target/arm: Fix SCR RES1 handling
+Peter Maydell (2):
+      arm: Update infocenter.arm.com URLs
+      accel/tcg: Add URL of clang bug to comment about our workaround
+Rebecca Cran (4):
+      target/arm: Add support for FEAT_DIT, Data Independent Timing
+      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
+      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
+      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
+ include/hw/dma/pl080.h                 |  7 ++--
+ include/hw/misc/arm_integrator_debug.h |  2 +-
+ include/hw/ssi/pl022.h                 |  5 ++-
+ target/arm/cpu.h                       | 17 ++++++++
+ target/arm/internals.h                 |  6 +++
+ accel/tcg/cpu-exec.c                   | 25 +++++++++---
+ hw/arm/aspeed_ast2600.c                |  2 +-
+ hw/arm/musca.c                         |  4 +-
+ hw/arm/npcm7xx.c                       |  8 ----
+ hw/arm/xlnx-versal.c                   |  4 +-
+ hw/misc/arm_integrator_debug.c         |  2 +-
+ hw/timer/arm_timer.c                   |  7 ++--
+ target/arm/cpu.c                       |  4 ++
+ target/arm/cpu64.c                     |  5 +++
+ target/arm/helper-a64.c                | 27 +++++++++++--
+ target/arm/helper.c                    | 71 +++++++++++++++++++++++++++-------
+ target/arm/machine.c                   |  2 +-
+ target/arm/op_helper.c                 |  9 +----
+ target/arm/translate-a64.c             | 12 ++++++
+files changed, 164 insertions(+), 55 deletions(-)

-[PULL 1/1] gicv3: fix ICH_MISR's LRENP computation
+Deleted patch
-From: Damien Hedde <damien.hedde@greensocs.com>
-According to the "Arm Generic Interrupt Controller Architecture
-Specification GIC architecture version 3 and 4" (version G: page 345
-for aarch64 or 509 for aarch32):
-LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
-ICH_HCR.EOIcount is non-zero.
-When only LRENPIE was set (and EOI count was zero), the LRENP bit was
-wrongly set and MISR value was wrong.
-As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
-the maintenance interrupt was constantly fired. It happens since patch
-cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
-which fixed another bug about maintenance interrupt (most significant
-bits of misr, including this one, were ignored in the interrupt trigger).
-Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
-Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/intc/arm_gicv3_cpuif.c | 3 ++-
-file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
-     /* Scan list registers and fill in the U, NP and EOI bits */
-     eoi_maintenance_interrupt_state(cs, &value);
--    if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
-+    if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
-+        (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
-         value |= ICH_MISR_EL2_LRENP;
-     }
---
-.25.1

Last minute pullreq with one patch, fixing the GICv3 ICH_MISR_EL2.LRENP
calculation. I went back-and-forth on whether to put this in, but:
 * it's an effective regression from 6.1 (the bug itself has been
   present since before then, but it was previously masked by the
   other bug which we fixed in 9cee1efe92)
 * I just realized it could cause a screaming maintenance interrupt
   even for hypervisors like KVM that don't set LRENPIE

On the other hand this is very late and we haven't seen it be a
problem with any guest except Qualcomm's hypervisor. So if you want
to decide it's better not going in that's OK too.

Tested on the gitlab CI and with a local test of nested KVM.

-- PMM

The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-06 11:18:06 -0800)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211207

for you to fetch changes up to 2958e5150dfa297dd5a51fe57a29156b8744f07f:

gicv3: fix ICH_MISR's LRENP computation (2021-12-07 15:30:08 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
   of maintenance interrupts

----------------------------------------------------------------
Damien Hedde (1):
      gicv3: fix ICH_MISR's LRENP computation

hw/intc/arm_gicv3_cpuif.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Damien Hedde <damien.hedde@greensocs.com>

According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.EOIcount is non-zero.

When only LRENPIE was set (and EOI count was zero), the LRENP bit was
wrongly set and MISR value was wrong.

As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
the maintenance interrupt was constantly fired. It happens since patch
9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
which fixed another bug about maintenance interrupt (most significant
bits of misr, including this one, were ignored in the interrupt trigger).

Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
     /* Scan list registers and fill in the U, NP and EOI bits */
     eoi_maintenance_interrupt_state(cs, &value);
 
-    if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
+    if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
+        (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
         value |= ICH_MISR_EL2_LRENP;
     }
 
-- 
2.25.1

Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
ethernet device failed 'make check' on big-endian hosts.

-- PMM

The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:

Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1

for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:

target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)

----------------------------------------------------------------
target-arm queue:
 * Correctly initialize MDCR_EL2.HPMN
 * versal: Use nr_apu_cpus in favor of hard coding 2
 * accel/tcg: Add URL of clang bug to comment about our workaround
 * Add support for FEAT_DIT, Data Independent Timing
 * Remove GPIO from unimplemented NPCM7XX
 * Fix SCR RES1 handling
 * Don't migrate CPUARMState.features

----------------------------------------------------------------
Aaron Lindsay (1):
      target/arm: Don't migrate CPUARMState.features

Daniel Müller (1):
      target/arm: Correctly initialize MDCR_EL2.HPMN

Edgar E. Iglesias (1):
      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2

Hao Wu (1):
      hw/arm: Remove GPIO from unimplemented NPCM7XX

Mike Nawrocki (1):
      target/arm: Fix SCR RES1 handling

Peter Maydell (2):
      arm: Update infocenter.arm.com URLs
      accel/tcg: Add URL of clang bug to comment about our workaround

Rebecca Cran (4):
      target/arm: Add support for FEAT_DIT, Data Independent Timing
      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU