[PULL for-6.2 0/1] target-arm queue
[PULL v2 00/29] target-arm queue
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Last minute pullreq with one patch, fixing the GICv3 ICH_MISR_EL2.LRENP
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v2: drop pvpanic-pci patches.
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calculation. I went back-and-forth on whether to put this in, but:
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* it's an effective regression from 6.1 (the bug itself has been
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present since before then, but it was previously masked by the
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other bug which we fixed in 9cee1efe92)
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* I just realized it could cause a screaming maintenance interrupt
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even for hypervisors like KVM that don't set LRENPIE
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On the other hand this is very late and we haven't seen it be a
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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problem with any guest except Qualcomm's hypervisor. So if you want
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to decide it's better not going in that's OK too.
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Tested on the gitlab CI and with a local test of nested KVM.
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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-- PMM
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The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82:
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Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-06 11:18:06 -0800)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211207
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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for you to fetch changes up to 2958e5150dfa297dd5a51fe57a29156b8744f07f:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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gicv3: fix ICH_MISR's LRENP computation (2021-12-07 15:30:08 +0000)
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
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* Implement IMPDEF pauth algorithm
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of maintenance interrupts
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* Support ARMv8.4-SEL2
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Damien Hedde (1):
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Gan Qixin (1):
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gicv3: fix ICH_MISR's LRENP computation
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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hw/intc/arm_gicv3_cpuif.c | 3 ++-
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Peter Maydell (1):
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1 file changed, 2 insertions(+), 1 deletion(-)
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docs: Build and install all the docs in a single manual
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Philippe Mathieu-Daudé (1):
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Richard Henderson (7):
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: Add cpu properties to control pauth
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target/arm: Use object_property_add_bool for "sve" property
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target/arm: Introduce PREDDESC field definitions
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Rémi Denis-Courmont (19):
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target/arm: remove redundant tests
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target/arm: add arm_is_el2_enabled() helper
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: factor MDCR_EL2 common handling
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: handle VMID change in secure state
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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docs/conf.py | 46 ++++-
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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diff view generated by jsdifflib
[PULL 1/1] gicv3: fix ICH_MISR's LRENP computation
Deleted patch
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From: Damien Hedde <damien.hedde@greensocs.com>
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According to the "Arm Generic Interrupt Controller Architecture
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Specification GIC architecture version 3 and 4" (version G: page 345
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for aarch64 or 509 for aarch32):
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LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
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ICH_HCR.EOIcount is non-zero.
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When only LRENPIE was set (and EOI count was zero), the LRENP bit was
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wrongly set and MISR value was wrong.
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As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
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the maintenance interrupt was constantly fired. It happens since patch
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9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
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which fixed another bug about maintenance interrupt (most significant
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bits of misr, including this one, were ignored in the interrupt trigger).
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Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
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Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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hw/intc/arm_gicv3_cpuif.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/intc/arm_gicv3_cpuif.c
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+++ b/hw/intc/arm_gicv3_cpuif.c
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@@ -XXX,XX +XXX,XX @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
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/* Scan list registers and fill in the U, NP and EOI bits */
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eoi_maintenance_interrupt_state(cs, &value);
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- if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
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+ if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
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+ (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
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value |= ICH_MISR_EL2_LRENP;
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}
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--
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2.25.1
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diff view generated by jsdifflib

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