[PULL 0/5] target-arm queue
[PULL 00/26] target-arm queue
1
Hi; this is a collection of mostly GIC related patches for rc3.
1
The following changes since commit e670f6d825d4dee248b311197fd4048469d6772b:
2
The "Update cached state after LPI state changes" fix is important
3
and fixes what would otherwise be a regression since we enable the
4
ITS by default in the virt board now. The others are not regressions
5
but I think are OK for rc3 as they're fairly self contained (and two
6
of them are fixes to new-in-6.2 functionality).
7
2
8
thanks
3
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into staging (2022-02-20 15:05:41 +0000)
9
-- PMM
10
11
The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
12
13
Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
14
4
15
are available in the Git repository at:
5
are available in the Git repository at:
16
6
17
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220221
18
8
19
for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
9
for you to fetch changes up to d6333e2543fa41aed4d33f77c808168373e39bff:
20
10
21
hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)
11
ui/cocoa: Fix the leak of qemu_console_get_label (2022-02-21 09:12:18 +0000)
22
12
23
----------------------------------------------------------------
13
----------------------------------------------------------------
24
target-arm queue:
14
arm, cocoa and misc:
25
* virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
15
* MAINTAINERS file updates
26
* GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
16
* Mark remaining global TypeInfo instances as const
27
* GICv3: Update cached state after LPI state changes
17
* checkpatch: Ensure that TypeInfos are const
28
* GICv3: Fix handling of LPIs in list registers
18
* tests/qtest: add qtests for npcm7xx sdhci
19
* arm hvf: Handle unknown ID registers as RES0
20
* Make KVM -cpu max exactly like -cpu host
21
* Fix '-cpu max' for HVF
22
* Support PAuth extension for hvf
23
* Kconfig: Add I2C_DEVICES device group
24
* Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
25
* hw/arm/armv7m: Handle disconnected clock inputs
26
* osdep.h: pull out various things into new header files
27
* hw/timer: fix a9gtimer vmstate
28
* hw/arm: add initial mori-bmc board
29
* ui/cocoa: Remove allowedFileTypes restriction in SavePanel
30
* ui/cocoa: Do not alert even without block devices
31
* ui/cocoa: Fix the leak of qemu_console_get_label
29
32
30
----------------------------------------------------------------
33
----------------------------------------------------------------
31
Alexander Graf (1):
34
Akihiko Odaki (3):
32
hw/arm/virt: Extend nested and mte checks to hvf
35
MAINTAINERS: Add Akihiko Odaki to macOS-relateds
36
ui/cocoa: Do not alert even without block devices
37
ui/cocoa: Fix the leak of qemu_console_get_label
33
38
34
Peter Maydell (3):
39
Alexander Graf (2):
35
hw/intc/arm_gicv3: Update cached state after LPI state changes
40
hvf: arm: Use macros for sysreg shift/masking
36
hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
41
hvf: arm: Handle unknown ID registers as RES0
37
hw/intc/arm_gicv3: fix handling of LPIs in list registers
38
42
39
Shashi Mallela (1):
43
Ani Sinha (1):
40
hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
44
MAINTAINERS: Adding myself as a reviewer of some components
41
45
42
hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++
46
Bernhard Beschow (2):
43
hw/arm/virt.c | 15 +++++++++------
47
Mark remaining global TypeInfo instances as const
44
hw/intc/arm_gicv3.c | 6 ++++--
48
checkpatch: Ensure that TypeInfos are const
45
hw/intc/arm_gicv3_cpuif.c | 9 ++++-----
46
hw/intc/arm_gicv3_its.c | 7 ++++---
47
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
48
6 files changed, 61 insertions(+), 20 deletions(-)
49
49
50
Patrick Venture (1):
51
hw/arm: add initial mori-bmc board
52
53
Pavel Dovgalyuk (1):
54
hw/timer: fix a9gtimer vmstate
55
56
Peter Maydell (14):
57
target/arm: Move '-cpu host' code to cpu64.c
58
target/arm: Use aarch64_cpu_register() for 'host' CPU type
59
target/arm: Make KVM -cpu max exactly like -cpu host
60
target/arm: Unindent unnecessary else-clause
61
target/arm: Fix '-cpu max' for HVF
62
target/arm: Support PAuth extension for hvf
63
Kconfig: Add I2C_DEVICES device group
64
Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
65
hw/arm/armv7m: Handle disconnected clock inputs
66
include: Move qemu_madvise() and related #defines to new qemu/madvise.h
67
include: Move qemu_mprotect_*() to new qemu/mprotect.h
68
include: Move QEMU_MAP_* constants to mmap-alloc.h
69
include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h
70
include: Move hardware version declarations to new qemu/hw-version.h
71
72
Philippe Mathieu-Daudé (1):
73
ui/cocoa: Remove allowedFileTypes restriction in SavePanel
74
75
Shengtan Mao (1):
76
tests/qtest: add qtests for npcm7xx sdhci
77
78
docs/devel/kconfig.rst | 8 +-
79
docs/system/arm/nuvoton.rst | 1 +
80
include/qemu/cacheinfo.h | 21 +++
81
include/qemu/hw-version.h | 27 ++++
82
include/qemu/madvise.h | 95 +++++++++++
83
include/qemu/mmap-alloc.h | 23 +++
84
include/qemu/mprotect.h | 14 ++
85
include/qemu/osdep.h | 132 ----------------
86
accel/tcg/translate-all.c | 1 +
87
backends/hostmem-file.c | 1 +
88
backends/hostmem.c | 1 +
89
hw/arm/armv7m.c | 26 ++-
90
hw/arm/npcm7xx_boards.c | 32 ++++
91
hw/arm/nseries.c | 1 +
92
hw/core/generic-loader.c | 2 +-
93
hw/core/guest-loader.c | 2 +-
94
hw/display/bcm2835_fb.c | 2 +-
95
hw/display/i2c-ddc.c | 2 +-
96
hw/display/macfb.c | 4 +-
97
hw/display/virtio-vga.c | 2 +-
98
hw/dma/bcm2835_dma.c | 2 +-
99
hw/i386/pc_piix.c | 2 +-
100
hw/i386/sgx-epc.c | 2 +-
101
hw/ide/core.c | 1 +
102
hw/intc/bcm2835_ic.c | 2 +-
103
hw/intc/bcm2836_control.c | 2 +-
104
hw/ipmi/ipmi.c | 4 +-
105
hw/mem/nvdimm.c | 2 +-
106
hw/mem/pc-dimm.c | 2 +-
107
hw/misc/bcm2835_mbox.c | 2 +-
108
hw/misc/bcm2835_powermgt.c | 2 +-
109
hw/misc/bcm2835_property.c | 2 +-
110
hw/misc/bcm2835_rng.c | 2 +-
111
hw/misc/pvpanic-isa.c | 2 +-
112
hw/misc/pvpanic-pci.c | 2 +-
113
hw/net/fsl_etsec/etsec.c | 2 +-
114
hw/ppc/prep_systemio.c | 2 +-
115
hw/ppc/spapr_iommu.c | 2 +-
116
hw/s390x/s390-pci-bus.c | 2 +-
117
hw/s390x/sclp.c | 2 +-
118
hw/s390x/tod-kvm.c | 2 +-
119
hw/s390x/tod-tcg.c | 2 +-
120
hw/s390x/tod.c | 2 +-
121
hw/scsi/lsi53c895a.c | 2 +-
122
hw/scsi/megasas.c | 1 +
123
hw/scsi/scsi-bus.c | 1 +
124
hw/scsi/scsi-disk.c | 1 +
125
hw/sd/allwinner-sdhost.c | 2 +-
126
hw/sd/aspeed_sdhci.c | 2 +-
127
hw/sd/bcm2835_sdhost.c | 2 +-
128
hw/sd/cadence_sdhci.c | 2 +-
129
hw/sd/npcm7xx_sdhci.c | 2 +-
130
hw/timer/a9gtimer.c | 21 +++
131
hw/usb/dev-mtp.c | 2 +-
132
hw/usb/host-libusb.c | 2 +-
133
hw/vfio/igd.c | 2 +-
134
hw/virtio/virtio-balloon.c | 1 +
135
hw/virtio/virtio-pmem.c | 2 +-
136
migration/postcopy-ram.c | 1 +
137
migration/qemu-file.c | 1 +
138
migration/ram.c | 1 +
139
plugins/loader.c | 1 +
140
qom/object.c | 4 +-
141
softmmu/physmem.c | 1 +
142
softmmu/vl.c | 1 +
143
target/arm/cpu.c | 30 ----
144
target/arm/cpu64.c | 331 +++++++++++++++++++++------------------
145
target/arm/hvf/hvf.c | 83 +++++++---
146
target/i386/cpu.c | 1 +
147
target/s390x/cpu_models.c | 1 +
148
tcg/region.c | 3 +
149
tcg/tcg.c | 1 +
150
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
151
util/atomic64.c | 1 +
152
util/cacheflush.c | 1 +
153
util/cacheinfo.c | 1 +
154
util/osdep.c | 3 +
155
util/oslib-posix.c | 1 +
156
MAINTAINERS | 5 +
157
hw/arm/Kconfig | 10 ++
158
hw/i2c/Kconfig | 5 +
159
hw/rtc/Kconfig | 2 +
160
hw/sensor/Kconfig | 5 +
161
scripts/checkpatch.pl | 1 +
162
tests/qtest/meson.build | 1 +
163
ui/cocoa.m | 15 +-
164
86 files changed, 822 insertions(+), 393 deletions(-)
165
create mode 100644 include/qemu/cacheinfo.h
166
create mode 100644 include/qemu/hw-version.h
167
create mode 100644 include/qemu/madvise.h
168
create mode 100644 include/qemu/mprotect.h
169
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
170
diff view generated by jsdifflib
New patch
[PULL 01/26] MAINTAINERS: Adding myself as a reviewer of some components
1
From: Ani Sinha <ani@anisinha.ca>
1
2
3
Added myself as a reviewer of vmgenid, unimplemented device and empty slot.
4
5
Signed-off-by: Ani Sinha <ani@anisinha.ca>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20220131122001.1476101-1-ani@anisinha.ca
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
MAINTAINERS | 3 +++
11
1 file changed, 3 insertions(+)
12
13
diff --git a/MAINTAINERS b/MAINTAINERS
14
index XXXXXXX..XXXXXXX 100644
15
--- a/MAINTAINERS
16
+++ b/MAINTAINERS
17
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/prom-env-test.c
18
19
VM Generation ID
20
S: Orphan
21
+R: Ani Sinha <ani@anisinha.ca>
22
F: hw/acpi/vmgenid.c
23
F: include/hw/acpi/vmgenid.h
24
F: docs/specs/vmgenid.txt
25
@@ -XXX,XX +XXX,XX @@ F: hw/misc/led.c
26
Unimplemented device
27
M: Peter Maydell <peter.maydell@linaro.org>
28
R: Philippe Mathieu-Daudé <f4bug@amsat.org>
29
+R: Ani Sinha <ani@anisinha.ca>
30
S: Maintained
31
F: include/hw/misc/unimp.h
32
F: hw/misc/unimp.c
33
@@ -XXX,XX +XXX,XX @@ F: hw/misc/unimp.c
34
Empty slot
35
M: Artyom Tarasenko <atar4qemu@gmail.com>
36
R: Philippe Mathieu-Daudé <f4bug@amsat.org>
37
+R: Ani Sinha <ani@anisinha.ca>
38
S: Maintained
39
F: include/hw/misc/empty_slot.h
40
F: hw/misc/empty_slot.c
41
--
42
2.25.1
43
44
diff view generated by jsdifflib
New patch
[PULL 02/26] tests/qtest: add qtests for npcm7xx sdhci
1
1
From: Shengtan Mao <stmao@google.com>
2
3
Reviewed-by: Hao Wu <wuhaotsh@google.com>
4
Reviewed-by: Chris Rauer <crauer@google.com>
5
Signed-off-by: Shengtan Mao <stmao@google.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Message-id: 20220208181843.4003568-1-venture@google.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++
12
tests/qtest/meson.build | 1 +
13
2 files changed, 216 insertions(+)
14
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
15
16
diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/tests/qtest/npcm7xx_sdhci-test.c
21
@@ -XXX,XX +XXX,XX @@
22
+/*
23
+ * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller
24
+ *
25
+ * Copyright (c) 2022 Google LLC
26
+ *
27
+ * This program is free software; you can redistribute it and/or modify it
28
+ * under the terms of the GNU General Public License as published by the
29
+ * Free Software Foundation; either version 2 of the License, or
30
+ * (at your option) any later version.
31
+ *
32
+ * This program is distributed in the hope that it will be useful, but WITHOUT
33
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
34
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
35
+ * for more details.
36
+ */
37
+
38
+#include "qemu/osdep.h"
39
+#include "hw/sd/npcm7xx_sdhci.h"
40
+
41
+#include "libqos/libqtest.h"
42
+#include "libqtest-single.h"
43
+#include "libqos/sdhci-cmd.h"
44
+
45
+#define NPCM7XX_REG_SIZE 0x100
46
+#define NPCM7XX_MMC_BA 0xF0842000
47
+#define NPCM7XX_BLK_SIZE 512
48
+#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30)
49
+
50
+char *sd_path;
51
+
52
+static QTestState *setup_sd_card(void)
53
+{
54
+ QTestState *qts = qtest_initf(
55
+ "-machine kudo-bmc "
56
+ "-device sd-card,drive=drive0 "
57
+ "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off",
58
+ sd_path);
59
+
60
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL);
61
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON,
62
+ SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE |
63
+ SDHC_CLOCK_INT_EN);
64
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD);
65
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8));
66
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID);
67
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR);
68
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0,
69
+ SDHC_SELECT_DESELECT_CARD);
70
+
71
+ return qts;
72
+}
73
+
74
+static void write_sdread(QTestState *qts, const char *msg)
75
+{
76
+ int fd, ret;
77
+ size_t len = strlen(msg);
78
+ char *rmsg = g_malloc(len);
79
+
80
+ /* write message to sd */
81
+ fd = open(sd_path, O_WRONLY);
82
+ g_assert(fd >= 0);
83
+ ret = write(fd, msg, len);
84
+ close(fd);
85
+ g_assert(ret == len);
86
+
87
+ /* read message using sdhci */
88
+ ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len);
89
+ g_assert(ret == len);
90
+ g_assert(!strcmp(rmsg, msg));
91
+
92
+ g_free(rmsg);
93
+}
94
+
95
+/* Check MMC can read values from sd */
96
+static void test_read_sd(void)
97
+{
98
+ QTestState *qts = setup_sd_card();
99
+
100
+ write_sdread(qts, "hello world");
101
+ write_sdread(qts, "goodbye");
102
+
103
+ qtest_quit(qts);
104
+}
105
+
106
+static void sdwrite_read(QTestState *qts, const char *msg)
107
+{
108
+ int fd, ret;
109
+ size_t len = strlen(msg);
110
+ char *rmsg = g_malloc(len);
111
+
112
+ /* write message using sdhci */
113
+ sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE);
114
+
115
+ /* read message from sd */
116
+ fd = open(sd_path, O_RDONLY);
117
+ g_assert(fd >= 0);
118
+ ret = read(fd, rmsg, len);
119
+ close(fd);
120
+ g_assert(ret == len);
121
+
122
+ g_assert(!strcmp(rmsg, msg));
123
+
124
+ g_free(rmsg);
125
+}
126
+
127
+/* Check MMC can write values to sd */
128
+static void test_write_sd(void)
129
+{
130
+ QTestState *qts = setup_sd_card();
131
+
132
+ sdwrite_read(qts, "hello world");
133
+ sdwrite_read(qts, "goodbye");
134
+
135
+ qtest_quit(qts);
136
+}
137
+
138
+/* Check SDHCI has correct default values. */
139
+static void test_reset(void)
140
+{
141
+ QTestState *qts = qtest_init("-machine kudo-bmc");
142
+ uint64_t addr = NPCM7XX_MMC_BA;
143
+ uint64_t end_addr = addr + NPCM7XX_REG_SIZE;
144
+ uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET,
145
+ NPCM7XX_PRSTVALS_1_RESET,
146
+ 0,
147
+ NPCM7XX_PRSTVALS_3_RESET,
148
+ 0,
149
+ 0};
150
+ int i;
151
+ uint32_t mask;
152
+
153
+ while (addr < end_addr) {
154
+ switch (addr - NPCM7XX_MMC_BA) {
155
+ case SDHC_PRNSTS:
156
+ /*
157
+ * ignores bits 20 to 24: they are changed when reading registers
158
+ */
159
+ mask = 0x1f00000;
160
+ g_assert_cmphex(qtest_readl(qts, addr) | mask, ==,
161
+ NPCM7XX_PRSNTS_RESET | mask);
162
+ addr += 4;
163
+ break;
164
+ case SDHC_BLKGAP:
165
+ g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET);
166
+ addr += 1;
167
+ break;
168
+ case SDHC_CAPAB:
169
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET);
170
+ addr += 8;
171
+ break;
172
+ case SDHC_MAXCURR:
173
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET);
174
+ addr += 8;
175
+ break;
176
+ case SDHC_HCVER:
177
+ g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET);
178
+ addr += 2;
179
+ break;
180
+ case NPCM7XX_PRSTVALS:
181
+ for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) {
182
+ g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==,
183
+ prstvals_resets[i]);
184
+ }
185
+ addr += NPCM7XX_PRSTVALS_SIZE * 2;
186
+ break;
187
+ default:
188
+ g_assert_cmphex(qtest_readb(qts, addr), ==, 0);
189
+ addr += 1;
190
+ }
191
+ }
192
+
193
+ qtest_quit(qts);
194
+}
195
+
196
+static void drive_destroy(void)
197
+{
198
+ unlink(sd_path);
199
+ g_free(sd_path);
200
+}
201
+
202
+static void drive_create(void)
203
+{
204
+ int fd, ret;
205
+ GError *error = NULL;
206
+
207
+ /* Create a temporary raw image */
208
+ fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error);
209
+ if (fd == -1) {
210
+ fprintf(stderr, "unable to create sdhci file: %s\n", error->message);
211
+ g_error_free(error);
212
+ }
213
+ g_assert(sd_path != NULL);
214
+
215
+ ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE);
216
+ g_assert_cmpint(ret, ==, 0);
217
+ g_message("%s", sd_path);
218
+ close(fd);
219
+}
220
+
221
+int main(int argc, char **argv)
222
+{
223
+ int ret;
224
+
225
+ drive_create();
226
+
227
+ g_test_init(&argc, &argv, NULL);
228
+
229
+ qtest_add_func("npcm7xx_sdhci/reset", test_reset);
230
+ qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd);
231
+ qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd);
232
+
233
+ ret = g_test_run();
234
+ drive_destroy();
235
+ return ret;
236
+}
237
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
238
index XXXXXXX..XXXXXXX 100644
239
--- a/tests/qtest/meson.build
240
+++ b/tests/qtest/meson.build
241
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
242
'npcm7xx_gpio-test',
243
'npcm7xx_pwm-test',
244
'npcm7xx_rng-test',
245
+ 'npcm7xx_sdhci-test',
246
'npcm7xx_smbus-test',
247
'npcm7xx_timer-test',
248
'npcm7xx_watchdog_timer-test'] + \
249
--
250
2.25.1
251
252
diff view generated by jsdifflib
New patch
[PULL 03/26] hvf: arm: Use macros for sysreg shift/masking
1
From: Alexander Graf <agraf@csgraf.de>
1
2
3
We are parsing the syndrome field for sysregs in multiple places across
4
the hvf code, but repeat shift/mask operations with hard coded constants
5
every time. This is an error prone approach and makes it harder to reason
6
about the correctness of these operations.
7
8
Let's introduce macros that allow us to unify the constants used as well
9
as create new helpers to extract fields from the sysreg value.
10
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Alexander Graf <agraf@csgraf.de>
13
Reviewed-by: Cameron Esfahani <dirty@apple.com <mailto:dirty@apple.com>>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20220209124135.69183-1-agraf@csgraf.de
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/hvf/hvf.c | 69 ++++++++++++++++++++++++++++++--------------
19
1 file changed, 47 insertions(+), 22 deletions(-)
20
21
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/hvf/hvf.c
24
+++ b/target/arm/hvf/hvf.c
25
@@ -XXX,XX +XXX,XX @@
26
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
27
#define PL1_WRITE_MASK 0x4
28
29
+#define SYSREG_OP0_SHIFT 20
30
+#define SYSREG_OP0_MASK 0x3
31
+#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
32
+#define SYSREG_OP1_SHIFT 14
33
+#define SYSREG_OP1_MASK 0x7
34
+#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
35
+#define SYSREG_CRN_SHIFT 10
36
+#define SYSREG_CRN_MASK 0xf
37
+#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
38
+#define SYSREG_CRM_SHIFT 1
39
+#define SYSREG_CRM_MASK 0xf
40
+#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
41
+#define SYSREG_OP2_SHIFT 17
42
+#define SYSREG_OP2_MASK 0x7
43
+#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
44
+
45
#define SYSREG(op0, op1, crn, crm, op2) \
46
- ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))
47
-#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)
48
+ ((op0 << SYSREG_OP0_SHIFT) | \
49
+ (op1 << SYSREG_OP1_SHIFT) | \
50
+ (crn << SYSREG_CRN_SHIFT) | \
51
+ (crm << SYSREG_CRM_SHIFT) | \
52
+ (op2 << SYSREG_OP2_SHIFT))
53
+#define SYSREG_MASK \
54
+ SYSREG(SYSREG_OP0_MASK, \
55
+ SYSREG_OP1_MASK, \
56
+ SYSREG_CRN_MASK, \
57
+ SYSREG_CRM_MASK, \
58
+ SYSREG_OP2_MASK)
59
#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
60
#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
61
#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
62
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
63
default:
64
cpu_synchronize_state(cpu);
65
trace_hvf_unhandled_sysreg_read(env->pc, reg,
66
- (reg >> 20) & 0x3,
67
- (reg >> 14) & 0x7,
68
- (reg >> 10) & 0xf,
69
- (reg >> 1) & 0xf,
70
- (reg >> 17) & 0x7);
71
+ SYSREG_OP0(reg),
72
+ SYSREG_OP1(reg),
73
+ SYSREG_CRN(reg),
74
+ SYSREG_CRM(reg),
75
+ SYSREG_OP2(reg));
76
hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
77
return 1;
78
}
79
80
trace_hvf_sysreg_read(reg,
81
- (reg >> 20) & 0x3,
82
- (reg >> 14) & 0x7,
83
- (reg >> 10) & 0xf,
84
- (reg >> 1) & 0xf,
85
- (reg >> 17) & 0x7,
86
+ SYSREG_OP0(reg),
87
+ SYSREG_OP1(reg),
88
+ SYSREG_CRN(reg),
89
+ SYSREG_CRM(reg),
90
+ SYSREG_OP2(reg),
91
val);
92
hvf_set_reg(cpu, rt, val);
93
94
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
95
CPUARMState *env = &arm_cpu->env;
96
97
trace_hvf_sysreg_write(reg,
98
- (reg >> 20) & 0x3,
99
- (reg >> 14) & 0x7,
100
- (reg >> 10) & 0xf,
101
- (reg >> 1) & 0xf,
102
- (reg >> 17) & 0x7,
103
+ SYSREG_OP0(reg),
104
+ SYSREG_OP1(reg),
105
+ SYSREG_CRN(reg),
106
+ SYSREG_CRM(reg),
107
+ SYSREG_OP2(reg),
108
val);
109
110
switch (reg) {
111
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
112
default:
113
cpu_synchronize_state(cpu);
114
trace_hvf_unhandled_sysreg_write(env->pc, reg,
115
- (reg >> 20) & 0x3,
116
- (reg >> 14) & 0x7,
117
- (reg >> 10) & 0xf,
118
- (reg >> 1) & 0xf,
119
- (reg >> 17) & 0x7);
120
+ SYSREG_OP0(reg),
121
+ SYSREG_OP1(reg),
122
+ SYSREG_CRN(reg),
123
+ SYSREG_CRM(reg),
124
+ SYSREG_OP2(reg));
125
hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
126
return 1;
127
}
128
--
129
2.25.1
130
131
diff view generated by jsdifflib
[PULL 1/5] hw/arm/virt: Extend nested and mte checks to hvf
[PULL 04/26] hvf: arm: Handle unknown ID registers as RES0
1
From: Alexander Graf <agraf@csgraf.de>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
The virt machine has properties to enable MTE and Nested Virtualization
3
Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1,
4
support. However, its check to ensure the backing accel implementation
4
those reads trap into QEMU which handles them as faults.
5
supports it today only looks for KVM and bails out if it finds it.
6
5
7
Extend the checks to HVF as well as it does not support either today.
6
However, AArch64 ID registers should always read as RES0. Let's
8
This will cause QEMU to print a useful error message rather than
7
handle them accordingly.
9
silently ignoring the attempt by the user to enable either MTE or
10
the Virtualization extensions.
11
8
12
Reported-by: saar amar <saaramar5@gmail.com>
9
This fixes booting Linux 5.17 guests.
10
11
Cc: qemu-stable@nongnu.org
12
Reported-by: Ivan Babrou <ivan@cloudflare.com>
13
Signed-off-by: Alexander Graf <agraf@csgraf.de>
13
Signed-off-by: Alexander Graf <agraf@csgraf.de>
14
Message-id: 20211123122859.22452-1-agraf@csgraf.de
14
Message-id: 20220209124135.69183-2-agraf@csgraf.de
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
17
---
18
hw/arm/virt.c | 15 +++++++++------
18
target/arm/hvf/hvf.c | 14 ++++++++++++++
19
1 file changed, 9 insertions(+), 6 deletions(-)
19
1 file changed, 14 insertions(+)
20
20
21
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
22
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/virt.c
23
--- a/target/arm/hvf/hvf.c
24
+++ b/hw/arm/virt.c
24
+++ b/target/arm/hvf/hvf.c
25
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
26
#include "sysemu/runstate.h"
26
return true;
27
#include "sysemu/tpm.h"
27
}
28
#include "sysemu/kvm.h"
28
29
+#include "sysemu/hvf.h"
29
+static bool is_id_sysreg(uint32_t reg)
30
#include "hw/loader.h"
30
+{
31
#include "qapi/error.h"
31
+ return SYSREG_OP0(reg) == 3 &&
32
#include "qemu/bitops.h"
32
+ SYSREG_OP1(reg) == 0 &&
33
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
33
+ SYSREG_CRN(reg) == 0 &&
34
exit(1);
34
+ SYSREG_CRM(reg) >= 1 &&
35
}
35
+ SYSREG_CRM(reg) < 8;
36
36
+}
37
- if (vms->virt && kvm_enabled()) {
37
+
38
- error_report("mach-virt: KVM does not support providing "
38
static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
39
- "Virtualization extensions to the guest CPU");
39
{
40
+ if (vms->virt && (kvm_enabled() || hvf_enabled())) {
40
ARMCPU *arm_cpu = ARM_CPU(cpu);
41
+ error_report("mach-virt: %s does not support providing "
41
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
42
+ "Virtualization extensions to the guest CPU",
42
/* Dummy register */
43
+ kvm_enabled() ? "KVM" : "HVF");
43
break;
44
exit(1);
44
default:
45
}
45
+ if (is_id_sysreg(reg)) {
46
46
+ /* ID system registers read as RES0 */
47
- if (vms->mte && kvm_enabled()) {
47
+ val = 0;
48
- error_report("mach-virt: KVM does not support providing "
48
+ break;
49
- "MTE to the guest CPU");
49
+ }
50
+ if (vms->mte && (kvm_enabled() || hvf_enabled())) {
50
cpu_synchronize_state(cpu);
51
+ error_report("mach-virt: %s does not support providing "
51
trace_hvf_unhandled_sysreg_read(env->pc, reg,
52
+ "MTE to the guest CPU",
52
SYSREG_OP0(reg),
53
+ kvm_enabled() ? "KVM" : "HVF");
54
exit(1);
55
}
56
57
--
53
--
58
2.25.1
54
2.25.1
59
55
60
56
diff view generated by jsdifflib
New patch
[PULL 05/26] Mark remaining global TypeInfo instances as const
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
More than 1k of TypeInfo instances are already marked as const. Mark the
4
remaining ones, too.
5
6
This commit was created with:
7
git grep -z -l 'static TypeInfo' -- '*.c' | \
8
xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/'
9
10
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
16
Acked-by: Corey Minyard <cminyard@mvista.com>
17
Message-id: 20220117145805.173070-2-shentey@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/core/generic-loader.c | 2 +-
21
hw/core/guest-loader.c | 2 +-
22
hw/display/bcm2835_fb.c | 2 +-
23
hw/display/i2c-ddc.c | 2 +-
24
hw/display/macfb.c | 4 ++--
25
hw/display/virtio-vga.c | 2 +-
26
hw/dma/bcm2835_dma.c | 2 +-
27
hw/i386/pc_piix.c | 2 +-
28
hw/i386/sgx-epc.c | 2 +-
29
hw/intc/bcm2835_ic.c | 2 +-
30
hw/intc/bcm2836_control.c | 2 +-
31
hw/ipmi/ipmi.c | 4 ++--
32
hw/mem/nvdimm.c | 2 +-
33
hw/mem/pc-dimm.c | 2 +-
34
hw/misc/bcm2835_mbox.c | 2 +-
35
hw/misc/bcm2835_powermgt.c | 2 +-
36
hw/misc/bcm2835_property.c | 2 +-
37
hw/misc/bcm2835_rng.c | 2 +-
38
hw/misc/pvpanic-isa.c | 2 +-
39
hw/misc/pvpanic-pci.c | 2 +-
40
hw/net/fsl_etsec/etsec.c | 2 +-
41
hw/ppc/prep_systemio.c | 2 +-
42
hw/ppc/spapr_iommu.c | 2 +-
43
hw/s390x/s390-pci-bus.c | 2 +-
44
hw/s390x/sclp.c | 2 +-
45
hw/s390x/tod-kvm.c | 2 +-
46
hw/s390x/tod-tcg.c | 2 +-
47
hw/s390x/tod.c | 2 +-
48
hw/scsi/lsi53c895a.c | 2 +-
49
hw/sd/allwinner-sdhost.c | 2 +-
50
hw/sd/aspeed_sdhci.c | 2 +-
51
hw/sd/bcm2835_sdhost.c | 2 +-
52
hw/sd/cadence_sdhci.c | 2 +-
53
hw/sd/npcm7xx_sdhci.c | 2 +-
54
hw/usb/dev-mtp.c | 2 +-
55
hw/usb/host-libusb.c | 2 +-
56
hw/vfio/igd.c | 2 +-
57
hw/virtio/virtio-pmem.c | 2 +-
58
qom/object.c | 4 ++--
59
39 files changed, 42 insertions(+), 42 deletions(-)
60
61
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/core/generic-loader.c
64
+++ b/hw/core/generic-loader.c
65
@@ -XXX,XX +XXX,XX @@ static void generic_loader_class_init(ObjectClass *klass, void *data)
66
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
67
}
68
69
-static TypeInfo generic_loader_info = {
70
+static const TypeInfo generic_loader_info = {
71
.name = TYPE_GENERIC_LOADER,
72
.parent = TYPE_DEVICE,
73
.instance_size = sizeof(GenericLoaderState),
74
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/core/guest-loader.c
77
+++ b/hw/core/guest-loader.c
78
@@ -XXX,XX +XXX,XX @@ static void guest_loader_class_init(ObjectClass *klass, void *data)
79
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
80
}
81
82
-static TypeInfo guest_loader_info = {
83
+static const TypeInfo guest_loader_info = {
84
.name = TYPE_GUEST_LOADER,
85
.parent = TYPE_DEVICE,
86
.instance_size = sizeof(GuestLoaderState),
87
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/display/bcm2835_fb.c
90
+++ b/hw/display/bcm2835_fb.c
91
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_class_init(ObjectClass *klass, void *data)
92
dc->vmsd = &vmstate_bcm2835_fb;
93
}
94
95
-static TypeInfo bcm2835_fb_info = {
96
+static const TypeInfo bcm2835_fb_info = {
97
.name = TYPE_BCM2835_FB,
98
.parent = TYPE_SYS_BUS_DEVICE,
99
.instance_size = sizeof(BCM2835FBState),
100
diff --git a/hw/display/i2c-ddc.c b/hw/display/i2c-ddc.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/display/i2c-ddc.c
103
+++ b/hw/display/i2c-ddc.c
104
@@ -XXX,XX +XXX,XX @@ static void i2c_ddc_class_init(ObjectClass *oc, void *data)
105
isc->send = i2c_ddc_tx;
106
}
107
108
-static TypeInfo i2c_ddc_info = {
109
+static const TypeInfo i2c_ddc_info = {
110
.name = TYPE_I2CDDC,
111
.parent = TYPE_I2C_SLAVE,
112
.instance_size = sizeof(I2CDDCState),
113
diff --git a/hw/display/macfb.c b/hw/display/macfb.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/hw/display/macfb.c
116
+++ b/hw/display/macfb.c
117
@@ -XXX,XX +XXX,XX @@ static void macfb_nubus_class_init(ObjectClass *klass, void *data)
118
device_class_set_props(dc, macfb_nubus_properties);
119
}
120
121
-static TypeInfo macfb_sysbus_info = {
122
+static const TypeInfo macfb_sysbus_info = {
123
.name = TYPE_MACFB,
124
.parent = TYPE_SYS_BUS_DEVICE,
125
.instance_size = sizeof(MacfbSysBusState),
126
.class_init = macfb_sysbus_class_init,
127
};
128
129
-static TypeInfo macfb_nubus_info = {
130
+static const TypeInfo macfb_nubus_info = {
131
.name = TYPE_NUBUS_MACFB,
132
.parent = TYPE_NUBUS_DEVICE,
133
.instance_size = sizeof(MacfbNubusState),
134
diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c
135
index XXXXXXX..XXXXXXX 100644
136
--- a/hw/display/virtio-vga.c
137
+++ b/hw/display/virtio-vga.c
138
@@ -XXX,XX +XXX,XX @@ static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
139
virtio_vga_set_big_endian_fb);
140
}
141
142
-static TypeInfo virtio_vga_base_info = {
143
+static const TypeInfo virtio_vga_base_info = {
144
.name = TYPE_VIRTIO_VGA_BASE,
145
.parent = TYPE_VIRTIO_PCI,
146
.instance_size = sizeof(VirtIOVGABase),
147
diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/hw/dma/bcm2835_dma.c
150
+++ b/hw/dma/bcm2835_dma.c
151
@@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
152
dc->vmsd = &vmstate_bcm2835_dma;
153
}
154
155
-static TypeInfo bcm2835_dma_info = {
156
+static const TypeInfo bcm2835_dma_info = {
157
.name = TYPE_BCM2835_DMA,
158
.parent = TYPE_SYS_BUS_DEVICE,
159
.instance_size = sizeof(BCM2835DMAState),
160
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/hw/i386/pc_piix.c
163
+++ b/hw/i386/pc_piix.c
164
@@ -XXX,XX +XXX,XX @@ static void isa_bridge_class_init(ObjectClass *klass, void *data)
165
k->class_id = PCI_CLASS_BRIDGE_ISA;
166
};
167
168
-static TypeInfo isa_bridge_info = {
169
+static const TypeInfo isa_bridge_info = {
170
.name = "igd-passthrough-isa-bridge",
171
.parent = TYPE_PCI_DEVICE,
172
.instance_size = sizeof(PCIDevice),
173
diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/i386/sgx-epc.c
176
+++ b/hw/i386/sgx-epc.c
177
@@ -XXX,XX +XXX,XX @@ static void sgx_epc_class_init(ObjectClass *oc, void *data)
178
mdc->fill_device_info = sgx_epc_md_fill_device_info;
179
}
180
181
-static TypeInfo sgx_epc_info = {
182
+static const TypeInfo sgx_epc_info = {
183
.name = TYPE_SGX_EPC,
184
.parent = TYPE_DEVICE,
185
.instance_size = sizeof(SGXEPCDevice),
186
diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/hw/intc/bcm2835_ic.c
189
+++ b/hw/intc/bcm2835_ic.c
190
@@ -XXX,XX +XXX,XX @@ static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
191
dc->vmsd = &vmstate_bcm2835_ic;
192
}
193
194
-static TypeInfo bcm2835_ic_info = {
195
+static const TypeInfo bcm2835_ic_info = {
196
.name = TYPE_BCM2835_IC,
197
.parent = TYPE_SYS_BUS_DEVICE,
198
.instance_size = sizeof(BCM2835ICState),
199
diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/intc/bcm2836_control.c
202
+++ b/hw/intc/bcm2836_control.c
203
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_class_init(ObjectClass *klass, void *data)
204
dc->vmsd = &vmstate_bcm2836_control;
205
}
206
207
-static TypeInfo bcm2836_control_info = {
208
+static const TypeInfo bcm2836_control_info = {
209
.name = TYPE_BCM2836_CONTROL,
210
.parent = TYPE_SYS_BUS_DEVICE,
211
.instance_size = sizeof(BCM2836ControlState),
212
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
213
index XXXXXXX..XXXXXXX 100644
214
--- a/hw/ipmi/ipmi.c
215
+++ b/hw/ipmi/ipmi.c
216
@@ -XXX,XX +XXX,XX @@ static void ipmi_interface_class_init(ObjectClass *class, void *data)
217
ik->do_hw_op = ipmi_do_hw_op;
218
}
219
220
-static TypeInfo ipmi_interface_type_info = {
221
+static const TypeInfo ipmi_interface_type_info = {
222
.name = TYPE_IPMI_INTERFACE,
223
.parent = TYPE_INTERFACE,
224
.class_size = sizeof(IPMIInterfaceClass),
225
@@ -XXX,XX +XXX,XX @@ static void bmc_class_init(ObjectClass *oc, void *data)
226
device_class_set_props(dc, ipmi_bmc_properties);
227
}
228
229
-static TypeInfo ipmi_bmc_type_info = {
230
+static const TypeInfo ipmi_bmc_type_info = {
231
.name = TYPE_IPMI_BMC,
232
.parent = TYPE_DEVICE,
233
.instance_size = sizeof(IPMIBmc),
234
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
235
index XXXXXXX..XXXXXXX 100644
236
--- a/hw/mem/nvdimm.c
237
+++ b/hw/mem/nvdimm.c
238
@@ -XXX,XX +XXX,XX @@ static void nvdimm_class_init(ObjectClass *oc, void *data)
239
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
240
}
241
242
-static TypeInfo nvdimm_info = {
243
+static const TypeInfo nvdimm_info = {
244
.name = TYPE_NVDIMM,
245
.parent = TYPE_PC_DIMM,
246
.class_size = sizeof(NVDIMMClass),
247
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
248
index XXXXXXX..XXXXXXX 100644
249
--- a/hw/mem/pc-dimm.c
250
+++ b/hw/mem/pc-dimm.c
251
@@ -XXX,XX +XXX,XX @@ static void pc_dimm_class_init(ObjectClass *oc, void *data)
252
mdc->fill_device_info = pc_dimm_md_fill_device_info;
253
}
254
255
-static TypeInfo pc_dimm_info = {
256
+static const TypeInfo pc_dimm_info = {
257
.name = TYPE_PC_DIMM,
258
.parent = TYPE_DEVICE,
259
.instance_size = sizeof(PCDIMMDevice),
260
diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c
261
index XXXXXXX..XXXXXXX 100644
262
--- a/hw/misc/bcm2835_mbox.c
263
+++ b/hw/misc/bcm2835_mbox.c
264
@@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_class_init(ObjectClass *klass, void *data)
265
dc->vmsd = &vmstate_bcm2835_mbox;
266
}
267
268
-static TypeInfo bcm2835_mbox_info = {
269
+static const TypeInfo bcm2835_mbox_info = {
270
.name = TYPE_BCM2835_MBOX,
271
.parent = TYPE_SYS_BUS_DEVICE,
272
.instance_size = sizeof(BCM2835MboxState),
273
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
274
index XXXXXXX..XXXXXXX 100644
275
--- a/hw/misc/bcm2835_powermgt.c
276
+++ b/hw/misc/bcm2835_powermgt.c
277
@@ -XXX,XX +XXX,XX @@ static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
278
dc->vmsd = &vmstate_bcm2835_powermgt;
279
}
280
281
-static TypeInfo bcm2835_powermgt_info = {
282
+static const TypeInfo bcm2835_powermgt_info = {
283
.name = TYPE_BCM2835_POWERMGT,
284
.parent = TYPE_SYS_BUS_DEVICE,
285
.instance_size = sizeof(BCM2835PowerMgtState),
286
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
287
index XXXXXXX..XXXXXXX 100644
288
--- a/hw/misc/bcm2835_property.c
289
+++ b/hw/misc/bcm2835_property.c
290
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_class_init(ObjectClass *klass, void *data)
291
dc->vmsd = &vmstate_bcm2835_property;
292
}
293
294
-static TypeInfo bcm2835_property_info = {
295
+static const TypeInfo bcm2835_property_info = {
296
.name = TYPE_BCM2835_PROPERTY,
297
.parent = TYPE_SYS_BUS_DEVICE,
298
.instance_size = sizeof(BCM2835PropertyState),
299
diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c
300
index XXXXXXX..XXXXXXX 100644
301
--- a/hw/misc/bcm2835_rng.c
302
+++ b/hw/misc/bcm2835_rng.c
303
@@ -XXX,XX +XXX,XX @@ static void bcm2835_rng_class_init(ObjectClass *klass, void *data)
304
dc->vmsd = &vmstate_bcm2835_rng;
305
}
306
307
-static TypeInfo bcm2835_rng_info = {
308
+static const TypeInfo bcm2835_rng_info = {
309
.name = TYPE_BCM2835_RNG,
310
.parent = TYPE_SYS_BUS_DEVICE,
311
.instance_size = sizeof(BCM2835RngState),
312
diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
313
index XXXXXXX..XXXXXXX 100644
314
--- a/hw/misc/pvpanic-isa.c
315
+++ b/hw/misc/pvpanic-isa.c
316
@@ -XXX,XX +XXX,XX @@ static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
317
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
318
}
319
320
-static TypeInfo pvpanic_isa_info = {
321
+static const TypeInfo pvpanic_isa_info = {
322
.name = TYPE_PVPANIC_ISA_DEVICE,
323
.parent = TYPE_ISA_DEVICE,
324
.instance_size = sizeof(PVPanicISAState),
325
diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c
326
index XXXXXXX..XXXXXXX 100644
327
--- a/hw/misc/pvpanic-pci.c
328
+++ b/hw/misc/pvpanic-pci.c
329
@@ -XXX,XX +XXX,XX @@ static void pvpanic_pci_class_init(ObjectClass *klass, void *data)
330
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
331
}
332
333
-static TypeInfo pvpanic_pci_info = {
334
+static const TypeInfo pvpanic_pci_info = {
335
.name = TYPE_PVPANIC_PCI_DEVICE,
336
.parent = TYPE_PCI_DEVICE,
337
.instance_size = sizeof(PVPanicPCIState),
338
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
339
index XXXXXXX..XXXXXXX 100644
340
--- a/hw/net/fsl_etsec/etsec.c
341
+++ b/hw/net/fsl_etsec/etsec.c
342
@@ -XXX,XX +XXX,XX @@ static void etsec_class_init(ObjectClass *klass, void *data)
343
dc->user_creatable = true;
344
}
345
346
-static TypeInfo etsec_info = {
347
+static const TypeInfo etsec_info = {
348
.name = TYPE_ETSEC_COMMON,
349
.parent = TYPE_SYS_BUS_DEVICE,
350
.instance_size = sizeof(eTSEC),
351
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
352
index XXXXXXX..XXXXXXX 100644
353
--- a/hw/ppc/prep_systemio.c
354
+++ b/hw/ppc/prep_systemio.c
355
@@ -XXX,XX +XXX,XX @@ static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
356
device_class_set_props(dc, prep_systemio_properties);
357
}
358
359
-static TypeInfo prep_systemio800_info = {
360
+static const TypeInfo prep_systemio800_info = {
361
.name = TYPE_PREP_SYSTEMIO,
362
.parent = TYPE_ISA_DEVICE,
363
.instance_size = sizeof(PrepSystemIoState),
364
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
365
index XXXXXXX..XXXXXXX 100644
366
--- a/hw/ppc/spapr_iommu.c
367
+++ b/hw/ppc/spapr_iommu.c
368
@@ -XXX,XX +XXX,XX @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
369
spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
370
}
371
372
-static TypeInfo spapr_tce_table_info = {
373
+static const TypeInfo spapr_tce_table_info = {
374
.name = TYPE_SPAPR_TCE_TABLE,
375
.parent = TYPE_DEVICE,
376
.instance_size = sizeof(SpaprTceTable),
377
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
378
index XXXXXXX..XXXXXXX 100644
379
--- a/hw/s390x/s390-pci-bus.c
380
+++ b/hw/s390x/s390-pci-bus.c
381
@@ -XXX,XX +XXX,XX @@ static const TypeInfo s390_pci_device_info = {
382
.class_init = s390_pci_device_class_init,
383
};
384
385
-static TypeInfo s390_pci_iommu_info = {
386
+static const TypeInfo s390_pci_iommu_info = {
387
.name = TYPE_S390_PCI_IOMMU,
388
.parent = TYPE_OBJECT,
389
.instance_size = sizeof(S390PCIIOMMU),
390
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
391
index XXXXXXX..XXXXXXX 100644
392
--- a/hw/s390x/sclp.c
393
+++ b/hw/s390x/sclp.c
394
@@ -XXX,XX +XXX,XX @@ static void sclp_class_init(ObjectClass *oc, void *data)
395
sc->service_interrupt = service_interrupt;
396
}
397
398
-static TypeInfo sclp_info = {
399
+static const TypeInfo sclp_info = {
400
.name = TYPE_SCLP,
401
.parent = TYPE_DEVICE,
402
.instance_init = sclp_init,
403
diff --git a/hw/s390x/tod-kvm.c b/hw/s390x/tod-kvm.c
404
index XXXXXXX..XXXXXXX 100644
405
--- a/hw/s390x/tod-kvm.c
406
+++ b/hw/s390x/tod-kvm.c
407
@@ -XXX,XX +XXX,XX @@ static void kvm_s390_tod_init(Object *obj)
408
td->stopped = false;
409
}
410
411
-static TypeInfo kvm_s390_tod_info = {
412
+static const TypeInfo kvm_s390_tod_info = {
413
.name = TYPE_KVM_S390_TOD,
414
.parent = TYPE_S390_TOD,
415
.instance_size = sizeof(S390TODState),
416
diff --git a/hw/s390x/tod-tcg.c b/hw/s390x/tod-tcg.c
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/s390x/tod-tcg.c
419
+++ b/hw/s390x/tod-tcg.c
420
@@ -XXX,XX +XXX,XX @@ static void qemu_s390_tod_init(Object *obj)
421
}
422
}
423
424
-static TypeInfo qemu_s390_tod_info = {
425
+static const TypeInfo qemu_s390_tod_info = {
426
.name = TYPE_QEMU_S390_TOD,
427
.parent = TYPE_S390_TOD,
428
.instance_size = sizeof(S390TODState),
429
diff --git a/hw/s390x/tod.c b/hw/s390x/tod.c
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/s390x/tod.c
432
+++ b/hw/s390x/tod.c
433
@@ -XXX,XX +XXX,XX @@ static void s390_tod_class_init(ObjectClass *oc, void *data)
434
dc->user_creatable = false;
435
}
436
437
-static TypeInfo s390_tod_info = {
438
+static const TypeInfo s390_tod_info = {
439
.name = TYPE_S390_TOD,
440
.parent = TYPE_DEVICE,
441
.instance_size = sizeof(S390TODState),
442
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
443
index XXXXXXX..XXXXXXX 100644
444
--- a/hw/scsi/lsi53c895a.c
445
+++ b/hw/scsi/lsi53c895a.c
446
@@ -XXX,XX +XXX,XX @@ static void lsi53c810_class_init(ObjectClass *klass, void *data)
447
k->device_id = PCI_DEVICE_ID_LSI_53C810;
448
}
449
450
-static TypeInfo lsi53c810_info = {
451
+static const TypeInfo lsi53c810_info = {
452
.name = TYPE_LSI53C810,
453
.parent = TYPE_LSI53C895A,
454
.class_init = lsi53c810_class_init,
455
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
456
index XXXXXXX..XXXXXXX 100644
457
--- a/hw/sd/allwinner-sdhost.c
458
+++ b/hw/sd/allwinner-sdhost.c
459
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
460
sc->max_desc_size = 64 * KiB;
461
}
462
463
-static TypeInfo allwinner_sdhost_info = {
464
+static const TypeInfo allwinner_sdhost_info = {
465
.name = TYPE_AW_SDHOST,
466
.parent = TYPE_SYS_BUS_DEVICE,
467
.instance_init = allwinner_sdhost_init,
468
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/hw/sd/aspeed_sdhci.c
471
+++ b/hw/sd/aspeed_sdhci.c
472
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
473
device_class_set_props(dc, aspeed_sdhci_properties);
474
}
475
476
-static TypeInfo aspeed_sdhci_info = {
477
+static const TypeInfo aspeed_sdhci_info = {
478
.name = TYPE_ASPEED_SDHCI,
479
.parent = TYPE_SYS_BUS_DEVICE,
480
.instance_size = sizeof(AspeedSDHCIState),
481
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
482
index XXXXXXX..XXXXXXX 100644
483
--- a/hw/sd/bcm2835_sdhost.c
484
+++ b/hw/sd/bcm2835_sdhost.c
485
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
486
dc->vmsd = &vmstate_bcm2835_sdhost;
487
}
488
489
-static TypeInfo bcm2835_sdhost_info = {
490
+static const TypeInfo bcm2835_sdhost_info = {
491
.name = TYPE_BCM2835_SDHOST,
492
.parent = TYPE_SYS_BUS_DEVICE,
493
.instance_size = sizeof(BCM2835SDHostState),
494
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
495
index XXXXXXX..XXXXXXX 100644
496
--- a/hw/sd/cadence_sdhci.c
497
+++ b/hw/sd/cadence_sdhci.c
498
@@ -XXX,XX +XXX,XX @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
499
dc->vmsd = &vmstate_cadence_sdhci;
500
}
501
502
-static TypeInfo cadence_sdhci_info = {
503
+static const TypeInfo cadence_sdhci_info = {
504
.name = TYPE_CADENCE_SDHCI,
505
.parent = TYPE_SYS_BUS_DEVICE,
506
.instance_size = sizeof(CadenceSDHCIState),
507
diff --git a/hw/sd/npcm7xx_sdhci.c b/hw/sd/npcm7xx_sdhci.c
508
index XXXXXXX..XXXXXXX 100644
509
--- a/hw/sd/npcm7xx_sdhci.c
510
+++ b/hw/sd/npcm7xx_sdhci.c
511
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_sdhci_instance_init(Object *obj)
512
TYPE_SYSBUS_SDHCI);
513
}
514
515
-static TypeInfo npcm7xx_sdhci_info = {
516
+static const TypeInfo npcm7xx_sdhci_info = {
517
.name = TYPE_NPCM7XX_SDHCI,
518
.parent = TYPE_SYS_BUS_DEVICE,
519
.instance_size = sizeof(NPCM7xxSDHCIState),
520
diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
521
index XXXXXXX..XXXXXXX 100644
522
--- a/hw/usb/dev-mtp.c
523
+++ b/hw/usb/dev-mtp.c
524
@@ -XXX,XX +XXX,XX @@ static void usb_mtp_class_initfn(ObjectClass *klass, void *data)
525
device_class_set_props(dc, mtp_properties);
526
}
527
528
-static TypeInfo mtp_info = {
529
+static const TypeInfo mtp_info = {
530
.name = TYPE_USB_MTP,
531
.parent = TYPE_USB_DEVICE,
532
.instance_size = sizeof(MTPState),
533
diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c
534
index XXXXXXX..XXXXXXX 100644
535
--- a/hw/usb/host-libusb.c
536
+++ b/hw/usb/host-libusb.c
537
@@ -XXX,XX +XXX,XX @@ static void usb_host_class_initfn(ObjectClass *klass, void *data)
538
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
539
}
540
541
-static TypeInfo usb_host_dev_info = {
542
+static const TypeInfo usb_host_dev_info = {
543
.name = TYPE_USB_HOST_DEVICE,
544
.parent = TYPE_USB_DEVICE,
545
.instance_size = sizeof(USBHostDevice),
546
diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
547
index XXXXXXX..XXXXXXX 100644
548
--- a/hw/vfio/igd.c
549
+++ b/hw/vfio/igd.c
550
@@ -XXX,XX +XXX,XX @@ static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data)
551
k->class_id = PCI_CLASS_BRIDGE_ISA;
552
}
553
554
-static TypeInfo vfio_pci_igd_lpc_bridge_info = {
555
+static const TypeInfo vfio_pci_igd_lpc_bridge_info = {
556
.name = "vfio-pci-igd-lpc-bridge",
557
.parent = TYPE_PCI_DEVICE,
558
.class_init = vfio_pci_igd_lpc_bridge_class_init,
559
diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c
560
index XXXXXXX..XXXXXXX 100644
561
--- a/hw/virtio/virtio-pmem.c
562
+++ b/hw/virtio/virtio-pmem.c
563
@@ -XXX,XX +XXX,XX @@ static void virtio_pmem_class_init(ObjectClass *klass, void *data)
564
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
565
}
566
567
-static TypeInfo virtio_pmem_info = {
568
+static const TypeInfo virtio_pmem_info = {
569
.name = TYPE_VIRTIO_PMEM,
570
.parent = TYPE_VIRTIO_DEVICE,
571
.class_size = sizeof(VirtIOPMEMClass),
572
diff --git a/qom/object.c b/qom/object.c
573
index XXXXXXX..XXXXXXX 100644
574
--- a/qom/object.c
575
+++ b/qom/object.c
576
@@ -XXX,XX +XXX,XX @@ static void object_class_init(ObjectClass *klass, void *data)
577
578
static void register_types(void)
579
{
580
- static TypeInfo interface_info = {
581
+ static const TypeInfo interface_info = {
582
.name = TYPE_INTERFACE,
583
.class_size = sizeof(InterfaceClass),
584
.abstract = true,
585
};
586
587
- static TypeInfo object_info = {
588
+ static const TypeInfo object_info = {
589
.name = TYPE_OBJECT,
590
.instance_size = sizeof(Object),
591
.class_init = object_class_init,
592
--
593
2.25.1
594
595
diff view generated by jsdifflib
New patch
[PULL 06/26] checkpatch: Ensure that TypeInfos are const
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Now that all static TypeInfo instances are declared const, prevent that
4
new non-const instances are created.
5
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220117145805.173070-3-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
scripts/checkpatch.pl | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
15
index XXXXXXX..XXXXXXX 100755
16
--- a/scripts/checkpatch.pl
17
+++ b/scripts/checkpatch.pl
18
@@ -XXX,XX +XXX,XX @@ sub process {
19
                SCSIBusInfo|
20
                SCSIReqOps|
21
                Spice[A-Z][a-zA-Z0-9]*Interface|
22
+                TypeInfo|
23
                USBDesc[A-Z][a-zA-Z0-9]*|
24
                VhostOps|
25
                VMStateDescription|
26
--
27
2.25.1
28
29
diff view generated by jsdifflib
[PULL 3/5] hw/intc/arm_gicv3: Update cached state after LPI state changes
[PULL 07/26] target/arm: Move '-cpu host' code to cpu64.c
1
The logic of gicv3_redist_update() is as follows:
1
Now that KVM has dropped AArch32 host support, the 'host' CPU type is
2
* it must be called in any code path that changes the state of
2
always AArch64, and we can move it to cpu64.c. This move will allow
3
(only) redistributor interrupts
3
us to share code between it and '-cpu max', which should behave
4
* if it finds a redistributor interrupt that is (now) higher
4
the same as '-cpu host' when using KVM or HVF.
5
priority than the previous highest-priority pending interrupt,
6
then this must be the new highest-priority pending interrupt
7
* if it does *not* find a better redistributor interrupt, then:
8
- if the previous state was "no interrupts pending" then
9
the new state is still "no interrupts pending"
10
- if the previous best interrupt was not a redistributor
11
interrupt then that remains the best interrupt
12
- if the previous best interrupt *was* a redistributor interrupt,
13
then the new best interrupt must be some non-redistributor
14
interrupt, but we don't know which so must do a full scan
15
16
In commit 17fb5e36aabd4b2c125 we effectively added the LPI interrupts
17
as a kind of "redistributor interrupt" for this purpose, by adding
18
cs->hpplpi to the set of things that gicv3_redist_update() considers
19
before it gives up and decides to do a full scan of distributor
20
interrupts. However we didn't quite get this right:
21
* the condition check for "was the previous best interrupt a
22
redistributor interrupt" must be updated to include LPIs
23
in what it considers to be redistributor interrupts
24
* every code path which updates the LPI state which
25
gicv3_redist_update() checks must also call gicv3_redist_update():
26
this is cs->hpplpi and the GICR_CTLR ENABLE_LPIS bit
27
28
This commit fixes this by:
29
* correcting the test on cs->hppi.irq in gicv3_redist_update()
30
* making gicv3_redist_update_lpi() always call gicv3_redist_update()
31
* introducing a new gicv3_redist_update_lpi_only() for the one
32
callsite (the post-load hook) which must not call
33
gicv3_redist_update()
34
* making gicv3_redist_lpi_pending() always call gicv3_redist_update(),
35
either directly or via gicv3_redist_update_lpi()
36
* removing a couple of now-unnecessary calls to gicv3_redist_update()
37
from some callers of those two functions
38
* calling gicv3_redist_update() when the GICR_CTLR ENABLE_LPIS
39
bit is cleared
40
41
(This means that the not-file-local gicv3_redist_* LPI related
42
functions now all take care of the updates of internally cached
43
GICv3 information, in the same way the older functions
44
gicv3_redist_set_irq() and gicv3_redist_send_sgi() do.)
45
46
The visible effect of this bug was that when the guest acknowledged
47
an LPI by reading ICC_IAR1_EL1, we marked it as not pending in the
48
LPI data structure but still left it in cs->hppi so we would offer it
49
to the guest again. In particular for setups using an emulated GICv3
50
and ITS and using devices which use LPIs (ie PCI devices) a Linux
51
guest would complain "irq 54: nobody cared" and then hang. (The hang
52
was intermittent, presumably depending on the timing between
53
different interrupts arriving and being completed.)
54
5
55
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
56
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
57
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
58
Message-id: 20211124202005.989935-1-peter.maydell@linaro.org
9
Reviewed-by: Alexander Graf <agraf@csgraf.de>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220204165506.2846058-2-peter.maydell@linaro.org
59
---
12
---
60
hw/intc/gicv3_internal.h | 17 +++++++++++++++++
13
target/arm/cpu.c | 30 ------------------------------
61
hw/intc/arm_gicv3.c | 6 ++++--
14
target/arm/cpu64.c | 30 ++++++++++++++++++++++++++++++
62
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
15
2 files changed, 30 insertions(+), 30 deletions(-)
63
3 files changed, 31 insertions(+), 6 deletions(-)
64
16
65
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
66
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/intc/gicv3_internal.h
19
--- a/target/arm/cpu.c
68
+++ b/hw/intc/gicv3_internal.h
20
+++ b/target/arm/cpu.c
69
@@ -XXX,XX +XXX,XX @@ void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
21
@@ -XXX,XX +XXX,XX @@
70
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
22
#include "sysemu/tcg.h"
71
void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level);
23
#include "sysemu/hw_accel.h"
72
void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level);
24
#include "kvm_arm.h"
73
+/**
25
-#include "hvf_arm.h"
74
+ * gicv3_redist_update_lpi:
26
#include "disas/capstone.h"
75
+ * @cs: GICv3CPUState
27
#include "fpu/softfloat.h"
76
+ *
28
77
+ * Scan the LPI pending table and recalculate the highest priority
29
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
78
+ * pending LPI and also the overall highest priority pending interrupt.
30
#endif /* CONFIG_TCG */
79
+ */
31
}
80
void gicv3_redist_update_lpi(GICv3CPUState *cs);
32
81
+/**
33
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
82
+ * gicv3_redist_update_lpi_only:
34
-static void arm_host_initfn(Object *obj)
83
+ * @cs: GICv3CPUState
35
-{
84
+ *
36
- ARMCPU *cpu = ARM_CPU(obj);
85
+ * Scan the LPI pending table and recalculate cs->hpplpi only,
37
-
86
+ * without calling gicv3_redist_update() to recalculate the overall
38
-#ifdef CONFIG_KVM
87
+ * highest priority pending interrupt. This should be called after
39
- kvm_arm_set_cpu_features_from_host(cpu);
88
+ * an incoming migration has loaded new state.
40
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
89
+ */
41
- aarch64_add_sve_properties(obj);
90
+void gicv3_redist_update_lpi_only(GICv3CPUState *cs);
42
- aarch64_add_pauth_properties(obj);
91
void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
43
- }
92
void gicv3_init_cpuif(GICv3State *s);
44
-#else
93
45
- hvf_arm_set_cpu_features_from_host(cpu);
94
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
46
-#endif
47
- arm_cpu_post_init(obj);
48
-}
49
-
50
-static const TypeInfo host_arm_cpu_type_info = {
51
- .name = TYPE_ARM_HOST_CPU,
52
- .parent = TYPE_AARCH64_CPU,
53
- .instance_init = arm_host_initfn,
54
-};
55
-
56
-#endif
57
-
58
static void arm_cpu_instance_init(Object *obj)
59
{
60
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
61
@@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = {
62
static void arm_cpu_register_types(void)
63
{
64
type_register_static(&arm_cpu_type_info);
65
-
66
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
67
- type_register_static(&host_arm_cpu_type_info);
68
-#endif
69
}
70
71
type_init(arm_cpu_register_types)
72
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
95
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/intc/arm_gicv3.c
74
--- a/target/arm/cpu64.c
97
+++ b/hw/intc/arm_gicv3.c
75
+++ b/target/arm/cpu64.c
98
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
76
@@ -XXX,XX +XXX,XX @@
99
* interrupt has reduced in priority and any other interrupt could
77
#endif
100
* now be the new best one).
78
#include "sysemu/kvm.h"
101
*/
79
#include "kvm_arm.h"
102
- if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) {
80
+#include "hvf_arm.h"
103
+ if (!seenbetter && cs->hppi.prio != 0xff &&
81
#include "qapi/visitor.h"
104
+ (cs->hppi.irq < GIC_INTERNAL ||
82
#include "hw/qdev-properties.h"
105
+ cs->hppi.irq >= GICV3_LPI_INTID_START)) {
83
106
gicv3_full_update_noirqset(cs->gic);
84
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
107
}
85
}
108
}
86
}
109
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_post_load(GICv3State *s)
87
110
* pending interrupt, but don't set IRQ or FIQ lines.
88
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
111
*/
89
+static void arm_host_initfn(Object *obj)
112
for (i = 0; i < s->num_cpu; i++) {
113
- gicv3_redist_update_lpi(&s->cpu[i]);
114
+ gicv3_redist_update_lpi_only(&s->cpu[i]);
115
}
116
gicv3_full_update_noirqset(s);
117
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
118
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/hw/intc/arm_gicv3_redist.c
121
+++ b/hw/intc/arm_gicv3_redist.c
122
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
123
cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
124
/* Check for any pending interr in pending table */
125
gicv3_redist_update_lpi(cs);
126
- gicv3_redist_update(cs);
127
} else {
128
cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
129
+ /* cs->hppi might have been an LPI; recalculate */
130
+ gicv3_redist_update(cs);
131
}
132
}
133
return MEMTX_OK;
134
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq)
135
}
136
}
137
138
-void gicv3_redist_update_lpi(GICv3CPUState *cs)
139
+void gicv3_redist_update_lpi_only(GICv3CPUState *cs)
140
{
141
/*
142
* This function scans the LPI pending table and for each pending
143
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_update_lpi(GICv3CPUState *cs)
144
}
145
}
146
147
+void gicv3_redist_update_lpi(GICv3CPUState *cs)
148
+{
90
+{
149
+ gicv3_redist_update_lpi_only(cs);
91
+ ARMCPU *cpu = ARM_CPU(obj);
150
+ gicv3_redist_update(cs);
92
+
93
+#ifdef CONFIG_KVM
94
+ kvm_arm_set_cpu_features_from_host(cpu);
95
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
96
+ aarch64_add_sve_properties(obj);
97
+ aarch64_add_pauth_properties(obj);
98
+ }
99
+#else
100
+ hvf_arm_set_cpu_features_from_host(cpu);
101
+#endif
102
+ arm_cpu_post_init(obj);
151
+}
103
+}
152
+
104
+
153
void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
105
+static const TypeInfo host_arm_cpu_type_info = {
154
{
106
+ .name = TYPE_ARM_HOST_CPU,
155
/*
107
+ .parent = TYPE_AARCH64_CPU,
156
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
108
+ .instance_init = arm_host_initfn,
157
*/
109
+};
158
if (level) {
110
+
159
gicv3_redist_check_lpi_priority(cs, irq);
111
+#endif
160
+ gicv3_redist_update(cs);
112
+
161
} else {
113
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
162
if (irq == cs->hpplpi.irq) {
114
* otherwise, a CPU with as many features enabled as our emulation supports.
163
gicv3_redist_update_lpi(cs);
115
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
164
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level)
116
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_register_types(void)
165
117
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
166
/* set/clear the pending bit for this irq */
118
aarch64_cpu_register(&aarch64_cpus[i]);
167
gicv3_redist_lpi_pending(cs, irq, level);
119
}
168
-
120
+
169
- gicv3_redist_update(cs);
121
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
122
+ type_register_static(&host_arm_cpu_type_info);
123
+#endif
170
}
124
}
171
125
172
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)
126
type_init(aarch64_cpu_register_types)
173
--
127
--
174
2.25.1
128
2.25.1
175
129
176
130
diff view generated by jsdifflib
New patch
[PULL 08/26] target/arm: Use aarch64_cpu_register() for 'host' CPU type
1
Use the aarch64_cpu_register() machinery to register the 'host' CPU
2
type. This doesn't gain us anything functionally, but it does mean
3
that the code for initializing it looks more like that for the other
4
CPU types, in that its initfn then doesn't need to call
5
arm_cpu_post_init() (because aarch64_cpu_instance_init() does that
6
for it).
1
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
Reviewed-by: Alexander Graf <agraf@csgraf.de>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220204165506.2846058-3-peter.maydell@linaro.org
14
---
15
target/arm/cpu64.c | 17 ++++-------------
16
1 file changed, 4 insertions(+), 13 deletions(-)
17
18
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu64.c
21
+++ b/target/arm/cpu64.c
22
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
23
}
24
25
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
26
-static void arm_host_initfn(Object *obj)
27
+static void aarch64_host_initfn(Object *obj)
28
{
29
ARMCPU *cpu = ARM_CPU(obj);
30
31
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
32
#else
33
hvf_arm_set_cpu_features_from_host(cpu);
34
#endif
35
- arm_cpu_post_init(obj);
36
}
37
-
38
-static const TypeInfo host_arm_cpu_type_info = {
39
- .name = TYPE_ARM_HOST_CPU,
40
- .parent = TYPE_AARCH64_CPU,
41
- .instance_init = arm_host_initfn,
42
-};
43
-
44
#endif
45
46
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
47
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
48
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
49
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
50
{ .name = "max", .initfn = aarch64_max_initfn },
51
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
52
+ { .name = "host", .initfn = aarch64_host_initfn },
53
+#endif
54
};
55
56
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
57
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_register_types(void)
58
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
59
aarch64_cpu_register(&aarch64_cpus[i]);
60
}
61
-
62
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
63
- type_register_static(&host_arm_cpu_type_info);
64
-#endif
65
}
66
67
type_init(aarch64_cpu_register_types)
68
--
69
2.25.1
70
71
diff view generated by jsdifflib
New patch
[PULL 09/26] target/arm: Make KVM -cpu max exactly like -cpu host
1
Currently for KVM the intention is that '-cpu max' and '-cpu host'
2
are the same thing, but because we did this with two separate
3
pieces of code they have got a little bit out of sync. Specifically,
4
'max' has a 'sve-max-vq' property, and 'host' does not.
1
5
6
Bring the two together by having the initfn for 'max' actually
7
call the initfn for 'host'. This will result in 'max' no longer
8
exposing the 'sve-max-vq' property when using KVM.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
13
Reviewed-by: Alexander Graf <agraf@csgraf.de>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220204165506.2846058-4-peter.maydell@linaro.org
16
---
17
target/arm/cpu64.c | 14 ++++++++------
18
1 file changed, 8 insertions(+), 6 deletions(-)
19
20
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu64.c
23
+++ b/target/arm/cpu64.c
24
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
25
}
26
}
27
28
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
29
static void aarch64_host_initfn(Object *obj)
30
{
31
+#if defined(CONFIG_KVM)
32
ARMCPU *cpu = ARM_CPU(obj);
33
-
34
-#ifdef CONFIG_KVM
35
kvm_arm_set_cpu_features_from_host(cpu);
36
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
37
aarch64_add_sve_properties(obj);
38
aarch64_add_pauth_properties(obj);
39
}
40
-#else
41
+#elif defined(CONFIG_HVF)
42
+ ARMCPU *cpu = ARM_CPU(obj);
43
hvf_arm_set_cpu_features_from_host(cpu);
44
+#else
45
+ g_assert_not_reached();
46
#endif
47
}
48
-#endif
49
50
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
51
* otherwise, a CPU with as many features enabled as our emulation supports.
52
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
53
ARMCPU *cpu = ARM_CPU(obj);
54
55
if (kvm_enabled()) {
56
- kvm_arm_set_cpu_features_from_host(cpu);
57
+ /* With KVM, '-cpu max' is identical to '-cpu host' */
58
+ aarch64_host_initfn(obj);
59
+ return;
60
} else {
61
uint64_t t;
62
uint32_t u;
63
--
64
2.25.1
65
66
diff view generated by jsdifflib
New patch
[PULL 10/26] target/arm: Unindent unnecessary else-clause
1
Now that the if() branch of the condition in aarch64_max_initfn()
2
returns early, we don't need to keep the rest of the code in
3
the function inside an else block. Remove the else, unindenting
4
that code.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Alexander Graf <agraf@csgraf.de>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org
12
---
13
target/arm/cpu64.c | 289 +++++++++++++++++++++++----------------------
14
1 file changed, 146 insertions(+), 143 deletions(-)
15
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
19
+++ b/target/arm/cpu64.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_host_initfn(Object *obj)
21
static void aarch64_max_initfn(Object *obj)
22
{
23
ARMCPU *cpu = ARM_CPU(obj);
24
+ uint64_t t;
25
+ uint32_t u;
26
27
if (kvm_enabled()) {
28
/* With KVM, '-cpu max' is identical to '-cpu host' */
29
aarch64_host_initfn(obj);
30
return;
31
- } else {
32
- uint64_t t;
33
- uint32_t u;
34
- aarch64_a57_initfn(obj);
35
+ }
36
37
- /*
38
- * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
39
- * one and try to apply errata workarounds or use impdef features we
40
- * don't provide.
41
- * An IMPLEMENTER field of 0 means "reserved for software use";
42
- * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
43
- * to see which features are present";
44
- * the VARIANT, PARTNUM and REVISION fields are all implementation
45
- * defined and we choose to define PARTNUM just in case guest
46
- * code needs to distinguish this QEMU CPU from other software
47
- * implementations, though this shouldn't be needed.
48
- */
49
- t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
50
- t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
51
- t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
52
- t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
53
- t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
54
- cpu->midr = t;
55
+ /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
56
57
- t = cpu->isar.id_aa64isar0;
58
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
59
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
61
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
62
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
63
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
64
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
65
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
66
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
67
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
68
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
69
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
70
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
71
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
72
- cpu->isar.id_aa64isar0 = t;
73
+ aarch64_a57_initfn(obj);
74
75
- t = cpu->isar.id_aa64isar1;
76
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
77
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
78
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
79
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
80
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
81
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
82
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
83
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
84
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
85
- cpu->isar.id_aa64isar1 = t;
86
+ /*
87
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
88
+ * one and try to apply errata workarounds or use impdef features we
89
+ * don't provide.
90
+ * An IMPLEMENTER field of 0 means "reserved for software use";
91
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
92
+ * to see which features are present";
93
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
94
+ * defined and we choose to define PARTNUM just in case guest
95
+ * code needs to distinguish this QEMU CPU from other software
96
+ * implementations, though this shouldn't be needed.
97
+ */
98
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
99
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
100
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
101
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
102
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
103
+ cpu->midr = t;
104
105
- t = cpu->isar.id_aa64pfr0;
106
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
107
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
108
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
109
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
110
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
111
- cpu->isar.id_aa64pfr0 = t;
112
+ t = cpu->isar.id_aa64isar0;
113
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
114
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
115
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
116
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
117
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
118
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
119
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
120
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
121
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
122
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
123
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
124
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
125
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
126
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
127
+ cpu->isar.id_aa64isar0 = t;
128
129
- t = cpu->isar.id_aa64pfr1;
130
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
131
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
132
- /*
133
- * Begin with full support for MTE. This will be downgraded to MTE=0
134
- * during realize if the board provides no tag memory, much like
135
- * we do for EL2 with the virtualization=on property.
136
- */
137
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
138
- cpu->isar.id_aa64pfr1 = t;
139
+ t = cpu->isar.id_aa64isar1;
140
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
141
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
142
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
143
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
144
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
145
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
146
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
147
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
148
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
149
+ cpu->isar.id_aa64isar1 = t;
150
151
- t = cpu->isar.id_aa64mmfr0;
152
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
153
- cpu->isar.id_aa64mmfr0 = t;
154
+ t = cpu->isar.id_aa64pfr0;
155
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
156
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
157
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
158
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
159
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
160
+ cpu->isar.id_aa64pfr0 = t;
161
162
- t = cpu->isar.id_aa64mmfr1;
163
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
164
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
165
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
166
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
167
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
168
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
169
- cpu->isar.id_aa64mmfr1 = t;
170
+ t = cpu->isar.id_aa64pfr1;
171
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
172
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
173
+ /*
174
+ * Begin with full support for MTE. This will be downgraded to MTE=0
175
+ * during realize if the board provides no tag memory, much like
176
+ * we do for EL2 with the virtualization=on property.
177
+ */
178
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
179
+ cpu->isar.id_aa64pfr1 = t;
180
181
- t = cpu->isar.id_aa64mmfr2;
182
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
183
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
184
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
185
- cpu->isar.id_aa64mmfr2 = t;
186
+ t = cpu->isar.id_aa64mmfr0;
187
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
188
+ cpu->isar.id_aa64mmfr0 = t;
189
190
- t = cpu->isar.id_aa64zfr0;
191
- t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
192
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
193
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
194
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
195
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
196
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
197
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
198
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
199
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
200
- cpu->isar.id_aa64zfr0 = t;
201
+ t = cpu->isar.id_aa64mmfr1;
202
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
203
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
204
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
205
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
206
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
207
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
208
+ cpu->isar.id_aa64mmfr1 = t;
209
210
- /* Replicate the same data to the 32-bit id registers. */
211
- u = cpu->isar.id_isar5;
212
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
213
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
214
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
215
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
216
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
217
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
218
- cpu->isar.id_isar5 = u;
219
+ t = cpu->isar.id_aa64mmfr2;
220
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
221
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
222
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
223
+ cpu->isar.id_aa64mmfr2 = t;
224
225
- u = cpu->isar.id_isar6;
226
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
227
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
228
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
229
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
230
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
231
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
232
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
233
- cpu->isar.id_isar6 = u;
234
+ t = cpu->isar.id_aa64zfr0;
235
+ t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
236
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
237
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
238
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
239
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
240
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
241
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
242
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
243
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
244
+ cpu->isar.id_aa64zfr0 = t;
245
246
- u = cpu->isar.id_pfr0;
247
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
248
- cpu->isar.id_pfr0 = u;
249
+ /* Replicate the same data to the 32-bit id registers. */
250
+ u = cpu->isar.id_isar5;
251
+ u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
252
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
253
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
254
+ u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
255
+ u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
256
+ u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
257
+ cpu->isar.id_isar5 = u;
258
259
- u = cpu->isar.id_pfr2;
260
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
261
- cpu->isar.id_pfr2 = u;
262
+ u = cpu->isar.id_isar6;
263
+ u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
264
+ u = FIELD_DP32(u, ID_ISAR6, DP, 1);
265
+ u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
266
+ u = FIELD_DP32(u, ID_ISAR6, SB, 1);
267
+ u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
268
+ u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
269
+ u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
270
+ cpu->isar.id_isar6 = u;
271
272
- u = cpu->isar.id_mmfr3;
273
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
274
- cpu->isar.id_mmfr3 = u;
275
+ u = cpu->isar.id_pfr0;
276
+ u = FIELD_DP32(u, ID_PFR0, DIT, 1);
277
+ cpu->isar.id_pfr0 = u;
278
279
- u = cpu->isar.id_mmfr4;
280
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
281
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
282
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
283
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
284
- cpu->isar.id_mmfr4 = u;
285
+ u = cpu->isar.id_pfr2;
286
+ u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
287
+ cpu->isar.id_pfr2 = u;
288
289
- t = cpu->isar.id_aa64dfr0;
290
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
291
- cpu->isar.id_aa64dfr0 = t;
292
+ u = cpu->isar.id_mmfr3;
293
+ u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
294
+ cpu->isar.id_mmfr3 = u;
295
296
- u = cpu->isar.id_dfr0;
297
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
298
- cpu->isar.id_dfr0 = u;
299
+ u = cpu->isar.id_mmfr4;
300
+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
301
+ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
302
+ u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
303
+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
304
+ cpu->isar.id_mmfr4 = u;
305
306
- u = cpu->isar.mvfr1;
307
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
308
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
309
- cpu->isar.mvfr1 = u;
310
+ t = cpu->isar.id_aa64dfr0;
311
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
312
+ cpu->isar.id_aa64dfr0 = t;
313
+
314
+ u = cpu->isar.id_dfr0;
315
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
316
+ cpu->isar.id_dfr0 = u;
317
+
318
+ u = cpu->isar.mvfr1;
319
+ u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
320
+ u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
321
+ cpu->isar.mvfr1 = u;
322
323
#ifdef CONFIG_USER_ONLY
324
- /* For usermode -cpu max we can use a larger and more efficient DCZ
325
- * blocksize since we don't have to follow what the hardware does.
326
- */
327
- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
328
- cpu->dcz_blocksize = 7; /* 512 bytes */
329
+ /*
330
+ * For usermode -cpu max we can use a larger and more efficient DCZ
331
+ * blocksize since we don't have to follow what the hardware does.
332
+ */
333
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
334
+ cpu->dcz_blocksize = 7; /* 512 bytes */
335
#endif
336
337
- bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
338
- }
339
+ bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
340
341
aarch64_add_pauth_properties(obj);
342
aarch64_add_sve_properties(obj);
343
--
344
2.25.1
345
346
diff view generated by jsdifflib
New patch
[PULL 11/26] target/arm: Fix '-cpu max' for HVF
1
Currently when using hvf we mishandle '-cpu max': we fall through to
2
the TCG version of its initfn, which then sets a lot of feature bits
3
that the real host CPU doesn't have. The hvf accelerator code then
4
exposes these bogus ID register values to the guest because it
5
doesn't check that the host really has the features.
1
6
7
Make '-cpu host' be like '-cpu max' for hvf, as we do with kvm.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Alexander Graf <agraf@csgraf.de>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220204165506.2846058-6-peter.maydell@linaro.org
15
---
16
target/arm/cpu64.c | 5 +++--
17
1 file changed, 3 insertions(+), 2 deletions(-)
18
19
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu64.c
22
+++ b/target/arm/cpu64.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/loader.h"
25
#endif
26
#include "sysemu/kvm.h"
27
+#include "sysemu/hvf.h"
28
#include "kvm_arm.h"
29
#include "hvf_arm.h"
30
#include "qapi/visitor.h"
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
uint64_t t;
33
uint32_t u;
34
35
- if (kvm_enabled()) {
36
- /* With KVM, '-cpu max' is identical to '-cpu host' */
37
+ if (kvm_enabled() || hvf_enabled()) {
38
+ /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
aarch64_host_initfn(obj);
40
return;
41
}
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
[PULL 12/26] target/arm: Support PAuth extension for hvf
1
Currently we don't allow guests under hvf to use the PAuth extension,
2
because we didn't have any special code to handle that, and therefore
3
in arm_cpu_pauth_finalize() we will sanitize the ID_AA64ISAR1 value
4
the guest sees to clear the PAuth related fields.
1
5
6
Add support for this in the same way that KVM does it, by defaulting
7
to "PAuth enabled" if the host CPU has it and allowing the user to
8
disable it via '-cpu pauth=no' on the command line.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
13
Reviewed-by: Alexander Graf <agraf@csgraf.de>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220204165506.2846058-7-peter.maydell@linaro.org
16
---
17
target/arm/cpu64.c | 14 ++++++++++----
18
1 file changed, 10 insertions(+), 4 deletions(-)
19
20
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu64.c
23
+++ b/target/arm/cpu64.c
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
25
uint64_t t;
26
27
/* Exit early if PAuth is enabled, and fall through to disable it */
28
- if (kvm_enabled() && cpu->prop_pauth) {
29
+ if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) {
30
if (!cpu_isar_feature(aa64_pauth, cpu)) {
31
- error_setg(errp, "'pauth' feature not supported by KVM on this host");
32
+ error_setg(errp, "'pauth' feature not supported by %s on this host",
33
+ kvm_enabled() ? "KVM" : "hvf");
34
}
35
36
return;
37
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
38
39
/* Default to PAUTH on, with the architected algorithm on TCG. */
40
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
41
- if (kvm_enabled()) {
42
+ if (kvm_enabled() || hvf_enabled()) {
43
/*
44
* Mirror PAuth support from the probed sysregs back into the
45
- * property for KVM. Is it just a bit backward? Yes it is!
46
+ * property for KVM or hvf. Is it just a bit backward? Yes it is!
47
+ * Note that prop_pauth is true whether the host CPU supports the
48
+ * architected QARMA5 algorithm or the IMPDEF one. We don't
49
+ * provide the separate pauth-impdef property for KVM or hvf,
50
+ * only for TCG.
51
*/
52
cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu);
53
} else {
54
@@ -XXX,XX +XXX,XX @@ static void aarch64_host_initfn(Object *obj)
55
#elif defined(CONFIG_HVF)
56
ARMCPU *cpu = ARM_CPU(obj);
57
hvf_arm_set_cpu_features_from_host(cpu);
58
+ aarch64_add_pauth_properties(obj);
59
#else
60
g_assert_not_reached();
61
#endif
62
--
63
2.25.1
64
65
diff view generated by jsdifflib
New patch
[PULL 13/26] Kconfig: Add I2C_DEVICES device group
1
Currently there is no way for a board model's Kconfig stanza to
2
say "I have an i2c bus which the user can plug an i2c device into,
3
build all the free-standing i2c devices". The Kconfig mechanism
4
for this is the "device group". Add an I2C_DEVICES group along
5
the same lines as the existing PCI_DEVICES. Simple free-standing
6
i2c devices which a user might plausibly want to be able to
7
plug in on the QEMU commandline should have
8
default y if I2C_DEVICES
9
and board models which have an i2c bus that is user-accessible
10
should use
11
imply I2C_DEVICES
12
to cause those pluggable devices to be built.
1
13
14
In this commit we mark only a fairly conservative set of i2c devices
15
as belonging to the I2C_DEVICES group: the simple sensors and RTCs
16
(not including PMBus devices or devices which need GPIO lines to be
17
connected).
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Reviewed-by: Hao Wu <wuhaotsh@google.com>
23
Message-id: 20220208155911.3408455-2-peter.maydell@linaro.org
24
---
25
docs/devel/kconfig.rst | 8 ++++++--
26
hw/i2c/Kconfig | 5 +++++
27
hw/rtc/Kconfig | 2 ++
28
hw/sensor/Kconfig | 5 +++++
29
4 files changed, 18 insertions(+), 2 deletions(-)
30
31
diff --git a/docs/devel/kconfig.rst b/docs/devel/kconfig.rst
32
index XXXXXXX..XXXXXXX 100644
33
--- a/docs/devel/kconfig.rst
34
+++ b/docs/devel/kconfig.rst
35
@@ -XXX,XX +XXX,XX @@ declares its dependencies in different ways:
36
no directive and are not used in the Makefile either; they only appear
37
as conditions for ``default y`` directives.
38
39
- QEMU currently has two device groups, ``PCI_DEVICES`` and
40
- ``TEST_DEVICES``. PCI devices usually have a ``default y if
41
+ QEMU currently has three device groups, ``PCI_DEVICES``, ``I2C_DEVICES``,
42
+ and ``TEST_DEVICES``. PCI devices usually have a ``default y if
43
PCI_DEVICES`` directive rather than just ``default y``. This lets
44
some boards (notably s390) easily support a subset of PCI devices,
45
for example only VFIO (passthrough) and virtio-pci devices.
46
+ ``I2C_DEVICES`` is similar to ``PCI_DEVICES``. It contains i2c devices
47
+ that users might reasonably want to plug in to an i2c bus on any
48
+ board (and not ones which are very board-specific or that need
49
+ to be wired up in a way that can't be done on the command line).
50
``TEST_DEVICES`` instead is used for devices that are rarely used on
51
production virtual machines, but provide useful hooks to test QEMU
52
or KVM.
53
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/i2c/Kconfig
56
+++ b/hw/i2c/Kconfig
57
@@ -XXX,XX +XXX,XX @@
58
config I2C
59
bool
60
61
+config I2C_DEVICES
62
+ # Device group for i2c devices which can reasonably be user-plugged
63
+ # to any board's i2c bus
64
+ bool
65
+
66
config SMBUS
67
bool
68
select I2C
69
diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/rtc/Kconfig
72
+++ b/hw/rtc/Kconfig
73
@@ -XXX,XX +XXX,XX @@
74
config DS1338
75
bool
76
depends on I2C
77
+ default y if I2C_DEVICES
78
79
config M41T80
80
bool
81
depends on I2C
82
+ default y if I2C_DEVICES
83
84
config M48T59
85
bool
86
diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/sensor/Kconfig
89
+++ b/hw/sensor/Kconfig
90
@@ -XXX,XX +XXX,XX @@
91
config TMP105
92
bool
93
depends on I2C
94
+ default y if I2C_DEVICES
95
96
config TMP421
97
bool
98
depends on I2C
99
+ default y if I2C_DEVICES
100
101
config DPS310
102
bool
103
depends on I2C
104
+ default y if I2C_DEVICES
105
106
config EMC141X
107
bool
108
depends on I2C
109
+ default y if I2C_DEVICES
110
111
config ADM1272
112
bool
113
@@ -XXX,XX +XXX,XX @@ config MAX34451
114
config LSM303DLHC_MAG
115
bool
116
depends on I2C
117
+ default y if I2C_DEVICES
118
--
119
2.25.1
120
121
diff view generated by jsdifflib
New patch
[PULL 14/26] Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
1
For arm boards with an i2c bus which a user could reasonably
2
want to plug arbitrary devices, add 'imply I2C_DEVICES' to the
3
Kconfig stanza.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20220208155911.3408455-3-peter.maydell@linaro.org
10
---
11
hw/arm/Kconfig | 10 ++++++++++
12
1 file changed, 10 insertions(+)
13
14
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Kconfig
17
+++ b/hw/arm/Kconfig
18
@@ -XXX,XX +XXX,XX @@ config DIGIC
19
20
config EXYNOS4
21
bool
22
+ imply I2C_DEVICES
23
select A9MPCORE
24
select I2C
25
select LAN9118
26
@@ -XXX,XX +XXX,XX @@ config REALVIEW
27
bool
28
imply PCI_DEVICES
29
imply PCI_TESTDEV
30
+ imply I2C_DEVICES
31
select SMC91C111
32
select LAN9118
33
select A9MPCORE
34
@@ -XXX,XX +XXX,XX @@ config SABRELITE
35
36
config STELLARIS
37
bool
38
+ imply I2C_DEVICES
39
select ARM_V7M
40
select CMSDK_APB_WATCHDOG
41
select I2C
42
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
43
44
config FSL_IMX25
45
bool
46
+ imply I2C_DEVICES
47
select IMX
48
select IMX_FEC
49
select IMX_I2C
50
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
51
52
config FSL_IMX31
53
bool
54
+ imply I2C_DEVICES
55
select SERIAL
56
select IMX
57
select IMX_I2C
58
@@ -XXX,XX +XXX,XX @@ config FSL_IMX31
59
60
config FSL_IMX6
61
bool
62
+ imply I2C_DEVICES
63
select A9MPCORE
64
select IMX
65
select IMX_FEC
66
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
67
68
config MPS2
69
bool
70
+ imply I2C_DEVICES
71
select ARMSSE
72
select LAN9118
73
select MPS2_FPGAIO
74
@@ -XXX,XX +XXX,XX @@ config FSL_IMX7
75
bool
76
imply PCI_DEVICES
77
imply TEST_DEVICES
78
+ imply I2C_DEVICES
79
select A15MPCORE
80
select PCI
81
select IMX
82
@@ -XXX,XX +XXX,XX @@ config ARM_SMMUV3
83
84
config FSL_IMX6UL
85
bool
86
+ imply I2C_DEVICES
87
select A15MPCORE
88
select IMX
89
select IMX_FEC
90
@@ -XXX,XX +XXX,XX @@ config MICROBIT
91
92
config NRF51_SOC
93
bool
94
+ imply I2C_DEVICES
95
select I2C
96
select ARM_V7M
97
select UNIMP
98
--
99
2.25.1
100
101
diff view generated by jsdifflib
[PULL 5/5] hw/intc/arm_gicv3: fix handling of LPIs in list registers
[PULL 15/26] hw/arm/armv7m: Handle disconnected clock inputs
1
It is valid for an OS to put virtual interrupt ID values into the
1
In the armv7m object, handle clock inputs that aren't connected.
2
list registers ICH_LR<n> which are greater than 1023. This
2
This is always an error for 'cpuclk'. For 'refclk' it is OK for this
3
corresponds to (for example) KVM using the in-kernel emulated ITS to
3
to be disconnected, but we need to handle it by not trying to connect
4
give a (nested) guest an ITS. LPIs are delivered by the L1 kernel to
4
a sourceless-clock to the systick device.
5
the L2 guest via the list registers in the same way as non-LPI
6
interrupts.
7
5
8
QEMU's code for handling writes to ICV_IARn (which happen when the L2
6
This fixes a bug where on the mps2-an521 and similar boards (which
9
guest acknowledges an interrupt) and to ICV_EOIRn (which happen at
7
do not have a refclk) the systick device incorrectly reset with
10
the end of the interrupt) did not consider LPIs, so it would
8
SYST_CSR.CLKSOURCE 0 ("use refclk") rather than 1 ("use CPU clock").
11
incorrectly treat interrupt IDs above 1023 as invalid. Fix this by
12
using the correct condition, which is gicv3_intid_is_special().
13
9
14
Note that the condition in icv_dir_write() is correct -- LPIs
10
Cc: qemu-stable@nongnu.org
15
are not valid there and so we want to ignore both "special" ID
11
Reported-by: Richard Petri <git@rpls.de>
16
values and LPIs.
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220208171643.3486277-1-peter.maydell@linaro.org
16
---
17
hw/arm/armv7m.c | 26 ++++++++++++++++++++++----
18
1 file changed, 22 insertions(+), 4 deletions(-)
17
19
18
(In the pseudocode this logic is in:
20
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
19
- VirtualReadIAR0(), VirtualReadIAR1(), which call IsSpecial()
20
- VirtualWriteEOIR0(), VirtualWriteEOIR1(), which call
21
VirtualIdentifierValid(data, TRUE) meaning "LPIs OK"
22
- VirtualWriteDIR(), which calls VirtualIdentifierValid(data, FALSE)
23
meaning "LPIs not OK")
24
25
This bug doesn't seem to have any visible effect on Linux L2 guests
26
most of the time, because the two bugs cancel each other out: we
27
neither mark the interrupt active nor deactivate it. However it does
28
mean that the L2 vCPU priority while the LPI handler is running will
29
not be correct, so the interrupt handler could be unexpectedly
30
interrupted by a different interrupt.
31
32
(NB: this has nothing to do with using QEMU's emulated ITS.)
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Marc Zyngier <maz@kernel.org>
36
---
37
hw/intc/arm_gicv3_cpuif.c | 5 ++---
38
1 file changed, 2 insertions(+), 3 deletions(-)
39
40
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
41
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/intc/arm_gicv3_cpuif.c
22
--- a/hw/arm/armv7m.c
43
+++ b/hw/intc/arm_gicv3_cpuif.c
23
+++ b/hw/arm/armv7m.c
44
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
24
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
45
46
if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
47
intid = ich_lr_vintid(lr);
48
- if (intid < INTID_SECURE) {
49
+ if (!gicv3_intid_is_special(intid)) {
50
icv_activate_irq(cs, idx, grp);
51
} else {
52
/* Interrupt goes from Pending to Invalid */
53
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
54
trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
55
gicv3_redist_affid(cs), value);
56
57
- if (irq >= GICV3_MAXIRQ) {
58
- /* Also catches special interrupt numbers and LPIs */
59
+ if (gicv3_intid_is_special(irq)) {
60
return;
25
return;
61
}
26
}
27
28
+ /* cpuclk must be connected; refclk is optional */
29
+ if (!clock_has_source(s->cpuclk)) {
30
+ error_setg(errp, "armv7m: cpuclk must be connected");
31
+ return;
32
+ }
33
+
34
memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
35
36
s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
37
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
38
&s->sysreg_ns_mem);
39
}
40
41
- /* Create and map the systick devices */
42
- qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk);
43
+ /*
44
+ * Create and map the systick devices. Note that we only connect
45
+ * refclk if it has been connected to us; otherwise the systick
46
+ * device gets the wrong answer for clock_has_source(refclk), because
47
+ * it has an immediate source (the ARMv7M's clock object) but not
48
+ * an ultimate source, and then it won't correctly auto-select the
49
+ * CPU clock as its only possible clock source.
50
+ */
51
+ if (clock_has_source(s->refclk)) {
52
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk",
53
+ s->refclk);
54
+ }
55
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
56
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
57
return;
58
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
59
*/
60
object_initialize_child(OBJECT(dev), "systick-reg-s",
61
&s->systick[M_REG_S], TYPE_SYSTICK);
62
- qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
63
- s->refclk);
64
+ if (clock_has_source(s->refclk)) {
65
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
66
+ s->refclk);
67
+ }
68
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
69
s->cpuclk);
62
70
63
--
71
--
64
2.25.1
72
2.25.1
65
73
66
74
diff view generated by jsdifflib
New patch
[PULL 16/26] include: Move qemu_madvise() and related #defines to new qemu/madvise.h
1
The function qemu_madvise() and the QEMU_MADV_* constants associated
2
with it are used in only 10 files. Move them out of osdep.h to a new
3
qemu/madvise.h header that is included where it is needed.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220208200856.3558249-2-peter.maydell@linaro.org
9
---
10
include/qemu/madvise.h | 95 ++++++++++++++++++++++++++++++++++++++
11
include/qemu/osdep.h | 82 --------------------------------
12
backends/hostmem-file.c | 1 +
13
backends/hostmem.c | 1 +
14
hw/virtio/virtio-balloon.c | 1 +
15
migration/postcopy-ram.c | 1 +
16
migration/qemu-file.c | 1 +
17
migration/ram.c | 1 +
18
softmmu/physmem.c | 1 +
19
tcg/region.c | 1 +
20
util/osdep.c | 1 +
21
util/oslib-posix.c | 1 +
22
12 files changed, 105 insertions(+), 82 deletions(-)
23
create mode 100644 include/qemu/madvise.h
24
25
diff --git a/include/qemu/madvise.h b/include/qemu/madvise.h
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/include/qemu/madvise.h
30
@@ -XXX,XX +XXX,XX @@
31
+/*
32
+ * QEMU madvise wrapper functions
33
+ *
34
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
35
+ * See the COPYING file in the top-level directory.
36
+ */
37
+
38
+#ifndef QEMU_MADVISE_H
39
+#define QEMU_MADVISE_H
40
+
41
+#define QEMU_MADV_INVALID -1
42
+
43
+#if defined(CONFIG_MADVISE)
44
+
45
+#define QEMU_MADV_WILLNEED MADV_WILLNEED
46
+#define QEMU_MADV_DONTNEED MADV_DONTNEED
47
+#ifdef MADV_DONTFORK
48
+#define QEMU_MADV_DONTFORK MADV_DONTFORK
49
+#else
50
+#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
51
+#endif
52
+#ifdef MADV_MERGEABLE
53
+#define QEMU_MADV_MERGEABLE MADV_MERGEABLE
54
+#else
55
+#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
56
+#endif
57
+#ifdef MADV_UNMERGEABLE
58
+#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE
59
+#else
60
+#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
61
+#endif
62
+#ifdef MADV_DODUMP
63
+#define QEMU_MADV_DODUMP MADV_DODUMP
64
+#else
65
+#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
66
+#endif
67
+#ifdef MADV_DONTDUMP
68
+#define QEMU_MADV_DONTDUMP MADV_DONTDUMP
69
+#else
70
+#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
71
+#endif
72
+#ifdef MADV_HUGEPAGE
73
+#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE
74
+#else
75
+#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
76
+#endif
77
+#ifdef MADV_NOHUGEPAGE
78
+#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE
79
+#else
80
+#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
81
+#endif
82
+#ifdef MADV_REMOVE
83
+#define QEMU_MADV_REMOVE MADV_REMOVE
84
+#else
85
+#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
86
+#endif
87
+#ifdef MADV_POPULATE_WRITE
88
+#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE
89
+#else
90
+#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
91
+#endif
92
+
93
+#elif defined(CONFIG_POSIX_MADVISE)
94
+
95
+#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED
96
+#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED
97
+#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
98
+#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
99
+#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
100
+#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
101
+#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
102
+#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
103
+#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
104
+#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
105
+#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
106
+
107
+#else /* no-op */
108
+
109
+#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID
110
+#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID
111
+#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
112
+#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
113
+#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
114
+#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
115
+#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
116
+#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
117
+#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
118
+#define QEMU_MADV_REMOVE QEMU_MADV_INVALID
119
+#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
120
+
121
+#endif
122
+
123
+int qemu_madvise(void *addr, size_t len, int advice);
124
+
125
+#endif
126
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
127
index XXXXXXX..XXXXXXX 100644
128
--- a/include/qemu/osdep.h
129
+++ b/include/qemu/osdep.h
130
@@ -XXX,XX +XXX,XX @@ static inline void qemu_cleanup_generic_vfree(void *p)
131
#define QEMU_MAP_NORESERVE (1 << 3)
132
133
134
-#define QEMU_MADV_INVALID -1
135
-
136
-#if defined(CONFIG_MADVISE)
137
-
138
-#define QEMU_MADV_WILLNEED MADV_WILLNEED
139
-#define QEMU_MADV_DONTNEED MADV_DONTNEED
140
-#ifdef MADV_DONTFORK
141
-#define QEMU_MADV_DONTFORK MADV_DONTFORK
142
-#else
143
-#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
144
-#endif
145
-#ifdef MADV_MERGEABLE
146
-#define QEMU_MADV_MERGEABLE MADV_MERGEABLE
147
-#else
148
-#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
149
-#endif
150
-#ifdef MADV_UNMERGEABLE
151
-#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE
152
-#else
153
-#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
154
-#endif
155
-#ifdef MADV_DODUMP
156
-#define QEMU_MADV_DODUMP MADV_DODUMP
157
-#else
158
-#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
159
-#endif
160
-#ifdef MADV_DONTDUMP
161
-#define QEMU_MADV_DONTDUMP MADV_DONTDUMP
162
-#else
163
-#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
164
-#endif
165
-#ifdef MADV_HUGEPAGE
166
-#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE
167
-#else
168
-#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
169
-#endif
170
-#ifdef MADV_NOHUGEPAGE
171
-#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE
172
-#else
173
-#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
174
-#endif
175
-#ifdef MADV_REMOVE
176
-#define QEMU_MADV_REMOVE MADV_REMOVE
177
-#else
178
-#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
179
-#endif
180
-#ifdef MADV_POPULATE_WRITE
181
-#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE
182
-#else
183
-#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
184
-#endif
185
-
186
-#elif defined(CONFIG_POSIX_MADVISE)
187
-
188
-#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED
189
-#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED
190
-#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
191
-#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
192
-#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
193
-#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
194
-#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
195
-#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
196
-#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
197
-#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED
198
-#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
199
-
200
-#else /* no-op */
201
-
202
-#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID
203
-#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID
204
-#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID
205
-#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID
206
-#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID
207
-#define QEMU_MADV_DODUMP QEMU_MADV_INVALID
208
-#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID
209
-#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID
210
-#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID
211
-#define QEMU_MADV_REMOVE QEMU_MADV_INVALID
212
-#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID
213
-
214
-#endif
215
216
#ifdef _WIN32
217
#define HAVE_CHARDEV_SERIAL 1
218
@@ -XXX,XX +XXX,XX @@ void sigaction_invoke(struct sigaction *action,
219
struct qemu_signalfd_siginfo *info);
220
#endif
221
222
-int qemu_madvise(void *addr, size_t len, int advice);
223
int qemu_mprotect_rw(void *addr, size_t size);
224
int qemu_mprotect_rwx(void *addr, size_t size);
225
int qemu_mprotect_none(void *addr, size_t size);
226
diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
227
index XXXXXXX..XXXXXXX 100644
228
--- a/backends/hostmem-file.c
229
+++ b/backends/hostmem-file.c
230
@@ -XXX,XX +XXX,XX @@
231
#include "qapi/error.h"
232
#include "qemu/error-report.h"
233
#include "qemu/module.h"
234
+#include "qemu/madvise.h"
235
#include "sysemu/hostmem.h"
236
#include "qom/object_interfaces.h"
237
#include "qom/object.h"
238
diff --git a/backends/hostmem.c b/backends/hostmem.c
239
index XXXXXXX..XXXXXXX 100644
240
--- a/backends/hostmem.c
241
+++ b/backends/hostmem.c
242
@@ -XXX,XX +XXX,XX @@
243
#include "qemu/config-file.h"
244
#include "qom/object_interfaces.h"
245
#include "qemu/mmap-alloc.h"
246
+#include "qemu/madvise.h"
247
248
#ifdef CONFIG_NUMA
249
#include <numaif.h>
250
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/hw/virtio/virtio-balloon.c
253
+++ b/hw/virtio/virtio-balloon.c
254
@@ -XXX,XX +XXX,XX @@
255
#include "qemu/iov.h"
256
#include "qemu/module.h"
257
#include "qemu/timer.h"
258
+#include "qemu/madvise.h"
259
#include "hw/virtio/virtio.h"
260
#include "hw/mem/pc-dimm.h"
261
#include "hw/qdev-properties.h"
262
diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c
263
index XXXXXXX..XXXXXXX 100644
264
--- a/migration/postcopy-ram.c
265
+++ b/migration/postcopy-ram.c
266
@@ -XXX,XX +XXX,XX @@
267
268
#include "qemu/osdep.h"
269
#include "qemu/rcu.h"
270
+#include "qemu/madvise.h"
271
#include "exec/target_page.h"
272
#include "migration.h"
273
#include "qemu-file.h"
274
diff --git a/migration/qemu-file.c b/migration/qemu-file.c
275
index XXXXXXX..XXXXXXX 100644
276
--- a/migration/qemu-file.c
277
+++ b/migration/qemu-file.c
278
@@ -XXX,XX +XXX,XX @@
279
*/
280
#include "qemu/osdep.h"
281
#include <zlib.h>
282
+#include "qemu/madvise.h"
283
#include "qemu/error-report.h"
284
#include "qemu/iov.h"
285
#include "migration.h"
286
diff --git a/migration/ram.c b/migration/ram.c
287
index XXXXXXX..XXXXXXX 100644
288
--- a/migration/ram.c
289
+++ b/migration/ram.c
290
@@ -XXX,XX +XXX,XX @@
291
#include "qemu/cutils.h"
292
#include "qemu/bitops.h"
293
#include "qemu/bitmap.h"
294
+#include "qemu/madvise.h"
295
#include "qemu/main-loop.h"
296
#include "xbzrle.h"
297
#include "ram.h"
298
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
299
index XXXXXXX..XXXXXXX 100644
300
--- a/softmmu/physmem.c
301
+++ b/softmmu/physmem.c
302
@@ -XXX,XX +XXX,XX @@
303
304
#include "qemu/cutils.h"
305
#include "qemu/cacheflush.h"
306
+#include "qemu/madvise.h"
307
308
#ifdef CONFIG_TCG
309
#include "hw/core/tcg-cpu-ops.h"
310
diff --git a/tcg/region.c b/tcg/region.c
311
index XXXXXXX..XXXXXXX 100644
312
--- a/tcg/region.c
313
+++ b/tcg/region.c
314
@@ -XXX,XX +XXX,XX @@
315
316
#include "qemu/osdep.h"
317
#include "qemu/units.h"
318
+#include "qemu/madvise.h"
319
#include "qapi/error.h"
320
#include "exec/exec-all.h"
321
#include "tcg/tcg.h"
322
diff --git a/util/osdep.c b/util/osdep.c
323
index XXXXXXX..XXXXXXX 100644
324
--- a/util/osdep.c
325
+++ b/util/osdep.c
326
@@ -XXX,XX +XXX,XX @@ extern int madvise(char *, size_t, int);
327
#include "qemu/cutils.h"
328
#include "qemu/sockets.h"
329
#include "qemu/error-report.h"
330
+#include "qemu/madvise.h"
331
#include "monitor/monitor.h"
332
333
static bool fips_enabled = false;
334
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
335
index XXXXXXX..XXXXXXX 100644
336
--- a/util/oslib-posix.c
337
+++ b/util/oslib-posix.c
338
@@ -XXX,XX +XXX,XX @@
339
#include "trace.h"
340
#include "qapi/error.h"
341
#include "qemu/error-report.h"
342
+#include "qemu/madvise.h"
343
#include "qemu/sockets.h"
344
#include "qemu/thread.h"
345
#include <libgen.h>
346
--
347
2.25.1
348
349
diff view generated by jsdifflib
New patch
[PULL 17/26] include: Move qemu_mprotect_*() to new qemu/mprotect.h
1
The qemu_mprotect_*() family of functions are used in very few files;
2
move them from osdep.h to a new qemu/mprotect.h.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220208200856.3558249-3-peter.maydell@linaro.org
8
---
9
include/qemu/mprotect.h | 14 ++++++++++++++
10
include/qemu/osdep.h | 4 ----
11
tcg/region.c | 1 +
12
util/osdep.c | 1 +
13
4 files changed, 16 insertions(+), 4 deletions(-)
14
create mode 100644 include/qemu/mprotect.h
15
16
diff --git a/include/qemu/mprotect.h b/include/qemu/mprotect.h
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/include/qemu/mprotect.h
21
@@ -XXX,XX +XXX,XX @@
22
+/*
23
+ * QEMU mprotect functions
24
+ *
25
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
26
+ * See the COPYING file in the top-level directory.
27
+ */
28
+#ifndef QEMU_MPROTECT_H
29
+#define QEMU_MPROTECT_H
30
+
31
+int qemu_mprotect_rw(void *addr, size_t size);
32
+int qemu_mprotect_rwx(void *addr, size_t size);
33
+int qemu_mprotect_none(void *addr, size_t size);
34
+
35
+#endif
36
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/qemu/osdep.h
39
+++ b/include/qemu/osdep.h
40
@@ -XXX,XX +XXX,XX @@ void sigaction_invoke(struct sigaction *action,
41
struct qemu_signalfd_siginfo *info);
42
#endif
43
44
-int qemu_mprotect_rw(void *addr, size_t size);
45
-int qemu_mprotect_rwx(void *addr, size_t size);
46
-int qemu_mprotect_none(void *addr, size_t size);
47
-
48
/*
49
* Don't introduce new usage of this function, prefer the following
50
* qemu_open/qemu_create that take an "Error **errp"
51
diff --git a/tcg/region.c b/tcg/region.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/region.c
54
+++ b/tcg/region.c
55
@@ -XXX,XX +XXX,XX @@
56
#include "qemu/osdep.h"
57
#include "qemu/units.h"
58
#include "qemu/madvise.h"
59
+#include "qemu/mprotect.h"
60
#include "qapi/error.h"
61
#include "exec/exec-all.h"
62
#include "tcg/tcg.h"
63
diff --git a/util/osdep.c b/util/osdep.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/util/osdep.c
66
+++ b/util/osdep.c
67
@@ -XXX,XX +XXX,XX @@ extern int madvise(char *, size_t, int);
68
#include "qemu/sockets.h"
69
#include "qemu/error-report.h"
70
#include "qemu/madvise.h"
71
+#include "qemu/mprotect.h"
72
#include "monitor/monitor.h"
73
74
static bool fips_enabled = false;
75
--
76
2.25.1
77
78
diff view generated by jsdifflib
New patch
[PULL 18/26] include: Move QEMU_MAP_* constants to mmap-alloc.h
1
The QEMU_MAP_* constants are used only as arguments to the
2
qemu_ram_mmap() function. Move them to mmap-alloc.h, where that
3
function's prototype is defined.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220208200856.3558249-4-peter.maydell@linaro.org
9
---
10
include/qemu/mmap-alloc.h | 23 +++++++++++++++++++++++
11
include/qemu/osdep.h | 25 -------------------------
12
2 files changed, 23 insertions(+), 25 deletions(-)
13
14
diff --git a/include/qemu/mmap-alloc.h b/include/qemu/mmap-alloc.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/qemu/mmap-alloc.h
17
+++ b/include/qemu/mmap-alloc.h
18
@@ -XXX,XX +XXX,XX @@ void *qemu_ram_mmap(int fd,
19
20
void qemu_ram_munmap(int fd, void *ptr, size_t size);
21
22
+/*
23
+ * Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example,
24
+ * consumed by qemu_ram_mmap().
25
+ */
26
+
27
+/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */
28
+#define QEMU_MAP_READONLY (1 << 0)
29
+
30
+/* Use MAP_SHARED instead of MAP_PRIVATE. */
31
+#define QEMU_MAP_SHARED (1 << 1)
32
+
33
+/*
34
+ * Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without
35
+ * QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC.
36
+ */
37
+#define QEMU_MAP_SYNC (1 << 2)
38
+
39
+/*
40
+ * Use MAP_NORESERVE to skip reservation of swap space (or huge pages if
41
+ * applicable). Bail out if not supported/effective.
42
+ */
43
+#define QEMU_MAP_NORESERVE (1 << 3)
44
+
45
#endif
46
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/qemu/osdep.h
49
+++ b/include/qemu/osdep.h
50
@@ -XXX,XX +XXX,XX @@ static inline void qemu_cleanup_generic_vfree(void *p)
51
*/
52
#define QEMU_AUTO_VFREE __attribute__((cleanup(qemu_cleanup_generic_vfree)))
53
54
-/*
55
- * Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example,
56
- * consumed by qemu_ram_mmap().
57
- */
58
-
59
-/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */
60
-#define QEMU_MAP_READONLY (1 << 0)
61
-
62
-/* Use MAP_SHARED instead of MAP_PRIVATE. */
63
-#define QEMU_MAP_SHARED (1 << 1)
64
-
65
-/*
66
- * Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without
67
- * QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC.
68
- */
69
-#define QEMU_MAP_SYNC (1 << 2)
70
-
71
-/*
72
- * Use MAP_NORESERVE to skip reservation of swap space (or huge pages if
73
- * applicable). Bail out if not supported/effective.
74
- */
75
-#define QEMU_MAP_NORESERVE (1 << 3)
76
-
77
-
78
-
79
#ifdef _WIN32
80
#define HAVE_CHARDEV_SERIAL 1
81
#elif defined(__linux__) || defined(__sun__) || defined(__FreeBSD__) \
82
--
83
2.25.1
84
85
diff view generated by jsdifflib
New patch
[PULL 19/26] include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h
1
The qemu_icache_linesize, qemu_icache_linesize_log,
2
qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not
3
used in many files. Move them out of osdep.h to a new
4
qemu/cacheinfo.h, and document them.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org
10
---
11
include/qemu/cacheinfo.h | 21 +++++++++++++++++++++
12
include/qemu/osdep.h | 5 -----
13
accel/tcg/translate-all.c | 1 +
14
plugins/loader.c | 1 +
15
tcg/region.c | 1 +
16
tcg/tcg.c | 1 +
17
util/atomic64.c | 1 +
18
util/cacheflush.c | 1 +
19
util/cacheinfo.c | 1 +
20
9 files changed, 28 insertions(+), 5 deletions(-)
21
create mode 100644 include/qemu/cacheinfo.h
22
23
diff --git a/include/qemu/cacheinfo.h b/include/qemu/cacheinfo.h
24
new file mode 100644
25
index XXXXXXX..XXXXXXX
26
--- /dev/null
27
+++ b/include/qemu/cacheinfo.h
28
@@ -XXX,XX +XXX,XX @@
29
+/*
30
+ * QEMU host cacheinfo information
31
+ *
32
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
33
+ * See the COPYING file in the top-level directory.
34
+ */
35
+#ifndef QEMU_CACHEINFO_H
36
+#define QEMU_CACHEINFO_H
37
+
38
+/*
39
+ * These variables represent our best guess at the host icache and
40
+ * dcache sizes, expressed both as the size in bytes and as the
41
+ * base-2 log of the size in bytes. They are initialized at startup
42
+ * (via an attribute 'constructor' function).
43
+ */
44
+extern int qemu_icache_linesize;
45
+extern int qemu_icache_linesize_log;
46
+extern int qemu_dcache_linesize;
47
+extern int qemu_dcache_linesize_log;
48
+
49
+#endif
50
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/include/qemu/osdep.h
53
+++ b/include/qemu/osdep.h
54
@@ -XXX,XX +XXX,XX @@ pid_t qemu_fork(Error **errp);
55
extern uintptr_t qemu_real_host_page_size;
56
extern intptr_t qemu_real_host_page_mask;
57
58
-extern int qemu_icache_linesize;
59
-extern int qemu_icache_linesize_log;
60
-extern int qemu_dcache_linesize;
61
-extern int qemu_dcache_linesize_log;
62
-
63
/*
64
* After using getopt or getopt_long, if you need to parse another set
65
* of options, then you must reset optind. Unfortunately the way to
66
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/accel/tcg/translate-all.c
69
+++ b/accel/tcg/translate-all.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "qemu/qemu-print.h"
72
#include "qemu/timer.h"
73
#include "qemu/main-loop.h"
74
+#include "qemu/cacheinfo.h"
75
#include "exec/log.h"
76
#include "sysemu/cpus.h"
77
#include "sysemu/cpu-timers.h"
78
diff --git a/plugins/loader.c b/plugins/loader.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/plugins/loader.c
81
+++ b/plugins/loader.c
82
@@ -XXX,XX +XXX,XX @@
83
#include "qemu/rcu_queue.h"
84
#include "qemu/qht.h"
85
#include "qemu/bitmap.h"
86
+#include "qemu/cacheinfo.h"
87
#include "qemu/xxhash.h"
88
#include "qemu/plugin.h"
89
#include "hw/core/cpu.h"
90
diff --git a/tcg/region.c b/tcg/region.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/tcg/region.c
93
+++ b/tcg/region.c
94
@@ -XXX,XX +XXX,XX @@
95
#include "qemu/units.h"
96
#include "qemu/madvise.h"
97
#include "qemu/mprotect.h"
98
+#include "qemu/cacheinfo.h"
99
#include "qapi/error.h"
100
#include "exec/exec-all.h"
101
#include "tcg/tcg.h"
102
diff --git a/tcg/tcg.c b/tcg/tcg.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/tcg/tcg.c
105
+++ b/tcg/tcg.c
106
@@ -XXX,XX +XXX,XX @@
107
#include "qemu/qemu-print.h"
108
#include "qemu/timer.h"
109
#include "qemu/cacheflush.h"
110
+#include "qemu/cacheinfo.h"
111
112
/* Note: the long term plan is to reduce the dependencies on the QEMU
113
CPU definitions. Currently they are used for qemu_ld/st
114
diff --git a/util/atomic64.c b/util/atomic64.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/util/atomic64.c
117
+++ b/util/atomic64.c
118
@@ -XXX,XX +XXX,XX @@
119
#include "qemu/osdep.h"
120
#include "qemu/atomic.h"
121
#include "qemu/thread.h"
122
+#include "qemu/cacheinfo.h"
123
124
#ifdef CONFIG_ATOMIC64
125
#error This file must only be compiled if !CONFIG_ATOMIC64
126
diff --git a/util/cacheflush.c b/util/cacheflush.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/util/cacheflush.c
129
+++ b/util/cacheflush.c
130
@@ -XXX,XX +XXX,XX @@
131
132
#include "qemu/osdep.h"
133
#include "qemu/cacheflush.h"
134
+#include "qemu/cacheinfo.h"
135
#include "qemu/bitops.h"
136
137
138
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
139
index XXXXXXX..XXXXXXX 100644
140
--- a/util/cacheinfo.c
141
+++ b/util/cacheinfo.c
142
@@ -XXX,XX +XXX,XX @@
143
#include "qemu/osdep.h"
144
#include "qemu/host-utils.h"
145
#include "qemu/atomic.h"
146
+#include "qemu/cacheinfo.h"
147
148
int qemu_icache_linesize = 0;
149
int qemu_icache_linesize_log;
150
--
151
2.25.1
152
153
diff view generated by jsdifflib
New patch
[PULL 20/26] include: Move hardware version declarations to new qemu/hw-version.h
1
The "hardware version" machinery (qemu_set_hw_version(),
2
qemu_hw_version(), and the QEMU_HW_VERSION define) is used by fewer
3
than 10 files. Move it out from osdep.h into a new
4
qemu/hw-version.h.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220208200856.3558249-6-peter.maydell@linaro.org
10
---
11
include/qemu/hw-version.h | 27 +++++++++++++++++++++++++++
12
include/qemu/osdep.h | 16 ----------------
13
hw/arm/nseries.c | 1 +
14
hw/ide/core.c | 1 +
15
hw/scsi/megasas.c | 1 +
16
hw/scsi/scsi-bus.c | 1 +
17
hw/scsi/scsi-disk.c | 1 +
18
softmmu/vl.c | 1 +
19
target/i386/cpu.c | 1 +
20
target/s390x/cpu_models.c | 1 +
21
util/osdep.c | 1 +
22
11 files changed, 36 insertions(+), 16 deletions(-)
23
create mode 100644 include/qemu/hw-version.h
24
25
diff --git a/include/qemu/hw-version.h b/include/qemu/hw-version.h
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/include/qemu/hw-version.h
30
@@ -XXX,XX +XXX,XX @@
31
+/*
32
+ * QEMU "hardware version" machinery
33
+ *
34
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
35
+ * See the COPYING file in the top-level directory.
36
+ */
37
+#ifndef QEMU_HW_VERSION_H
38
+#define QEMU_HW_VERSION_H
39
+
40
+/*
41
+ * Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
42
+ * instead of QEMU_VERSION, so setting hw_version on MachineClass
43
+ * is no longer mandatory.
44
+ *
45
+ * Do NOT change this string, or it will break compatibility on all
46
+ * machine classes that don't set hw_version.
47
+ */
48
+#define QEMU_HW_VERSION "2.5+"
49
+
50
+/* QEMU "hardware version" setting. Used to replace code that exposed
51
+ * QEMU_VERSION to guests in the past and need to keep compatibility.
52
+ * Do not use qemu_hw_version() in new code.
53
+ */
54
+void qemu_set_hw_version(const char *);
55
+const char *qemu_hw_version(void);
56
+
57
+#endif
58
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
59
index XXXXXXX..XXXXXXX 100644
60
--- a/include/qemu/osdep.h
61
+++ b/include/qemu/osdep.h
62
@@ -XXX,XX +XXX,XX @@ static inline void qemu_timersub(const struct timeval *val1,
63
64
void qemu_set_cloexec(int fd);
65
66
-/* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default
67
- * instead of QEMU_VERSION, so setting hw_version on MachineClass
68
- * is no longer mandatory.
69
- *
70
- * Do NOT change this string, or it will break compatibility on all
71
- * machine classes that don't set hw_version.
72
- */
73
-#define QEMU_HW_VERSION "2.5+"
74
-
75
-/* QEMU "hardware version" setting. Used to replace code that exposed
76
- * QEMU_VERSION to guests in the past and need to keep compatibility.
77
- * Do not use qemu_hw_version() in new code.
78
- */
79
-void qemu_set_hw_version(const char *);
80
-const char *qemu_hw_version(void);
81
-
82
void fips_set_state(bool requested);
83
bool fips_get_state(void);
84
85
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/arm/nseries.c
88
+++ b/hw/arm/nseries.c
89
@@ -XXX,XX +XXX,XX @@
90
#include "chardev/char.h"
91
#include "qemu/cutils.h"
92
#include "qemu/bswap.h"
93
+#include "qemu/hw-version.h"
94
#include "sysemu/reset.h"
95
#include "sysemu/runstate.h"
96
#include "sysemu/sysemu.h"
97
diff --git a/hw/ide/core.c b/hw/ide/core.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/ide/core.c
100
+++ b/hw/ide/core.c
101
@@ -XXX,XX +XXX,XX @@
102
#include "qemu/error-report.h"
103
#include "qemu/main-loop.h"
104
#include "qemu/timer.h"
105
+#include "qemu/hw-version.h"
106
#include "sysemu/sysemu.h"
107
#include "sysemu/blockdev.h"
108
#include "sysemu/dma.h"
109
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/hw/scsi/megasas.c
112
+++ b/hw/scsi/megasas.c
113
@@ -XXX,XX +XXX,XX @@
114
#include "hw/pci/msix.h"
115
#include "qemu/iov.h"
116
#include "qemu/module.h"
117
+#include "qemu/hw-version.h"
118
#include "hw/scsi/scsi.h"
119
#include "scsi/constants.h"
120
#include "trace.h"
121
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/hw/scsi/scsi-bus.c
124
+++ b/hw/scsi/scsi-bus.c
125
@@ -XXX,XX +XXX,XX @@
126
#include "qemu/error-report.h"
127
#include "qemu/module.h"
128
#include "qemu/option.h"
129
+#include "qemu/hw-version.h"
130
#include "hw/qdev-properties.h"
131
#include "hw/scsi/scsi.h"
132
#include "migration/qemu-file-types.h"
133
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/hw/scsi/scsi-disk.c
136
+++ b/hw/scsi/scsi-disk.c
137
@@ -XXX,XX +XXX,XX @@
138
#include "qemu/error-report.h"
139
#include "qemu/main-loop.h"
140
#include "qemu/module.h"
141
+#include "qemu/hw-version.h"
142
#include "hw/scsi/scsi.h"
143
#include "migration/qemu-file-types.h"
144
#include "migration/vmstate.h"
145
diff --git a/softmmu/vl.c b/softmmu/vl.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/softmmu/vl.c
148
+++ b/softmmu/vl.c
149
@@ -XXX,XX +XXX,XX @@
150
#include "qemu-version.h"
151
#include "qemu/cutils.h"
152
#include "qemu/help_option.h"
153
+#include "qemu/hw-version.h"
154
#include "qemu/uuid.h"
155
#include "sysemu/reset.h"
156
#include "sysemu/runstate.h"
157
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/i386/cpu.c
160
+++ b/target/i386/cpu.c
161
@@ -XXX,XX +XXX,XX @@
162
#include "qemu/units.h"
163
#include "qemu/cutils.h"
164
#include "qemu/qemu-print.h"
165
+#include "qemu/hw-version.h"
166
#include "cpu.h"
167
#include "tcg/helper-tcg.h"
168
#include "sysemu/reset.h"
169
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/target/s390x/cpu_models.c
172
+++ b/target/s390x/cpu_models.c
173
@@ -XXX,XX +XXX,XX @@
174
#include "qapi/error.h"
175
#include "qapi/visitor.h"
176
#include "qemu/module.h"
177
+#include "qemu/hw-version.h"
178
#include "qemu/qemu-print.h"
179
#ifndef CONFIG_USER_ONLY
180
#include "sysemu/sysemu.h"
181
diff --git a/util/osdep.c b/util/osdep.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/util/osdep.c
184
+++ b/util/osdep.c
185
@@ -XXX,XX +XXX,XX @@ extern int madvise(char *, size_t, int);
186
#include "qemu/error-report.h"
187
#include "qemu/madvise.h"
188
#include "qemu/mprotect.h"
189
+#include "qemu/hw-version.h"
190
#include "monitor/monitor.h"
191
192
static bool fips_enabled = false;
193
--
194
2.25.1
195
196
diff view generated by jsdifflib
New patch
[PULL 21/26] MAINTAINERS: Add Akihiko Odaki to macOS-relateds
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
1
2
3
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
4
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20220213021215.1974-1-akihiko.odaki@gmail.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
MAINTAINERS | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/MAINTAINERS b/MAINTAINERS
13
index XXXXXXX..XXXXXXX 100644
14
--- a/MAINTAINERS
15
+++ b/MAINTAINERS
16
@@ -XXX,XX +XXX,XX @@ F: audio/alsaaudio.c
17
Core Audio framework backend
18
M: Gerd Hoffmann <kraxel@redhat.com>
19
R: Christian Schoenebeck <qemu_oss@crudebyte.com>
20
+R: Akihiko Odaki <akihiko.odaki@gmail.com>
21
S: Odd Fixes
22
F: audio/coreaudio.c
23
24
@@ -XXX,XX +XXX,XX @@ F: util/drm.c
25
26
Cocoa graphics
27
M: Peter Maydell <peter.maydell@linaro.org>
28
+R: Akihiko Odaki <akihiko.odaki@gmail.com>
29
S: Odd Fixes
30
F: ui/cocoa.m
31
32
--
33
2.25.1
34
35
diff view generated by jsdifflib
New patch
[PULL 22/26] hw/timer: fix a9gtimer vmstate
1
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
1
2
3
A9 gtimer includes global control field and number of per-cpu fields.
4
But only per-cpu ones are migrated. This patch adds a subsection for
5
global control field migration.
6
7
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
8
Message-id: 164422345976.2186660.1104517592452494510.stgit@pasha-ThinkPad-X280
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/timer/a9gtimer.c | 21 +++++++++++++++++++++
13
1 file changed, 21 insertions(+)
14
15
diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/a9gtimer.c
18
+++ b/hw/timer/a9gtimer.c
19
@@ -XXX,XX +XXX,XX @@ static void a9_gtimer_realize(DeviceState *dev, Error **errp)
20
}
21
}
22
23
+static bool vmstate_a9_gtimer_control_needed(void *opaque)
24
+{
25
+ A9GTimerState *s = opaque;
26
+ return s->control != 0;
27
+}
28
+
29
static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
30
.name = "arm.cortex-a9-global-timer.percpu",
31
.version_id = 1,
32
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
33
}
34
};
35
36
+static const VMStateDescription vmstate_a9_gtimer_control = {
37
+ .name = "arm.cortex-a9-global-timer.control",
38
+ .version_id = 1,
39
+ .minimum_version_id = 1,
40
+ .needed = vmstate_a9_gtimer_control_needed,
41
+ .fields = (VMStateField[]) {
42
+ VMSTATE_UINT32(control, A9GTimerState),
43
+ VMSTATE_END_OF_LIST()
44
+ }
45
+};
46
+
47
static const VMStateDescription vmstate_a9_gtimer = {
48
.name = "arm.cortex-a9-global-timer",
49
.version_id = 1,
50
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_a9_gtimer = {
51
1, vmstate_a9_gtimer_per_cpu,
52
A9GTimerPerCPU),
53
VMSTATE_END_OF_LIST()
54
+ },
55
+ .subsections = (const VMStateDescription*[]) {
56
+ &vmstate_a9_gtimer_control,
57
+ NULL
58
}
59
};
60
61
--
62
2.25.1
63
64
diff view generated by jsdifflib
[PULL 4/5] hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
[PULL 23/26] hw/arm: add initial mori-bmc board
1
The GICv3/v4 pseudocode has a function IsSpecial() which returns true
1
From: Patrick Venture <venture@google.com>
2
if passed a "special" interrupt ID number (anything between 1020 and
3
1023 inclusive). We open-code this condition in a couple of places,
4
so abstract it out into a new function gicv3_intid_is_special().
5
2
3
This is the BMC attached to the OpenBMC Mori board.
4
5
Signed-off-by: Patrick Venture <venture@google.com>
6
Reviewed-by: Chris Rauer <crauer@google.com>
7
Reviewed-by: Ilkyun Choi <ikchoi@google.com>
8
Message-id: 20220208233104.284425-1-venture@google.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Marc Zyngier <maz@kernel.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
---
11
---
10
hw/intc/gicv3_internal.h | 13 +++++++++++++
12
docs/system/arm/nuvoton.rst | 1 +
11
hw/intc/arm_gicv3_cpuif.c | 4 ++--
13
hw/arm/npcm7xx_boards.c | 32 ++++++++++++++++++++++++++++++++
12
2 files changed, 15 insertions(+), 2 deletions(-)
14
2 files changed, 33 insertions(+)
13
15
14
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
16
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/gicv3_internal.h
18
--- a/docs/system/arm/nuvoton.rst
17
+++ b/hw/intc/gicv3_internal.h
19
+++ b/docs/system/arm/nuvoton.rst
18
@@ -XXX,XX +XXX,XX @@ FIELD(MAPC, RDBASE, 16, 32)
20
@@ -XXX,XX +XXX,XX @@ Hyperscale applications. The following machines are based on this chip :
19
21
- ``quanta-gbs-bmc`` Quanta GBS server BMC
20
/* Functions internal to the emulated GICv3 */
22
- ``quanta-gsj`` Quanta GSJ server BMC
21
23
- ``kudo-bmc`` Fii USA Kudo server BMC
22
+/**
24
+- ``mori-bmc`` Fii USA Mori server BMC
23
+ * gicv3_intid_is_special:
25
24
+ * @intid: interrupt ID
26
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
25
+ *
27
variants of NPCM750 and NPCM730, respectively. These are currently not
26
+ * Return true if @intid is a special interrupt ID (1020 to
28
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
27
+ * 1023 inclusive). This corresponds to the GIC spec pseudocode
29
index XXXXXXX..XXXXXXX 100644
28
+ * IsSpecial() function.
30
--- a/hw/arm/npcm7xx_boards.c
29
+ */
31
+++ b/hw/arm/npcm7xx_boards.c
30
+static inline bool gicv3_intid_is_special(int intid)
32
@@ -XXX,XX +XXX,XX @@
33
#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
34
#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
35
#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
36
+#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
37
38
static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
39
40
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_init(MachineState *machine)
41
npcm7xx_load_kernel(machine, soc);
42
}
43
44
+static void mori_bmc_init(MachineState *machine)
31
+{
45
+{
32
+ return intid >= INTID_SECURE && intid <= INTID_SPURIOUS;
46
+ NPCM7xxState *soc;
47
+
48
+ soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS);
49
+ npcm7xx_connect_dram(soc, machine->ram);
50
+ qdev_realize(DEVICE(soc), NULL, &error_fatal);
51
+
52
+ npcm7xx_load_bootrom(machine, soc);
53
+ npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
54
+ drive_get(IF_MTD, 3, 0));
55
+
56
+ npcm7xx_load_kernel(machine, soc);
33
+}
57
+}
34
+
58
+
35
/**
59
static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
36
* gicv3_redist_update:
60
{
37
* @cs: GICv3CPUState for this redistributor
61
NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
38
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
62
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)
39
index XXXXXXX..XXXXXXX 100644
63
mc->default_ram_size = 1 * GiB;
40
--- a/hw/intc/arm_gicv3_cpuif.c
64
};
41
+++ b/hw/intc/arm_gicv3_cpuif.c
65
42
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri)
66
+static void mori_bmc_machine_class_init(ObjectClass *oc, void *data)
43
intid = icc_hppir0_value(cs, env);
67
+{
44
}
68
+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
45
69
+ MachineClass *mc = MACHINE_CLASS(oc);
46
- if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
70
+
47
+ if (!gicv3_intid_is_special(intid)) {
71
+ npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
48
icc_activate_irq(cs, intid);
72
+
49
}
73
+ mc->desc = "Mori BMC (Cortex-A9)";
50
74
+ mc->init = mori_bmc_init;
51
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
75
+ mc->default_ram_size = 1 * GiB;
52
intid = icc_hppir1_value(cs, env);
76
+}
53
}
77
+
54
78
static const TypeInfo npcm7xx_machine_types[] = {
55
- if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
79
{
56
+ if (!gicv3_intid_is_special(intid)) {
80
.name = TYPE_NPCM7XX_MACHINE,
57
icc_activate_irq(cs, intid);
81
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_machine_types[] = {
58
}
82
.name = MACHINE_TYPE_NAME("kudo-bmc"),
83
.parent = TYPE_NPCM7XX_MACHINE,
84
.class_init = kudo_bmc_machine_class_init,
85
+ }, {
86
+ .name = MACHINE_TYPE_NAME("mori-bmc"),
87
+ .parent = TYPE_NPCM7XX_MACHINE,
88
+ .class_init = mori_bmc_machine_class_init,
89
},
90
};
59
91
60
--
92
--
61
2.25.1
93
2.25.1
62
94
63
95
diff view generated by jsdifflib
New patch
[PULL 24/26] ui/cocoa: Remove allowedFileTypes restriction in SavePanel
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
setAllowedFileTypes is deprecated in macOS 12.
4
5
Per Akihiko Odaki [*]:
6
7
An image file, which is being chosen by the panel, can be a
8
raw file and have a variety of file extensions and many are not
9
covered by the provided list (e.g. "udf"). Other platforms like
10
GTK can provide an option to open a file with an extension not
11
listed, but Cocoa can't. It forces the user to rename the file
12
to give an extension in the list. Moreover, Cocoa does not tell
13
which extensions are in the list so the user needs to read the
14
source code, which is pretty bad.
15
16
Since this code is harming the usability rather than improving it,
17
simply remove the [NSSavePanel allowedFileTypes:] call, fixing:
18
19
[2789/6622] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o
20
ui/cocoa.m:1411:16: error: 'setAllowedFileTypes:' is deprecated: first deprecated in macOS 12.0 - Use -allowedContentTypes instead [-Werror,-Wdeprecated-declarations]
21
[openPanel setAllowedFileTypes: supportedImageFileTypes];
22
^
23
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSSavePanel.h:215:49: note: property 'allowedFileTypes' is declared deprecated here
24
@property (nullable, copy) NSArray<NSString *> *allowedFileTypes API_DEPRECATED("Use -allowedContentTypes instead", macos(10.3,12.0));
25
^
26
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSSavePanel.h:215:49: note: 'setAllowedFileTypes:' has been explicitly marked deprecated here
27
FAILED: libcommon.fa.p/ui_cocoa.m.o
28
29
[*] https://lore.kernel.org/qemu-devel/4dde2e66-63cb-4390-9538-c032310db3e3@gmail.com/
30
31
Suggested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
32
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
33
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
34
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
36
Message-id: 20220215080307.69550-11-f4bug@amsat.org
37
Reviewed by: Cameron Esfahani <dirty@apple.com>
38
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
39
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
40
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
43
ui/cocoa.m | 6 ------
44
1 file changed, 6 deletions(-)
45
46
diff --git a/ui/cocoa.m b/ui/cocoa.m
47
index XXXXXXX..XXXXXXX 100644
48
--- a/ui/cocoa.m
49
+++ b/ui/cocoa.m
50
@@ -XXX,XX +XXX,XX @@ static int gArgc;
51
static char **gArgv;
52
static bool stretch_video;
53
static NSTextField *pauseLabel;
54
-static NSArray * supportedImageFileTypes;
55
56
static QemuSemaphore display_init_sem;
57
static QemuSemaphore app_started_sem;
58
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
59
[pauseLabel setTextColor: [NSColor blackColor]];
60
[pauseLabel sizeToFit];
61
62
- // set the supported image file types that can be opened
63
- supportedImageFileTypes = [NSArray arrayWithObjects: @"img", @"iso", @"dmg",
64
- @"qcow", @"qcow2", @"cloop", @"vmdk", @"cdr",
65
- @"toast", nil];
66
[self make_about_window];
67
}
68
return self;
69
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
70
openPanel = [NSOpenPanel openPanel];
71
[openPanel setCanChooseFiles: YES];
72
[openPanel setAllowsMultipleSelection: NO];
73
- [openPanel setAllowedFileTypes: supportedImageFileTypes];
74
if([openPanel runModal] == NSModalResponseOK) {
75
NSString * file = [[[openPanel URLs] objectAtIndex: 0] path];
76
if(file == nil) {
77
--
78
2.25.1
79
80
diff view generated by jsdifflib
New patch
[PULL 25/26] ui/cocoa: Do not alert even without block devices
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
1
2
3
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
4
Message-id: 20220215080307.69550-13-f4bug@amsat.org
5
Message-Id: <20220213021418.2155-1-akihiko.odaki@gmail.com>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
ui/cocoa.m | 5 -----
10
1 file changed, 5 deletions(-)
11
12
diff --git a/ui/cocoa.m b/ui/cocoa.m
13
index XXXXXXX..XXXXXXX 100644
14
--- a/ui/cocoa.m
15
+++ b/ui/cocoa.m
16
@@ -XXX,XX +XXX,XX @@ static void addRemovableDevicesMenuItems(void)
17
18
currentDevice = qmp_query_block(NULL);
19
pointerToFree = currentDevice;
20
- if(currentDevice == NULL) {
21
- NSBeep();
22
- QEMU_Alert(@"Failed to query for block devices!");
23
- return;
24
- }
25
26
menu = [[[NSApp mainMenu] itemWithTitle:@"Machine"] submenu];
27
28
--
29
2.25.1
30
31
diff view generated by jsdifflib
[PULL 2/5] hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
[PULL 26/26] ui/cocoa: Fix the leak of qemu_console_get_label
1
From: Shashi Mallela <shashi.mallela@linaro.org>
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
2
2
3
When Enabled bit is cleared in GITS_CTLR,ITS feature continues
3
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
4
to be enabled.This patch fixes the issue.
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
5
Message-id: 20220215080307.69550-14-f4bug@amsat.org
6
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
6
Message-Id: <20220213021329.2066-1-akihiko.odaki@gmail.com>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
[PMD: Use g_autofree, suggested by Zoltan BALATON]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20211124182246.67691-1-shashi.mallela@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/intc/arm_gicv3_its.c | 7 ++++---
11
ui/cocoa.m | 4 +++-
13
1 file changed, 4 insertions(+), 3 deletions(-)
12
1 file changed, 3 insertions(+), 1 deletion(-)
14
13
15
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
14
diff --git a/ui/cocoa.m b/ui/cocoa.m
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_its.c
16
--- a/ui/cocoa.m
18
+++ b/hw/intc/arm_gicv3_its.c
17
+++ b/ui/cocoa.m
19
@@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset,
18
@@ -XXX,XX +XXX,XX @@ static void create_initial_menus(void)
20
19
/* Returns a name for a given console */
21
switch (offset) {
20
static NSString * getConsoleName(QemuConsole * console)
22
case GITS_CTLR:
21
{
23
- s->ctlr |= (value & ~(s->ctlr));
22
- return [NSString stringWithFormat: @"%s", qemu_console_get_label(console)];
24
-
23
+ g_autofree char *label = qemu_console_get_label(console);
25
- if (s->ctlr & ITS_CTLR_ENABLED) {
24
+
26
+ if (value & R_GITS_CTLR_ENABLED_MASK) {
25
+ return [NSString stringWithUTF8String:label];
27
+ s->ctlr |= ITS_CTLR_ENABLED;
26
}
28
extract_table_params(s);
27
29
extract_cmdq_params(s);
28
/* Add an entry to the View menu for each console */
30
s->creadr = 0;
31
process_cmdq(s);
32
+ } else {
33
+ s->ctlr &= ~ITS_CTLR_ENABLED;
34
}
35
break;
36
case GITS_CBASER:
37
--
29
--
38
2.25.1
30
2.25.1
39
31
40
32
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.