On 11/26/21 08:53, Cédric Le Goater wrote:
> These bits control the availability of interrupt features : StoreEOI,
> PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
> exploitation mode. These bits can be set at early boot time of the
> system to activate/deactivate a feature for testing purposes. The
> default value should be '1'.
>
> The 'XIVE exploitation mode' bit is a software bit that skiboot could
> use to disable the XIVE OS interface and propose a P8 style XICS
> interface instead. There are no plans for that for the moment.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/intc/pnv_xive2_regs.h | 5 +++++
> hw/intc/pnv_xive2.c | 4 ++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
> index 084fccc8d3e9..46d4fb378135 100644
> --- a/hw/intc/pnv_xive2_regs.h
> +++ b/hw/intc/pnv_xive2_regs.h
> @@ -31,6 +31,11 @@
> #define CQ_XIVE_CAP_VP_INT_PRIO_8 3
> #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
>
> +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
> +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
> +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
> +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
> +
> /* XIVE2 Configuration */
> #define X_CQ_XIVE_CFG 0x03
> #define CQ_XIVE_CFG 0x018
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index 186ab66e105d..cb12cea14fc6 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -1708,9 +1708,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
> };
>
> /*
> - * POWER10 default capabilities: 0x2000120076f00000
> + * POWER10 default capabilities: 0x2000120076f000FC
> */
> -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
> +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
>
> /*
> * POWER10 default configuration: 0x0030000033000000