1 | Apologies for sending two pullreqs today; Eric's patch came in a | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
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2 | few hours after I sent the first one but it's definitely a | 2 | we were using uninitialized data for the guarded bit when |
3 | release-critical fix. | 3 | combining stage 1 and stage 2 attrs. |
4 | 4 | ||
5 | thanks | ||
5 | -- PMM | 6 | -- PMM |
6 | 7 | ||
7 | The following changes since commit 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a: | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
8 | 9 | ||
9 | Merge tag 'pull-target-arm-20211122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2021-11-22 16:35:54 +0100) | 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) |
10 | 11 | ||
11 | are available in the Git repository at: | 12 | are available in the Git repository at: |
12 | 13 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122-1 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
14 | 15 | ||
15 | for you to fetch changes up to 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
16 | 17 | ||
17 | hw/intc/arm_gicv3_its: Revert version increments in vmstate_its (2021-11-22 18:17:19 +0000) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
18 | 19 | ||
19 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
20 | target-arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
21 | * drop spurious bump of ITS vmstate version fields | 22 | guarded bit state when combining S1/S2 attrs |
22 | 23 | ||
23 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
24 | Eric Auger (1): | 25 | Richard Henderson (2): |
25 | hw/intc/arm_gicv3_its: Revert version increments in vmstate_its | 26 | target/arm: PTE bit GP only applies to stage1 |
27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
26 | 28 | ||
27 | hw/intc/arm_gicv3_its_common.c | 2 -- | 29 | target/arm/ptw.c | 11 ++++++----- |
28 | 1 file changed, 2 deletions(-) | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
29 | diff view generated by jsdifflib |
New patch | |||
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1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Only perform the extract of GP during the stage1 walk. | ||
4 | |||
5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/ptw.c | 10 +++++----- | ||
12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/ptw.c | ||
17 | +++ b/target/arm/ptw.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
19 | result->f.attrs.secure = false; | ||
20 | } | ||
21 | |||
22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
25 | - } | ||
26 | - | ||
27 | if (regime_is_stage2(mmu_idx)) { | ||
28 | result->cacheattrs.is_s2_format = true; | ||
29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
31 | assert(attrindx <= 7); | ||
32 | result->cacheattrs.is_s2_format = false; | ||
33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
34 | + | ||
35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
38 | + } | ||
39 | } | ||
40 | |||
41 | /* | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework") | 3 | The guarded bit comes from the stage1 walk. |
4 | incremented version_id and minimum_version_id fields of | ||
5 | VMStateDescription vmstate_its. This breaks the migration between | ||
6 | 6.2 and 6.1 with the following message: | ||
7 | 4 | ||
8 | qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0 | 5 | Fixes: Coverity CID 1507929 |
9 | qemu-system-aarch64: load of migration failed: Invalid argument | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | |||
11 | Revert that change. | ||
12 | |||
13 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
14 | Message-id: 20211122171020.1195483-1-eric.auger@redhat.com | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 10 | --- |
18 | hw/intc/arm_gicv3_its_common.c | 2 -- | 11 | target/arm/ptw.c | 1 + |
19 | 1 file changed, 2 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
20 | 13 | ||
21 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/intc/arm_gicv3_its_common.c | 16 | --- a/target/arm/ptw.c |
24 | +++ b/hw/intc/arm_gicv3_its_common.c | 17 | +++ b/target/arm/ptw.c |
25 | @@ -XXX,XX +XXX,XX @@ static int gicv3_its_post_load(void *opaque, int version_id) | 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, |
26 | 19 | ||
27 | static const VMStateDescription vmstate_its = { | 20 | assert(!s1.is_s2_format); |
28 | .name = "arm_gicv3_its", | 21 | ret.is_s2_format = false; |
29 | - .version_id = 1, | 22 | + ret.guarded = s1.guarded; |
30 | - .minimum_version_id = 1, | 23 | |
31 | .pre_save = gicv3_its_pre_save, | 24 | if (s1.attrs == 0xf0) { |
32 | .post_load = gicv3_its_post_load, | 25 | tagged = true; |
33 | .priority = MIG_PRI_GICV3_ITS, | ||
34 | -- | 26 | -- |
35 | 2.25.1 | 27 | 2.34.1 |
36 | |||
37 | diff view generated by jsdifflib |