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Apologies for sending two pullreqs today; Eric's patch came in a
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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few hours after I sent the first one but it's definitely a
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we were using uninitialized data for the guarded bit when
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release-critical fix.
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a:
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge tag 'pull-target-arm-20211122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2021-11-22 16:35:54 +0100)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its (2021-11-22 18:17:19 +0000)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* drop spurious bump of ITS vmstate version fields
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guarded bit state when combining S1/S2 attrs
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----------------------------------------------------------------
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----------------------------------------------------------------
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Eric Auger (1):
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Richard Henderson (2):
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/intc/arm_gicv3_its_common.c | 2 --
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target/arm/ptw.c | 11 ++++++-----
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1 file changed, 2 deletions(-)
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1 file changed, 6 insertions(+), 5 deletions(-)
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diff view generated by jsdifflib
New patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
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From: Eric Auger <eric.auger@redhat.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework")
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The guarded bit comes from the stage1 walk.
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incremented version_id and minimum_version_id fields of
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VMStateDescription vmstate_its. This breaks the migration between
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6.2 and 6.1 with the following message:
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qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0
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Fixes: Coverity CID 1507929
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qemu-system-aarch64: load of migration failed: Invalid argument
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revert that change.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Message-id: 20211122171020.1195483-1-eric.auger@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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hw/intc/arm_gicv3_its_common.c | 2 --
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target/arm/ptw.c | 1 +
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1 file changed, 2 deletions(-)
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1 file changed, 1 insertion(+)
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diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/intc/arm_gicv3_its_common.c
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--- a/target/arm/ptw.c
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+++ b/hw/intc/arm_gicv3_its_common.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static int gicv3_its_post_load(void *opaque, int version_id)
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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static const VMStateDescription vmstate_its = {
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assert(!s1.is_s2_format);
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.name = "arm_gicv3_its",
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ret.is_s2_format = false;
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- .version_id = 1,
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+ ret.guarded = s1.guarded;
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- .minimum_version_id = 1,
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.pre_save = gicv3_its_pre_save,
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if (s1.attrs == 0xf0) {
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.post_load = gicv3_its_post_load,
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tagged = true;
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.priority = MIG_PRI_GICV3_ITS,
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--
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--
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2.25.1
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2.34.1
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diff view generated by jsdifflib