1 | Apologies for sending two pullreqs today; Eric's patch came in a | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
---|---|---|---|
2 | few hours after I sent the first one but it's definitely a | 2 | ethernet device failed 'make check' on big-endian hosts. |
3 | release-critical fix. | ||
4 | 3 | ||
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
8 | 7 | ||
9 | Merge tag 'pull-target-arm-20211122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2021-11-22 16:35:54 +0100) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
14 | 13 | ||
15 | for you to fetch changes up to 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
16 | 15 | ||
17 | hw/intc/arm_gicv3_its: Revert version increments in vmstate_its (2021-11-22 18:17:19 +0000) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * drop spurious bump of ITS vmstate version fields | 20 | * Correctly initialize MDCR_EL2.HPMN |
21 | * versal: Use nr_apu_cpus in favor of hard coding 2 | ||
22 | * accel/tcg: Add URL of clang bug to comment about our workaround | ||
23 | * Add support for FEAT_DIT, Data Independent Timing | ||
24 | * Remove GPIO from unimplemented NPCM7XX | ||
25 | * Fix SCR RES1 handling | ||
26 | * Don't migrate CPUARMState.features | ||
22 | 27 | ||
23 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
24 | Eric Auger (1): | 29 | Aaron Lindsay (1): |
25 | hw/intc/arm_gicv3_its: Revert version increments in vmstate_its | 30 | target/arm: Don't migrate CPUARMState.features |
26 | 31 | ||
27 | hw/intc/arm_gicv3_its_common.c | 2 -- | 32 | Daniel Müller (1): |
28 | 1 file changed, 2 deletions(-) | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
29 | 34 | ||
35 | Edgar E. Iglesias (1): | ||
36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 | ||
37 | |||
38 | Hao Wu (1): | ||
39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | ||
40 | |||
41 | Mike Nawrocki (1): | ||
42 | target/arm: Fix SCR RES1 handling | ||
43 | |||
44 | Peter Maydell (2): | ||
45 | arm: Update infocenter.arm.com URLs | ||
46 | accel/tcg: Add URL of clang bug to comment about our workaround | ||
47 | |||
48 | Rebecca Cran (4): | ||
49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | ||
50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
53 | |||
54 | include/hw/dma/pl080.h | 7 ++-- | ||
55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
56 | include/hw/ssi/pl022.h | 5 ++- | ||
57 | target/arm/cpu.h | 17 ++++++++ | ||
58 | target/arm/internals.h | 6 +++ | ||
59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
61 | hw/arm/musca.c | 4 +- | ||
62 | hw/arm/npcm7xx.c | 8 ---- | ||
63 | hw/arm/xlnx-versal.c | 4 +- | ||
64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
65 | hw/timer/arm_timer.c | 7 ++-- | ||
66 | target/arm/cpu.c | 4 ++ | ||
67 | target/arm/cpu64.c | 5 +++ | ||
68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
70 | target/arm/machine.c | 2 +- | ||
71 | target/arm/op_helper.c | 9 +---- | ||
72 | target/arm/translate-a64.c | 12 ++++++ | ||
73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
2 | 1 | ||
3 | Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework") | ||
4 | incremented version_id and minimum_version_id fields of | ||
5 | VMStateDescription vmstate_its. This breaks the migration between | ||
6 | 6.2 and 6.1 with the following message: | ||
7 | |||
8 | qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0 | ||
9 | qemu-system-aarch64: load of migration failed: Invalid argument | ||
10 | |||
11 | Revert that change. | ||
12 | |||
13 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
14 | Message-id: 20211122171020.1195483-1-eric.auger@redhat.com | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | hw/intc/arm_gicv3_its_common.c | 2 -- | ||
19 | 1 file changed, 2 deletions(-) | ||
20 | |||
21 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/intc/arm_gicv3_its_common.c | ||
24 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static int gicv3_its_post_load(void *opaque, int version_id) | ||
26 | |||
27 | static const VMStateDescription vmstate_its = { | ||
28 | .name = "arm_gicv3_its", | ||
29 | - .version_id = 1, | ||
30 | - .minimum_version_id = 1, | ||
31 | .pre_save = gicv3_its_pre_save, | ||
32 | .post_load = gicv3_its_post_load, | ||
33 | .priority = MIG_PRI_GICV3_ITS, | ||
34 | -- | ||
35 | 2.25.1 | ||
36 | |||
37 | diff view generated by jsdifflib |