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Apologies for sending two pullreqs today; Eric's patch came in a
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v2: drop pvpanic-pci patches.
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few hours after I sent the first one but it's definitely a
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release-critical fix.
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-- PMM
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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The following changes since commit 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a:
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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Merge tag 'pull-target-arm-20211122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2021-11-22 16:35:54 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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for you to fetch changes up to 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its (2021-11-22 18:17:19 +0000)
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* drop spurious bump of ITS vmstate version fields
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* Implement IMPDEF pauth algorithm
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* Support ARMv8.4-SEL2
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Eric Auger (1):
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Gan Qixin (1):
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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hw/intc/arm_gicv3_its_common.c | 2 --
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Peter Maydell (1):
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1 file changed, 2 deletions(-)
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docs: Build and install all the docs in a single manual
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Philippe Mathieu-Daudé (1):
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Richard Henderson (7):
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: Add cpu properties to control pauth
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target/arm: Use object_property_add_bool for "sve" property
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target/arm: Introduce PREDDESC field definitions
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Rémi Denis-Courmont (19):
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target/arm: remove redundant tests
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target/arm: add arm_is_el2_enabled() helper
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: factor MDCR_EL2 common handling
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: handle VMID change in secure state
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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docs/conf.py | 46 ++++-
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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diff view generated by jsdifflib
Deleted patch
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From: Eric Auger <eric.auger@redhat.com>
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Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework")
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incremented version_id and minimum_version_id fields of
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VMStateDescription vmstate_its. This breaks the migration between
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6.2 and 6.1 with the following message:
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qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0
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qemu-system-aarch64: load of migration failed: Invalid argument
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Revert that change.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Message-id: 20211122171020.1195483-1-eric.auger@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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hw/intc/arm_gicv3_its_common.c | 2 --
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1 file changed, 2 deletions(-)
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diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/intc/arm_gicv3_its_common.c
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+++ b/hw/intc/arm_gicv3_its_common.c
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@@ -XXX,XX +XXX,XX @@ static int gicv3_its_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_its = {
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.name = "arm_gicv3_its",
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- .version_id = 1,
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- .minimum_version_id = 1,
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.pre_save = gicv3_its_pre_save,
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.post_load = gicv3_its_post_load,
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.priority = MIG_PRI_GICV3_ITS,
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--
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2.25.1
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diff view generated by jsdifflib