1 | Just one patch for rc2, a revert. | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
---|---|---|---|
2 | 2 | ||
3 | -- PMM | 3 | -- PMM |
4 | 4 | ||
5 | The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2: | 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: |
6 | 6 | ||
7 | Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100) | 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) |
8 | 8 | ||
9 | are available in the Git repository at: | 9 | are available in the Git repository at: |
10 | 10 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
12 | 12 | ||
13 | for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
14 | 14 | ||
15 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
16 | 16 | ||
17 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
18 | target-arm queue: | 18 | target-arm queue: |
19 | * revert SMCCC/PSCI change, as it regresses some usecases for some boards | 19 | * Fix KVM SVE ID register probe code |
20 | 20 | ||
21 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
22 | Peter Maydell (1): | 22 | Richard Henderson (3): |
23 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
24 | 26 | ||
25 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
26 | 1 file changed, 29 insertions(+), 6 deletions(-) | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
27 | diff view generated by jsdifflib |
New patch | |||
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1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Indication for support for SVE will not depend on whether we | ||
4 | perform the query on the main kvm_state or the temp vcpu. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/kvm64.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/kvm64.c | ||
17 | +++ b/target/arm/kvm64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
23 | + sve_supported = kvm_arm_sve_supported(); | ||
24 | |||
25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
26 | if (sve_supported) { | ||
27 | -- | ||
28 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
4 | was always returning zero. This also obviates the adjustment | ||
5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
6 | |||
7 | The effects of the bug are not visible, because the only thing that | ||
8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
10 | |||
11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
19 | |||
20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/kvm64.c | ||
23 | +++ b/target/arm/kvm64.c | ||
24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
25 | bool sve_supported; | ||
26 | bool pmu_supported = false; | ||
27 | uint64_t features = 0; | ||
28 | - uint64_t t; | ||
29 | int err; | ||
30 | |||
31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
34 | |||
35 | /* | ||
36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
39 | - * we have to use the actual ID regs. | ||
40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
41 | + * which is otherwise RAZ. | ||
42 | + */ | ||
43 | + sve_supported = kvm_arm_sve_supported(); | ||
44 | + if (sve_supported) { | ||
45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
46 | + } | ||
47 | + | ||
48 | + /* | ||
49 | + * Ask for Pointer Authentication if supported, so that we get | ||
50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
51 | */ | ||
52 | if (kvm_arm_pauth_supported()) { | ||
53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
55 | } | ||
56 | } | ||
57 | |||
58 | - sve_supported = kvm_arm_sve_supported(); | ||
59 | - | ||
60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
61 | if (sve_supported) { | ||
62 | - t = ahcf->isar.id_aa64pfr0; | ||
63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
64 | - ahcf->isar.id_aa64pfr0 = t; | ||
65 | - | ||
66 | /* | ||
67 | * There is a range of kernels between kernel commit 73433762fcae | ||
68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
70 | - * SVE support, so we only read it here, rather than together with all | ||
71 | - * the other ID registers earlier. | ||
72 | + * SVE support, which resulted in an error rather than RAZ. | ||
73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
74 | */ | ||
75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
77 | -- | ||
78 | 2.25.1 | diff view generated by jsdifflib |
1 | This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | This change turns out to cause regressions, for instance on the | 3 | The test for the IF block indicates no ID registers are exposed, much |
4 | imx6ul boards as described here: | 4 | less host support for SVE. Move the SVE probe into the ELSE block. |
5 | https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/ | ||
6 | 5 | ||
7 | The primary cause of that regression is that the guest code running | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | at EL3 expects SMCs (not related to PSCI) to do what they would if | 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org |
9 | our PSCI emulation was not present at all, but after this change | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | they instead set a value in R0/X0 and continue. | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | ||
11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
11 | 13 | ||
12 | We could fix that by a refactoring that allowed us to only turn on | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
13 | the PSCI emulation if we weren't booting the guest at EL3, but there | ||
14 | is a more tangled problem with the highbank board, which: | ||
15 | (1) wants to enable PSCI emulation | ||
16 | (2) has a bit of guest code that it wants to run at EL3 and | ||
17 | to perform SMC calls that trap to the monitor vector table: | ||
18 | this is the boot stub code that is written to memory by | ||
19 | arm_write_secure_board_setup_dummy_smc() and which the | ||
20 | highbank board enables by setting bootinfo->secure_board_setup | ||
21 | |||
22 | We can't satisfy both of those and also have the PSCI emulation | ||
23 | handle all SMC instruction executions regardless of function | ||
24 | identifier value. | ||
25 | |||
26 | This is too tricky to try to sort out before 6.2 is released; | ||
27 | revert this commit so we can take the time to get it right in | ||
28 | the 7.0 release. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Message-id: 20211119163419.557623-1-peter.maydell@linaro.org | ||
32 | --- | ||
33 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | ||
34 | 1 file changed, 29 insertions(+), 6 deletions(-) | ||
35 | |||
36 | diff --git a/target/arm/psci.c b/target/arm/psci.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/psci.c | 16 | --- a/target/arm/kvm64.c |
39 | +++ b/target/arm/psci.c | 17 | +++ b/target/arm/kvm64.c |
40 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
41 | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | |
42 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
43 | { | 21 | } |
44 | - /* | 22 | - } |
45 | - * Return true if the exception type matches the configured PSCI conduit. | 23 | |
46 | - * This is called before the SMC/HVC instruction is executed, to decide | 24 | - if (sve_supported) { |
47 | - * whether we should treat it as a PSCI call or with the architecturally | 25 | - /* |
48 | + /* Return true if the r0/x0 value indicates a PSCI call and | 26 | - * There is a range of kernels between kernel commit 73433762fcae |
49 | + * the exception type matches the configured PSCI conduit. This is | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
50 | + * called before the SMC/HVC instruction is executed, to decide whether | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
51 | + * we should treat it as a PSCI call or with the architecturally | 29 | - * SVE support, which resulted in an error rather than RAZ. |
52 | * defined behaviour for an SMC or HVC (which might be UNDEF or trap | 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. |
53 | * to EL2 or to EL3). | 31 | - */ |
54 | */ | 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
55 | + CPUARMState *env = &cpu->env; | 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); |
56 | + uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; | 34 | + if (sve_supported) { |
57 | 35 | + /* | |
58 | switch (excp_type) { | 36 | + * There is a range of kernels between kernel commit 73433762fcae |
59 | case EXCP_HVC: | 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't |
60 | @@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has |
61 | return false; | 39 | + * enabled SVE support, which resulted in an error rather than RAZ. |
40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
41 | + */ | ||
42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
44 | + } | ||
62 | } | 45 | } |
63 | 46 | ||
64 | - return true; | 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); |
65 | + switch (param) { | ||
66 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
67 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
68 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: | ||
69 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
70 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
71 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
72 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
73 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
74 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
75 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
76 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
77 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
78 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
79 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
80 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
81 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
82 | + return true; | ||
83 | + default: | ||
84 | + return false; | ||
85 | + } | ||
86 | } | ||
87 | |||
88 | void arm_handle_psci_call(ARMCPU *cpu) | ||
89 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
90 | break; | ||
91 | case QEMU_PSCI_0_1_FN_MIGRATE: | ||
92 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
93 | - default: | ||
94 | ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
95 | break; | ||
96 | + default: | ||
97 | + g_assert_not_reached(); | ||
98 | } | ||
99 | |||
100 | err: | ||
101 | -- | 48 | -- |
102 | 2.25.1 | 49 | 2.25.1 |
103 | |||
104 | diff view generated by jsdifflib |