1 | Just one patch for rc2, a revert. | 1 | Squashed in a trivial fix for 32-bit hosts: |
---|---|---|---|
2 | |||
3 | --- a/target/arm/mve_helper.c | ||
4 | +++ b/target/arm/mve_helper.c | ||
5 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | ||
6 | acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
7 | m[H##ESIZE(e)])); \ | ||
8 | } \ | ||
9 | - acc = int128_add(acc, 1 << 7); \ | ||
10 | + acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
11 | } \ | ||
12 | } \ | ||
13 | mve_advance_vpt(env); \ | ||
2 | 14 | ||
3 | -- PMM | 15 | -- PMM |
4 | 16 | ||
5 | The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2: | 17 | The following changes since commit 53f306f316549d20c76886903181413d20842423: |
6 | 18 | ||
7 | Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100) | 19 | Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100) |
8 | 20 | ||
9 | are available in the Git repository at: | 21 | are available in the Git repository at: |
10 | 22 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122 | 23 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624 |
12 | 24 | ||
13 | for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d: | 25 | for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee: |
14 | 26 | ||
15 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000) | 27 | docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100) |
16 | 28 | ||
17 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
18 | target-arm queue: | 30 | target-arm queue: |
19 | * revert SMCCC/PSCI change, as it regresses some usecases for some boards | 31 | * Don't require 'virt' board to be compiled in for ACPI GHES code |
32 | * docs: Document which architecture extensions we emulate | ||
33 | * Fix bugs in M-profile FPCXT_NS accesses | ||
34 | * First slice of MVE patches | ||
35 | * Implement MTE3 | ||
36 | * docs/system: arm: Add nRF boards description | ||
20 | 37 | ||
21 | ---------------------------------------------------------------- | 38 | ---------------------------------------------------------------- |
22 | Peter Maydell (1): | 39 | Alexandre Iooss (1): |
23 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" | 40 | docs/system: arm: Add nRF boards description |
24 | 41 | ||
25 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | 42 | Peter Collingbourne (1): |
26 | 1 file changed, 29 insertions(+), 6 deletions(-) | 43 | target/arm: Implement MTE3 |
27 | 44 | ||
45 | Peter Maydell (55): | ||
46 | hw/acpi: Provide stub version of acpi_ghes_record_errors() | ||
47 | hw/acpi: Provide function acpi_ghes_present() | ||
48 | target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors | ||
49 | docs/system/arm: Document which architecture extensions we emulate | ||
50 | target/arm/translate-vfp.c: Whitespace fixes | ||
51 | target/arm: Handle FPU being disabled in FPCXT_NS accesses | ||
52 | target/arm: Don't NOCP fault for FPCXT_NS accesses | ||
53 | target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access | ||
54 | target/arm: Factor FP context update code out into helper function | ||
55 | target/arm: Split vfp_access_check() into A and M versions | ||
56 | target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() | ||
57 | target/arm: Implement MVE VLDR/VSTR (non-widening forms) | ||
58 | target/arm: Implement widening/narrowing MVE VLDR/VSTR insns | ||
59 | target/arm: Implement MVE VCLZ | ||
60 | target/arm: Implement MVE VCLS | ||
61 | target/arm: Implement MVE VREV16, VREV32, VREV64 | ||
62 | target/arm: Implement MVE VMVN (register) | ||
63 | target/arm: Implement MVE VABS | ||
64 | target/arm: Implement MVE VNEG | ||
65 | tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 | ||
66 | target/arm: Implement MVE VDUP | ||
67 | target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR | ||
68 | target/arm: Implement MVE VADD, VSUB, VMUL | ||
69 | target/arm: Implement MVE VMULH | ||
70 | target/arm: Implement MVE VRMULH | ||
71 | target/arm: Implement MVE VMAX, VMIN | ||
72 | target/arm: Implement MVE VABD | ||
73 | target/arm: Implement MVE VHADD, VHSUB | ||
74 | target/arm: Implement MVE VMULL | ||
75 | target/arm: Implement MVE VMLALDAV | ||
76 | target/arm: Implement MVE VMLSLDAV | ||
77 | target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH | ||
78 | target/arm: Implement MVE VADD (scalar) | ||
79 | target/arm: Implement MVE VSUB, VMUL (scalar) | ||
80 | target/arm: Implement MVE VHADD, VHSUB (scalar) | ||
81 | target/arm: Implement MVE VBRSR | ||
82 | target/arm: Implement MVE VPST | ||
83 | target/arm: Implement MVE VQADD and VQSUB | ||
84 | target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) | ||
85 | target/arm: Implement MVE VQDMULL scalar | ||
86 | target/arm: Implement MVE VQDMULH, VQRDMULH (vector) | ||
87 | target/arm: Implement MVE VQADD, VQSUB (vector) | ||
88 | target/arm: Implement MVE VQSHL (vector) | ||
89 | target/arm: Implement MVE VQRSHL | ||
90 | target/arm: Implement MVE VSHL insn | ||
91 | target/arm: Implement MVE VRSHL | ||
92 | target/arm: Implement MVE VQDMLADH and VQRDMLADH | ||
93 | target/arm: Implement MVE VQDMLSDH and VQRDMLSDH | ||
94 | target/arm: Implement MVE VQDMULL (vector) | ||
95 | target/arm: Implement MVE VRHADD | ||
96 | target/arm: Implement MVE VADC, VSBC | ||
97 | target/arm: Implement MVE VCADD | ||
98 | target/arm: Implement MVE VHCADD | ||
99 | target/arm: Implement MVE VADDV | ||
100 | target/arm: Make VMOV scalar <-> gpreg beatwise for MVE | ||
101 | |||
102 | docs/system/arm/emulation.rst | 103 ++++ | ||
103 | docs/system/arm/nrf.rst | 51 ++ | ||
104 | docs/system/target-arm.rst | 7 + | ||
105 | include/hw/acpi/ghes.h | 9 + | ||
106 | include/tcg/tcg-op.h | 8 + | ||
107 | include/tcg/tcg.h | 1 - | ||
108 | target/arm/helper-mve.h | 357 +++++++++++++ | ||
109 | target/arm/helper.h | 2 + | ||
110 | target/arm/internals.h | 11 + | ||
111 | target/arm/translate-a32.h | 3 + | ||
112 | target/arm/translate.h | 10 + | ||
113 | target/arm/m-nocp.decode | 24 + | ||
114 | target/arm/mve.decode | 240 +++++++++ | ||
115 | target/arm/vfp.decode | 14 - | ||
116 | hw/acpi/ghes-stub.c | 22 + | ||
117 | hw/acpi/ghes.c | 17 + | ||
118 | target/arm/cpu64.c | 2 +- | ||
119 | target/arm/kvm64.c | 6 +- | ||
120 | target/arm/mte_helper.c | 82 +-- | ||
121 | target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++ | ||
122 | target/arm/translate-m-nocp.c | 550 +++++++++++++++++++ | ||
123 | target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++ | ||
124 | target/arm/translate-vfp.c | 741 +++++++------------------- | ||
125 | tcg/tcg-op-gvec.c | 20 +- | ||
126 | MAINTAINERS | 1 + | ||
127 | hw/acpi/meson.build | 6 +- | ||
128 | target/arm/meson.build | 1 + | ||
129 | 27 files changed, 3578 insertions(+), 629 deletions(-) | ||
130 | create mode 100644 docs/system/arm/emulation.rst | ||
131 | create mode 100644 docs/system/arm/nrf.rst | ||
132 | create mode 100644 target/arm/helper-mve.h | ||
133 | create mode 100644 hw/acpi/ghes-stub.c | ||
134 | create mode 100644 target/arm/mve_helper.c | ||
135 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4. | ||
2 | 1 | ||
3 | This change turns out to cause regressions, for instance on the | ||
4 | imx6ul boards as described here: | ||
5 | https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/ | ||
6 | |||
7 | The primary cause of that regression is that the guest code running | ||
8 | at EL3 expects SMCs (not related to PSCI) to do what they would if | ||
9 | our PSCI emulation was not present at all, but after this change | ||
10 | they instead set a value in R0/X0 and continue. | ||
11 | |||
12 | We could fix that by a refactoring that allowed us to only turn on | ||
13 | the PSCI emulation if we weren't booting the guest at EL3, but there | ||
14 | is a more tangled problem with the highbank board, which: | ||
15 | (1) wants to enable PSCI emulation | ||
16 | (2) has a bit of guest code that it wants to run at EL3 and | ||
17 | to perform SMC calls that trap to the monitor vector table: | ||
18 | this is the boot stub code that is written to memory by | ||
19 | arm_write_secure_board_setup_dummy_smc() and which the | ||
20 | highbank board enables by setting bootinfo->secure_board_setup | ||
21 | |||
22 | We can't satisfy both of those and also have the PSCI emulation | ||
23 | handle all SMC instruction executions regardless of function | ||
24 | identifier value. | ||
25 | |||
26 | This is too tricky to try to sort out before 6.2 is released; | ||
27 | revert this commit so we can take the time to get it right in | ||
28 | the 7.0 release. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Message-id: 20211119163419.557623-1-peter.maydell@linaro.org | ||
32 | --- | ||
33 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | ||
34 | 1 file changed, 29 insertions(+), 6 deletions(-) | ||
35 | |||
36 | diff --git a/target/arm/psci.c b/target/arm/psci.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/psci.c | ||
39 | +++ b/target/arm/psci.c | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | |||
42 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | ||
43 | { | ||
44 | - /* | ||
45 | - * Return true if the exception type matches the configured PSCI conduit. | ||
46 | - * This is called before the SMC/HVC instruction is executed, to decide | ||
47 | - * whether we should treat it as a PSCI call or with the architecturally | ||
48 | + /* Return true if the r0/x0 value indicates a PSCI call and | ||
49 | + * the exception type matches the configured PSCI conduit. This is | ||
50 | + * called before the SMC/HVC instruction is executed, to decide whether | ||
51 | + * we should treat it as a PSCI call or with the architecturally | ||
52 | * defined behaviour for an SMC or HVC (which might be UNDEF or trap | ||
53 | * to EL2 or to EL3). | ||
54 | */ | ||
55 | + CPUARMState *env = &cpu->env; | ||
56 | + uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; | ||
57 | |||
58 | switch (excp_type) { | ||
59 | case EXCP_HVC: | ||
60 | @@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | - return true; | ||
65 | + switch (param) { | ||
66 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
67 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
68 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: | ||
69 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
70 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
71 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
72 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
73 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
74 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
75 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
76 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
77 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
78 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
79 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
80 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
81 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
82 | + return true; | ||
83 | + default: | ||
84 | + return false; | ||
85 | + } | ||
86 | } | ||
87 | |||
88 | void arm_handle_psci_call(ARMCPU *cpu) | ||
89 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
90 | break; | ||
91 | case QEMU_PSCI_0_1_FN_MIGRATE: | ||
92 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
93 | - default: | ||
94 | ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
95 | break; | ||
96 | + default: | ||
97 | + g_assert_not_reached(); | ||
98 | } | ||
99 | |||
100 | err: | ||
101 | -- | ||
102 | 2.25.1 | ||
103 | |||
104 | diff view generated by jsdifflib |