1 | Just one patch for rc2, a revert. | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
---|---|---|---|
2 | ethernet device failed 'make check' on big-endian hosts. | ||
2 | 3 | ||
3 | -- PMM | 4 | -- PMM |
4 | 5 | ||
5 | The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
6 | 7 | ||
7 | Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
8 | 9 | ||
9 | are available in the Git repository at: | 10 | are available in the Git repository at: |
10 | 11 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
12 | 13 | ||
13 | for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
14 | 15 | ||
15 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
16 | 17 | ||
17 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
18 | target-arm queue: | 19 | target-arm queue: |
19 | * revert SMCCC/PSCI change, as it regresses some usecases for some boards | 20 | * Correctly initialize MDCR_EL2.HPMN |
21 | * versal: Use nr_apu_cpus in favor of hard coding 2 | ||
22 | * accel/tcg: Add URL of clang bug to comment about our workaround | ||
23 | * Add support for FEAT_DIT, Data Independent Timing | ||
24 | * Remove GPIO from unimplemented NPCM7XX | ||
25 | * Fix SCR RES1 handling | ||
26 | * Don't migrate CPUARMState.features | ||
20 | 27 | ||
21 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
22 | Peter Maydell (1): | 29 | Aaron Lindsay (1): |
23 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" | 30 | target/arm: Don't migrate CPUARMState.features |
24 | 31 | ||
25 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | 32 | Daniel Müller (1): |
26 | 1 file changed, 29 insertions(+), 6 deletions(-) | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
27 | 34 | ||
35 | Edgar E. Iglesias (1): | ||
36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 | ||
37 | |||
38 | Hao Wu (1): | ||
39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | ||
40 | |||
41 | Mike Nawrocki (1): | ||
42 | target/arm: Fix SCR RES1 handling | ||
43 | |||
44 | Peter Maydell (2): | ||
45 | arm: Update infocenter.arm.com URLs | ||
46 | accel/tcg: Add URL of clang bug to comment about our workaround | ||
47 | |||
48 | Rebecca Cran (4): | ||
49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | ||
50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
53 | |||
54 | include/hw/dma/pl080.h | 7 ++-- | ||
55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
56 | include/hw/ssi/pl022.h | 5 ++- | ||
57 | target/arm/cpu.h | 17 ++++++++ | ||
58 | target/arm/internals.h | 6 +++ | ||
59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
61 | hw/arm/musca.c | 4 +- | ||
62 | hw/arm/npcm7xx.c | 8 ---- | ||
63 | hw/arm/xlnx-versal.c | 4 +- | ||
64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
65 | hw/timer/arm_timer.c | 7 ++-- | ||
66 | target/arm/cpu.c | 4 ++ | ||
67 | target/arm/cpu64.c | 5 +++ | ||
68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
70 | target/arm/machine.c | 2 +- | ||
71 | target/arm/op_helper.c | 9 +---- | ||
72 | target/arm/translate-a64.c | 12 ++++++ | ||
73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4. | ||
2 | 1 | ||
3 | This change turns out to cause regressions, for instance on the | ||
4 | imx6ul boards as described here: | ||
5 | https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/ | ||
6 | |||
7 | The primary cause of that regression is that the guest code running | ||
8 | at EL3 expects SMCs (not related to PSCI) to do what they would if | ||
9 | our PSCI emulation was not present at all, but after this change | ||
10 | they instead set a value in R0/X0 and continue. | ||
11 | |||
12 | We could fix that by a refactoring that allowed us to only turn on | ||
13 | the PSCI emulation if we weren't booting the guest at EL3, but there | ||
14 | is a more tangled problem with the highbank board, which: | ||
15 | (1) wants to enable PSCI emulation | ||
16 | (2) has a bit of guest code that it wants to run at EL3 and | ||
17 | to perform SMC calls that trap to the monitor vector table: | ||
18 | this is the boot stub code that is written to memory by | ||
19 | arm_write_secure_board_setup_dummy_smc() and which the | ||
20 | highbank board enables by setting bootinfo->secure_board_setup | ||
21 | |||
22 | We can't satisfy both of those and also have the PSCI emulation | ||
23 | handle all SMC instruction executions regardless of function | ||
24 | identifier value. | ||
25 | |||
26 | This is too tricky to try to sort out before 6.2 is released; | ||
27 | revert this commit so we can take the time to get it right in | ||
28 | the 7.0 release. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Message-id: 20211119163419.557623-1-peter.maydell@linaro.org | ||
32 | --- | ||
33 | target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ | ||
34 | 1 file changed, 29 insertions(+), 6 deletions(-) | ||
35 | |||
36 | diff --git a/target/arm/psci.c b/target/arm/psci.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/psci.c | ||
39 | +++ b/target/arm/psci.c | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | |||
42 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | ||
43 | { | ||
44 | - /* | ||
45 | - * Return true if the exception type matches the configured PSCI conduit. | ||
46 | - * This is called before the SMC/HVC instruction is executed, to decide | ||
47 | - * whether we should treat it as a PSCI call or with the architecturally | ||
48 | + /* Return true if the r0/x0 value indicates a PSCI call and | ||
49 | + * the exception type matches the configured PSCI conduit. This is | ||
50 | + * called before the SMC/HVC instruction is executed, to decide whether | ||
51 | + * we should treat it as a PSCI call or with the architecturally | ||
52 | * defined behaviour for an SMC or HVC (which might be UNDEF or trap | ||
53 | * to EL2 or to EL3). | ||
54 | */ | ||
55 | + CPUARMState *env = &cpu->env; | ||
56 | + uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; | ||
57 | |||
58 | switch (excp_type) { | ||
59 | case EXCP_HVC: | ||
60 | @@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | - return true; | ||
65 | + switch (param) { | ||
66 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
67 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
68 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: | ||
69 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
70 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
71 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
72 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
73 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
74 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
75 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
76 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
77 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
78 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
79 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
80 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
81 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
82 | + return true; | ||
83 | + default: | ||
84 | + return false; | ||
85 | + } | ||
86 | } | ||
87 | |||
88 | void arm_handle_psci_call(ARMCPU *cpu) | ||
89 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
90 | break; | ||
91 | case QEMU_PSCI_0_1_FN_MIGRATE: | ||
92 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
93 | - default: | ||
94 | ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
95 | break; | ||
96 | + default: | ||
97 | + g_assert_not_reached(); | ||
98 | } | ||
99 | |||
100 | err: | ||
101 | -- | ||
102 | 2.25.1 | ||
103 | |||
104 | diff view generated by jsdifflib |