[PULL 0/1] target-arm queue
[PULL v2 00/29] target-arm queue
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Just one patch for rc2, a revert.
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v2: drop pvpanic-pci patches.
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-- PMM
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2:
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000)
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* revert SMCCC/PSCI change, as it regresses some usecases for some boards
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* Implement IMPDEF pauth algorithm
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* Support ARMv8.4-SEL2
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Gan Qixin (1):
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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Peter Maydell (1):
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Peter Maydell (1):
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Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
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docs: Build and install all the docs in a single manual
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target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
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Philippe Mathieu-Daudé (1):
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1 file changed, 29 insertions(+), 6 deletions(-)
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Richard Henderson (7):
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: Add cpu properties to control pauth
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target/arm: Use object_property_add_bool for "sve" property
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target/arm: Introduce PREDDESC field definitions
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Rémi Denis-Courmont (19):
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target/arm: remove redundant tests
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target/arm: add arm_is_el2_enabled() helper
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: factor MDCR_EL2 common handling
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: handle VMID change in secure state
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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docs/conf.py | 46 ++++-
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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diff view generated by jsdifflib
[PULL 1/1] Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
Deleted patch
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This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4.
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This change turns out to cause regressions, for instance on the
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imx6ul boards as described here:
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https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/
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The primary cause of that regression is that the guest code running
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at EL3 expects SMCs (not related to PSCI) to do what they would if
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our PSCI emulation was not present at all, but after this change
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they instead set a value in R0/X0 and continue.
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We could fix that by a refactoring that allowed us to only turn on
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the PSCI emulation if we weren't booting the guest at EL3, but there
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is a more tangled problem with the highbank board, which:
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(1) wants to enable PSCI emulation
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(2) has a bit of guest code that it wants to run at EL3 and
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to perform SMC calls that trap to the monitor vector table:
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this is the boot stub code that is written to memory by
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arm_write_secure_board_setup_dummy_smc() and which the
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highbank board enables by setting bootinfo->secure_board_setup
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We can't satisfy both of those and also have the PSCI emulation
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handle all SMC instruction executions regardless of function
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identifier value.
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This is too tricky to try to sort out before 6.2 is released;
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revert this commit so we can take the time to get it right in
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the 7.0 release.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20211119163419.557623-1-peter.maydell@linaro.org
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---
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target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
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1 file changed, 29 insertions(+), 6 deletions(-)
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diff --git a/target/arm/psci.c b/target/arm/psci.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/psci.c
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+++ b/target/arm/psci.c
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@@ -XXX,XX +XXX,XX @@
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bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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{
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- /*
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- * Return true if the exception type matches the configured PSCI conduit.
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- * This is called before the SMC/HVC instruction is executed, to decide
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- * whether we should treat it as a PSCI call or with the architecturally
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+ /* Return true if the r0/x0 value indicates a PSCI call and
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+ * the exception type matches the configured PSCI conduit. This is
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+ * called before the SMC/HVC instruction is executed, to decide whether
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+ * we should treat it as a PSCI call or with the architecturally
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* defined behaviour for an SMC or HVC (which might be UNDEF or trap
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* to EL2 or to EL3).
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*/
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+ CPUARMState *env = &cpu->env;
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+ uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
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switch (excp_type) {
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case EXCP_HVC:
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@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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return false;
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}
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- return true;
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+ switch (param) {
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+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
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+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
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+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
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+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
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+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
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+ case QEMU_PSCI_0_1_FN_CPU_ON:
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+ case QEMU_PSCI_0_2_FN_CPU_ON:
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+ case QEMU_PSCI_0_2_FN64_CPU_ON:
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+ case QEMU_PSCI_0_1_FN_CPU_OFF:
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+ case QEMU_PSCI_0_2_FN_CPU_OFF:
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+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
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+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
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+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
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+ case QEMU_PSCI_0_1_FN_MIGRATE:
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+ case QEMU_PSCI_0_2_FN_MIGRATE:
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+ return true;
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+ default:
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+ return false;
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+ }
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}
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void arm_handle_psci_call(ARMCPU *cpu)
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@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
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break;
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case QEMU_PSCI_0_1_FN_MIGRATE:
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case QEMU_PSCI_0_2_FN_MIGRATE:
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- default:
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ret = QEMU_PSCI_RET_NOT_SUPPORTED;
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break;
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+ default:
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+ g_assert_not_reached();
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}
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err:
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--
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2.25.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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