Series comparison

-[PULL 0/1] target-arm queue
+[Qemu-devel] [PULL v2 00/23] target-arm queue
-Just one patch for rc2, a revert.
+v2: dropped patches that add the microbit nRF51 non-volatile memories
 and the test case for them.
+thanks
 -- PMM
-The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2:
-  Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100)
+The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:
   Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129
-for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d:
+for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:
-  Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000)
+  gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * revert SMCCC/PSCI change, as it regresses some usecases for some boards
+ * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
  * v8m: Ensure IDAU is respected if SAU is disabled
  * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
  * exec.c: Use correct attrs in cpu_memory_rw_debug()
  * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
  * target/arm: Don't clear supported PMU events when initializing PMCEID1
  * memory: add memory_region_flush_rom_device()
  * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
  * tests/microbit-test: extend testing of microbit devices
  * checkpatch: Don't emit spurious warnings about block comments
  * aspeed/smc: misc bug fixes
  * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
  * xlnx-zynqmp: Realize cluster after putting RPUs in it
  * accel/tcg: Add cluster number to TCG TB hash so differently configured
    CPUs don't pick up cached TBs for the wrong kind of CPU
 ----------------------------------------------------------------
-Peter Maydell (1):
+Aaron Lindsay OS (1):
-      Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
+      target/arm: Don't clear supported PMU events when initializing PMCEID1
- target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
+Cédric Le Goater (4):
-file changed, 29 insertions(+), 6 deletions(-)
+      aspeed/smc: fix default read value
       aspeed/smc: define registers for all possible CS
       aspeed/smc: Add dummy data register
       aspeed/smc: snoop SPI transfers to fake dummy cycles
+Julia Suvorova (3):
+      tests/libqtest: Introduce qtest_init_with_serial()
+      tests/microbit-test: Make test independent of global_qtest
+      tests/microbit-test: Check nRF51 UART functionality
+Luc Michel (1):
+      gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
+Peter Maydell (8):
+      exec.c: Use correct attrs in cpu_memory_rw_debug()
+      accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
+      checkpatch: Don't emit spurious warnings about block comments
+      xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
+      hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
+      qom/cpu: Add cluster_index to CPUState
+      accel/tcg: Add cluster number to TCG TB hash
+      gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
+Richard Henderson (1):
+      target/arm: Fix validation of 32-bit address spaces for aa32
+Stefan Hajnoczi (3):
+      tests/microbit-test: add TWI stub device test
+      MAINTAINERS: update microbit ARM board files
+      memory: add memory_region_flush_rom_device()
+Steffen Görtz (1):
+      arm: Stub out NRF51 TWI magnetometer/accelerometer detection
+Thomas Roth (1):
+      target/arm: v8m: Ensure IDAU is respected if SAU is disabled
+ hw/i2c/Makefile.objs          |   1 +
+ include/exec/exec-all.h       |   4 +-
+ include/exec/memory.h         |  18 +++
+ include/hw/arm/nrf51.h        |   2 +
+ include/hw/arm/nrf51_soc.h    |   1 +
+ include/hw/cpu/cluster.h      |  24 +++
+ include/hw/i2c/microbit_i2c.h |  42 +++++
+ include/hw/ssi/aspeed_smc.h   |   3 +
+ include/qom/cpu.h             |   7 +
+ target/arm/cpu.h              |  11 +-
+ tests/libqtest.h              |  11 ++
+ accel/tcg/cpu-exec.c          |   3 +
+ accel/tcg/translate-all.c     |   3 +
+ accel/tcg/user-exec.c         |  66 ++++++--
+ exec.c                        |  19 ++-
+ gdbstub.c                     | 120 ++++++---------
+ hw/arm/microbit.c             |  16 ++
+ hw/arm/xlnx-zynqmp.c          |   9 +-
+ hw/cpu/cluster.c              |  46 ++++++
+ hw/i2c/microbit_i2c.c         | 127 +++++++++++++++
+ hw/ssi/aspeed_smc.c           | 128 ++++++++++++++-
+ qom/cpu.c                     |   1 +
+ target/arm/cpu.c              |   3 +-
+ target/arm/helper.c           |  67 ++++----
+ tests/libqtest.c              |  25 +++
+ tests/microbit-test.c         | 350 +++++++++++++++++++++++++++++-------------
+ MAINTAINERS                   |   8 +-
+ scripts/checkpatch.pl         |   2 +-
+files changed, 874 insertions(+), 243 deletions(-)
+ create mode 100644 include/hw/i2c/microbit_i2c.h
+ create mode 100644 hw/i2c/microbit_i2c.c

-[PULL 1/1] Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
+Deleted patch
-This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4.
-This change turns out to cause regressions, for instance on the
-imx6ul boards as described here:
-https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/
-The primary cause of that regression is that the guest code running
-at EL3 expects SMCs (not related to PSCI) to do what they would if
-our PSCI emulation was not present at all, but after this change
-they instead set a value in R0/X0 and continue.
-We could fix that by a refactoring that allowed us to only turn on
-the PSCI emulation if we weren't booting the guest at EL3, but there
-is a more tangled problem with the highbank board, which:
- (1) wants to enable PSCI emulation
- (2) has a bit of guest code that it wants to run at EL3 and
-     to perform SMC calls that trap to the monitor vector table:
-     this is the boot stub code that is written to memory by
-     arm_write_secure_board_setup_dummy_smc() and which the
-     highbank board enables by setting bootinfo->secure_board_setup
-We can't satisfy both of those and also have the PSCI emulation
-handle all SMC instruction executions regardless of function
-identifier value.
-This is too tricky to try to sort out before 6.2 is released;
-revert this commit so we can take the time to get it right in
-the 7.0 release.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20211119163419.557623-1-peter.maydell@linaro.org
----
- target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
-file changed, 29 insertions(+), 6 deletions(-)
-diff --git a/target/arm/psci.c b/target/arm/psci.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/psci.c
-+++ b/target/arm/psci.c
-@@ -XXX,XX +XXX,XX @@
- bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
- {
--    /*
--     * Return true if the exception type matches the configured PSCI conduit.
--     * This is called before the SMC/HVC instruction is executed, to decide
--     * whether we should treat it as a PSCI call or with the architecturally
-+    /* Return true if the r0/x0 value indicates a PSCI call and
-+     * the exception type matches the configured PSCI conduit. This is
-+     * called before the SMC/HVC instruction is executed, to decide whether
-+     * we should treat it as a PSCI call or with the architecturally
-      * defined behaviour for an SMC or HVC (which might be UNDEF or trap
-      * to EL2 or to EL3).
-      */
-+    CPUARMState *env = &cpu->env;
-+    uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
-     switch (excp_type) {
-     case EXCP_HVC:
-@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
-         return false;
-     }
--    return true;
-+    switch (param) {
-+    case QEMU_PSCI_0_2_FN_PSCI_VERSION:
-+    case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
-+    case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
-+    case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
-+    case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
-+    case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
-+    case QEMU_PSCI_0_1_FN_CPU_ON:
-+    case QEMU_PSCI_0_2_FN_CPU_ON:
-+    case QEMU_PSCI_0_2_FN64_CPU_ON:
-+    case QEMU_PSCI_0_1_FN_CPU_OFF:
-+    case QEMU_PSCI_0_2_FN_CPU_OFF:
-+    case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
-+    case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
-+    case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
-+    case QEMU_PSCI_0_1_FN_MIGRATE:
-+    case QEMU_PSCI_0_2_FN_MIGRATE:
-+        return true;
-+    default:
-+        return false;
-+    }
- }
- void arm_handle_psci_call(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
-         break;
-     case QEMU_PSCI_0_1_FN_MIGRATE:
-     case QEMU_PSCI_0_2_FN_MIGRATE:
--    default:
-         ret = QEMU_PSCI_RET_NOT_SUPPORTED;
-         break;
-+    default:
-+        g_assert_not_reached();
-     }
- err:
---
-.25.1

This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4.

This change turns out to cause regressions, for instance on the
imx6ul boards as described here:
https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/

The primary cause of that regression is that the guest code running
at EL3 expects SMCs (not related to PSCI) to do what they would if
our PSCI emulation was not present at all, but after this change
they instead set a value in R0/X0 and continue.

We could fix that by a refactoring that allowed us to only turn on
the PSCI emulation if we weren't booting the guest at EL3, but there
is a more tangled problem with the highbank board, which:
 (1) wants to enable PSCI emulation
 (2) has a bit of guest code that it wants to run at EL3 and
     to perform SMC calls that trap to the monitor vector table:
     this is the boot stub code that is written to memory by
     arm_write_secure_board_setup_dummy_smc() and which the
     highbank board enables by setting bootinfo->secure_board_setup

We can't satisfy both of those and also have the PSCI emulation
handle all SMC instruction executions regardless of function
identifier value.

This is too tricky to try to sort out before 6.2 is released;
revert this commit so we can take the time to get it right in
the 7.0 release.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211119163419.557623-1-peter.maydell@linaro.org
---
 target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/target/arm/psci.c b/target/arm/psci.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/psci.c
+++ b/target/arm/psci.c
@@ -XXX,XX +XXX,XX @@
 
 bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 {
-    /*
-     * Return true if the exception type matches the configured PSCI conduit.
-     * This is called before the SMC/HVC instruction is executed, to decide
-     * whether we should treat it as a PSCI call or with the architecturally
+    /* Return true if the r0/x0 value indicates a PSCI call and
+     * the exception type matches the configured PSCI conduit. This is
+     * called before the SMC/HVC instruction is executed, to decide whether
+     * we should treat it as a PSCI call or with the architecturally
      * defined behaviour for an SMC or HVC (which might be UNDEF or trap
      * to EL2 or to EL3).
      */
+    CPUARMState *env = &cpu->env;
+    uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
 
     switch (excp_type) {
     case EXCP_HVC:
@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
         return false;
     }
 
-    return true;
+    switch (param) {
+    case QEMU_PSCI_0_2_FN_PSCI_VERSION:
+    case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+    case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
+    case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
+    case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
+    case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
+    case QEMU_PSCI_0_1_FN_CPU_ON:
+    case QEMU_PSCI_0_2_FN_CPU_ON:
+    case QEMU_PSCI_0_2_FN64_CPU_ON:
+    case QEMU_PSCI_0_1_FN_CPU_OFF:
+    case QEMU_PSCI_0_2_FN_CPU_OFF:
+    case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
+    case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
+    case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
+    case QEMU_PSCI_0_1_FN_MIGRATE:
+    case QEMU_PSCI_0_2_FN_MIGRATE:
+        return true;
+    default:
+        return false;
+    }
 }
 
 void arm_handle_psci_call(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
         break;
     case QEMU_PSCI_0_1_FN_MIGRATE:
     case QEMU_PSCI_0_2_FN_MIGRATE:
-    default:
         ret = QEMU_PSCI_RET_NOT_SUPPORTED;
         break;
+    default:
+        g_assert_not_reached();
     }
 
 err:
-- 
2.25.1

v2: dropped patches that add the microbit nRF51 non-volatile memories
and the test case for them.

thanks
-- PMM

The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129

for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:

gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
 * v8m: Ensure IDAU is respected if SAU is disabled
 * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
 * exec.c: Use correct attrs in cpu_memory_rw_debug()
 * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
 * target/arm: Don't clear supported PMU events when initializing PMCEID1
 * memory: add memory_region_flush_rom_device()
 * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
 * tests/microbit-test: extend testing of microbit devices
 * checkpatch: Don't emit spurious warnings about block comments
 * aspeed/smc: misc bug fixes
 * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
 * xlnx-zynqmp: Realize cluster after putting RPUs in it
 * accel/tcg: Add cluster number to TCG TB hash so differently configured
   CPUs don't pick up cached TBs for the wrong kind of CPU

----------------------------------------------------------------
Aaron Lindsay OS (1):
      target/arm: Don't clear supported PMU events when initializing PMCEID1

Cédric Le Goater (4):
      aspeed/smc: fix default read value
      aspeed/smc: define registers for all possible CS
      aspeed/smc: Add dummy data register
      aspeed/smc: snoop SPI transfers to fake dummy cycles

Julia Suvorova (3):
      tests/libqtest: Introduce qtest_init_with_serial()
      tests/microbit-test: Make test independent of global_qtest
      tests/microbit-test: Check nRF51 UART functionality

Luc Michel (1):
      gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0

Peter Maydell (8):
      exec.c: Use correct attrs in cpu_memory_rw_debug()
      accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
      checkpatch: Don't emit spurious warnings about block comments
      xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
      hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
      qom/cpu: Add cluster_index to CPUState
      accel/tcg: Add cluster number to TCG TB hash
      gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index

Richard Henderson (1):
      target/arm: Fix validation of 32-bit address spaces for aa32

Stefan Hajnoczi (3):
      tests/microbit-test: add TWI stub device test
      MAINTAINERS: update microbit ARM board files
      memory: add memory_region_flush_rom_device()

Steffen Görtz (1):
      arm: Stub out NRF51 TWI magnetometer/accelerometer detection

Thomas Roth (1):
      target/arm: v8m: Ensure IDAU is respected if SAU is disabled