1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | The following changes since commit 3944e93af06f06eb07316e0bef46b007573e0309: |
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2 | 2 | ||
3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: | 3 | Update version for v8.1.0-rc3 release (2023-08-10 12:49:56 -0700) |
4 | |||
5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | ||
6 | 4 | ||
7 | are available in the Git repository at: | 5 | are available in the Git repository at: |
8 | 6 | ||
9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 | 7 | https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230811-3 |
10 | 8 | ||
11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: | 9 | for you to fetch changes up to b274c2388e9fcde75d60c6e7c7d8f888874b61b7: |
12 | 10 | ||
13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) | 11 | hw/riscv/virt.c: change 'aclint' TCG check (2023-08-11 14:16:26 -0400) |
14 | 12 | ||
15 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
16 | Seventh RISC-V PR for QEMU 6.2 | 14 | Sixth RISC-V PR for 8.1 |
17 | 15 | ||
18 | - Deprecate IF_NONE for SiFive OTP | 16 | This is a last minute PR for RISC-V. |
19 | - Don't reset SiFive OTP content | 17 | |
18 | The main goal is to fix | ||
19 | https://gitlab.com/qemu-project/qemu/-/issues/1823 | ||
20 | which is a regression that means the aclint option | ||
21 | cannot be enabled. | ||
22 | |||
23 | While we are here we also fixup KVM issue. | ||
24 | |||
25 | * KVM: fix mvendorid size | ||
26 | * Fixup aclint check | ||
20 | 27 | ||
21 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
22 | Philippe Mathieu-Daudé (1): | 29 | Daniel Henrique Barboza (2): |
23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset | 30 | target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() |
31 | hw/riscv/virt.c: change 'aclint' TCG check | ||
24 | 32 | ||
25 | Thomas Huth (1): | 33 | hw/riscv/virt.c | 20 +++++++++++++------- |
26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE | 34 | target/riscv/kvm.c | 9 ++++++++- |
27 | 35 | 2 files changed, 21 insertions(+), 8 deletions(-) | |
28 | docs/about/deprecated.rst | 6 ++++++ | ||
29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- | ||
30 | 2 files changed, 19 insertions(+), 9 deletions(-) | ||
31 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
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2 | 2 | ||
3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. | 3 | cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write |
4 | a target_ulong val, i.e. a 64 bit field in a 64 bit host. | ||
4 | 5 | ||
5 | Do not re-initialize the OTP content in the DeviceReset handler, | 6 | Given that we're passing a pointer to the mvendorid field, the reg is |
6 | initialize it once in the DeviceRealize one. | 7 | reading 64 bits starting from mvendorid and going 32 bits in the next |
8 | field, marchid. Here's an example: | ||
7 | 9 | ||
8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") | 10 | $ ./qemu-system-riscv64 -machine virt,accel=kvm -m 2G -smp 1 \ |
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | -cpu rv64,marchid=0xab,mvendorid=0xcd,mimpid=0xef(...) |
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 12 | |
11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> | 13 | (inside the guest) |
14 | # cat /proc/cpuinfo | ||
15 | processor : 0 | ||
16 | hart : 0 | ||
17 | isa : rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc | ||
18 | mmu : sv57 | ||
19 | mvendorid : 0xab000000cd | ||
20 | marchid : 0xab | ||
21 | mimpid : 0xef | ||
22 | |||
23 | 'mvendorid' was written as a combination of 0xab (the value from the | ||
24 | adjacent field, marchid) and its intended value 0xcd. | ||
25 | |||
26 | Fix it by assigning cpu->cfg.mvendorid to a target_ulong var 'reg' and | ||
27 | use it as input for kvm_set_one_reg(). Here's the result with this patch | ||
28 | applied and using the same QEMU command line: | ||
29 | |||
30 | # cat /proc/cpuinfo | ||
31 | processor : 0 | ||
32 | hart : 0 | ||
33 | isa : rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc | ||
34 | mmu : sv57 | ||
35 | mvendorid : 0xcd | ||
36 | marchid : 0xab | ||
37 | mimpid : 0xef | ||
38 | |||
39 | This bug affects only the generic (rv64) CPUs when running with KVM in a | ||
40 | 64 bit env since the 'host' CPU does not allow the machine IDs to be | ||
41 | changed via command line. | ||
42 | |||
43 | Fixes: 1fb5a622f7 ("target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs") | ||
44 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
45 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
46 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
47 | Message-ID: <20230802180058.281385-1-dbarboza@ventanamicro.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 48 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
13 | --- | 49 | --- |
14 | hw/misc/sifive_u_otp.c | 13 +++++-------- | 50 | target/riscv/kvm.c | 9 ++++++++- |
15 | 1 file changed, 5 insertions(+), 8 deletions(-) | 51 | 1 file changed, 8 insertions(+), 1 deletion(-) |
16 | 52 | ||
17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 53 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c |
18 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/misc/sifive_u_otp.c | 55 | --- a/target/riscv/kvm.c |
20 | +++ b/hw/misc/sifive_u_otp.c | 56 | +++ b/target/riscv/kvm.c |
21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 57 | @@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s) |
22 | 58 | static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) | |
23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { | 59 | { |
24 | error_setg(errp, "failed to read the initial flash content"); | 60 | CPURISCVState *env = &cpu->env; |
25 | + return; | 61 | + target_ulong reg; |
26 | } | 62 | uint64_t id; |
27 | } | 63 | int ret; |
64 | |||
65 | id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
66 | KVM_REG_RISCV_CONFIG_REG(mvendorid)); | ||
67 | - ret = kvm_set_one_reg(cs, id, &cpu->cfg.mvendorid); | ||
68 | + /* | ||
69 | + * cfg.mvendorid is an uint32 but a target_ulong will | ||
70 | + * be written. Assign it to a target_ulong var to avoid | ||
71 | + * writing pieces of other cpu->cfg fields in the reg. | ||
72 | + */ | ||
73 | + reg = cpu->cfg.mvendorid; | ||
74 | + ret = kvm_set_one_reg(cs, id, ®); | ||
75 | if (ret != 0) { | ||
76 | return ret; | ||
28 | } | 77 | } |
29 | -} | ||
30 | - | ||
31 | -static void sifive_u_otp_reset(DeviceState *dev) | ||
32 | -{ | ||
33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); | ||
34 | |||
35 | /* Initialize all fuses' initial value to 0xFFs */ | ||
36 | memset(s->fuse, 0xff, sizeof(s->fuse)); | ||
37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | ||
38 | serial_data = s->serial; | ||
39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | ||
40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | ||
41 | - error_report("write error index<%d>", index); | ||
42 | + error_setg(errp, "failed to write index<%d>", index); | ||
43 | + return; | ||
44 | } | ||
45 | |||
46 | serial_data = ~(s->serial); | ||
47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | ||
48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | ||
49 | - error_report("write error index<%d>", index + 1); | ||
50 | + error_setg(errp, "failed to write index<%d>", index + 1); | ||
51 | + return; | ||
52 | } | ||
53 | } | ||
54 | |||
55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) | ||
56 | |||
57 | device_class_set_props(dc, sifive_u_otp_properties); | ||
58 | dc->realize = sifive_u_otp_realize; | ||
59 | - dc->reset = sifive_u_otp_reset; | ||
60 | } | ||
61 | |||
62 | static const TypeInfo sifive_u_otp_info = { | ||
63 | -- | 78 | -- |
64 | 2.31.1 | 79 | 2.41.0 |
65 | |||
66 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
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2 | 2 | ||
3 | Configuring a drive with "if=none" is meant for creation of a backend | 3 | The 'aclint' property is being conditioned with tcg acceleration in |
4 | only, it should not get automatically assigned to a device frontend. | 4 | virt_machine_class_init(). But acceleration code starts later than the |
5 | Use "if=pflash" for the One-Time-Programmable device instead (like | 5 | class init of the board, meaning that tcg_enabled() will be always be |
6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | 6 | false during class_init(), and the option is never being declared even |
7 | when declaring TCG accel: | ||
7 | 8 | ||
8 | Since the old way of configuring the device has already been published | 9 | $ ./build/qemu-system-riscv64 -M virt,accel=tcg,aclint=on |
9 | with the previous QEMU versions, we cannot remove this immediately, but | 10 | qemu-system-riscv64: Property 'virt-machine.aclint' not found |
10 | have to deprecate it and support it for at least two more releases. | ||
11 | 11 | ||
12 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 12 | Fix it by moving the check from class_init() to machine_init(). Tune the |
13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 13 | description to mention that the option is TCG only. |
14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 14 | |
15 | Cc: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
16 | Fixes: c0716c81b ("hw/riscv/virt: Restrict ACLINT to TCG") | ||
17 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1823 | ||
18 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 19 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
16 | Message-id: 20211119102549.217755-1-thuth@redhat.com | 20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
21 | Message-ID: <20230811160224.440697-2-dbarboza@ventanamicro.com> | ||
17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
18 | --- | 23 | --- |
19 | docs/about/deprecated.rst | 6 ++++++ | 24 | hw/riscv/virt.c | 20 +++++++++++++------- |
20 | hw/misc/sifive_u_otp.c | 9 ++++++++- | 25 | 1 file changed, 13 insertions(+), 7 deletions(-) |
21 | 2 files changed, 14 insertions(+), 1 deletion(-) | ||
22 | 26 | ||
23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst | 27 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
24 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/docs/about/deprecated.rst | 29 | --- a/hw/riscv/virt.c |
26 | +++ b/docs/about/deprecated.rst | 30 | +++ b/hw/riscv/virt.c |
27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. | 31 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` | 32 | exit(1); |
29 | form is preferred. | 33 | } |
30 | 34 | ||
31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) | 35 | + if (!tcg_enabled() && s->have_aclint) { |
32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | 36 | + error_report("'aclint' is only available with TCG acceleration"); |
37 | + exit(1); | ||
38 | + } | ||
33 | + | 39 | + |
34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u | 40 | /* Initialize sockets */ |
35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. | 41 | mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; |
42 | for (i = 0; i < socket_count; i++) { | ||
43 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
44 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); | ||
45 | #endif | ||
46 | |||
47 | - if (tcg_enabled()) { | ||
48 | - object_class_property_add_bool(oc, "aclint", virt_get_aclint, | ||
49 | - virt_set_aclint); | ||
50 | - object_class_property_set_description(oc, "aclint", | ||
51 | - "Set on/off to enable/disable " | ||
52 | - "emulating ACLINT devices"); | ||
53 | - } | ||
36 | + | 54 | + |
37 | 55 | + object_class_property_add_bool(oc, "aclint", virt_get_aclint, | |
38 | QEMU Machine Protocol (QMP) commands | 56 | + virt_set_aclint); |
39 | ------------------------------------ | 57 | + object_class_property_set_description(oc, "aclint", |
40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 58 | + "(TCG only) Set on/off to " |
41 | index XXXXXXX..XXXXXXX 100644 | 59 | + "enable/disable emulating " |
42 | --- a/hw/misc/sifive_u_otp.c | 60 | + "ACLINT devices"); |
43 | +++ b/hw/misc/sifive_u_otp.c | 61 | + |
44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 62 | object_class_property_add_str(oc, "aia", virt_get_aia, |
45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); | 63 | virt_set_aia); |
46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); | 64 | object_class_property_set_description(oc, "aia", |
47 | |||
48 | - dinfo = drive_get_next(IF_NONE); | ||
49 | + dinfo = drive_get_next(IF_PFLASH); | ||
50 | + if (!dinfo) { | ||
51 | + dinfo = drive_get_next(IF_NONE); | ||
52 | + if (dinfo) { | ||
53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " | ||
54 | + "use \"-drive if=pflash\" instead."); | ||
55 | + } | ||
56 | + } | ||
57 | if (dinfo) { | ||
58 | int ret; | ||
59 | uint64_t perm; | ||
60 | -- | 65 | -- |
61 | 2.31.1 | 66 | 2.41.0 |
62 | 67 | ||
63 | 68 | diff view generated by jsdifflib |