Zhao Liu (1):

hw/riscv: Fix typo field in error_report

docs/system/target-riscv.rst | 24 ++++++++++++++++--------

disas/riscv.h | 2 ++

disas/riscv.c | 19 ++++++++++++++++---

hw/riscv/numa.c | 4 ++--

target/riscv/cpu.c | 3 ++-

target/riscv/vector_helper.c | 4 ++--

6 files changed, 40 insertions(+), 16 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This is how the content of the "RISC-V CPU firmware" section is

displayed after the html is generated:

"When using the sifive_u or virt machine there are three different

firmware boot options: 1. -bios default - This is the default behaviour

if no -bios option is included. (...) 3. -bios <file> - Tells QEMU to

load the specified file as the firmware."

It's all in the same paragraph, in a numbered list, and no special

formatting for the options.

Tidy it a bit by adding line breaks between items and its description.

Remove the numbered list. And apply formatting for the options cited in

the middle of the text.

Cc: qemu-trivial@nongnu.org

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-Id: <20230712143728.383528-1-dbarboza@ventanamicro.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

docs/system/target-riscv.rst | 24 ++++++++++++++++--------

1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/target-riscv.rst

+++ b/docs/system/target-riscv.rst

@@ -XXX,XX +XXX,XX @@ RISC-V CPU firmware

When using the ``sifive_u`` or ``virt`` machine there are three different

firmware boot options:

-1. ``-bios default`` - This is the default behaviour if no -bios option

-is included. This option will load the default OpenSBI firmware automatically.

-The firmware is included with the QEMU release and no user interaction is

-required. All a user needs to do is specify the kernel they want to boot

-with the -kernel option

-2. ``-bios none`` - QEMU will not automatically load any firmware. It is up

-to the user to load all the images they need.

-3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware.

+

+* ``-bios default``

+

+This is the default behaviour if no ``-bios`` option is included. This option

+will load the default OpenSBI firmware automatically. The firmware is included

+with the QEMU release and no user interaction is required. All a user needs to

+do is specify the kernel they want to boot with the ``-kernel`` option

+

+* ``-bios none``

+

+QEMU will not automatically load any firmware. It is up to the user to load all

+the images they need.

+

+* ``-bios <file>``

+

+Tells QEMU to load the specified file as the firmware.

--

2.40.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit bd30559568 made changes in how we're checking and disabling

extensions based on env->priv_ver. One of the changes was to move the

extension disablement code to the end of realize(), being able to

disable extensions after we've auto-enabled some of them.

An unfortunate side effect of this change started to happen with CPUs

that has an older priv version, like sifive-u54. Starting on commit

2288a5ce43e5 we're auto-enabling zca, zcd and zcf if RVC is enabled,

but these extensions are priv version 1.12.0. When running a cpu that

has an older priv ver (like sifive-u54) the user is spammed with

warnings like these:

qemu-system-riscv64: warning: disabling zca extension for hart 0x0000000000000000 because privilege spec version does not match

qemu-system-riscv64: warning: disabling zcd extension for hart 0x0000000000000000 because privilege spec version does not match

The warnings are part of the code that disables the extension, but in this

case we're throwing user warnings for stuff that we enabled on our own,

without user intervention. Users are left wondering what they did wrong.

A quick 8.1 fix for this nuisance is to check the CPU priv spec before

auto-enabling zca/zcd/zcf. A more appropriate fix will include a more

robust framework that will account for both priv_ver and user choice

when auto-enabling/disabling extensions, but for 8.1 we'll make it do

with this simple check.

It's also worth noticing that this is the only case where we're

auto-enabling extensions based on a criteria (in this case RVC) that

doesn't match the priv spec of the extensions we're enabling. There's no

need for more 8.1 band-aids.

Cc: Conor Dooley <conor@kernel.org>

Fixes: 2288a5ce43e5 ("target/riscv: add cfg properties for Zc* extension")

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Tested-by: Conor Dooley <conor.dooley@microchip.com>

Message-Id: <20230717154141.60898-1-dbarboza@ventanamicro.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

target/riscv/cpu.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu.c

+++ b/target/riscv/cpu.c

@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)

}

}

- if (riscv_has_ext(env, RVC)) {

+ /* zca, zcd and zcf has a PRIV 1.12.0 restriction */

+ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {

cpu->cfg.ext_zca = true;

if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {

cpu->cfg.ext_zcf = true;

--

2.40.1

From: Zhao Liu <zhao1.liu@intel.com>

"smp.cpus" means the number of online CPUs and "smp.max_cpus" means the

total number of CPUs.

riscv_numa_get_default_cpu_node_id() checks "smp.cpus" and the

"available CPUs" description in the next error message also indicates

online CPUs.

So report "smp.cpus" in error_report() instand of "smp.max_cpus".

Since "smp.cpus" is "unsigned int", use "%u".

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-Id: <20230718080712.503333-1-zhao1.liu@linux.intel.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

hw/riscv/numa.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/riscv/numa.c

+++ b/hw/riscv/numa.c

@@ -XXX,XX +XXX,XX @@ int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)

if (ms->numa_state->num_nodes > ms->smp.cpus) {

error_report("Number of NUMA nodes (%d)"

- " cannot exceed the number of available CPUs (%d).",

- ms->numa_state->num_nodes, ms->smp.max_cpus);

+ " cannot exceed the number of available CPUs (%u).",

+ ms->numa_state->num_nodes, ms->smp.cpus);

exit(EXIT_FAILURE);

}

if (ms->numa_state->num_nodes) {

--

2.40.1