1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
---|---|---|---|
2 | 2 | ||
3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: | 3 | The following changes since commit 239b8b0699a222fd21da1c5fdeba0a2456085a47: |
4 | 4 | ||
5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | 5 | Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-01-19 15:05:29 +0000) |
6 | 6 | ||
7 | are available in the Git repository at: | 7 | are available in the Git repository at: |
8 | 8 | ||
9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 | 9 | https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230120 |
10 | 10 | ||
11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: | 11 | for you to fetch changes up to b748352c555b42d497fe8ee00ee2e44eb8627660: |
12 | 12 | ||
13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) | 13 | hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() (2023-01-20 10:14:14 +1000) |
14 | 14 | ||
15 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
16 | Seventh RISC-V PR for QEMU 6.2 | 16 | Second RISC-V PR for QEMU 8.0 |
17 | 17 | ||
18 | - Deprecate IF_NONE for SiFive OTP | 18 | * riscv_htif: Support console output via proxy syscall |
19 | - Don't reset SiFive OTP content | 19 | * Cleanup firmware and device tree loading |
20 | * Fix elen check when using vector extensions | ||
21 | * add RISC-V OpenSBI boot test | ||
22 | * Ensure we always follow MISA parsing | ||
23 | * Fix up masking of vsip/vsie accesses | ||
24 | * Trap on writes to stimecmp from VS when hvictl.VTI=1 | ||
25 | * Introduce helper_set_rounding_mode_chkfrm | ||
20 | 26 | ||
21 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
22 | Philippe Mathieu-Daudé (1): | 28 | Andrew Bresticker (2): |
23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset | 29 | target/riscv: Fix up masking of vsip/vsie accesses |
30 | target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 | ||
24 | 31 | ||
25 | Thomas Huth (1): | 32 | Bin Meng (11): |
26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE | 33 | hw/char: riscv_htif: Avoid using magic numbers |
34 | hw/char: riscv_htif: Drop {to, from}host_size in HTIFState | ||
35 | hw/char: riscv_htif: Drop useless assignment of memory region | ||
36 | hw/char: riscv_htif: Use conventional 's' for HTIFState | ||
37 | hw/char: riscv_htif: Move registers from CPUArchState to HTIFState | ||
38 | hw/char: riscv_htif: Remove forward declarations for non-existent variables | ||
39 | hw/char: riscv_htif: Support console output via proxy syscall | ||
40 | hw/riscv: spike: Remove the out-of-date comments | ||
41 | hw/riscv/boot.c: Introduce riscv_find_firmware() | ||
42 | hw/riscv: spike: Decouple create_fdt() dependency to ELF loading | ||
43 | target/riscv: Use TARGET_FMT_lx for env->mhartid | ||
27 | 44 | ||
28 | docs/about/deprecated.rst | 6 ++++++ | 45 | Daniel Henrique Barboza (20): |
29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- | 46 | hw/riscv/boot.c: make riscv_find_firmware() static |
30 | 2 files changed, 19 insertions(+), 9 deletions(-) | 47 | hw/riscv/boot.c: introduce riscv_default_firmware_name() |
48 | tests/avocado: add RISC-V OpenSBI boot test | ||
49 | hw/riscv/spike: use 'fdt' from MachineState | ||
50 | hw/riscv/sifive_u: use 'fdt' from MachineState | ||
51 | hw/riscv/boot.c: exit early if filename is NULL in load functions | ||
52 | hw/riscv/spike.c: load initrd right after riscv_load_kernel() | ||
53 | hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() | ||
54 | hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() | ||
55 | hw/riscv/boot.c: use MachineState in riscv_load_initrd() | ||
56 | hw/riscv/boot.c: use MachineState in riscv_load_kernel() | ||
57 | target/riscv/cpu: set cpu->cfg in register_cpu_props() | ||
58 | target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() | ||
59 | hw/riscv/spike.c: simplify create_fdt() | ||
60 | hw/riscv/virt.c: simplify create_fdt() | ||
61 | hw/riscv/sifive_u.c: simplify create_fdt() | ||
62 | hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() | ||
63 | hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() | ||
64 | hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() | ||
65 | hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() | ||
31 | 66 | ||
67 | Dongxue Zhang (1): | ||
68 | target/riscv/cpu.c: Fix elen check | ||
69 | |||
70 | Richard Henderson (3): | ||
71 | tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst | ||
72 | target/riscv: Introduce helper_set_rounding_mode_chkfrm | ||
73 | target/riscv: Remove helper_set_rod_rounding_mode | ||
74 | |||
75 | include/hw/char/riscv_htif.h | 19 +- | ||
76 | include/hw/riscv/boot.h | 9 +- | ||
77 | include/hw/riscv/numa.h | 10 +- | ||
78 | include/hw/riscv/sifive_u.h | 3 - | ||
79 | include/hw/riscv/spike.h | 2 - | ||
80 | target/riscv/cpu.h | 8 +- | ||
81 | target/riscv/helper.h | 2 +- | ||
82 | hw/char/riscv_htif.c | 172 +++++++----- | ||
83 | hw/riscv/boot.c | 105 +++++--- | ||
84 | hw/riscv/microchip_pfsoc.c | 12 +- | ||
85 | hw/riscv/numa.c | 14 +- | ||
86 | hw/riscv/opentitan.c | 3 +- | ||
87 | hw/riscv/sifive_e.c | 3 +- | ||
88 | hw/riscv/sifive_u.c | 53 ++-- | ||
89 | hw/riscv/spike.c | 108 ++++---- | ||
90 | hw/riscv/virt.c | 86 +++--- | ||
91 | target/riscv/cpu.c | 445 ++++++++++++++++++-------------- | ||
92 | target/riscv/csr.c | 41 ++- | ||
93 | target/riscv/fpu_helper.c | 36 ++- | ||
94 | target/riscv/machine.c | 6 +- | ||
95 | target/riscv/translate.c | 21 +- | ||
96 | target/riscv/insn_trans/trans_rvv.c.inc | 24 +- | ||
97 | tcg/riscv/tcg-target.c.inc | 2 +- | ||
98 | tests/avocado/riscv_opensbi.py | 65 +++++ | ||
99 | 24 files changed, 713 insertions(+), 536 deletions(-) | ||
100 | create mode 100644 tests/avocado/riscv_opensbi.py | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | The Spike HTIF is poorly documented. The only relevant info we can | ||
4 | get from the internet is from Andrew Waterman at [1]. | ||
5 | |||
6 | Add a comment block before htif_handle_tohost_write() to explain | ||
7 | the tohost register format, and use meaningful macros instead of | ||
8 | magic numbers in the codes. | ||
9 | |||
10 | While we are here, correct 2 multi-line comment blocks that have | ||
11 | wrong format. | ||
12 | |||
13 | Link: https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754 [1] | ||
14 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
15 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | Message-Id: <20221229091828.1945072-2-bmeng@tinylab.org> | ||
18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | --- | ||
20 | hw/char/riscv_htif.c | 72 ++++++++++++++++++++++++++++++++------------ | ||
21 | 1 file changed, 52 insertions(+), 20 deletions(-) | ||
22 | |||
23 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/hw/char/riscv_htif.c | ||
26 | +++ b/hw/char/riscv_htif.c | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | } \ | ||
29 | } while (0) | ||
30 | |||
31 | +#define HTIF_DEV_SHIFT 56 | ||
32 | +#define HTIF_CMD_SHIFT 48 | ||
33 | + | ||
34 | +#define HTIF_DEV_SYSTEM 0 | ||
35 | +#define HTIF_DEV_CONSOLE 1 | ||
36 | + | ||
37 | +#define HTIF_SYSTEM_CMD_SYSCALL 0 | ||
38 | +#define HTIF_CONSOLE_CMD_GETC 0 | ||
39 | +#define HTIF_CONSOLE_CMD_PUTC 1 | ||
40 | + | ||
41 | static uint64_t fromhost_addr, tohost_addr; | ||
42 | static int address_symbol_set; | ||
43 | |||
44 | @@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size) | ||
45 | return; | ||
46 | } | ||
47 | |||
48 | - /* TODO - we need to check whether mfromhost is zero which indicates | ||
49 | - the device is ready to receive. The current implementation | ||
50 | - will drop characters */ | ||
51 | + /* | ||
52 | + * TODO - we need to check whether mfromhost is zero which indicates | ||
53 | + * the device is ready to receive. The current implementation | ||
54 | + * will drop characters | ||
55 | + */ | ||
56 | |||
57 | uint64_t val_written = htifstate->pending_read; | ||
58 | uint64_t resp = 0x100 | *buf; | ||
59 | @@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque) | ||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | +/* | ||
64 | + * See below the tohost register format. | ||
65 | + * | ||
66 | + * Bits 63:56 indicate the "device". | ||
67 | + * Bits 55:48 indicate the "command". | ||
68 | + * | ||
69 | + * Device 0 is the syscall device, which is used to emulate Unixy syscalls. | ||
70 | + * It only implements command 0, which has two subfunctions: | ||
71 | + * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct | ||
72 | + * describing the syscall. | ||
73 | + * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero | ||
74 | + * value indicating success and other values indicating failure. | ||
75 | + * | ||
76 | + * Device 1 is the blocking character device. | ||
77 | + * - Command 0 reads a character | ||
78 | + * - Command 1 writes a character from the 8 LSBs of tohost | ||
79 | + * | ||
80 | + * For RV32, the tohost register is zero-extended, so only device=0 and | ||
81 | + * command=0 (i.e. HTIF syscalls/exit codes) are supported. | ||
82 | + */ | ||
83 | static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
84 | { | ||
85 | - uint8_t device = val_written >> 56; | ||
86 | - uint8_t cmd = val_written >> 48; | ||
87 | + uint8_t device = val_written >> HTIF_DEV_SHIFT; | ||
88 | + uint8_t cmd = val_written >> HTIF_CMD_SHIFT; | ||
89 | uint64_t payload = val_written & 0xFFFFFFFFFFFFULL; | ||
90 | int resp = 0; | ||
91 | |||
92 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
93 | * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy) | ||
94 | * 1: Console | ||
95 | */ | ||
96 | - if (unlikely(device == 0x0)) { | ||
97 | + if (unlikely(device == HTIF_DEV_SYSTEM)) { | ||
98 | /* frontend syscall handler, shutdown and exit code support */ | ||
99 | - if (cmd == 0x0) { | ||
100 | + if (cmd == HTIF_SYSTEM_CMD_SYSCALL) { | ||
101 | if (payload & 0x1) { | ||
102 | /* exit code */ | ||
103 | int exit_code = payload >> 1; | ||
104 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
105 | } else { | ||
106 | qemu_log("HTIF device %d: unknown command\n", device); | ||
107 | } | ||
108 | - } else if (likely(device == 0x1)) { | ||
109 | + } else if (likely(device == HTIF_DEV_CONSOLE)) { | ||
110 | /* HTIF Console */ | ||
111 | - if (cmd == 0x0) { | ||
112 | + if (cmd == HTIF_CONSOLE_CMD_GETC) { | ||
113 | /* this should be a queue, but not yet implemented as such */ | ||
114 | htifstate->pending_read = val_written; | ||
115 | htifstate->env->mtohost = 0; /* clear to indicate we read */ | ||
116 | return; | ||
117 | - } else if (cmd == 0x1) { | ||
118 | + } else if (cmd == HTIF_CONSOLE_CMD_PUTC) { | ||
119 | qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); | ||
120 | resp = 0x100 | (uint8_t)payload; | ||
121 | } else { | ||
122 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
123 | " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload); | ||
124 | } | ||
125 | /* | ||
126 | - * - latest bbl does not set fromhost to 0 if there is a value in tohost | ||
127 | - * - with this code enabled, qemu hangs waiting for fromhost to go to 0 | ||
128 | - * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10 | ||
129 | - * - HTIF needs protocol documentation and a more complete state machine | ||
130 | - | ||
131 | - while (!htifstate->fromhost_inprogress && | ||
132 | - htifstate->env->mfromhost != 0x0) { | ||
133 | - } | ||
134 | - */ | ||
135 | + * Latest bbl does not set fromhost to 0 if there is a value in tohost. | ||
136 | + * With this code enabled, qemu hangs waiting for fromhost to go to 0. | ||
137 | + * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10. | ||
138 | + * HTIF needs protocol documentation and a more complete state machine. | ||
139 | + * | ||
140 | + * while (!htifstate->fromhost_inprogress && | ||
141 | + * htifstate->env->mfromhost != 0x0) { | ||
142 | + * } | ||
143 | + */ | ||
144 | htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
145 | htifstate->env->mtohost = 0; /* clear to indicate we read */ | ||
146 | } | ||
147 | @@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) | ||
148 | |||
149 | /* CPU wrote to an HTIF register */ | ||
150 | static void htif_mm_write(void *opaque, hwaddr addr, | ||
151 | - uint64_t value, unsigned size) | ||
152 | + uint64_t value, unsigned size) | ||
153 | { | ||
154 | HTIFState *htifstate = opaque; | ||
155 | if (addr == TOHOST_OFFSET1) { | ||
156 | -- | ||
157 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | These are not used anywhere. Drop them. | ||
4 | |||
5 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
6 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-Id: <20221229091828.1945072-3-bmeng@tinylab.org> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | include/hw/char/riscv_htif.h | 2 -- | ||
12 | 1 file changed, 2 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/char/riscv_htif.h | ||
17 | +++ b/include/hw/char/riscv_htif.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef struct HTIFState { | ||
19 | |||
20 | hwaddr tohost_offset; | ||
21 | hwaddr fromhost_offset; | ||
22 | - uint64_t tohost_size; | ||
23 | - uint64_t fromhost_size; | ||
24 | MemoryRegion mmio; | ||
25 | MemoryRegion *address_space; | ||
26 | MemoryRegion *main_mem; | ||
27 | -- | ||
28 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | struct HTIFState has 3 members for address space and memory region, | ||
4 | and are initialized during htif_mm_init(). But they are actually | ||
5 | useless. Drop them. | ||
6 | |||
7 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-Id: <20221229091828.1945072-4-bmeng@tinylab.org> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | include/hw/char/riscv_htif.h | 7 ++----- | ||
14 | hw/char/riscv_htif.c | 7 ++----- | ||
15 | hw/riscv/spike.c | 5 ++--- | ||
16 | 3 files changed, 6 insertions(+), 13 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/char/riscv_htif.h | ||
21 | +++ b/include/hw/char/riscv_htif.h | ||
22 | @@ -XXX,XX +XXX,XX @@ typedef struct HTIFState { | ||
23 | hwaddr tohost_offset; | ||
24 | hwaddr fromhost_offset; | ||
25 | MemoryRegion mmio; | ||
26 | - MemoryRegion *address_space; | ||
27 | - MemoryRegion *main_mem; | ||
28 | - void *main_mem_ram_ptr; | ||
29 | |||
30 | CPURISCVState *env; | ||
31 | CharBackend chr; | ||
32 | @@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, | ||
33 | bool htif_uses_elf_symbols(void); | ||
34 | |||
35 | /* legacy pre qom */ | ||
36 | -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, | ||
37 | - CPURISCVState *env, Chardev *chr, uint64_t nonelf_base); | ||
38 | +HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, | ||
39 | + Chardev *chr, uint64_t nonelf_base); | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/char/riscv_htif.c | ||
45 | +++ b/hw/char/riscv_htif.c | ||
46 | @@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void) | ||
47 | return (address_symbol_set == 3) ? true : false; | ||
48 | } | ||
49 | |||
50 | -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, | ||
51 | - CPURISCVState *env, Chardev *chr, uint64_t nonelf_base) | ||
52 | +HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, | ||
53 | + Chardev *chr, uint64_t nonelf_base) | ||
54 | { | ||
55 | uint64_t base, size, tohost_offset, fromhost_offset; | ||
56 | |||
57 | @@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, | ||
58 | fromhost_offset = fromhost_addr - base; | ||
59 | |||
60 | HTIFState *s = g_new0(HTIFState, 1); | ||
61 | - s->address_space = address_space; | ||
62 | - s->main_mem = main_mem; | ||
63 | - s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem); | ||
64 | s->env = env; | ||
65 | s->tohost_offset = tohost_offset; | ||
66 | s->fromhost_offset = fromhost_offset; | ||
67 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/hw/riscv/spike.c | ||
70 | +++ b/hw/riscv/spike.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
72 | fdt_load_addr); | ||
73 | |||
74 | /* initialize HTIF using symbols found in load_kernel */ | ||
75 | - htif_mm_init(system_memory, mask_rom, | ||
76 | - &s->soc[0].harts[0].env, serial_hd(0), | ||
77 | - memmap[SPIKE_HTIF].base); | ||
78 | + htif_mm_init(system_memory, &s->soc[0].harts[0].env, | ||
79 | + serial_hd(0), memmap[SPIKE_HTIF].base); | ||
80 | } | ||
81 | |||
82 | static void spike_machine_instance_init(Object *obj) | ||
83 | -- | ||
84 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | QEMU source codes tend to use 's' to represent the hardware state. | ||
4 | Let's use it for HTIFState. | ||
5 | |||
6 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
7 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <20221229091828.1945072-5-bmeng@tinylab.org> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | hw/char/riscv_htif.c | 64 ++++++++++++++++++++++---------------------- | ||
13 | 1 file changed, 32 insertions(+), 32 deletions(-) | ||
14 | |||
15 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/char/riscv_htif.c | ||
18 | +++ b/hw/char/riscv_htif.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static int htif_can_recv(void *opaque) | ||
20 | */ | ||
21 | static void htif_recv(void *opaque, const uint8_t *buf, int size) | ||
22 | { | ||
23 | - HTIFState *htifstate = opaque; | ||
24 | + HTIFState *s = opaque; | ||
25 | |||
26 | if (size != 1) { | ||
27 | return; | ||
28 | @@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size) | ||
29 | * will drop characters | ||
30 | */ | ||
31 | |||
32 | - uint64_t val_written = htifstate->pending_read; | ||
33 | + uint64_t val_written = s->pending_read; | ||
34 | uint64_t resp = 0x100 | *buf; | ||
35 | |||
36 | - htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
37 | + s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
38 | } | ||
39 | |||
40 | /* | ||
41 | @@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque) | ||
42 | * For RV32, the tohost register is zero-extended, so only device=0 and | ||
43 | * command=0 (i.e. HTIF syscalls/exit codes) are supported. | ||
44 | */ | ||
45 | -static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
46 | +static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) | ||
47 | { | ||
48 | uint8_t device = val_written >> HTIF_DEV_SHIFT; | ||
49 | uint8_t cmd = val_written >> HTIF_CMD_SHIFT; | ||
50 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
51 | /* HTIF Console */ | ||
52 | if (cmd == HTIF_CONSOLE_CMD_GETC) { | ||
53 | /* this should be a queue, but not yet implemented as such */ | ||
54 | - htifstate->pending_read = val_written; | ||
55 | - htifstate->env->mtohost = 0; /* clear to indicate we read */ | ||
56 | + s->pending_read = val_written; | ||
57 | + s->env->mtohost = 0; /* clear to indicate we read */ | ||
58 | return; | ||
59 | } else if (cmd == HTIF_CONSOLE_CMD_PUTC) { | ||
60 | - qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); | ||
61 | + qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); | ||
62 | resp = 0x100 | (uint8_t)payload; | ||
63 | } else { | ||
64 | qemu_log("HTIF device %d: unknown command\n", device); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) | ||
66 | * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10. | ||
67 | * HTIF needs protocol documentation and a more complete state machine. | ||
68 | * | ||
69 | - * while (!htifstate->fromhost_inprogress && | ||
70 | - * htifstate->env->mfromhost != 0x0) { | ||
71 | + * while (!s->fromhost_inprogress && | ||
72 | + * s->env->mfromhost != 0x0) { | ||
73 | * } | ||
74 | */ | ||
75 | - htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
76 | - htifstate->env->mtohost = 0; /* clear to indicate we read */ | ||
77 | + s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
78 | + s->env->mtohost = 0; /* clear to indicate we read */ | ||
79 | } | ||
80 | |||
81 | -#define TOHOST_OFFSET1 (htifstate->tohost_offset) | ||
82 | -#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4) | ||
83 | -#define FROMHOST_OFFSET1 (htifstate->fromhost_offset) | ||
84 | -#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4) | ||
85 | +#define TOHOST_OFFSET1 (s->tohost_offset) | ||
86 | +#define TOHOST_OFFSET2 (s->tohost_offset + 4) | ||
87 | +#define FROMHOST_OFFSET1 (s->fromhost_offset) | ||
88 | +#define FROMHOST_OFFSET2 (s->fromhost_offset + 4) | ||
89 | |||
90 | /* CPU wants to read an HTIF register */ | ||
91 | static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) | ||
92 | { | ||
93 | - HTIFState *htifstate = opaque; | ||
94 | + HTIFState *s = opaque; | ||
95 | if (addr == TOHOST_OFFSET1) { | ||
96 | - return htifstate->env->mtohost & 0xFFFFFFFF; | ||
97 | + return s->env->mtohost & 0xFFFFFFFF; | ||
98 | } else if (addr == TOHOST_OFFSET2) { | ||
99 | - return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF; | ||
100 | + return (s->env->mtohost >> 32) & 0xFFFFFFFF; | ||
101 | } else if (addr == FROMHOST_OFFSET1) { | ||
102 | - return htifstate->env->mfromhost & 0xFFFFFFFF; | ||
103 | + return s->env->mfromhost & 0xFFFFFFFF; | ||
104 | } else if (addr == FROMHOST_OFFSET2) { | ||
105 | - return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF; | ||
106 | + return (s->env->mfromhost >> 32) & 0xFFFFFFFF; | ||
107 | } else { | ||
108 | qemu_log("Invalid htif read: address %016" PRIx64 "\n", | ||
109 | (uint64_t)addr); | ||
110 | @@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) | ||
111 | static void htif_mm_write(void *opaque, hwaddr addr, | ||
112 | uint64_t value, unsigned size) | ||
113 | { | ||
114 | - HTIFState *htifstate = opaque; | ||
115 | + HTIFState *s = opaque; | ||
116 | if (addr == TOHOST_OFFSET1) { | ||
117 | - if (htifstate->env->mtohost == 0x0) { | ||
118 | - htifstate->allow_tohost = 1; | ||
119 | - htifstate->env->mtohost = value & 0xFFFFFFFF; | ||
120 | + if (s->env->mtohost == 0x0) { | ||
121 | + s->allow_tohost = 1; | ||
122 | + s->env->mtohost = value & 0xFFFFFFFF; | ||
123 | } else { | ||
124 | - htifstate->allow_tohost = 0; | ||
125 | + s->allow_tohost = 0; | ||
126 | } | ||
127 | } else if (addr == TOHOST_OFFSET2) { | ||
128 | - if (htifstate->allow_tohost) { | ||
129 | - htifstate->env->mtohost |= value << 32; | ||
130 | - htif_handle_tohost_write(htifstate, htifstate->env->mtohost); | ||
131 | + if (s->allow_tohost) { | ||
132 | + s->env->mtohost |= value << 32; | ||
133 | + htif_handle_tohost_write(s, s->env->mtohost); | ||
134 | } | ||
135 | } else if (addr == FROMHOST_OFFSET1) { | ||
136 | - htifstate->fromhost_inprogress = 1; | ||
137 | - htifstate->env->mfromhost = value & 0xFFFFFFFF; | ||
138 | + s->fromhost_inprogress = 1; | ||
139 | + s->env->mfromhost = value & 0xFFFFFFFF; | ||
140 | } else if (addr == FROMHOST_OFFSET2) { | ||
141 | - htifstate->env->mfromhost |= value << 32; | ||
142 | - htifstate->fromhost_inprogress = 0; | ||
143 | + s->env->mfromhost |= value << 32; | ||
144 | + s->fromhost_inprogress = 0; | ||
145 | } else { | ||
146 | qemu_log("Invalid htif write: address %016" PRIx64 "\n", | ||
147 | (uint64_t)addr); | ||
148 | -- | ||
149 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | At present for some unknown reason the HTIF registers (fromhost & | ||
4 | tohost) are defined in the RISC-V CPUArchState. It should really | ||
5 | be put in the HTIFState struct as it is only meaningful to HTIF. | ||
6 | |||
7 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | include/hw/char/riscv_htif.h | 8 ++++---- | ||
14 | target/riscv/cpu.h | 4 ---- | ||
15 | hw/char/riscv_htif.c | 35 +++++++++++++++++------------------ | ||
16 | hw/riscv/spike.c | 3 +-- | ||
17 | target/riscv/machine.c | 6 ++---- | ||
18 | 5 files changed, 24 insertions(+), 32 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/char/riscv_htif.h | ||
23 | +++ b/include/hw/char/riscv_htif.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "chardev/char.h" | ||
26 | #include "chardev/char-fe.h" | ||
27 | #include "exec/memory.h" | ||
28 | -#include "target/riscv/cpu.h" | ||
29 | |||
30 | #define TYPE_HTIF_UART "riscv.htif.uart" | ||
31 | |||
32 | @@ -XXX,XX +XXX,XX @@ typedef struct HTIFState { | ||
33 | int allow_tohost; | ||
34 | int fromhost_inprogress; | ||
35 | |||
36 | + uint64_t tohost; | ||
37 | + uint64_t fromhost; | ||
38 | hwaddr tohost_offset; | ||
39 | hwaddr fromhost_offset; | ||
40 | MemoryRegion mmio; | ||
41 | |||
42 | - CPURISCVState *env; | ||
43 | CharBackend chr; | ||
44 | uint64_t pending_read; | ||
45 | } HTIFState; | ||
46 | @@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, | ||
47 | bool htif_uses_elf_symbols(void); | ||
48 | |||
49 | /* legacy pre qom */ | ||
50 | -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, | ||
51 | - Chardev *chr, uint64_t nonelf_base); | ||
52 | +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, | ||
53 | + uint64_t nonelf_base); | ||
54 | |||
55 | #endif | ||
56 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/riscv/cpu.h | ||
59 | +++ b/target/riscv/cpu.h | ||
60 | @@ -XXX,XX +XXX,XX @@ struct CPUArchState { | ||
61 | target_ulong sscratch; | ||
62 | target_ulong mscratch; | ||
63 | |||
64 | - /* temporary htif regs */ | ||
65 | - uint64_t mfromhost; | ||
66 | - uint64_t mtohost; | ||
67 | - | ||
68 | /* Sstc CSRs */ | ||
69 | uint64_t stimecmp; | ||
70 | |||
71 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/hw/char/riscv_htif.c | ||
74 | +++ b/hw/char/riscv_htif.c | ||
75 | @@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size) | ||
76 | uint64_t val_written = s->pending_read; | ||
77 | uint64_t resp = 0x100 | *buf; | ||
78 | |||
79 | - s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
80 | + s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
81 | } | ||
82 | |||
83 | /* | ||
84 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) | ||
85 | if (cmd == HTIF_CONSOLE_CMD_GETC) { | ||
86 | /* this should be a queue, but not yet implemented as such */ | ||
87 | s->pending_read = val_written; | ||
88 | - s->env->mtohost = 0; /* clear to indicate we read */ | ||
89 | + s->tohost = 0; /* clear to indicate we read */ | ||
90 | return; | ||
91 | } else if (cmd == HTIF_CONSOLE_CMD_PUTC) { | ||
92 | qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); | ||
93 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) | ||
94 | * HTIF needs protocol documentation and a more complete state machine. | ||
95 | * | ||
96 | * while (!s->fromhost_inprogress && | ||
97 | - * s->env->mfromhost != 0x0) { | ||
98 | + * s->fromhost != 0x0) { | ||
99 | * } | ||
100 | */ | ||
101 | - s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
102 | - s->env->mtohost = 0; /* clear to indicate we read */ | ||
103 | + s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); | ||
104 | + s->tohost = 0; /* clear to indicate we read */ | ||
105 | } | ||
106 | |||
107 | #define TOHOST_OFFSET1 (s->tohost_offset) | ||
108 | @@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) | ||
109 | { | ||
110 | HTIFState *s = opaque; | ||
111 | if (addr == TOHOST_OFFSET1) { | ||
112 | - return s->env->mtohost & 0xFFFFFFFF; | ||
113 | + return s->tohost & 0xFFFFFFFF; | ||
114 | } else if (addr == TOHOST_OFFSET2) { | ||
115 | - return (s->env->mtohost >> 32) & 0xFFFFFFFF; | ||
116 | + return (s->tohost >> 32) & 0xFFFFFFFF; | ||
117 | } else if (addr == FROMHOST_OFFSET1) { | ||
118 | - return s->env->mfromhost & 0xFFFFFFFF; | ||
119 | + return s->fromhost & 0xFFFFFFFF; | ||
120 | } else if (addr == FROMHOST_OFFSET2) { | ||
121 | - return (s->env->mfromhost >> 32) & 0xFFFFFFFF; | ||
122 | + return (s->fromhost >> 32) & 0xFFFFFFFF; | ||
123 | } else { | ||
124 | qemu_log("Invalid htif read: address %016" PRIx64 "\n", | ||
125 | (uint64_t)addr); | ||
126 | @@ -XXX,XX +XXX,XX @@ static void htif_mm_write(void *opaque, hwaddr addr, | ||
127 | { | ||
128 | HTIFState *s = opaque; | ||
129 | if (addr == TOHOST_OFFSET1) { | ||
130 | - if (s->env->mtohost == 0x0) { | ||
131 | + if (s->tohost == 0x0) { | ||
132 | s->allow_tohost = 1; | ||
133 | - s->env->mtohost = value & 0xFFFFFFFF; | ||
134 | + s->tohost = value & 0xFFFFFFFF; | ||
135 | } else { | ||
136 | s->allow_tohost = 0; | ||
137 | } | ||
138 | } else if (addr == TOHOST_OFFSET2) { | ||
139 | if (s->allow_tohost) { | ||
140 | - s->env->mtohost |= value << 32; | ||
141 | - htif_handle_tohost_write(s, s->env->mtohost); | ||
142 | + s->tohost |= value << 32; | ||
143 | + htif_handle_tohost_write(s, s->tohost); | ||
144 | } | ||
145 | } else if (addr == FROMHOST_OFFSET1) { | ||
146 | s->fromhost_inprogress = 1; | ||
147 | - s->env->mfromhost = value & 0xFFFFFFFF; | ||
148 | + s->fromhost = value & 0xFFFFFFFF; | ||
149 | } else if (addr == FROMHOST_OFFSET2) { | ||
150 | - s->env->mfromhost |= value << 32; | ||
151 | + s->fromhost |= value << 32; | ||
152 | s->fromhost_inprogress = 0; | ||
153 | } else { | ||
154 | qemu_log("Invalid htif write: address %016" PRIx64 "\n", | ||
155 | @@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void) | ||
156 | return (address_symbol_set == 3) ? true : false; | ||
157 | } | ||
158 | |||
159 | -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, | ||
160 | - Chardev *chr, uint64_t nonelf_base) | ||
161 | +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, | ||
162 | + uint64_t nonelf_base) | ||
163 | { | ||
164 | uint64_t base, size, tohost_offset, fromhost_offset; | ||
165 | |||
166 | @@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, | ||
167 | fromhost_offset = fromhost_addr - base; | ||
168 | |||
169 | HTIFState *s = g_new0(HTIFState, 1); | ||
170 | - s->env = env; | ||
171 | s->tohost_offset = tohost_offset; | ||
172 | s->fromhost_offset = fromhost_offset; | ||
173 | s->pending_read = 0; | ||
174 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
175 | index XXXXXXX..XXXXXXX 100644 | ||
176 | --- a/hw/riscv/spike.c | ||
177 | +++ b/hw/riscv/spike.c | ||
178 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
179 | fdt_load_addr); | ||
180 | |||
181 | /* initialize HTIF using symbols found in load_kernel */ | ||
182 | - htif_mm_init(system_memory, &s->soc[0].harts[0].env, | ||
183 | - serial_hd(0), memmap[SPIKE_HTIF].base); | ||
184 | + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); | ||
185 | } | ||
186 | |||
187 | static void spike_machine_instance_init(Object *obj) | ||
188 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | ||
189 | index XXXXXXX..XXXXXXX 100644 | ||
190 | --- a/target/riscv/machine.c | ||
191 | +++ b/target/riscv/machine.c | ||
192 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = { | ||
193 | |||
194 | const VMStateDescription vmstate_riscv_cpu = { | ||
195 | .name = "cpu", | ||
196 | - .version_id = 5, | ||
197 | - .minimum_version_id = 5, | ||
198 | + .version_id = 6, | ||
199 | + .minimum_version_id = 6, | ||
200 | .post_load = riscv_cpu_post_load, | ||
201 | .fields = (VMStateField[]) { | ||
202 | VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), | ||
203 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
204 | VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS), | ||
205 | VMSTATE_UINTTL(env.sscratch, RISCVCPU), | ||
206 | VMSTATE_UINTTL(env.mscratch, RISCVCPU), | ||
207 | - VMSTATE_UINT64(env.mfromhost, RISCVCPU), | ||
208 | - VMSTATE_UINT64(env.mtohost, RISCVCPU), | ||
209 | VMSTATE_UINT64(env.stimecmp, RISCVCPU), | ||
210 | |||
211 | VMSTATE_END_OF_LIST() | ||
212 | -- | ||
213 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | There are forward declarations for 'vmstate_htif' and 'htif_io_ops' | ||
4 | in riscv_htif.h however there are no definitions in the C codes. | ||
5 | |||
6 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
7 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <20221229091828.1945072-7-bmeng@tinylab.org> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | include/hw/char/riscv_htif.h | 3 --- | ||
13 | 1 file changed, 3 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/char/riscv_htif.h | ||
18 | +++ b/include/hw/char/riscv_htif.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct HTIFState { | ||
20 | uint64_t pending_read; | ||
21 | } HTIFState; | ||
22 | |||
23 | -extern const VMStateDescription vmstate_htif; | ||
24 | -extern const MemoryRegionOps htif_io_ops; | ||
25 | - | ||
26 | /* HTIF symbol callback */ | ||
27 | void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, | ||
28 | uint64_t st_size); | ||
29 | -- | ||
30 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | At present the HTIF proxy syscall is unsupported. On RV32, only | ||
4 | device 0 is supported so there is no console device for RV32. | ||
5 | The only way to implement console funtionality on RV32 is to | ||
6 | support the SYS_WRITE syscall. | ||
7 | |||
8 | With this commit, the Spike machine is able to boot the 32-bit | ||
9 | OpenSBI generic image. | ||
10 | |||
11 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
12 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | Message-Id: <20221229091828.1945072-8-bmeng@tinylab.org> | ||
15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | --- | ||
17 | hw/char/riscv_htif.c | 17 ++++++++++++++++- | ||
18 | 1 file changed, 16 insertions(+), 1 deletion(-) | ||
19 | |||
20 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/char/riscv_htif.c | ||
23 | +++ b/hw/char/riscv_htif.c | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #define HTIF_CONSOLE_CMD_GETC 0 | ||
26 | #define HTIF_CONSOLE_CMD_PUTC 1 | ||
27 | |||
28 | +/* PK system call number */ | ||
29 | +#define PK_SYS_WRITE 64 | ||
30 | + | ||
31 | static uint64_t fromhost_addr, tohost_addr; | ||
32 | static int address_symbol_set; | ||
33 | |||
34 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) | ||
35 | int exit_code = payload >> 1; | ||
36 | exit(exit_code); | ||
37 | } else { | ||
38 | - qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n"); | ||
39 | + uint64_t syscall[8]; | ||
40 | + cpu_physical_memory_read(payload, syscall, sizeof(syscall)); | ||
41 | + if (syscall[0] == PK_SYS_WRITE && | ||
42 | + syscall[1] == HTIF_DEV_CONSOLE && | ||
43 | + syscall[3] == HTIF_CONSOLE_CMD_PUTC) { | ||
44 | + uint8_t ch; | ||
45 | + cpu_physical_memory_read(syscall[2], &ch, 1); | ||
46 | + qemu_chr_fe_write(&s->chr, &ch, 1); | ||
47 | + resp = 0x100 | (uint8_t)payload; | ||
48 | + } else { | ||
49 | + qemu_log_mask(LOG_UNIMP, | ||
50 | + "pk syscall proxy not supported\n"); | ||
51 | + } | ||
52 | } | ||
53 | } else { | ||
54 | qemu_log("HTIF device %d: unknown command\n", device); | ||
55 | -- | ||
56 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | Spike machine now supports OpenSBI plain binary bios image, so the | ||
4 | comments are no longer valid. | ||
5 | |||
6 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
7 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <20221229091828.1945072-9-bmeng@tinylab.org> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | hw/riscv/spike.c | 5 ----- | ||
13 | 1 file changed, 5 deletions(-) | ||
14 | |||
15 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/riscv/spike.c | ||
18 | +++ b/hw/riscv/spike.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
20 | memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, | ||
21 | mask_rom); | ||
22 | |||
23 | - /* | ||
24 | - * Not like other RISC-V machines that use plain binary bios images, | ||
25 | - * keeping ELF files here was intentional because BIN files don't work | ||
26 | - * for the Spike machine as HTIF emulation depends on ELF parsing. | ||
27 | - */ | ||
28 | if (riscv_is_32bit(&s->soc[0])) { | ||
29 | firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
30 | RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, | ||
31 | -- | ||
32 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | The only caller is riscv_find_and_load_firmware(), which is in the same | ||
4 | file. | ||
5 | |||
6 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
10 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
11 | Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com> | ||
12 | Message-Id: <20221229091828.1945072-10-bmeng@tinylab.org> | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | include/hw/riscv/boot.h | 1 - | ||
16 | hw/riscv/boot.c | 44 ++++++++++++++++++++--------------------- | ||
17 | 2 files changed, 22 insertions(+), 23 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/riscv/boot.h | ||
22 | +++ b/include/hw/riscv/boot.h | ||
23 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
24 | const char *default_machine_firmware, | ||
25 | hwaddr firmware_load_addr, | ||
26 | symbol_fn_t sym_cb); | ||
27 | -char *riscv_find_firmware(const char *firmware_filename); | ||
28 | target_ulong riscv_load_firmware(const char *firmware_filename, | ||
29 | hwaddr firmware_load_addr, | ||
30 | symbol_fn_t sym_cb); | ||
31 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/riscv/boot.c | ||
34 | +++ b/hw/riscv/boot.c | ||
35 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, | ||
36 | } | ||
37 | } | ||
38 | |||
39 | +static char *riscv_find_firmware(const char *firmware_filename) | ||
40 | +{ | ||
41 | + char *filename; | ||
42 | + | ||
43 | + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); | ||
44 | + if (filename == NULL) { | ||
45 | + if (!qtest_enabled()) { | ||
46 | + /* | ||
47 | + * We only ship OpenSBI binary bios images in the QEMU source. | ||
48 | + * For machines that use images other than the default bios, | ||
49 | + * running QEMU test will complain hence let's suppress the error | ||
50 | + * report for QEMU testing. | ||
51 | + */ | ||
52 | + error_report("Unable to load the RISC-V firmware \"%s\"", | ||
53 | + firmware_filename); | ||
54 | + exit(1); | ||
55 | + } | ||
56 | + } | ||
57 | + | ||
58 | + return filename; | ||
59 | +} | ||
60 | + | ||
61 | target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
62 | const char *default_machine_firmware, | ||
63 | hwaddr firmware_load_addr, | ||
64 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
65 | return firmware_end_addr; | ||
66 | } | ||
67 | |||
68 | -char *riscv_find_firmware(const char *firmware_filename) | ||
69 | -{ | ||
70 | - char *filename; | ||
71 | - | ||
72 | - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); | ||
73 | - if (filename == NULL) { | ||
74 | - if (!qtest_enabled()) { | ||
75 | - /* | ||
76 | - * We only ship OpenSBI binary bios images in the QEMU source. | ||
77 | - * For machines that use images other than the default bios, | ||
78 | - * running QEMU test will complain hence let's suppress the error | ||
79 | - * report for QEMU testing. | ||
80 | - */ | ||
81 | - error_report("Unable to load the RISC-V firmware \"%s\"", | ||
82 | - firmware_filename); | ||
83 | - exit(1); | ||
84 | - } | ||
85 | - } | ||
86 | - | ||
87 | - return filename; | ||
88 | -} | ||
89 | - | ||
90 | target_ulong riscv_load_firmware(const char *firmware_filename, | ||
91 | hwaddr firmware_load_addr, | ||
92 | symbol_fn_t sym_cb) | ||
93 | -- | ||
94 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | Some boards are duplicating the 'riscv_find_and_load_firmware' call | ||
4 | because the 32 and 64 bits images have different names. Create | ||
5 | a function to handle this detail instead of hardcoding it in the boards. | ||
6 | |||
7 | Ideally we would bake this logic inside riscv_find_and_load_firmware(), | ||
8 | or even create a riscv_load_default_firmware(), but at this moment we | ||
9 | cannot infer whether the machine is running 32 or 64 bits without | ||
10 | accessing RISCVHartArrayState, which in turn can't be accessed via the | ||
11 | common code from boot.c. In the end we would exchange 'firmware_name' | ||
12 | for a flag with riscv_is_32bit(), which isn't much better than what we | ||
13 | already have today. | ||
14 | |||
15 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
16 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
18 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
19 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
20 | Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com> | ||
21 | Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org> | ||
22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
23 | --- | ||
24 | include/hw/riscv/boot.h | 1 + | ||
25 | hw/riscv/boot.c | 9 +++++++++ | ||
26 | hw/riscv/sifive_u.c | 11 ++++------- | ||
27 | hw/riscv/spike.c | 14 +++++--------- | ||
28 | hw/riscv/virt.c | 10 +++------- | ||
29 | 5 files changed, 22 insertions(+), 23 deletions(-) | ||
30 | |||
31 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/include/hw/riscv/boot.h | ||
34 | +++ b/include/hw/riscv/boot.h | ||
35 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
36 | const char *default_machine_firmware, | ||
37 | hwaddr firmware_load_addr, | ||
38 | symbol_fn_t sym_cb); | ||
39 | +const char *riscv_default_firmware_name(RISCVHartArrayState *harts); | ||
40 | target_ulong riscv_load_firmware(const char *firmware_filename, | ||
41 | hwaddr firmware_load_addr, | ||
42 | symbol_fn_t sym_cb); | ||
43 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/riscv/boot.c | ||
46 | +++ b/hw/riscv/boot.c | ||
47 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, | ||
48 | } | ||
49 | } | ||
50 | |||
51 | +const char *riscv_default_firmware_name(RISCVHartArrayState *harts) | ||
52 | +{ | ||
53 | + if (riscv_is_32bit(harts)) { | ||
54 | + return RISCV32_BIOS_BIN; | ||
55 | + } | ||
56 | + | ||
57 | + return RISCV64_BIOS_BIN; | ||
58 | +} | ||
59 | + | ||
60 | static char *riscv_find_firmware(const char *firmware_filename) | ||
61 | { | ||
62 | char *filename; | ||
63 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/riscv/sifive_u.c | ||
66 | +++ b/hw/riscv/sifive_u.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
68 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); | ||
69 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; | ||
70 | target_ulong firmware_end_addr, kernel_start_addr; | ||
71 | + const char *firmware_name; | ||
72 | uint32_t start_addr_hi32 = 0x00000000; | ||
73 | int i; | ||
74 | uint32_t fdt_load_addr; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
76 | break; | ||
77 | } | ||
78 | |||
79 | - if (riscv_is_32bit(&s->soc.u_cpus)) { | ||
80 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
81 | - RISCV32_BIOS_BIN, start_addr, NULL); | ||
82 | - } else { | ||
83 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
84 | - RISCV64_BIOS_BIN, start_addr, NULL); | ||
85 | - } | ||
86 | + firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); | ||
87 | + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | ||
88 | + start_addr, NULL); | ||
89 | |||
90 | if (machine->kernel_filename) { | ||
91 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, | ||
92 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/hw/riscv/spike.c | ||
95 | +++ b/hw/riscv/spike.c | ||
96 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
97 | MemoryRegion *system_memory = get_system_memory(); | ||
98 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | ||
99 | target_ulong firmware_end_addr, kernel_start_addr; | ||
100 | + const char *firmware_name; | ||
101 | uint32_t fdt_load_addr; | ||
102 | uint64_t kernel_entry; | ||
103 | char *soc_name; | ||
104 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
105 | memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, | ||
106 | mask_rom); | ||
107 | |||
108 | - if (riscv_is_32bit(&s->soc[0])) { | ||
109 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
110 | - RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, | ||
111 | - htif_symbol_callback); | ||
112 | - } else { | ||
113 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
114 | - RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, | ||
115 | - htif_symbol_callback); | ||
116 | - } | ||
117 | + firmware_name = riscv_default_firmware_name(&s->soc[0]); | ||
118 | + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | ||
119 | + memmap[SPIKE_DRAM].base, | ||
120 | + htif_symbol_callback); | ||
121 | |||
122 | /* Load kernel */ | ||
123 | if (machine->kernel_filename) { | ||
124 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/hw/riscv/virt.c | ||
127 | +++ b/hw/riscv/virt.c | ||
128 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
129 | MachineState *machine = MACHINE(s); | ||
130 | target_ulong start_addr = memmap[VIRT_DRAM].base; | ||
131 | target_ulong firmware_end_addr, kernel_start_addr; | ||
132 | + const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); | ||
133 | uint32_t fdt_load_addr; | ||
134 | uint64_t kernel_entry; | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
137 | } | ||
138 | } | ||
139 | |||
140 | - if (riscv_is_32bit(&s->soc[0])) { | ||
141 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
142 | - RISCV32_BIOS_BIN, start_addr, NULL); | ||
143 | - } else { | ||
144 | - firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
145 | - RISCV64_BIOS_BIN, start_addr, NULL); | ||
146 | - } | ||
147 | + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | ||
148 | + start_addr, NULL); | ||
149 | |||
150 | /* | ||
151 | * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | ||
152 | -- | ||
153 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | Rename previous riscv_find_firmware() to riscv_find_bios(), and | ||
4 | introduce a new riscv_find_firmware() to implement the first half | ||
5 | part of the work done in riscv_find_and_load_firmware(). | ||
6 | |||
7 | This new API is helpful for machine that wants to know the final | ||
8 | chosen firmware file name but does not want to load it. | ||
9 | |||
10 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
11 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-Id: <20221229091828.1945072-12-bmeng@tinylab.org> | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | --- | ||
16 | include/hw/riscv/boot.h | 2 ++ | ||
17 | hw/riscv/boot.c | 39 +++++++++++++++++++++++++-------------- | ||
18 | 2 files changed, 27 insertions(+), 14 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/riscv/boot.h | ||
23 | +++ b/include/hw/riscv/boot.h | ||
24 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
25 | hwaddr firmware_load_addr, | ||
26 | symbol_fn_t sym_cb); | ||
27 | const char *riscv_default_firmware_name(RISCVHartArrayState *harts); | ||
28 | +char *riscv_find_firmware(const char *firmware_filename, | ||
29 | + const char *default_machine_firmware); | ||
30 | target_ulong riscv_load_firmware(const char *firmware_filename, | ||
31 | hwaddr firmware_load_addr, | ||
32 | symbol_fn_t sym_cb); | ||
33 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/riscv/boot.c | ||
36 | +++ b/hw/riscv/boot.c | ||
37 | @@ -XXX,XX +XXX,XX @@ const char *riscv_default_firmware_name(RISCVHartArrayState *harts) | ||
38 | return RISCV64_BIOS_BIN; | ||
39 | } | ||
40 | |||
41 | -static char *riscv_find_firmware(const char *firmware_filename) | ||
42 | +static char *riscv_find_bios(const char *bios_filename) | ||
43 | { | ||
44 | char *filename; | ||
45 | |||
46 | - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); | ||
47 | + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); | ||
48 | if (filename == NULL) { | ||
49 | if (!qtest_enabled()) { | ||
50 | /* | ||
51 | @@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename) | ||
52 | * running QEMU test will complain hence let's suppress the error | ||
53 | * report for QEMU testing. | ||
54 | */ | ||
55 | - error_report("Unable to load the RISC-V firmware \"%s\"", | ||
56 | - firmware_filename); | ||
57 | + error_report("Unable to find the RISC-V BIOS \"%s\"", | ||
58 | + bios_filename); | ||
59 | exit(1); | ||
60 | } | ||
61 | } | ||
62 | @@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename) | ||
63 | return filename; | ||
64 | } | ||
65 | |||
66 | -target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
67 | - const char *default_machine_firmware, | ||
68 | - hwaddr firmware_load_addr, | ||
69 | - symbol_fn_t sym_cb) | ||
70 | +char *riscv_find_firmware(const char *firmware_filename, | ||
71 | + const char *default_machine_firmware) | ||
72 | { | ||
73 | - char *firmware_filename = NULL; | ||
74 | - target_ulong firmware_end_addr = firmware_load_addr; | ||
75 | + char *filename = NULL; | ||
76 | |||
77 | - if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { | ||
78 | + if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { | ||
79 | /* | ||
80 | * The user didn't specify -bios, or has specified "-bios default". | ||
81 | * That means we are going to load the OpenSBI binary included in | ||
82 | * the QEMU source. | ||
83 | */ | ||
84 | - firmware_filename = riscv_find_firmware(default_machine_firmware); | ||
85 | - } else if (strcmp(machine->firmware, "none")) { | ||
86 | - firmware_filename = riscv_find_firmware(machine->firmware); | ||
87 | + filename = riscv_find_bios(default_machine_firmware); | ||
88 | + } else if (strcmp(firmware_filename, "none")) { | ||
89 | + filename = riscv_find_bios(firmware_filename); | ||
90 | } | ||
91 | |||
92 | + return filename; | ||
93 | +} | ||
94 | + | ||
95 | +target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
96 | + const char *default_machine_firmware, | ||
97 | + hwaddr firmware_load_addr, | ||
98 | + symbol_fn_t sym_cb) | ||
99 | +{ | ||
100 | + char *firmware_filename; | ||
101 | + target_ulong firmware_end_addr = firmware_load_addr; | ||
102 | + | ||
103 | + firmware_filename = riscv_find_firmware(machine->firmware, | ||
104 | + default_machine_firmware); | ||
105 | + | ||
106 | if (firmware_filename) { | ||
107 | /* If not "none" load the firmware */ | ||
108 | firmware_end_addr = riscv_load_firmware(firmware_filename, | ||
109 | -- | ||
110 | 2.39.0 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Bin Meng <bmeng@tinylab.org> |
---|---|---|---|
2 | 2 | ||
3 | Configuring a drive with "if=none" is meant for creation of a backend | 3 | At present create_fdt() calls htif_uses_elf_symbols() to determine |
4 | only, it should not get automatically assigned to a device frontend. | 4 | whether to insert a <reg> property for the HTIF. This unfortunately |
5 | Use "if=pflash" for the One-Time-Programmable device instead (like | 5 | creates a hidden dependency to riscv_load_{firmware,kernel} that |
6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | 6 | create_fdt() must be called after the ELF {firmware,kernel} image |
7 | 7 | has been loaded. | |
8 | Since the old way of configuring the device has already been published | 8 | |
9 | with the previous QEMU versions, we cannot remove this immediately, but | 9 | Decouple such dependency be adding a new parameter to create_fdt(), |
10 | have to deprecate it and support it for at least two more releases. | 10 | whether custom HTIF base address is used. The flag will be set if |
11 | 11 | non ELF {firmware,kernel} image is given by user. | |
12 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 12 | |
13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 13 | Signed-off-by: Bin Meng <bmeng@tinylab.org> |
14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 14 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Message-Id: <20221229091828.1945072-13-bmeng@tinylab.org> |
16 | Message-id: 20211119102549.217755-1-thuth@redhat.com | ||
17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
18 | --- | 17 | --- |
19 | docs/about/deprecated.rst | 6 ++++++ | 18 | include/hw/char/riscv_htif.h | 5 +-- |
20 | hw/misc/sifive_u_otp.c | 9 ++++++++- | 19 | hw/char/riscv_htif.c | 17 +++++----- |
21 | 2 files changed, 14 insertions(+), 1 deletion(-) | 20 | hw/riscv/spike.c | 61 ++++++++++++++++++++++++++++++------ |
22 | 21 | 3 files changed, 59 insertions(+), 24 deletions(-) | |
23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst | 22 | |
23 | diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/docs/about/deprecated.rst | 25 | --- a/include/hw/char/riscv_htif.h |
26 | +++ b/docs/about/deprecated.rst | 26 | +++ b/include/hw/char/riscv_htif.h |
27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. | 27 | @@ -XXX,XX +XXX,XX @@ typedef struct HTIFState { |
28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` | 28 | void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, |
29 | form is preferred. | 29 | uint64_t st_size); |
30 | 30 | ||
31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) | 31 | -/* Check if HTIF uses ELF symbols */ |
32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | 32 | -bool htif_uses_elf_symbols(void); |
33 | + | 33 | - |
34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u | 34 | /* legacy pre qom */ |
35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. | 35 | HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, |
36 | + | 36 | - uint64_t nonelf_base); |
37 | 37 | + uint64_t nonelf_base, bool custom_base); | |
38 | QEMU Machine Protocol (QMP) commands | 38 | |
39 | ------------------------------------ | 39 | #endif |
40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 40 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c |
41 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/hw/misc/sifive_u_otp.c | 42 | --- a/hw/char/riscv_htif.c |
43 | +++ b/hw/misc/sifive_u_otp.c | 43 | +++ b/hw/char/riscv_htif.c |
44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 44 | @@ -XXX,XX +XXX,XX @@ |
45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); | 45 | #define PK_SYS_WRITE 64 |
46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); | 46 | |
47 | 47 | static uint64_t fromhost_addr, tohost_addr; | |
48 | - dinfo = drive_get_next(IF_NONE); | 48 | -static int address_symbol_set; |
49 | + dinfo = drive_get_next(IF_PFLASH); | 49 | |
50 | + if (!dinfo) { | 50 | void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, |
51 | + dinfo = drive_get_next(IF_NONE); | 51 | uint64_t st_size) |
52 | + if (dinfo) { | 52 | { |
53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " | 53 | if (strcmp("fromhost", st_name) == 0) { |
54 | + "use \"-drive if=pflash\" instead."); | 54 | - address_symbol_set |= 1; |
55 | fromhost_addr = st_value; | ||
56 | if (st_size != 8) { | ||
57 | error_report("HTIF fromhost must be 8 bytes"); | ||
58 | exit(1); | ||
59 | } | ||
60 | } else if (strcmp("tohost", st_name) == 0) { | ||
61 | - address_symbol_set |= 2; | ||
62 | tohost_addr = st_value; | ||
63 | if (st_size != 8) { | ||
64 | error_report("HTIF tohost must be 8 bytes"); | ||
65 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = { | ||
66 | .write = htif_mm_write, | ||
67 | }; | ||
68 | |||
69 | -bool htif_uses_elf_symbols(void) | ||
70 | -{ | ||
71 | - return (address_symbol_set == 3) ? true : false; | ||
72 | -} | ||
73 | - | ||
74 | HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, | ||
75 | - uint64_t nonelf_base) | ||
76 | + uint64_t nonelf_base, bool custom_base) | ||
77 | { | ||
78 | uint64_t base, size, tohost_offset, fromhost_offset; | ||
79 | |||
80 | - if (!htif_uses_elf_symbols()) { | ||
81 | + if (custom_base) { | ||
82 | fromhost_addr = nonelf_base; | ||
83 | tohost_addr = nonelf_base + 8; | ||
84 | + } else { | ||
85 | + if (!fromhost_addr || !tohost_addr) { | ||
86 | + error_report("Invalid HTIF fromhost or tohost address"); | ||
87 | + exit(1); | ||
88 | + } | ||
89 | } | ||
90 | |||
91 | base = MIN(tohost_addr, fromhost_addr); | ||
92 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/hw/riscv/spike.c | ||
95 | +++ b/hw/riscv/spike.c | ||
96 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = { | ||
97 | }; | ||
98 | |||
99 | static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
100 | - uint64_t mem_size, const char *cmdline, bool is_32_bit) | ||
101 | + uint64_t mem_size, const char *cmdline, | ||
102 | + bool is_32_bit, bool htif_custom_base) | ||
103 | { | ||
104 | void *fdt; | ||
105 | uint64_t addr, size; | ||
106 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
107 | |||
108 | qemu_fdt_add_subnode(fdt, "/htif"); | ||
109 | qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); | ||
110 | - if (!htif_uses_elf_symbols()) { | ||
111 | + if (htif_custom_base) { | ||
112 | qemu_fdt_setprop_cells(fdt, "/htif", "reg", | ||
113 | 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); | ||
114 | } | ||
115 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
116 | } | ||
117 | } | ||
118 | |||
119 | +static bool spike_test_elf_image(char *filename) | ||
120 | +{ | ||
121 | + Error *err = NULL; | ||
122 | + | ||
123 | + load_elf_hdr(filename, NULL, NULL, &err); | ||
124 | + if (err) { | ||
125 | + error_free(err); | ||
126 | + return false; | ||
127 | + } else { | ||
128 | + return true; | ||
129 | + } | ||
130 | +} | ||
131 | + | ||
132 | static void spike_board_init(MachineState *machine) | ||
133 | { | ||
134 | const MemMapEntry *memmap = spike_memmap; | ||
135 | SpikeState *s = SPIKE_MACHINE(machine); | ||
136 | MemoryRegion *system_memory = get_system_memory(); | ||
137 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | ||
138 | - target_ulong firmware_end_addr, kernel_start_addr; | ||
139 | - const char *firmware_name; | ||
140 | + target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; | ||
141 | + target_ulong kernel_start_addr; | ||
142 | + char *firmware_name; | ||
143 | uint32_t fdt_load_addr; | ||
144 | uint64_t kernel_entry; | ||
145 | char *soc_name; | ||
146 | int i, base_hartid, hart_count; | ||
147 | + bool htif_custom_base = false; | ||
148 | |||
149 | /* Check socket count limit */ | ||
150 | if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { | ||
151 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
152 | memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, | ||
153 | mask_rom); | ||
154 | |||
155 | - firmware_name = riscv_default_firmware_name(&s->soc[0]); | ||
156 | - firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | ||
157 | - memmap[SPIKE_DRAM].base, | ||
158 | - htif_symbol_callback); | ||
159 | + /* Find firmware */ | ||
160 | + firmware_name = riscv_find_firmware(machine->firmware, | ||
161 | + riscv_default_firmware_name(&s->soc[0])); | ||
162 | + | ||
163 | + /* | ||
164 | + * Test the given firmware or kernel file to see if it is an ELF image. | ||
165 | + * If it is an ELF, we assume it contains the symbols required for | ||
166 | + * the HTIF console, otherwise we fall back to use the custom base | ||
167 | + * passed from device tree for the HTIF console. | ||
168 | + */ | ||
169 | + if (!firmware_name && !machine->kernel_filename) { | ||
170 | + htif_custom_base = true; | ||
171 | + } else { | ||
172 | + if (firmware_name) { | ||
173 | + htif_custom_base = !spike_test_elf_image(firmware_name); | ||
174 | + } | ||
175 | + if (!htif_custom_base && machine->kernel_filename) { | ||
176 | + htif_custom_base = !spike_test_elf_image(machine->kernel_filename); | ||
55 | + } | 177 | + } |
56 | + } | 178 | + } |
57 | if (dinfo) { | 179 | + |
58 | int ret; | 180 | + /* Load firmware */ |
59 | uint64_t perm; | 181 | + if (firmware_name) { |
182 | + firmware_end_addr = riscv_load_firmware(firmware_name, | ||
183 | + memmap[SPIKE_DRAM].base, | ||
184 | + htif_symbol_callback); | ||
185 | + g_free(firmware_name); | ||
186 | + } | ||
187 | |||
188 | /* Load kernel */ | ||
189 | if (machine->kernel_filename) { | ||
190 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
191 | |||
192 | /* Create device tree */ | ||
193 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
194 | - riscv_is_32bit(&s->soc[0])); | ||
195 | + riscv_is_32bit(&s->soc[0]), htif_custom_base); | ||
196 | |||
197 | /* Load initrd */ | ||
198 | if (machine->kernel_filename && machine->initrd_filename) { | ||
199 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
200 | fdt_load_addr); | ||
201 | |||
202 | /* initialize HTIF using symbols found in load_kernel */ | ||
203 | - htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); | ||
204 | + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, | ||
205 | + htif_custom_base); | ||
206 | } | ||
207 | |||
208 | static void spike_machine_instance_init(Object *obj) | ||
60 | -- | 209 | -- |
61 | 2.31.1 | 210 | 2.39.0 |
62 | |||
63 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Dongxue Zhang <elta.era@gmail.com> | ||
1 | 2 | ||
3 | The elen check should be cpu->cfg.elen in range [8, 64]. | ||
4 | |||
5 | Signed-off-by: Dongxue Zhang <elta.era@gmail.com> | ||
6 | Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com> | ||
7 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <167236721596.15277.2653405273227256289-0@git.sr.ht> | ||
10 | [ Changes by AF: | ||
11 | - Tidy up commit message | ||
12 | ] | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | target/riscv/cpu.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/cpu.c | ||
21 | +++ b/target/riscv/cpu.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
23 | "Vector extension ELEN must be power of 2"); | ||
24 | return; | ||
25 | } | ||
26 | - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { | ||
27 | + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { | ||
28 | error_setg(errp, | ||
29 | "Vector extension implementation only supports ELEN " | ||
30 | "in the range [8, 64]"); | ||
31 | -- | ||
32 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | This test is used to do a quick sanity check to ensure that we're able | ||
4 | to run the existing QEMU FW image. | ||
5 | |||
6 | 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and | ||
7 | 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | | ||
8 | RISCV32_BIOS_BIN firmware with minimal options. | ||
9 | |||
10 | The riscv32 'spike' machine isn't bootable at this moment, requiring an | ||
11 | OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that | ||
12 | or add a 'skip' test to remind us about it. To work as a reminder that | ||
13 | we have a riscv32 'spike' test that should be enabled as soon as OpenSBI | ||
14 | QEMU rom receives the fix, we're adding a 'skip' test: | ||
15 | |||
16 | (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: | ||
17 | SKIP: requires OpenSBI fix to work | ||
18 | |||
19 | [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ | ||
20 | [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 | ||
21 | |||
22 | Cc: Cleber Rosa <crosa@redhat.com> | ||
23 | Cc: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
24 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
25 | Tested-by: Bin Meng <bmeng@tinylab.org> | ||
26 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
27 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
28 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
29 | Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com> | ||
30 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
31 | --- | ||
32 | tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ | ||
33 | 1 file changed, 65 insertions(+) | ||
34 | create mode 100644 tests/avocado/riscv_opensbi.py | ||
35 | |||
36 | diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py | ||
37 | new file mode 100644 | ||
38 | index XXXXXXX..XXXXXXX | ||
39 | --- /dev/null | ||
40 | +++ b/tests/avocado/riscv_opensbi.py | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | +# OpenSBI boot test for RISC-V machines | ||
43 | +# | ||
44 | +# Copyright (c) 2022, Ventana Micro | ||
45 | +# | ||
46 | +# This work is licensed under the terms of the GNU GPL, version 2 or | ||
47 | +# later. See the COPYING file in the top-level directory. | ||
48 | + | ||
49 | +from avocado_qemu import QemuSystemTest | ||
50 | +from avocado import skip | ||
51 | +from avocado_qemu import wait_for_console_pattern | ||
52 | + | ||
53 | +class RiscvOpenSBI(QemuSystemTest): | ||
54 | + """ | ||
55 | + :avocado: tags=accel:tcg | ||
56 | + """ | ||
57 | + timeout = 5 | ||
58 | + | ||
59 | + def boot_opensbi(self): | ||
60 | + self.vm.set_console() | ||
61 | + self.vm.launch() | ||
62 | + wait_for_console_pattern(self, 'Platform Name') | ||
63 | + wait_for_console_pattern(self, 'Boot HART MEDELEG') | ||
64 | + | ||
65 | + @skip("requires OpenSBI fix to work") | ||
66 | + def test_riscv32_spike(self): | ||
67 | + """ | ||
68 | + :avocado: tags=arch:riscv32 | ||
69 | + :avocado: tags=machine:spike | ||
70 | + """ | ||
71 | + self.boot_opensbi() | ||
72 | + | ||
73 | + def test_riscv64_spike(self): | ||
74 | + """ | ||
75 | + :avocado: tags=arch:riscv64 | ||
76 | + :avocado: tags=machine:spike | ||
77 | + """ | ||
78 | + self.boot_opensbi() | ||
79 | + | ||
80 | + def test_riscv32_sifive_u(self): | ||
81 | + """ | ||
82 | + :avocado: tags=arch:riscv32 | ||
83 | + :avocado: tags=machine:sifive_u | ||
84 | + """ | ||
85 | + self.boot_opensbi() | ||
86 | + | ||
87 | + def test_riscv64_sifive_u(self): | ||
88 | + """ | ||
89 | + :avocado: tags=arch:riscv64 | ||
90 | + :avocado: tags=machine:sifive_u | ||
91 | + """ | ||
92 | + self.boot_opensbi() | ||
93 | + | ||
94 | + def test_riscv32_virt(self): | ||
95 | + """ | ||
96 | + :avocado: tags=arch:riscv32 | ||
97 | + :avocado: tags=machine:virt | ||
98 | + """ | ||
99 | + self.boot_opensbi() | ||
100 | + | ||
101 | + def test_riscv64_virt(self): | ||
102 | + """ | ||
103 | + :avocado: tags=arch:riscv64 | ||
104 | + :avocado: tags=machine:virt | ||
105 | + """ | ||
106 | + self.boot_opensbi() | ||
107 | -- | ||
108 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | The MachineState object provides a 'fdt' pointer that is already being | ||
4 | used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP | ||
5 | command. | ||
6 | |||
7 | Remove the 'fdt' pointer from SpikeState and use MachineState::fdt | ||
8 | instead. | ||
9 | |||
10 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
14 | Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com> | ||
15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | --- | ||
17 | include/hw/riscv/spike.h | 2 -- | ||
18 | hw/riscv/spike.c | 12 +++++------- | ||
19 | 2 files changed, 5 insertions(+), 9 deletions(-) | ||
20 | |||
21 | diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/include/hw/riscv/spike.h | ||
24 | +++ b/include/hw/riscv/spike.h | ||
25 | @@ -XXX,XX +XXX,XX @@ struct SpikeState { | ||
26 | |||
27 | /*< public >*/ | ||
28 | RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; | ||
29 | - void *fdt; | ||
30 | - int fdt_size; | ||
31 | }; | ||
32 | |||
33 | enum { | ||
34 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/riscv/spike.c | ||
37 | +++ b/hw/riscv/spike.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
39 | bool is_32_bit, bool htif_custom_base) | ||
40 | { | ||
41 | void *fdt; | ||
42 | + int fdt_size; | ||
43 | uint64_t addr, size; | ||
44 | unsigned long clint_addr; | ||
45 | int cpu, socket; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
47 | "sifive,clint0", "riscv,clint0" | ||
48 | }; | ||
49 | |||
50 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
51 | + fdt = mc->fdt = create_device_tree(&fdt_size); | ||
52 | if (!fdt) { | ||
53 | error_report("create_device_tree() failed"); | ||
54 | exit(1); | ||
55 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
56 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
57 | machine->ram_size, kernel_entry, | ||
58 | &start); | ||
59 | - qemu_fdt_setprop_cell(s->fdt, "/chosen", | ||
60 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
61 | "linux,initrd-start", start); | ||
62 | - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", | ||
63 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
64 | end); | ||
65 | } | ||
66 | |||
67 | /* Compute the fdt load address in dram */ | ||
68 | fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, | ||
69 | - machine->ram_size, s->fdt); | ||
70 | - | ||
71 | - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ | ||
72 | - machine->fdt = s->fdt; | ||
73 | + machine->ram_size, machine->fdt); | ||
74 | |||
75 | /* load the reset vector */ | ||
76 | riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, | ||
77 | -- | ||
78 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | The MachineState object provides a 'fdt' pointer that is already being | ||
4 | used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP | ||
5 | command. | ||
6 | |||
7 | Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt | ||
8 | instead. | ||
9 | |||
10 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
11 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
15 | Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | --- | ||
18 | include/hw/riscv/sifive_u.h | 3 --- | ||
19 | hw/riscv/sifive_u.c | 15 ++++++--------- | ||
20 | 2 files changed, 6 insertions(+), 12 deletions(-) | ||
21 | |||
22 | diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/include/hw/riscv/sifive_u.h | ||
25 | +++ b/include/hw/riscv/sifive_u.h | ||
26 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUState { | ||
27 | /*< public >*/ | ||
28 | SiFiveUSoCState soc; | ||
29 | |||
30 | - void *fdt; | ||
31 | - int fdt_size; | ||
32 | - | ||
33 | bool start_in_flash; | ||
34 | uint32_t msel; | ||
35 | uint32_t serial; | ||
36 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/riscv/sifive_u.c | ||
39 | +++ b/hw/riscv/sifive_u.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
41 | { | ||
42 | MachineState *ms = MACHINE(qdev_get_machine()); | ||
43 | void *fdt; | ||
44 | - int cpu; | ||
45 | + int cpu, fdt_size; | ||
46 | uint32_t *cells; | ||
47 | char *nodename; | ||
48 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; | ||
49 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
50 | }; | ||
51 | |||
52 | if (ms->dtb) { | ||
53 | - fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); | ||
54 | + fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); | ||
55 | if (!fdt) { | ||
56 | error_report("load_device_tree() failed"); | ||
57 | exit(1); | ||
58 | } | ||
59 | goto update_bootargs; | ||
60 | } else { | ||
61 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
62 | + fdt = ms->fdt = create_device_tree(&fdt_size); | ||
63 | if (!fdt) { | ||
64 | error_report("create_device_tree() failed"); | ||
65 | exit(1); | ||
66 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
67 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
68 | machine->ram_size, kernel_entry, | ||
69 | &start); | ||
70 | - qemu_fdt_setprop_cell(s->fdt, "/chosen", | ||
71 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
72 | "linux,initrd-start", start); | ||
73 | - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", | ||
74 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
75 | end); | ||
76 | } | ||
77 | } else { | ||
78 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
79 | |||
80 | /* Compute the fdt load address in dram */ | ||
81 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, | ||
82 | - machine->ram_size, s->fdt); | ||
83 | + machine->ram_size, machine->fdt); | ||
84 | if (!riscv_is_32bit(&s->soc.u_cpus)) { | ||
85 | start_addr_hi32 = (uint64_t)start_addr >> 32; | ||
86 | } | ||
87 | |||
88 | - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ | ||
89 | - machine->fdt = s->fdt; | ||
90 | - | ||
91 | /* reset vector */ | ||
92 | uint32_t reset_vec[12] = { | ||
93 | s->msel, /* MSEL pin state */ | ||
94 | -- | ||
95 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works | ||
4 | under the assumption that a 'filename' parameter is always not NULL. | ||
5 | |||
6 | This is currently the case since all callers of these functions are | ||
7 | checking for NULL before calling them. Add an g_assert() to make sure | ||
8 | that a NULL value in these cases are to be considered a bug. | ||
9 | |||
10 | Suggested-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
13 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | --- | ||
18 | hw/riscv/boot.c | 6 ++++++ | ||
19 | 1 file changed, 6 insertions(+) | ||
20 | |||
21 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/riscv/boot.c | ||
24 | +++ b/hw/riscv/boot.c | ||
25 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename, | ||
26 | uint64_t firmware_entry, firmware_end; | ||
27 | ssize_t firmware_size; | ||
28 | |||
29 | + g_assert(firmware_filename != NULL); | ||
30 | + | ||
31 | if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, | ||
32 | &firmware_entry, NULL, &firmware_end, NULL, | ||
33 | 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { | ||
34 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename, | ||
35 | { | ||
36 | uint64_t kernel_load_base, kernel_entry; | ||
37 | |||
38 | + g_assert(kernel_filename != NULL); | ||
39 | + | ||
40 | /* | ||
41 | * NB: Use low address not ELF entry point to ensure that the fw_dynamic | ||
42 | * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL | ||
43 | @@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
44 | { | ||
45 | ssize_t size; | ||
46 | |||
47 | + g_assert(filename != NULL); | ||
48 | + | ||
49 | /* | ||
50 | * We want to put the initrd far enough into RAM that when the | ||
51 | * kernel is uncompressed it will not clobber the initrd. However | ||
52 | -- | ||
53 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | This will make the code more in line with what the other boards are | ||
4 | doing. We'll also avoid an extra check to machine->kernel_filename since | ||
5 | we already checked that before executing riscv_load_kernel(). | ||
6 | |||
7 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
11 | Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | --- | ||
14 | hw/riscv/spike.c | 31 +++++++++++++++---------------- | ||
15 | 1 file changed, 15 insertions(+), 16 deletions(-) | ||
16 | |||
17 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/riscv/spike.c | ||
20 | +++ b/hw/riscv/spike.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
22 | g_free(firmware_name); | ||
23 | } | ||
24 | |||
25 | + /* Create device tree */ | ||
26 | + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
27 | + riscv_is_32bit(&s->soc[0]), htif_custom_base); | ||
28 | + | ||
29 | /* Load kernel */ | ||
30 | if (machine->kernel_filename) { | ||
31 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
32 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
33 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
34 | kernel_start_addr, | ||
35 | htif_symbol_callback); | ||
36 | + | ||
37 | + if (machine->initrd_filename) { | ||
38 | + hwaddr start; | ||
39 | + hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
40 | + machine->ram_size, kernel_entry, | ||
41 | + &start); | ||
42 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
43 | + "linux,initrd-start", start); | ||
44 | + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
45 | + end); | ||
46 | + } | ||
47 | } else { | ||
48 | /* | ||
49 | * If dynamic firmware is used, it doesn't know where is the next mode | ||
50 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
51 | kernel_entry = 0; | ||
52 | } | ||
53 | |||
54 | - /* Create device tree */ | ||
55 | - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
56 | - riscv_is_32bit(&s->soc[0]), htif_custom_base); | ||
57 | - | ||
58 | - /* Load initrd */ | ||
59 | - if (machine->kernel_filename && machine->initrd_filename) { | ||
60 | - hwaddr start; | ||
61 | - hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
62 | - machine->ram_size, kernel_entry, | ||
63 | - &start); | ||
64 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
65 | - "linux,initrd-start", start); | ||
66 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
67 | - end); | ||
68 | - } | ||
69 | - | ||
70 | /* Compute the fdt load address in dram */ | ||
71 | fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, | ||
72 | machine->ram_size, machine->fdt); | ||
73 | -- | ||
74 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | riscv_load_initrd() returns the initrd end addr while also writing a | ||
4 | 'start' var to mark the addr start. These informations are being used | ||
5 | just to write the initrd FDT node. Every existing caller of | ||
6 | riscv_load_initrd() is writing the FDT in the same manner. | ||
7 | |||
8 | We can simplify things by writing the FDT inside riscv_load_initrd(), | ||
9 | sparing callers from having to manage start/end addrs to write the FDT | ||
10 | themselves. | ||
11 | |||
12 | An 'if (fdt)' check is already inserted at the end of the function | ||
13 | because we'll end up using it later on with other boards that doesn´t | ||
14 | have a FDT. | ||
15 | |||
16 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
17 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
18 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
19 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
20 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
21 | Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com> | ||
22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
23 | --- | ||
24 | include/hw/riscv/boot.h | 4 ++-- | ||
25 | hw/riscv/boot.c | 18 ++++++++++++------ | ||
26 | hw/riscv/microchip_pfsoc.c | 10 ++-------- | ||
27 | hw/riscv/sifive_u.c | 10 ++-------- | ||
28 | hw/riscv/spike.c | 10 ++-------- | ||
29 | hw/riscv/virt.c | 10 ++-------- | ||
30 | 6 files changed, 22 insertions(+), 40 deletions(-) | ||
31 | |||
32 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/hw/riscv/boot.h | ||
35 | +++ b/include/hw/riscv/boot.h | ||
36 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename, | ||
37 | target_ulong riscv_load_kernel(const char *kernel_filename, | ||
38 | target_ulong firmware_end_addr, | ||
39 | symbol_fn_t sym_cb); | ||
40 | -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
41 | - uint64_t kernel_entry, hwaddr *start); | ||
42 | +void riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
43 | + uint64_t kernel_entry, void *fdt); | ||
44 | uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); | ||
45 | void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, | ||
46 | hwaddr saddr, | ||
47 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/riscv/boot.c | ||
50 | +++ b/hw/riscv/boot.c | ||
51 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename, | ||
52 | exit(1); | ||
53 | } | ||
54 | |||
55 | -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
56 | - uint64_t kernel_entry, hwaddr *start) | ||
57 | +void riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
58 | + uint64_t kernel_entry, void *fdt) | ||
59 | { | ||
60 | + hwaddr start, end; | ||
61 | ssize_t size; | ||
62 | |||
63 | g_assert(filename != NULL); | ||
64 | @@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
65 | * halfway into RAM, and for boards with 256MB of RAM or more we put | ||
66 | * the initrd at 128MB. | ||
67 | */ | ||
68 | - *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); | ||
69 | + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); | ||
70 | |||
71 | - size = load_ramdisk(filename, *start, mem_size - *start); | ||
72 | + size = load_ramdisk(filename, start, mem_size - start); | ||
73 | if (size == -1) { | ||
74 | - size = load_image_targphys(filename, *start, mem_size - *start); | ||
75 | + size = load_image_targphys(filename, start, mem_size - start); | ||
76 | if (size == -1) { | ||
77 | error_report("could not load ramdisk '%s'", filename); | ||
78 | exit(1); | ||
79 | } | ||
80 | } | ||
81 | |||
82 | - return *start + size; | ||
83 | + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ | ||
84 | + if (fdt) { | ||
85 | + end = start + size; | ||
86 | + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); | ||
87 | + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); | ||
88 | + } | ||
89 | } | ||
90 | |||
91 | uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) | ||
92 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/hw/riscv/microchip_pfsoc.c | ||
95 | +++ b/hw/riscv/microchip_pfsoc.c | ||
96 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
97 | kernel_start_addr, NULL); | ||
98 | |||
99 | if (machine->initrd_filename) { | ||
100 | - hwaddr start; | ||
101 | - hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
102 | - machine->ram_size, kernel_entry, | ||
103 | - &start); | ||
104 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
105 | - "linux,initrd-start", start); | ||
106 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
107 | - "linux,initrd-end", end); | ||
108 | + riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
109 | + kernel_entry, machine->fdt); | ||
110 | } | ||
111 | |||
112 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
113 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/hw/riscv/sifive_u.c | ||
116 | +++ b/hw/riscv/sifive_u.c | ||
117 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
118 | kernel_start_addr, NULL); | ||
119 | |||
120 | if (machine->initrd_filename) { | ||
121 | - hwaddr start; | ||
122 | - hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
123 | - machine->ram_size, kernel_entry, | ||
124 | - &start); | ||
125 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
126 | - "linux,initrd-start", start); | ||
127 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
128 | - end); | ||
129 | + riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
130 | + kernel_entry, machine->fdt); | ||
131 | } | ||
132 | } else { | ||
133 | /* | ||
134 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/hw/riscv/spike.c | ||
137 | +++ b/hw/riscv/spike.c | ||
138 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
139 | htif_symbol_callback); | ||
140 | |||
141 | if (machine->initrd_filename) { | ||
142 | - hwaddr start; | ||
143 | - hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
144 | - machine->ram_size, kernel_entry, | ||
145 | - &start); | ||
146 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
147 | - "linux,initrd-start", start); | ||
148 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
149 | - end); | ||
150 | + riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
151 | + kernel_entry, machine->fdt); | ||
152 | } | ||
153 | } else { | ||
154 | /* | ||
155 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/hw/riscv/virt.c | ||
158 | +++ b/hw/riscv/virt.c | ||
159 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
160 | kernel_start_addr, NULL); | ||
161 | |||
162 | if (machine->initrd_filename) { | ||
163 | - hwaddr start; | ||
164 | - hwaddr end = riscv_load_initrd(machine->initrd_filename, | ||
165 | - machine->ram_size, kernel_entry, | ||
166 | - &start); | ||
167 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", | ||
168 | - "linux,initrd-start", start); | ||
169 | - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | ||
170 | - end); | ||
171 | + riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
172 | + kernel_entry, machine->fdt); | ||
173 | } | ||
174 | } else { | ||
175 | /* | ||
176 | -- | ||
177 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | The sifive_u, spike and virt machines are writing the 'bootargs' FDT | ||
4 | node during their respective create_fdt(). | ||
5 | |||
6 | Given that bootargs is written only when '-append' is used, and this | ||
7 | option is only allowed with the '-kernel' option, which in turn is | ||
8 | already being check before executing riscv_load_kernel(), write | ||
9 | 'bootargs' in the same code path as riscv_load_kernel(). | ||
10 | |||
11 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
12 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
13 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com> | ||
17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
18 | --- | ||
19 | hw/riscv/sifive_u.c | 11 +++++------ | ||
20 | hw/riscv/spike.c | 9 +++++---- | ||
21 | hw/riscv/virt.c | 11 +++++------ | ||
22 | 3 files changed, 15 insertions(+), 16 deletions(-) | ||
23 | |||
24 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/riscv/sifive_u.c | ||
27 | +++ b/hw/riscv/sifive_u.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
29 | error_report("load_device_tree() failed"); | ||
30 | exit(1); | ||
31 | } | ||
32 | - goto update_bootargs; | ||
33 | } else { | ||
34 | fdt = ms->fdt = create_device_tree(&fdt_size); | ||
35 | if (!fdt) { | ||
36 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
37 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | ||
38 | |||
39 | g_free(nodename); | ||
40 | - | ||
41 | -update_bootargs: | ||
42 | - if (cmdline && *cmdline) { | ||
43 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
44 | - } | ||
45 | } | ||
46 | |||
47 | static void sifive_u_machine_reset(void *opaque, int n, int level) | ||
48 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
49 | riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
50 | kernel_entry, machine->fdt); | ||
51 | } | ||
52 | + | ||
53 | + if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
54 | + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", | ||
55 | + machine->kernel_cmdline); | ||
56 | + } | ||
57 | } else { | ||
58 | /* | ||
59 | * If dynamic firmware is used, it doesn't know where is the next mode | ||
60 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/riscv/spike.c | ||
63 | +++ b/hw/riscv/spike.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
65 | |||
66 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
67 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); | ||
68 | - | ||
69 | - if (cmdline && *cmdline) { | ||
70 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
71 | - } | ||
72 | } | ||
73 | |||
74 | static bool spike_test_elf_image(char *filename) | ||
75 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
76 | riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
77 | kernel_entry, machine->fdt); | ||
78 | } | ||
79 | + | ||
80 | + if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
81 | + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", | ||
82 | + machine->kernel_cmdline); | ||
83 | + } | ||
84 | } else { | ||
85 | /* | ||
86 | * If dynamic firmware is used, it doesn't know where is the next mode | ||
87 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/hw/riscv/virt.c | ||
90 | +++ b/hw/riscv/virt.c | ||
91 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | ||
92 | error_report("load_device_tree() failed"); | ||
93 | exit(1); | ||
94 | } | ||
95 | - goto update_bootargs; | ||
96 | } else { | ||
97 | mc->fdt = create_device_tree(&s->fdt_size); | ||
98 | if (!mc->fdt) { | ||
99 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | ||
100 | create_fdt_fw_cfg(s, memmap); | ||
101 | create_fdt_pmu(s); | ||
102 | |||
103 | -update_bootargs: | ||
104 | - if (cmdline && *cmdline) { | ||
105 | - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); | ||
106 | - } | ||
107 | - | ||
108 | /* Pass seed to RNG */ | ||
109 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); | ||
110 | qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); | ||
111 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
112 | riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
113 | kernel_entry, machine->fdt); | ||
114 | } | ||
115 | + | ||
116 | + if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
117 | + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", | ||
118 | + machine->kernel_cmdline); | ||
119 | + } | ||
120 | } else { | ||
121 | /* | ||
122 | * If dynamic firmware is used, it doesn't know where is the next mode | ||
123 | -- | ||
124 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be | ||
4 | retrieved by the MachineState object for all callers. | ||
5 | |||
6 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
7 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | --- | ||
14 | include/hw/riscv/boot.h | 3 +-- | ||
15 | hw/riscv/boot.c | 6 ++++-- | ||
16 | hw/riscv/microchip_pfsoc.c | 3 +-- | ||
17 | hw/riscv/sifive_u.c | 3 +-- | ||
18 | hw/riscv/spike.c | 3 +-- | ||
19 | hw/riscv/virt.c | 3 +-- | ||
20 | 6 files changed, 9 insertions(+), 12 deletions(-) | ||
21 | |||
22 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/include/hw/riscv/boot.h | ||
25 | +++ b/include/hw/riscv/boot.h | ||
26 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename, | ||
27 | target_ulong riscv_load_kernel(const char *kernel_filename, | ||
28 | target_ulong firmware_end_addr, | ||
29 | symbol_fn_t sym_cb); | ||
30 | -void riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
31 | - uint64_t kernel_entry, void *fdt); | ||
32 | +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); | ||
33 | uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); | ||
34 | void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, | ||
35 | hwaddr saddr, | ||
36 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/riscv/boot.c | ||
39 | +++ b/hw/riscv/boot.c | ||
40 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename, | ||
41 | exit(1); | ||
42 | } | ||
43 | |||
44 | -void riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
45 | - uint64_t kernel_entry, void *fdt) | ||
46 | +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) | ||
47 | { | ||
48 | + const char *filename = machine->initrd_filename; | ||
49 | + uint64_t mem_size = machine->ram_size; | ||
50 | + void *fdt = machine->fdt; | ||
51 | hwaddr start, end; | ||
52 | ssize_t size; | ||
53 | |||
54 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/riscv/microchip_pfsoc.c | ||
57 | +++ b/hw/riscv/microchip_pfsoc.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
59 | kernel_start_addr, NULL); | ||
60 | |||
61 | if (machine->initrd_filename) { | ||
62 | - riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
63 | - kernel_entry, machine->fdt); | ||
64 | + riscv_load_initrd(machine, kernel_entry); | ||
65 | } | ||
66 | |||
67 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
68 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/riscv/sifive_u.c | ||
71 | +++ b/hw/riscv/sifive_u.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
73 | kernel_start_addr, NULL); | ||
74 | |||
75 | if (machine->initrd_filename) { | ||
76 | - riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
77 | - kernel_entry, machine->fdt); | ||
78 | + riscv_load_initrd(machine, kernel_entry); | ||
79 | } | ||
80 | |||
81 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
82 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/hw/riscv/spike.c | ||
85 | +++ b/hw/riscv/spike.c | ||
86 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
87 | htif_symbol_callback); | ||
88 | |||
89 | if (machine->initrd_filename) { | ||
90 | - riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
91 | - kernel_entry, machine->fdt); | ||
92 | + riscv_load_initrd(machine, kernel_entry); | ||
93 | } | ||
94 | |||
95 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
96 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/hw/riscv/virt.c | ||
99 | +++ b/hw/riscv/virt.c | ||
100 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
101 | kernel_start_addr, NULL); | ||
102 | |||
103 | if (machine->initrd_filename) { | ||
104 | - riscv_load_initrd(machine->initrd_filename, machine->ram_size, | ||
105 | - kernel_entry, machine->fdt); | ||
106 | + riscv_load_initrd(machine, kernel_entry); | ||
107 | } | ||
108 | |||
109 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | ||
110 | -- | ||
111 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | All callers are using kernel_filename as machine->kernel_filename. | ||
4 | |||
5 | This will also simplify the changes in riscv_load_kernel() that we're | ||
6 | going to do next. | ||
7 | |||
8 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
9 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com> | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | --- | ||
16 | include/hw/riscv/boot.h | 2 +- | ||
17 | hw/riscv/boot.c | 3 ++- | ||
18 | hw/riscv/microchip_pfsoc.c | 3 +-- | ||
19 | hw/riscv/opentitan.c | 3 +-- | ||
20 | hw/riscv/sifive_e.c | 3 +-- | ||
21 | hw/riscv/sifive_u.c | 3 +-- | ||
22 | hw/riscv/spike.c | 3 +-- | ||
23 | hw/riscv/virt.c | 3 +-- | ||
24 | 8 files changed, 9 insertions(+), 14 deletions(-) | ||
25 | |||
26 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/include/hw/riscv/boot.h | ||
29 | +++ b/include/hw/riscv/boot.h | ||
30 | @@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename, | ||
31 | target_ulong riscv_load_firmware(const char *firmware_filename, | ||
32 | hwaddr firmware_load_addr, | ||
33 | symbol_fn_t sym_cb); | ||
34 | -target_ulong riscv_load_kernel(const char *kernel_filename, | ||
35 | +target_ulong riscv_load_kernel(MachineState *machine, | ||
36 | target_ulong firmware_end_addr, | ||
37 | symbol_fn_t sym_cb); | ||
38 | void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); | ||
39 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/hw/riscv/boot.c | ||
42 | +++ b/hw/riscv/boot.c | ||
43 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename, | ||
44 | exit(1); | ||
45 | } | ||
46 | |||
47 | -target_ulong riscv_load_kernel(const char *kernel_filename, | ||
48 | +target_ulong riscv_load_kernel(MachineState *machine, | ||
49 | target_ulong kernel_start_addr, | ||
50 | symbol_fn_t sym_cb) | ||
51 | { | ||
52 | + const char *kernel_filename = machine->kernel_filename; | ||
53 | uint64_t kernel_load_base, kernel_entry; | ||
54 | |||
55 | g_assert(kernel_filename != NULL); | ||
56 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/riscv/microchip_pfsoc.c | ||
59 | +++ b/hw/riscv/microchip_pfsoc.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
61 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, | ||
62 | firmware_end_addr); | ||
63 | |||
64 | - kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
65 | - kernel_start_addr, NULL); | ||
66 | + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); | ||
67 | |||
68 | if (machine->initrd_filename) { | ||
69 | riscv_load_initrd(machine, kernel_entry); | ||
70 | diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/hw/riscv/opentitan.c | ||
73 | +++ b/hw/riscv/opentitan.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static void opentitan_board_init(MachineState *machine) | ||
75 | } | ||
76 | |||
77 | if (machine->kernel_filename) { | ||
78 | - riscv_load_kernel(machine->kernel_filename, | ||
79 | - memmap[IBEX_DEV_RAM].base, NULL); | ||
80 | + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); | ||
81 | } | ||
82 | } | ||
83 | |||
84 | diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/riscv/sifive_e.c | ||
87 | +++ b/hw/riscv/sifive_e.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine) | ||
89 | memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); | ||
90 | |||
91 | if (machine->kernel_filename) { | ||
92 | - riscv_load_kernel(machine->kernel_filename, | ||
93 | - memmap[SIFIVE_E_DEV_DTIM].base, NULL); | ||
94 | + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); | ||
95 | } | ||
96 | } | ||
97 | |||
98 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/hw/riscv/sifive_u.c | ||
101 | +++ b/hw/riscv/sifive_u.c | ||
102 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
103 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, | ||
104 | firmware_end_addr); | ||
105 | |||
106 | - kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
107 | - kernel_start_addr, NULL); | ||
108 | + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); | ||
109 | |||
110 | if (machine->initrd_filename) { | ||
111 | riscv_load_initrd(machine, kernel_entry); | ||
112 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/hw/riscv/spike.c | ||
115 | +++ b/hw/riscv/spike.c | ||
116 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
117 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
118 | firmware_end_addr); | ||
119 | |||
120 | - kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
121 | - kernel_start_addr, | ||
122 | + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, | ||
123 | htif_symbol_callback); | ||
124 | |||
125 | if (machine->initrd_filename) { | ||
126 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/hw/riscv/virt.c | ||
129 | +++ b/hw/riscv/virt.c | ||
130 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
131 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
132 | firmware_end_addr); | ||
133 | |||
134 | - kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
135 | - kernel_start_addr, NULL); | ||
136 | + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); | ||
137 | |||
138 | if (machine->initrd_filename) { | ||
139 | riscv_load_initrd(machine, kernel_entry); | ||
140 | -- | ||
141 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | There is an informal contract between the cpu_init() functions and | ||
4 | riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the | ||
5 | default settings were loaded via register_cpu_props() and do validations | ||
6 | to set env.misa_ext. If it's not zero, skip this whole process and | ||
7 | assume that the board somehow did everything. | ||
8 | |||
9 | At this moment, all SiFive CPUs are setting a non-zero misa_ext during | ||
10 | their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This | ||
11 | causes problems when the code being skipped in riscv_cpu_realize() | ||
12 | contains fixes or assumptions that affects all CPUs, meaning that SiFive | ||
13 | CPUs are missing out. | ||
14 | |||
15 | To allow this code to not be skipped anymore, all the cpu->cfg.ext_* | ||
16 | attributes needs to be set during cpu_init() time. At this moment this | ||
17 | is being done in register_cpu_props(). The SiFive boards are setting | ||
18 | their own extensions during cpu_init() though, meaning that they don't | ||
19 | want all the defaults from register_cpu_props(). | ||
20 | |||
21 | Let's move the contract between *_cpu_init() and riscv_cpu_realize() to | ||
22 | register_cpu_props(). Inside this function we'll check if | ||
23 | cpu->env.misa_ext was set and, if that's the case, set all relevant | ||
24 | cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case | ||
25 | as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. | ||
26 | |||
27 | register_cpu_props() can then be called by all the cpu_init() functions, | ||
28 | including the SiFive ones. This will make all CPUs behave more in line | ||
29 | with what riscv_cpu_realize() expects. | ||
30 | |||
31 | This will also make the cpu_init() functions even more alike, but at this | ||
32 | moment we would need some design changes in how we're initializing | ||
33 | extensions/attributes (e.g. some CPUs are setting cfg options after | ||
34 | register_cpu_props(), so we can't simply add the function to a common | ||
35 | post_init() hook) to make a common cpu_init() code across all CPUs. | ||
36 | |||
37 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
38 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
39 | Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> | ||
40 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
41 | --- | ||
42 | target/riscv/cpu.h | 4 ++++ | ||
43 | target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ | ||
44 | 2 files changed, 44 insertions(+) | ||
45 | |||
46 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/riscv/cpu.h | ||
49 | +++ b/target/riscv/cpu.h | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | |||
52 | #define RV(x) ((target_ulong)1 << (x - 'A')) | ||
53 | |||
54 | +/* | ||
55 | + * Consider updating register_cpu_props() when adding | ||
56 | + * new MISA bits here. | ||
57 | + */ | ||
58 | #define RVI RV('I') | ||
59 | #define RVE RV('E') /* E and I are mutually exclusive */ | ||
60 | #define RVM RV('M') | ||
61 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/riscv/cpu.c | ||
64 | +++ b/target/riscv/cpu.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj) | ||
66 | { | ||
67 | CPURISCVState *env = &RISCV_CPU(obj)->env; | ||
68 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | ||
69 | + register_cpu_props(DEVICE(obj)); | ||
70 | set_priv_version(env, PRIV_VERSION_1_10_0); | ||
71 | } | ||
72 | |||
73 | @@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj) | ||
74 | RISCVCPU *cpu = RISCV_CPU(obj); | ||
75 | |||
76 | set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); | ||
77 | + register_cpu_props(DEVICE(obj)); | ||
78 | set_priv_version(env, PRIV_VERSION_1_10_0); | ||
79 | cpu->cfg.mmu = false; | ||
80 | } | ||
81 | @@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj) | ||
82 | { | ||
83 | CPURISCVState *env = &RISCV_CPU(obj)->env; | ||
84 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | ||
85 | + register_cpu_props(DEVICE(obj)); | ||
86 | set_priv_version(env, PRIV_VERSION_1_10_0); | ||
87 | } | ||
88 | |||
89 | @@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj) | ||
90 | RISCVCPU *cpu = RISCV_CPU(obj); | ||
91 | |||
92 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); | ||
93 | + register_cpu_props(DEVICE(obj)); | ||
94 | set_priv_version(env, PRIV_VERSION_1_10_0); | ||
95 | cpu->cfg.mmu = false; | ||
96 | } | ||
97 | @@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj) | ||
98 | RISCVCPU *cpu = RISCV_CPU(obj); | ||
99 | |||
100 | set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); | ||
101 | + register_cpu_props(DEVICE(obj)); | ||
102 | set_priv_version(env, PRIV_VERSION_1_11_0); | ||
103 | cpu->cfg.mmu = false; | ||
104 | cpu->cfg.epmp = true; | ||
105 | @@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) | ||
106 | RISCVCPU *cpu = RISCV_CPU(obj); | ||
107 | |||
108 | set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); | ||
109 | + register_cpu_props(DEVICE(obj)); | ||
110 | set_priv_version(env, PRIV_VERSION_1_10_0); | ||
111 | cpu->cfg.mmu = false; | ||
112 | } | ||
113 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
114 | DEFINE_PROP_END_OF_LIST(), | ||
115 | }; | ||
116 | |||
117 | +/* | ||
118 | + * Register CPU props based on env.misa_ext. If a non-zero | ||
119 | + * value was set, register only the required cpu->cfg.ext_* | ||
120 | + * properties and leave. env.misa_ext = 0 means that we want | ||
121 | + * all the default properties to be registered. | ||
122 | + */ | ||
123 | static void register_cpu_props(DeviceState *dev) | ||
124 | { | ||
125 | + RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); | ||
126 | + uint32_t misa_ext = cpu->env.misa_ext; | ||
127 | Property *prop; | ||
128 | |||
129 | + /* | ||
130 | + * If misa_ext is not zero, set cfg properties now to | ||
131 | + * allow them to be read during riscv_cpu_realize() | ||
132 | + * later on. | ||
133 | + */ | ||
134 | + if (cpu->env.misa_ext != 0) { | ||
135 | + cpu->cfg.ext_i = misa_ext & RVI; | ||
136 | + cpu->cfg.ext_e = misa_ext & RVE; | ||
137 | + cpu->cfg.ext_m = misa_ext & RVM; | ||
138 | + cpu->cfg.ext_a = misa_ext & RVA; | ||
139 | + cpu->cfg.ext_f = misa_ext & RVF; | ||
140 | + cpu->cfg.ext_d = misa_ext & RVD; | ||
141 | + cpu->cfg.ext_v = misa_ext & RVV; | ||
142 | + cpu->cfg.ext_c = misa_ext & RVC; | ||
143 | + cpu->cfg.ext_s = misa_ext & RVS; | ||
144 | + cpu->cfg.ext_u = misa_ext & RVU; | ||
145 | + cpu->cfg.ext_h = misa_ext & RVH; | ||
146 | + cpu->cfg.ext_j = misa_ext & RVJ; | ||
147 | + | ||
148 | + /* | ||
149 | + * We don't want to set the default riscv_cpu_extensions | ||
150 | + * in this case. | ||
151 | + */ | ||
152 | + return; | ||
153 | + } | ||
154 | + | ||
155 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { | ||
156 | qdev_property_add_static(dev, prop); | ||
157 | } | ||
158 | -- | ||
159 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, | ||
4 | meaning that there's no reason to skip all the misa validation and setup | ||
5 | if misa_ext was set beforehand - especially since we're setting an | ||
6 | updated value in set_misa() in the end. | ||
7 | |||
8 | Put this code chunk into a new riscv_cpu_validate_set_extensions() | ||
9 | helper and always execute it regardless of what the board set in | ||
10 | env->misa_ext. | ||
11 | |||
12 | This will put more responsibility in how each board is going to init | ||
13 | their attributes and extensions if they're not using the defaults. | ||
14 | It'll also allow realize() to do its job looking only at the extensions | ||
15 | enabled per se, not corner cases that some CPUs might have, and we won't | ||
16 | have to change multiple code paths to fix or change how extensions work. | ||
17 | |||
18 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
19 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
20 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
21 | Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> | ||
22 | [ Changes by AF: | ||
23 | - Rebase | ||
24 | ] | ||
25 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
26 | --- | ||
27 | target/riscv/cpu.c | 399 +++++++++++++++++++++++---------------------- | ||
28 | 1 file changed, 205 insertions(+), 194 deletions(-) | ||
29 | |||
30 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/riscv/cpu.c | ||
33 | +++ b/target/riscv/cpu.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) | ||
35 | } | ||
36 | } | ||
37 | |||
38 | +/* | ||
39 | + * Check consistency between chosen extensions while setting | ||
40 | + * cpu->cfg accordingly, doing a set_misa() in the end. | ||
41 | + */ | ||
42 | +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
43 | +{ | ||
44 | + CPURISCVState *env = &cpu->env; | ||
45 | + uint32_t ext = 0; | ||
46 | + | ||
47 | + /* Do some ISA extension error checking */ | ||
48 | + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | ||
49 | + cpu->cfg.ext_a && cpu->cfg.ext_f && | ||
50 | + cpu->cfg.ext_d && | ||
51 | + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | ||
52 | + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | ||
53 | + cpu->cfg.ext_i = true; | ||
54 | + cpu->cfg.ext_m = true; | ||
55 | + cpu->cfg.ext_a = true; | ||
56 | + cpu->cfg.ext_f = true; | ||
57 | + cpu->cfg.ext_d = true; | ||
58 | + cpu->cfg.ext_icsr = true; | ||
59 | + cpu->cfg.ext_ifencei = true; | ||
60 | + } | ||
61 | + | ||
62 | + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | ||
63 | + error_setg(errp, | ||
64 | + "I and E extensions are incompatible"); | ||
65 | + return; | ||
66 | + } | ||
67 | + | ||
68 | + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | ||
69 | + error_setg(errp, | ||
70 | + "Either I or E extension must be set"); | ||
71 | + return; | ||
72 | + } | ||
73 | + | ||
74 | + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | ||
75 | + error_setg(errp, | ||
76 | + "Setting S extension without U extension is illegal"); | ||
77 | + return; | ||
78 | + } | ||
79 | + | ||
80 | + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | ||
81 | + error_setg(errp, | ||
82 | + "H depends on an I base integer ISA with 32 x registers"); | ||
83 | + return; | ||
84 | + } | ||
85 | + | ||
86 | + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | ||
87 | + error_setg(errp, "H extension implicitly requires S-mode"); | ||
88 | + return; | ||
89 | + } | ||
90 | + | ||
91 | + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | ||
92 | + error_setg(errp, "F extension requires Zicsr"); | ||
93 | + return; | ||
94 | + } | ||
95 | + | ||
96 | + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | ||
97 | + error_setg(errp, "Zawrs extension requires A extension"); | ||
98 | + return; | ||
99 | + } | ||
100 | + | ||
101 | + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { | ||
102 | + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); | ||
103 | + return; | ||
104 | + } | ||
105 | + | ||
106 | + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | ||
107 | + error_setg(errp, "D extension requires F extension"); | ||
108 | + return; | ||
109 | + } | ||
110 | + | ||
111 | + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { | ||
112 | + error_setg(errp, "V extension requires D extension"); | ||
113 | + return; | ||
114 | + } | ||
115 | + | ||
116 | + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { | ||
117 | + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); | ||
118 | + return; | ||
119 | + } | ||
120 | + | ||
121 | + /* Set the ISA extensions, checks should have happened above */ | ||
122 | + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || | ||
123 | + cpu->cfg.ext_zhinxmin) { | ||
124 | + cpu->cfg.ext_zfinx = true; | ||
125 | + } | ||
126 | + | ||
127 | + if (cpu->cfg.ext_zfinx) { | ||
128 | + if (!cpu->cfg.ext_icsr) { | ||
129 | + error_setg(errp, "Zfinx extension requires Zicsr"); | ||
130 | + return; | ||
131 | + } | ||
132 | + if (cpu->cfg.ext_f) { | ||
133 | + error_setg(errp, | ||
134 | + "Zfinx cannot be supported together with F extension"); | ||
135 | + return; | ||
136 | + } | ||
137 | + } | ||
138 | + | ||
139 | + if (cpu->cfg.ext_zk) { | ||
140 | + cpu->cfg.ext_zkn = true; | ||
141 | + cpu->cfg.ext_zkr = true; | ||
142 | + cpu->cfg.ext_zkt = true; | ||
143 | + } | ||
144 | + | ||
145 | + if (cpu->cfg.ext_zkn) { | ||
146 | + cpu->cfg.ext_zbkb = true; | ||
147 | + cpu->cfg.ext_zbkc = true; | ||
148 | + cpu->cfg.ext_zbkx = true; | ||
149 | + cpu->cfg.ext_zkne = true; | ||
150 | + cpu->cfg.ext_zknd = true; | ||
151 | + cpu->cfg.ext_zknh = true; | ||
152 | + } | ||
153 | + | ||
154 | + if (cpu->cfg.ext_zks) { | ||
155 | + cpu->cfg.ext_zbkb = true; | ||
156 | + cpu->cfg.ext_zbkc = true; | ||
157 | + cpu->cfg.ext_zbkx = true; | ||
158 | + cpu->cfg.ext_zksed = true; | ||
159 | + cpu->cfg.ext_zksh = true; | ||
160 | + } | ||
161 | + | ||
162 | + if (cpu->cfg.ext_i) { | ||
163 | + ext |= RVI; | ||
164 | + } | ||
165 | + if (cpu->cfg.ext_e) { | ||
166 | + ext |= RVE; | ||
167 | + } | ||
168 | + if (cpu->cfg.ext_m) { | ||
169 | + ext |= RVM; | ||
170 | + } | ||
171 | + if (cpu->cfg.ext_a) { | ||
172 | + ext |= RVA; | ||
173 | + } | ||
174 | + if (cpu->cfg.ext_f) { | ||
175 | + ext |= RVF; | ||
176 | + } | ||
177 | + if (cpu->cfg.ext_d) { | ||
178 | + ext |= RVD; | ||
179 | + } | ||
180 | + if (cpu->cfg.ext_c) { | ||
181 | + ext |= RVC; | ||
182 | + } | ||
183 | + if (cpu->cfg.ext_s) { | ||
184 | + ext |= RVS; | ||
185 | + } | ||
186 | + if (cpu->cfg.ext_u) { | ||
187 | + ext |= RVU; | ||
188 | + } | ||
189 | + if (cpu->cfg.ext_h) { | ||
190 | + ext |= RVH; | ||
191 | + } | ||
192 | + if (cpu->cfg.ext_v) { | ||
193 | + int vext_version = VEXT_VERSION_1_00_0; | ||
194 | + ext |= RVV; | ||
195 | + if (!is_power_of_2(cpu->cfg.vlen)) { | ||
196 | + error_setg(errp, | ||
197 | + "Vector extension VLEN must be power of 2"); | ||
198 | + return; | ||
199 | + } | ||
200 | + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | ||
201 | + error_setg(errp, | ||
202 | + "Vector extension implementation only supports VLEN " | ||
203 | + "in the range [128, %d]", RV_VLEN_MAX); | ||
204 | + return; | ||
205 | + } | ||
206 | + if (!is_power_of_2(cpu->cfg.elen)) { | ||
207 | + error_setg(errp, | ||
208 | + "Vector extension ELEN must be power of 2"); | ||
209 | + return; | ||
210 | + } | ||
211 | + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { | ||
212 | + error_setg(errp, | ||
213 | + "Vector extension implementation only supports ELEN " | ||
214 | + "in the range [8, 64]"); | ||
215 | + return; | ||
216 | + } | ||
217 | + if (cpu->cfg.vext_spec) { | ||
218 | + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | ||
219 | + vext_version = VEXT_VERSION_1_00_0; | ||
220 | + } else { | ||
221 | + error_setg(errp, | ||
222 | + "Unsupported vector spec version '%s'", | ||
223 | + cpu->cfg.vext_spec); | ||
224 | + return; | ||
225 | + } | ||
226 | + } else { | ||
227 | + qemu_log("vector version is not specified, " | ||
228 | + "use the default value v1.0\n"); | ||
229 | + } | ||
230 | + set_vext_version(env, vext_version); | ||
231 | + } | ||
232 | + if (cpu->cfg.ext_j) { | ||
233 | + ext |= RVJ; | ||
234 | + } | ||
235 | + | ||
236 | + set_misa(env, env->misa_mxl, ext); | ||
237 | +} | ||
238 | + | ||
239 | static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
240 | { | ||
241 | CPUState *cs = CPU(dev); | ||
242 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
243 | } | ||
244 | assert(env->misa_mxl_max == env->misa_mxl); | ||
245 | |||
246 | - /* If only MISA_EXT is unset for misa, then set it from properties */ | ||
247 | - if (env->misa_ext == 0) { | ||
248 | - uint32_t ext = 0; | ||
249 | - | ||
250 | - /* Do some ISA extension error checking */ | ||
251 | - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && | ||
252 | - cpu->cfg.ext_a && cpu->cfg.ext_f && | ||
253 | - cpu->cfg.ext_d && | ||
254 | - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { | ||
255 | - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); | ||
256 | - cpu->cfg.ext_i = true; | ||
257 | - cpu->cfg.ext_m = true; | ||
258 | - cpu->cfg.ext_a = true; | ||
259 | - cpu->cfg.ext_f = true; | ||
260 | - cpu->cfg.ext_d = true; | ||
261 | - cpu->cfg.ext_icsr = true; | ||
262 | - cpu->cfg.ext_ifencei = true; | ||
263 | - } | ||
264 | - | ||
265 | - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { | ||
266 | - error_setg(errp, | ||
267 | - "I and E extensions are incompatible"); | ||
268 | - return; | ||
269 | - } | ||
270 | - | ||
271 | - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { | ||
272 | - error_setg(errp, | ||
273 | - "Either I or E extension must be set"); | ||
274 | - return; | ||
275 | - } | ||
276 | - | ||
277 | - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { | ||
278 | - error_setg(errp, | ||
279 | - "Setting S extension without U extension is illegal"); | ||
280 | - return; | ||
281 | - } | ||
282 | - | ||
283 | - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { | ||
284 | - error_setg(errp, | ||
285 | - "H depends on an I base integer ISA with 32 x registers"); | ||
286 | - return; | ||
287 | - } | ||
288 | - | ||
289 | - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { | ||
290 | - error_setg(errp, "H extension implicitly requires S-mode"); | ||
291 | - return; | ||
292 | - } | ||
293 | - | ||
294 | - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { | ||
295 | - error_setg(errp, "F extension requires Zicsr"); | ||
296 | - return; | ||
297 | - } | ||
298 | - | ||
299 | - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { | ||
300 | - error_setg(errp, "Zawrs extension requires A extension"); | ||
301 | - return; | ||
302 | - } | ||
303 | - | ||
304 | - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { | ||
305 | - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); | ||
306 | - return; | ||
307 | - } | ||
308 | - | ||
309 | - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { | ||
310 | - error_setg(errp, "D extension requires F extension"); | ||
311 | - return; | ||
312 | - } | ||
313 | - | ||
314 | - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { | ||
315 | - error_setg(errp, "V extension requires D extension"); | ||
316 | - return; | ||
317 | - } | ||
318 | - | ||
319 | - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { | ||
320 | - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); | ||
321 | - return; | ||
322 | - } | ||
323 | - | ||
324 | - /* Set the ISA extensions, checks should have happened above */ | ||
325 | - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || | ||
326 | - cpu->cfg.ext_zhinxmin) { | ||
327 | - cpu->cfg.ext_zfinx = true; | ||
328 | - } | ||
329 | - | ||
330 | - if (cpu->cfg.ext_zfinx) { | ||
331 | - if (!cpu->cfg.ext_icsr) { | ||
332 | - error_setg(errp, "Zfinx extension requires Zicsr"); | ||
333 | - return; | ||
334 | - } | ||
335 | - if (cpu->cfg.ext_f) { | ||
336 | - error_setg(errp, | ||
337 | - "Zfinx cannot be supported together with F extension"); | ||
338 | - return; | ||
339 | - } | ||
340 | - } | ||
341 | - | ||
342 | - if (cpu->cfg.ext_zk) { | ||
343 | - cpu->cfg.ext_zkn = true; | ||
344 | - cpu->cfg.ext_zkr = true; | ||
345 | - cpu->cfg.ext_zkt = true; | ||
346 | - } | ||
347 | - | ||
348 | - if (cpu->cfg.ext_zkn) { | ||
349 | - cpu->cfg.ext_zbkb = true; | ||
350 | - cpu->cfg.ext_zbkc = true; | ||
351 | - cpu->cfg.ext_zbkx = true; | ||
352 | - cpu->cfg.ext_zkne = true; | ||
353 | - cpu->cfg.ext_zknd = true; | ||
354 | - cpu->cfg.ext_zknh = true; | ||
355 | - } | ||
356 | - | ||
357 | - if (cpu->cfg.ext_zks) { | ||
358 | - cpu->cfg.ext_zbkb = true; | ||
359 | - cpu->cfg.ext_zbkc = true; | ||
360 | - cpu->cfg.ext_zbkx = true; | ||
361 | - cpu->cfg.ext_zksed = true; | ||
362 | - cpu->cfg.ext_zksh = true; | ||
363 | - } | ||
364 | - | ||
365 | - if (cpu->cfg.ext_i) { | ||
366 | - ext |= RVI; | ||
367 | - } | ||
368 | - if (cpu->cfg.ext_e) { | ||
369 | - ext |= RVE; | ||
370 | - } | ||
371 | - if (cpu->cfg.ext_m) { | ||
372 | - ext |= RVM; | ||
373 | - } | ||
374 | - if (cpu->cfg.ext_a) { | ||
375 | - ext |= RVA; | ||
376 | - } | ||
377 | - if (cpu->cfg.ext_f) { | ||
378 | - ext |= RVF; | ||
379 | - } | ||
380 | - if (cpu->cfg.ext_d) { | ||
381 | - ext |= RVD; | ||
382 | - } | ||
383 | - if (cpu->cfg.ext_c) { | ||
384 | - ext |= RVC; | ||
385 | - } | ||
386 | - if (cpu->cfg.ext_s) { | ||
387 | - ext |= RVS; | ||
388 | - } | ||
389 | - if (cpu->cfg.ext_u) { | ||
390 | - ext |= RVU; | ||
391 | - } | ||
392 | - if (cpu->cfg.ext_h) { | ||
393 | - ext |= RVH; | ||
394 | - } | ||
395 | - if (cpu->cfg.ext_v) { | ||
396 | - int vext_version = VEXT_VERSION_1_00_0; | ||
397 | - ext |= RVV; | ||
398 | - if (!is_power_of_2(cpu->cfg.vlen)) { | ||
399 | - error_setg(errp, | ||
400 | - "Vector extension VLEN must be power of 2"); | ||
401 | - return; | ||
402 | - } | ||
403 | - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { | ||
404 | - error_setg(errp, | ||
405 | - "Vector extension implementation only supports VLEN " | ||
406 | - "in the range [128, %d]", RV_VLEN_MAX); | ||
407 | - return; | ||
408 | - } | ||
409 | - if (!is_power_of_2(cpu->cfg.elen)) { | ||
410 | - error_setg(errp, | ||
411 | - "Vector extension ELEN must be power of 2"); | ||
412 | - return; | ||
413 | - } | ||
414 | - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { | ||
415 | - error_setg(errp, | ||
416 | - "Vector extension implementation only supports ELEN " | ||
417 | - "in the range [8, 64]"); | ||
418 | - return; | ||
419 | - } | ||
420 | - if (cpu->cfg.vext_spec) { | ||
421 | - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { | ||
422 | - vext_version = VEXT_VERSION_1_00_0; | ||
423 | - } else { | ||
424 | - error_setg(errp, | ||
425 | - "Unsupported vector spec version '%s'", | ||
426 | - cpu->cfg.vext_spec); | ||
427 | - return; | ||
428 | - } | ||
429 | - } else { | ||
430 | - qemu_log("vector version is not specified, " | ||
431 | - "use the default value v1.0\n"); | ||
432 | - } | ||
433 | - set_vext_version(env, vext_version); | ||
434 | - } | ||
435 | - if (cpu->cfg.ext_j) { | ||
436 | - ext |= RVJ; | ||
437 | - } | ||
438 | - | ||
439 | - set_misa(env, env->misa_mxl, ext); | ||
440 | + riscv_cpu_validate_set_extensions(cpu, &local_err); | ||
441 | + if (local_err != NULL) { | ||
442 | + error_propagate(errp, local_err); | ||
443 | + return; | ||
444 | } | ||
445 | |||
446 | #ifndef CONFIG_USER_ONLY | ||
447 | -- | ||
448 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng@tinylab.org> | ||
1 | 2 | ||
3 | env->mhartid is currently casted to long before printed, which drops | ||
4 | the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. | ||
5 | |||
6 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-Id: <20230109152655.340114-1-bmeng@tinylab.org> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | target/riscv/cpu.c | 6 +++--- | ||
12 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/riscv/cpu.c | ||
17 | +++ b/target/riscv/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
19 | (env->priv_ver < isa_edata_arr[i].min_version)) { | ||
20 | isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); | ||
21 | #ifndef CONFIG_USER_ONLY | ||
22 | - warn_report("disabling %s extension for hart 0x%lx because " | ||
23 | - "privilege spec version does not match", | ||
24 | - isa_edata_arr[i].name, (unsigned long)env->mhartid); | ||
25 | + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx | ||
26 | + " because privilege spec version does not match", | ||
27 | + isa_edata_arr[i].name, env->mhartid); | ||
28 | #else | ||
29 | warn_report("disabling %s extension because " | ||
30 | "privilege spec version does not match", | ||
31 | -- | ||
32 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | 'mem_size' and 'cmdline' are unused. | ||
4 | |||
5 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | hw/riscv/spike.c | 4 +--- | ||
12 | 1 file changed, 1 insertion(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/riscv/spike.c | ||
17 | +++ b/hw/riscv/spike.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = { | ||
19 | }; | ||
20 | |||
21 | static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
22 | - uint64_t mem_size, const char *cmdline, | ||
23 | bool is_32_bit, bool htif_custom_base) | ||
24 | { | ||
25 | void *fdt; | ||
26 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
27 | } | ||
28 | |||
29 | /* Create device tree */ | ||
30 | - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
31 | - riscv_is_32bit(&s->soc[0]), htif_custom_base); | ||
32 | + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); | ||
33 | |||
34 | /* Load kernel */ | ||
35 | if (machine->kernel_filename) { | ||
36 | -- | ||
37 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | 'mem_size' and 'cmdline' aren't being used. Remove them. | ||
4 | |||
5 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | hw/riscv/virt.c | 5 ++--- | ||
12 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/riscv/virt.c | ||
17 | +++ b/hw/riscv/virt.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) | ||
19 | } | ||
20 | |||
21 | static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | ||
22 | - uint64_t mem_size, const char *cmdline, bool is_32_bit) | ||
23 | + bool is_32_bit) | ||
24 | { | ||
25 | MachineState *mc = MACHINE(s); | ||
26 | uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; | ||
27 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
28 | virt_flash_map(s, system_memory); | ||
29 | |||
30 | /* create device tree */ | ||
31 | - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
32 | - riscv_is_32bit(&s->soc[0])); | ||
33 | + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); | ||
34 | |||
35 | s->machine_done.notify = virt_machine_done; | ||
36 | qemu_add_machine_init_done_notifier(&s->machine_done); | ||
37 | -- | ||
38 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | 'cmdline' isn't being used. Remove it. | ||
4 | |||
5 | A MachineState pointer is being retrieved via a MACHINE() macro calling | ||
6 | qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). | ||
7 | |||
8 | 'mem_size' is being set as machine->ram_size by the caller. Retrieve it | ||
9 | via ms->ram_size. | ||
10 | |||
11 | Cc: Palmer Dabbelt <palmer@dabbelt.com> | ||
12 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | --- | ||
18 | hw/riscv/sifive_u.c | 8 ++++---- | ||
19 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/riscv/sifive_u.c | ||
24 | +++ b/hw/riscv/sifive_u.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_u_memmap[] = { | ||
26 | #define GEM_REVISION 0x10070109 | ||
27 | |||
28 | static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
29 | - uint64_t mem_size, const char *cmdline, bool is_32_bit) | ||
30 | + bool is_32_bit) | ||
31 | { | ||
32 | - MachineState *ms = MACHINE(qdev_get_machine()); | ||
33 | + MachineState *ms = MACHINE(s); | ||
34 | + uint64_t mem_size = ms->ram_size; | ||
35 | void *fdt; | ||
36 | int cpu, fdt_size; | ||
37 | uint32_t *cells; | ||
38 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
39 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | ||
40 | |||
41 | /* create device tree */ | ||
42 | - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
43 | - riscv_is_32bit(&s->soc.u_cpus)); | ||
44 | + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); | ||
45 | |||
46 | if (s->start_in_flash) { | ||
47 | /* | ||
48 | -- | ||
49 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | create_fdt_socket_cpus() writes a different 'mmu-type' value if we're | ||
4 | running in 32 or 64 bits. However, the flag is being calculated during | ||
5 | virt_machine_init(), and is passed around in create_fdt(), then | ||
6 | create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of | ||
7 | the intermediate functions are using the flag, which is a bit | ||
8 | misleading. | ||
9 | |||
10 | Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it | ||
11 | using the already available RISCVVirtState pointer. This will also | ||
12 | change the signature of create_fdt_socket() and create_fdt(), making it | ||
13 | clear that these functions don't do anything special when we're running | ||
14 | in 32 bit mode. | ||
15 | |||
16 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
18 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com> | ||
20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
21 | --- | ||
22 | hw/riscv/virt.c | 18 +++++++++--------- | ||
23 | 1 file changed, 9 insertions(+), 9 deletions(-) | ||
24 | |||
25 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/riscv/virt.c | ||
28 | +++ b/hw/riscv/virt.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, | ||
30 | |||
31 | static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, | ||
32 | char *clust_name, uint32_t *phandle, | ||
33 | - bool is_32_bit, uint32_t *intc_phandles) | ||
34 | + uint32_t *intc_phandles) | ||
35 | { | ||
36 | int cpu; | ||
37 | uint32_t cpu_phandle; | ||
38 | MachineState *mc = MACHINE(s); | ||
39 | char *name, *cpu_name, *core_name, *intc_name; | ||
40 | + bool is_32_bit = riscv_is_32bit(&s->soc[0]); | ||
41 | |||
42 | for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { | ||
43 | cpu_phandle = (*phandle)++; | ||
44 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s) | ||
45 | } | ||
46 | |||
47 | static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, | ||
48 | - bool is_32_bit, uint32_t *phandle, | ||
49 | + uint32_t *phandle, | ||
50 | uint32_t *irq_mmio_phandle, | ||
51 | uint32_t *irq_pcie_phandle, | ||
52 | uint32_t *irq_virtio_phandle, | ||
53 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, | ||
54 | qemu_fdt_add_subnode(mc->fdt, clust_name); | ||
55 | |||
56 | create_fdt_socket_cpus(s, socket, clust_name, phandle, | ||
57 | - is_32_bit, &intc_phandles[phandle_pos]); | ||
58 | + &intc_phandles[phandle_pos]); | ||
59 | |||
60 | create_fdt_socket_memory(s, memmap, socket); | ||
61 | |||
62 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) | ||
63 | g_free(nodename); | ||
64 | } | ||
65 | |||
66 | -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | ||
67 | - bool is_32_bit) | ||
68 | +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) | ||
69 | { | ||
70 | MachineState *mc = MACHINE(s); | ||
71 | uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | ||
73 | qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); | ||
74 | qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); | ||
75 | |||
76 | - create_fdt_sockets(s, memmap, is_32_bit, &phandle, | ||
77 | - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, | ||
78 | - &msi_pcie_phandle); | ||
79 | + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, | ||
80 | + &irq_pcie_phandle, &irq_virtio_phandle, | ||
81 | + &msi_pcie_phandle); | ||
82 | |||
83 | create_fdt_virtio(s, memmap, irq_virtio_phandle); | ||
84 | |||
85 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
86 | virt_flash_map(s, system_memory); | ||
87 | |||
88 | /* create device tree */ | ||
89 | - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); | ||
90 | + create_fdt(s, memmap); | ||
91 | |||
92 | s->machine_done.notify = virt_machine_done; | ||
93 | qemu_add_machine_init_done_notifier(&s->machine_done); | ||
94 | -- | ||
95 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | There's no need to use a MachineState pointer and a fdt pointer now that | ||
4 | all RISC-V machines are using the FDT from the MachineState. | ||
5 | |||
6 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | include/hw/riscv/numa.h | 6 +++--- | ||
13 | hw/riscv/numa.c | 6 +++--- | ||
14 | hw/riscv/spike.c | 6 +++--- | ||
15 | hw/riscv/virt.c | 18 +++++++++--------- | ||
16 | 4 files changed, 18 insertions(+), 18 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/riscv/numa.h | ||
21 | +++ b/include/hw/riscv/numa.h | ||
22 | @@ -XXX,XX +XXX,XX @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); | ||
23 | * @ms: pointer to machine state | ||
24 | * @socket_id: socket index | ||
25 | * | ||
26 | - * Write NUMA node-id FDT property for given FDT node | ||
27 | + * Write NUMA node-id FDT property in MachineState->fdt | ||
28 | */ | ||
29 | -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, | ||
30 | - const char *node_name, int socket_id); | ||
31 | +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, | ||
32 | + int socket_id); | ||
33 | |||
34 | /** | ||
35 | * riscv_socket_fdt_write_distance_matrix: | ||
36 | diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/riscv/numa.c | ||
39 | +++ b/hw/riscv/numa.c | ||
40 | @@ -XXX,XX +XXX,XX @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) | ||
41 | ms->numa_state->nodes[socket_id].node_mem : 0; | ||
42 | } | ||
43 | |||
44 | -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, | ||
45 | - const char *node_name, int socket_id) | ||
46 | +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, | ||
47 | + int socket_id) | ||
48 | { | ||
49 | if (numa_enabled(ms)) { | ||
50 | - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); | ||
51 | + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id); | ||
52 | } | ||
53 | } | ||
54 | |||
55 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/hw/riscv/spike.c | ||
58 | +++ b/hw/riscv/spike.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
60 | qemu_fdt_setprop_cell(fdt, cpu_name, "reg", | ||
61 | s->soc[socket].hartid_base + cpu); | ||
62 | qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | ||
63 | - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); | ||
64 | + riscv_socket_fdt_write_id(mc, cpu_name, socket); | ||
65 | qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); | ||
66 | |||
67 | intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); | ||
68 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
69 | qemu_fdt_setprop_cells(fdt, mem_name, "reg", | ||
70 | addr >> 32, addr, size >> 32, size); | ||
71 | qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); | ||
72 | - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); | ||
73 | + riscv_socket_fdt_write_id(mc, mem_name, socket); | ||
74 | g_free(mem_name); | ||
75 | |||
76 | clint_addr = memmap[SPIKE_CLINT].base + | ||
77 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, | ||
78 | 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); | ||
79 | qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", | ||
80 | clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | ||
81 | - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); | ||
82 | + riscv_socket_fdt_write_id(mc, clint_name, socket); | ||
83 | |||
84 | g_free(clint_name); | ||
85 | g_free(clint_cells); | ||
86 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/riscv/virt.c | ||
89 | +++ b/hw/riscv/virt.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, | ||
91 | qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", | ||
92 | s->soc[socket].hartid_base + cpu); | ||
93 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); | ||
94 | - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); | ||
95 | + riscv_socket_fdt_write_id(mc, cpu_name, socket); | ||
96 | qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); | ||
97 | |||
98 | intc_phandles[cpu] = (*phandle)++; | ||
99 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_memory(RISCVVirtState *s, | ||
100 | qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", | ||
101 | addr >> 32, addr, size >> 32, size); | ||
102 | qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); | ||
103 | - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); | ||
104 | + riscv_socket_fdt_write_id(mc, mem_name, socket); | ||
105 | g_free(mem_name); | ||
106 | } | ||
107 | |||
108 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s, | ||
109 | 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); | ||
110 | qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", | ||
111 | clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | ||
112 | - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); | ||
113 | + riscv_socket_fdt_write_id(mc, clint_name, socket); | ||
114 | g_free(clint_name); | ||
115 | |||
116 | g_free(clint_cells); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s, | ||
118 | aclint_mswi_cells, aclint_cells_size); | ||
119 | qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); | ||
120 | qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); | ||
121 | - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | ||
122 | + riscv_socket_fdt_write_id(mc, name, socket); | ||
123 | g_free(name); | ||
124 | } | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s, | ||
127 | 0x0, RISCV_ACLINT_DEFAULT_MTIME); | ||
128 | qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", | ||
129 | aclint_mtimer_cells, aclint_cells_size); | ||
130 | - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | ||
131 | + riscv_socket_fdt_write_id(mc, name, socket); | ||
132 | g_free(name); | ||
133 | |||
134 | if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { | ||
135 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s, | ||
136 | aclint_sswi_cells, aclint_cells_size); | ||
137 | qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); | ||
138 | qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); | ||
139 | - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | ||
140 | + riscv_socket_fdt_write_id(mc, name, socket); | ||
141 | g_free(name); | ||
142 | } | ||
143 | |||
144 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s, | ||
145 | 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); | ||
146 | qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", | ||
147 | VIRT_IRQCHIP_NUM_SOURCES - 1); | ||
148 | - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); | ||
149 | + riscv_socket_fdt_write_id(mc, plic_name, socket); | ||
150 | qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", | ||
151 | plic_phandles[socket]); | ||
152 | |||
153 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
154 | aplic_s_phandle); | ||
155 | qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", | ||
156 | aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); | ||
157 | - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); | ||
158 | + riscv_socket_fdt_write_id(mc, aplic_name, socket); | ||
159 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); | ||
160 | g_free(aplic_name); | ||
161 | |||
162 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
163 | 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); | ||
164 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", | ||
165 | VIRT_IRQCHIP_NUM_SOURCES); | ||
166 | - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); | ||
167 | + riscv_socket_fdt_write_id(mc, aplic_name, socket); | ||
168 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); | ||
169 | |||
170 | if (!socket) { | ||
171 | -- | ||
172 | 2.39.0 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
---|---|---|---|
2 | 2 | ||
3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. | 3 | There's no need to use a MachineState pointer and a fdt pointer now that |
4 | all RISC-V machines are using the FDT from the MachineState. | ||
4 | 5 | ||
5 | Do not re-initialize the OTP content in the DeviceReset handler, | 6 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
6 | initialize it once in the DeviceRealize one. | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | |||
8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> | 9 | Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com> |
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
13 | --- | 11 | --- |
14 | hw/misc/sifive_u_otp.c | 13 +++++-------- | 12 | include/hw/riscv/numa.h | 4 ++-- |
15 | 1 file changed, 5 insertions(+), 8 deletions(-) | 13 | hw/riscv/numa.c | 8 ++++---- |
14 | hw/riscv/spike.c | 2 +- | ||
15 | hw/riscv/virt.c | 2 +- | ||
16 | 4 files changed, 8 insertions(+), 8 deletions(-) | ||
16 | 17 | ||
17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 18 | diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h |
18 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/misc/sifive_u_otp.c | 20 | --- a/include/hw/riscv/numa.h |
20 | +++ b/hw/misc/sifive_u_otp.c | 21 | +++ b/include/hw/riscv/numa.h |
21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 22 | @@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, |
22 | 23 | * @ms: pointer to machine state | |
23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { | 24 | * @socket_id: socket index |
24 | error_setg(errp, "failed to read the initial flash content"); | 25 | * |
25 | + return; | 26 | - * Write NUMA distance matrix in FDT for given machine |
27 | + * Write NUMA distance matrix in MachineState->fdt | ||
28 | */ | ||
29 | -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); | ||
30 | +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); | ||
31 | |||
32 | CpuInstanceProperties | ||
33 | riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); | ||
34 | diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/riscv/numa.c | ||
37 | +++ b/hw/riscv/numa.c | ||
38 | @@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, | ||
39 | } | ||
40 | } | ||
41 | |||
42 | -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) | ||
43 | +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) | ||
44 | { | ||
45 | int i, j, idx; | ||
46 | uint32_t *dist_matrix, dist_matrix_size; | ||
47 | @@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) | ||
26 | } | 48 | } |
27 | } | 49 | } |
50 | |||
51 | - qemu_fdt_add_subnode(fdt, "/distance-map"); | ||
52 | - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", | ||
53 | + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); | ||
54 | + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", | ||
55 | "numa-distance-map-v1"); | ||
56 | - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | ||
57 | + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", | ||
58 | dist_matrix, dist_matrix_size); | ||
59 | g_free(dist_matrix); | ||
28 | } | 60 | } |
29 | -} | 61 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c |
30 | - | 62 | index XXXXXXX..XXXXXXX 100644 |
31 | -static void sifive_u_otp_reset(DeviceState *dev) | 63 | --- a/hw/riscv/spike.c |
32 | -{ | 64 | +++ b/hw/riscv/spike.c |
33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); | 65 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, |
34 | 66 | g_free(clust_name); | |
35 | /* Initialize all fuses' initial value to 0xFFs */ | 67 | } |
36 | memset(s->fuse, 0xff, sizeof(s->fuse)); | 68 | |
37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | 69 | - riscv_socket_fdt_write_distance_matrix(mc, fdt); |
38 | serial_data = s->serial; | 70 | + riscv_socket_fdt_write_distance_matrix(mc); |
39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | 71 | |
40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 72 | qemu_fdt_add_subnode(fdt, "/chosen"); |
41 | - error_report("write error index<%d>", index); | 73 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); |
42 | + error_setg(errp, "failed to write index<%d>", index); | 74 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
43 | + return; | 75 | index XXXXXXX..XXXXXXX 100644 |
44 | } | 76 | --- a/hw/riscv/virt.c |
45 | 77 | +++ b/hw/riscv/virt.c | |
46 | serial_data = ~(s->serial); | 78 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, |
47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | ||
48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | ||
49 | - error_report("write error index<%d>", index + 1); | ||
50 | + error_setg(errp, "failed to write index<%d>", index + 1); | ||
51 | + return; | ||
52 | } | 79 | } |
53 | } | 80 | } |
54 | 81 | ||
55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) | 82 | - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); |
56 | 83 | + riscv_socket_fdt_write_distance_matrix(mc); | |
57 | device_class_set_props(dc, sifive_u_otp_properties); | ||
58 | dc->realize = sifive_u_otp_realize; | ||
59 | - dc->reset = sifive_u_otp_reset; | ||
60 | } | 84 | } |
61 | 85 | ||
62 | static const TypeInfo sifive_u_otp_info = { | 86 | static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, |
63 | -- | 87 | -- |
64 | 2.31.1 | 88 | 2.39.0 |
65 | |||
66 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Bresticker <abrestic@rivosinc.com> | ||
1 | 2 | ||
3 | The current logic attempts to shift the VS-level bits into their correct | ||
4 | position in mip while leaving the remaining bits in-tact. This is both | ||
5 | pointless and likely incorrect since one would expect that any new, future | ||
6 | VS-level interrupts will get their own position in mip rather than sharing | ||
7 | with their (H)S-level equivalent. Fix this, and make the logic more | ||
8 | readable, by just making off the VS-level bits and shifting them into | ||
9 | position. | ||
10 | |||
11 | This also fixes reads of vsip, which would only ever report vsip.VSSIP | ||
12 | since the non-writable bits got masked off as well. | ||
13 | |||
14 | Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32") | ||
15 | Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> | ||
16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com> | ||
18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | --- | ||
20 | target/riscv/csr.c | 35 +++++++++++------------------------ | ||
21 | 1 file changed, 11 insertions(+), 24 deletions(-) | ||
22 | |||
23 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/riscv/csr.c | ||
26 | +++ b/target/riscv/csr.c | ||
27 | @@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, | ||
28 | uint64_t new_val, uint64_t wr_mask) | ||
29 | { | ||
30 | RISCVException ret; | ||
31 | - uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; | ||
32 | + uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; | ||
33 | |||
34 | /* Bring VS-level bits to correct position */ | ||
35 | - vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); | ||
36 | - new_val &= ~(VS_MODE_INTERRUPTS >> 1); | ||
37 | - new_val |= vsbits << 1; | ||
38 | - vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); | ||
39 | - wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); | ||
40 | - wr_mask |= vsbits << 1; | ||
41 | + new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; | ||
42 | + wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; | ||
43 | |||
44 | ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); | ||
45 | if (ret_val) { | ||
46 | - rval &= mask; | ||
47 | - vsbits = rval & VS_MODE_INTERRUPTS; | ||
48 | - rval &= ~VS_MODE_INTERRUPTS; | ||
49 | - *ret_val = rval | (vsbits >> 1); | ||
50 | + *ret_val = (rval & mask) >> 1; | ||
51 | } | ||
52 | |||
53 | return ret; | ||
54 | @@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, | ||
55 | uint64_t new_val, uint64_t wr_mask) | ||
56 | { | ||
57 | RISCVException ret; | ||
58 | - uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; | ||
59 | + uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; | ||
60 | |||
61 | /* Bring VS-level bits to correct position */ | ||
62 | - vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); | ||
63 | - new_val &= ~(VS_MODE_INTERRUPTS >> 1); | ||
64 | - new_val |= vsbits << 1; | ||
65 | - vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); | ||
66 | - wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); | ||
67 | - wr_mask |= vsbits << 1; | ||
68 | - | ||
69 | - ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); | ||
70 | + new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; | ||
71 | + wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; | ||
72 | + | ||
73 | + ret = rmw_mip64(env, csrno, &rval, new_val, | ||
74 | + wr_mask & mask & vsip_writable_mask); | ||
75 | if (ret_val) { | ||
76 | - rval &= mask; | ||
77 | - vsbits = rval & VS_MODE_INTERRUPTS; | ||
78 | - rval &= ~VS_MODE_INTERRUPTS; | ||
79 | - *ret_val = rval | (vsbits >> 1); | ||
80 | + *ret_val = (rval & mask) >> 1; | ||
81 | } | ||
82 | |||
83 | return ret; | ||
84 | -- | ||
85 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Bresticker <abrestic@rivosinc.com> | ||
1 | 2 | ||
3 | Per the AIA specification, writes to stimecmp from VS level should | ||
4 | trap when hvictl.VTI is set since the write may cause vsip.STIP to | ||
5 | become unset. | ||
6 | |||
7 | Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") | ||
8 | Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | target/riscv/csr.c | 6 ++++++ | ||
14 | 1 file changed, 6 insertions(+) | ||
15 | |||
16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/riscv/csr.c | ||
19 | +++ b/target/riscv/csr.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, | ||
21 | RISCVCPU *cpu = env_archcpu(env); | ||
22 | |||
23 | if (riscv_cpu_virt_enabled(env)) { | ||
24 | + if (env->hvictl & HVICTL_VTI) { | ||
25 | + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
26 | + } | ||
27 | return write_vstimecmp(env, csrno, val); | ||
28 | } | ||
29 | |||
30 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, | ||
31 | RISCVCPU *cpu = env_archcpu(env); | ||
32 | |||
33 | if (riscv_cpu_virt_enabled(env)) { | ||
34 | + if (env->hvictl & HVICTL_VTI) { | ||
35 | + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
36 | + } | ||
37 | return write_vstimecmph(env, csrno, val); | ||
38 | } | ||
39 | |||
40 | -- | ||
41 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | We failed to update this with the w^x split, so misses the fact | ||
4 | that true pc-relative offsets are usually small. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | tcg/riscv/tcg-target.c.inc | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tcg/riscv/tcg-target.c.inc | ||
17 | +++ b/tcg/riscv/tcg-target.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, | ||
19 | intptr_t imm12 = sextreg(offset, 0, 12); | ||
20 | |||
21 | if (offset != imm12) { | ||
22 | - intptr_t diff = offset - (uintptr_t)s->code_ptr; | ||
23 | + intptr_t diff = tcg_pcrel_diff(s, (void *)offset); | ||
24 | |||
25 | if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { | ||
26 | imm12 = sextreg(diff, 0, 12); | ||
27 | -- | ||
28 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | The new helper always validates the contents of FRM, even | ||
4 | if the new rounding mode is not DYN. This is required by | ||
5 | the vector unit. | ||
6 | |||
7 | Track whether we've validated FRM separately from whether | ||
8 | we've updated fp_status with a given rounding mode, so that | ||
9 | we can elide calls correctly. | ||
10 | |||
11 | This partially reverts d6c4d3f2a69 which attempted the to do | ||
12 | the same thing, but with two calls to gen_set_rm(), which is | ||
13 | both inefficient and tickles an assertion in decode_save_opc. | ||
14 | |||
15 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
18 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org> | ||
20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
21 | --- | ||
22 | target/riscv/helper.h | 1 + | ||
23 | target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ | ||
24 | target/riscv/translate.c | 19 +++++++++++++ | ||
25 | target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- | ||
26 | 4 files changed, 61 insertions(+), 20 deletions(-) | ||
27 | |||
28 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/riscv/helper.h | ||
31 | +++ b/target/riscv/helper.h | ||
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) | ||
33 | |||
34 | /* Floating Point - rounding mode */ | ||
35 | DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) | ||
36 | +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) | ||
37 | DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) | ||
38 | |||
39 | /* Floating Point - fused */ | ||
40 | diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/riscv/fpu_helper.c | ||
43 | +++ b/target/riscv/fpu_helper.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) | ||
45 | set_float_rounding_mode(softrm, &env->fp_status); | ||
46 | } | ||
47 | |||
48 | +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) | ||
49 | +{ | ||
50 | + int softrm; | ||
51 | + | ||
52 | + /* Always validate frm, even if rm != DYN. */ | ||
53 | + if (unlikely(env->frm >= 5)) { | ||
54 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
55 | + } | ||
56 | + if (rm == RISCV_FRM_DYN) { | ||
57 | + rm = env->frm; | ||
58 | + } | ||
59 | + switch (rm) { | ||
60 | + case RISCV_FRM_RNE: | ||
61 | + softrm = float_round_nearest_even; | ||
62 | + break; | ||
63 | + case RISCV_FRM_RTZ: | ||
64 | + softrm = float_round_to_zero; | ||
65 | + break; | ||
66 | + case RISCV_FRM_RDN: | ||
67 | + softrm = float_round_down; | ||
68 | + break; | ||
69 | + case RISCV_FRM_RUP: | ||
70 | + softrm = float_round_up; | ||
71 | + break; | ||
72 | + case RISCV_FRM_RMM: | ||
73 | + softrm = float_round_ties_away; | ||
74 | + break; | ||
75 | + case RISCV_FRM_ROD: | ||
76 | + softrm = float_round_to_odd; | ||
77 | + break; | ||
78 | + default: | ||
79 | + g_assert_not_reached(); | ||
80 | + } | ||
81 | + | ||
82 | + set_float_rounding_mode(softrm, &env->fp_status); | ||
83 | +} | ||
84 | + | ||
85 | void helper_set_rod_rounding_mode(CPURISCVState *env) | ||
86 | { | ||
87 | set_float_rounding_mode(float_round_to_odd, &env->fp_status); | ||
88 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/riscv/translate.c | ||
91 | +++ b/target/riscv/translate.c | ||
92 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
93 | bool pm_base_enabled; | ||
94 | /* Use icount trigger for native debug */ | ||
95 | bool itrigger; | ||
96 | + /* FRM is known to contain a valid value. */ | ||
97 | + bool frm_valid; | ||
98 | /* TCG of the current insn_start */ | ||
99 | TCGOp *insn_start; | ||
100 | } DisasContext; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm) | ||
102 | gen_helper_set_rod_rounding_mode(cpu_env); | ||
103 | return; | ||
104 | } | ||
105 | + if (rm == RISCV_FRM_DYN) { | ||
106 | + /* The helper will return only if frm valid. */ | ||
107 | + ctx->frm_valid = true; | ||
108 | + } | ||
109 | |||
110 | /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ | ||
111 | decode_save_opc(ctx); | ||
112 | gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); | ||
113 | } | ||
114 | |||
115 | +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) | ||
116 | +{ | ||
117 | + if (ctx->frm == rm && ctx->frm_valid) { | ||
118 | + return; | ||
119 | + } | ||
120 | + ctx->frm = rm; | ||
121 | + ctx->frm_valid = true; | ||
122 | + | ||
123 | + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ | ||
124 | + decode_save_opc(ctx); | ||
125 | + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); | ||
126 | +} | ||
127 | + | ||
128 | static int ex_plus_1(DisasContext *ctx, int nf) | ||
129 | { | ||
130 | return nf + 1; | ||
131 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
134 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
135 | @@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a, | ||
136 | int rm) | ||
137 | { | ||
138 | if (checkfn(s, a)) { | ||
139 | - if (rm != RISCV_FRM_DYN) { | ||
140 | - gen_set_rm(s, RISCV_FRM_DYN); | ||
141 | - } | ||
142 | - | ||
143 | uint32_t data = 0; | ||
144 | TCGLabel *over = gen_new_label(); | ||
145 | - gen_set_rm(s, rm); | ||
146 | + gen_set_rm_chkfrm(s, rm); | ||
147 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
148 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
149 | |||
150 | @@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) | ||
151 | static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
152 | { \ | ||
153 | if (CHECK(s, a)) { \ | ||
154 | - if (FRM != RISCV_FRM_DYN) { \ | ||
155 | - gen_set_rm(s, RISCV_FRM_DYN); \ | ||
156 | - } \ | ||
157 | - \ | ||
158 | uint32_t data = 0; \ | ||
159 | static gen_helper_gvec_3_ptr * const fns[2] = { \ | ||
160 | gen_helper_##HELPER##_h, \ | ||
161 | gen_helper_##HELPER##_w, \ | ||
162 | }; \ | ||
163 | TCGLabel *over = gen_new_label(); \ | ||
164 | - gen_set_rm(s, FRM); \ | ||
165 | + gen_set_rm_chkfrm(s, FRM); \ | ||
166 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
167 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
168 | \ | ||
169 | @@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) | ||
170 | static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
171 | { \ | ||
172 | if (CHECK(s, a)) { \ | ||
173 | - if (FRM != RISCV_FRM_DYN) { \ | ||
174 | - gen_set_rm(s, RISCV_FRM_DYN); \ | ||
175 | - } \ | ||
176 | - \ | ||
177 | uint32_t data = 0; \ | ||
178 | static gen_helper_gvec_3_ptr * const fns[2] = { \ | ||
179 | gen_helper_##HELPER##_h, \ | ||
180 | gen_helper_##HELPER##_w, \ | ||
181 | }; \ | ||
182 | TCGLabel *over = gen_new_label(); \ | ||
183 | - gen_set_rm(s, FRM); \ | ||
184 | + gen_set_rm_chkfrm(s, FRM); \ | ||
185 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
186 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
187 | \ | ||
188 | @@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) | ||
189 | static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
190 | { \ | ||
191 | if (opxfv_narrow_check(s, a)) { \ | ||
192 | - if (FRM != RISCV_FRM_DYN) { \ | ||
193 | - gen_set_rm(s, RISCV_FRM_DYN); \ | ||
194 | - } \ | ||
195 | - \ | ||
196 | uint32_t data = 0; \ | ||
197 | static gen_helper_gvec_3_ptr * const fns[3] = { \ | ||
198 | gen_helper_##HELPER##_b, \ | ||
199 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
200 | gen_helper_##HELPER##_w, \ | ||
201 | }; \ | ||
202 | TCGLabel *over = gen_new_label(); \ | ||
203 | - gen_set_rm(s, FRM); \ | ||
204 | + gen_set_rm_chkfrm(s, FRM); \ | ||
205 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
206 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
207 | \ | ||
208 | -- | ||
209 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | The only setting of RISCV_FRM_ROD is from the vector unit, | ||
4 | and now handled by helper_set_rounding_mode_chkfrm. | ||
5 | This helper is now unused. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | target/riscv/helper.h | 1 - | ||
14 | target/riscv/fpu_helper.c | 5 ----- | ||
15 | target/riscv/translate.c | 4 ---- | ||
16 | 3 files changed, 10 deletions(-) | ||
17 | |||
18 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/helper.h | ||
21 | +++ b/target/riscv/helper.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) | ||
23 | /* Floating Point - rounding mode */ | ||
24 | DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) | ||
25 | DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) | ||
26 | -DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) | ||
27 | |||
28 | /* Floating Point - fused */ | ||
29 | DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) | ||
30 | diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/riscv/fpu_helper.c | ||
33 | +++ b/target/riscv/fpu_helper.c | ||
34 | @@ -XXX,XX +XXX,XX @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) | ||
35 | set_float_rounding_mode(softrm, &env->fp_status); | ||
36 | } | ||
37 | |||
38 | -void helper_set_rod_rounding_mode(CPURISCVState *env) | ||
39 | -{ | ||
40 | - set_float_rounding_mode(float_round_to_odd, &env->fp_status); | ||
41 | -} | ||
42 | - | ||
43 | static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, | ||
44 | uint64_t rs3, int flags) | ||
45 | { | ||
46 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/riscv/translate.c | ||
49 | +++ b/target/riscv/translate.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm) | ||
51 | } | ||
52 | ctx->frm = rm; | ||
53 | |||
54 | - if (rm == RISCV_FRM_ROD) { | ||
55 | - gen_helper_set_rod_rounding_mode(cpu_env); | ||
56 | - return; | ||
57 | - } | ||
58 | if (rm == RISCV_FRM_DYN) { | ||
59 | /* The helper will return only if frm valid. */ | ||
60 | ctx->frm_valid = true; | ||
61 | -- | ||
62 | 2.39.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") | ||
4 | moved the initialization of fw_cfg to the virt_machine_done() callback. | ||
5 | |||
6 | Problem is that the validation of fw_cfg by devices such as ramfb is | ||
7 | done before the machine done notifier is called. Moving create_fw_cfg() | ||
8 | to machine_done() results in QEMU failing to boot when using a ramfb | ||
9 | device: | ||
10 | |||
11 | ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio | ||
12 | qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA | ||
13 | |||
14 | The fix is simple: move create_fw_cfg() config back to | ||
15 | virt_machine_init(). This happens to be the same way the ARM 'virt' | ||
16 | machine deals with fw_cfg (see machvirt_init() and virt_machine_done() | ||
17 | in hw/arm/virt.c), so we're keeping consistency with how other machines | ||
18 | handle this device. | ||
19 | |||
20 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 | ||
21 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
22 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
23 | Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com> | ||
24 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
25 | --- | ||
26 | hw/riscv/virt.c | 14 +++++++------- | ||
27 | 1 file changed, 7 insertions(+), 7 deletions(-) | ||
28 | |||
29 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/riscv/virt.c | ||
32 | +++ b/hw/riscv/virt.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
34 | firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | ||
35 | start_addr, NULL); | ||
36 | |||
37 | - /* | ||
38 | - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | ||
39 | - * tree cannot be altered and we get FDT_ERR_NOSPACE. | ||
40 | - */ | ||
41 | - s->fw_cfg = create_fw_cfg(machine); | ||
42 | - rom_set_fw(s->fw_cfg); | ||
43 | - | ||
44 | if (drive_get(IF_PFLASH, 0, 1)) { | ||
45 | /* | ||
46 | * S-mode FW like EDK2 will be kept in second plash (unit 1). | ||
47 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
48 | memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, | ||
49 | mask_rom); | ||
50 | |||
51 | + /* | ||
52 | + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the | ||
53 | + * device tree cannot be altered and we get FDT_ERR_NOSPACE. | ||
54 | + */ | ||
55 | + s->fw_cfg = create_fw_cfg(machine); | ||
56 | + rom_set_fw(s->fw_cfg); | ||
57 | + | ||
58 | /* SiFive Test MMIO device */ | ||
59 | sifive_test_create(memmap[VIRT_TEST].base); | ||
60 | |||
61 | -- | ||
62 | 2.39.0 | diff view generated by jsdifflib |