[PULL 0/2] riscv-to-apply queue
[PULL v2 00/22] riscv-to-apply queue
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
3
The following changes since commit 99d6b11b5b44d7dd64f4cb1973184e40a4a174f8:
4
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Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
5
Merge tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-09-26 13:38:26 -0400)
6
6
7
are available in the Git repository at:
7
are available in the Git repository at:
8
8
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
9
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20220927
10
10
11
for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
11
for you to fetch changes up to a3ab69f9f6c000481c439923d16416b8941d5b37:
12
12
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
13
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered (2022-09-27 11:23:57 +1000)
14
14
15
----------------------------------------------------------------
15
----------------------------------------------------------------
16
Seventh RISC-V PR for QEMU 6.2
16
Second RISC-V PR for QEMU 7.2
17
17
18
- Deprecate IF_NONE for SiFive OTP
18
* Fixup typos and register addresses for Ibex SPI
19
- Don't reset SiFive OTP content
19
* Cleanup the RISC-V virt machine documentation
20
* Remove the sideleg and sedeleg CSR macros
21
* Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
22
* Remove fixed numbering from GDB xml feature files
23
* Allow setting the resetvec for the OpenTitan machine
24
* Check the correct exception cause in vector GDB stub
25
* Fix inheritance of SiFiveEState
26
* Improvements to the RISC-V debugger spec
27
* Simplify some vector code
20
28
21
----------------------------------------------------------------
29
----------------------------------------------------------------
22
Philippe Mathieu-Daudé (1):
30
Alex Bennée (1):
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
31
docs/system: clean up code escape for riscv virt platform
24
32
25
Thomas Huth (1):
33
Alistair Francis (3):
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
34
target/riscv: Set the CPU resetvec directly
35
hw/riscv: opentitan: Fixup resetvec
36
hw/riscv: opentitan: Expose the resetvec as a SoC property
27
37
28
docs/about/deprecated.rst | 6 ++++++
38
Andrew Burgess (2):
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
39
target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml
30
2 files changed, 19 insertions(+), 9 deletions(-)
40
target/riscv: remove fixed numbering from GDB xml feature files
31
41
42
Bernhard Beschow (1):
43
hw/riscv/sifive_e: Fix inheritance of SiFiveEState
44
45
Frank Chang (9):
46
target/riscv: Check the correct exception cause in vector GDB stub
47
target/riscv: debug: Determine the trigger type from tdata1.type
48
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
49
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
50
target/riscv: debug: Restrict the range of tselect value can be written
51
target/riscv: debug: Introduce tinfo CSR
52
target/riscv: debug: Create common trigger actions function
53
target/riscv: debug: Check VU/VS modes for type 2 trigger
54
target/riscv: debug: Add initial support of type 6 trigger
55
56
Rahul Pathak (1):
57
target/riscv: Remove sideleg and sedeleg
58
59
Weiwei Li (1):
60
target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
61
62
Wilfred Mallawa (2):
63
hw/ssi: ibex_spi: fixup typos in ibex_spi_host
64
hw/ssi: ibex_spi: update reg addr
65
66
Yang Liu (2):
67
target/riscv: rvv-1.0: Simplify vfwredsum code
68
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
69
70
docs/system/riscv/virt.rst | 13 +-
71
include/hw/riscv/opentitan.h | 2 +
72
include/hw/riscv/sifive_e.h | 3 +-
73
target/riscv/cpu.h | 9 +-
74
target/riscv/cpu_bits.h | 3 +-
75
target/riscv/debug.h | 55 ++--
76
target/riscv/helper.h | 15 +-
77
target/riscv/insn32.decode | 6 +-
78
disas/riscv.c | 2 -
79
hw/riscv/opentitan.c | 8 +-
80
hw/ssi/ibex_spi_host.c | 8 +-
81
target/riscv/cpu.c | 13 +-
82
target/riscv/csr.c | 23 +-
83
target/riscv/debug.c | 484 +++++++++++++++++++++++++-------
84
target/riscv/gdbstub.c | 36 +--
85
target/riscv/machine.c | 26 +-
86
target/riscv/vector_helper.c | 69 ++---
87
target/riscv/insn_trans/trans_rvv.c.inc | 6 +-
88
gdb-xml/riscv-32bit-cpu.xml | 6 +-
89
gdb-xml/riscv-32bit-fpu.xml | 10 +-
90
gdb-xml/riscv-64bit-cpu.xml | 6 +-
91
gdb-xml/riscv-64bit-fpu.xml | 10 +-
92
22 files changed, 531 insertions(+), 282 deletions(-)
diff view generated by jsdifflib
New patch
[PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host
1
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
1
2
3
This patch fixes up minor typos in ibex_spi_host
4
5
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
8
Message-Id: <20220823061201.132342-2-wilfred.mallawa@opensource.wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/ssi/ibex_spi_host.c | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/ssi/ibex_spi_host.c
17
+++ b/hw/ssi/ibex_spi_host.c
18
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
19
& R_INTR_STATE_SPI_EVENT_MASK;
20
int err_irq = 0, event_irq = 0;
21
22
- /* Error IRQ enabled and Error IRQ Cleared*/
23
+ /* Error IRQ enabled and Error IRQ Cleared */
24
if (error_en && !err_pending) {
25
/* Event enabled, Interrupt Test Error */
26
if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
27
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
28
case IBEX_SPI_HOST_TXDATA:
29
/*
30
* This is a hardware `feature` where
31
- * the first word written TXDATA after init is omitted entirely
32
+ * the first word written to TXDATA after init is omitted entirely
33
*/
34
if (s->init_status) {
35
s->init_status = false;
36
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
37
break;
38
case IBEX_SPI_HOST_ERROR_STATUS:
39
/*
40
- * Indicates that any errors that have occurred.
41
+ * Indicates any errors that have occurred.
42
* When an error occurs, the corresponding bit must be cleared
43
* here before issuing any further commands
44
*/
45
--
46
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 02/22] hw/ssi: ibex_spi: update reg addr
1
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
1
2
3
Updates the `EVENT_ENABLE` register to offset `0x34` as per
4
OpenTitan spec [1].
5
6
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
7
8
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/ssi/ibex_spi_host.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/ibex_spi_host.c
19
+++ b/hw/ssi/ibex_spi_host.c
20
@@ -XXX,XX +XXX,XX @@ REG32(ERROR_STATUS, 0x30)
21
FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
22
FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
23
FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
24
-REG32(EVENT_ENABLE, 0x30)
25
+REG32(EVENT_ENABLE, 0x34)
26
FIELD(EVENT_ENABLE, RXFULL, 0, 1)
27
FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
28
FIELD(EVENT_ENABLE, RXWM, 2, 1)
29
--
30
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 03/22] docs/system: clean up code escape for riscv virt platform
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
The example code is rendered slightly mangled due to missing code
4
block. Properly escape the code block and add shell prompt and qemu to
5
fit in with the other examples on the page.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
docs/system/riscv/virt.rst | 13 +++++++++----
13
1 file changed, 9 insertions(+), 4 deletions(-)
14
15
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/riscv/virt.rst
18
+++ b/docs/system/riscv/virt.rst
19
@@ -XXX,XX +XXX,XX @@ Enabling TPM
20
21
A TPM device can be connected to the virt board by following the steps below.
22
23
-First launch the TPM emulator
24
+First launch the TPM emulator:
25
26
- swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
27
+.. code-block:: bash
28
+
29
+ $ swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
30
--ctrl type=unixio,path=swtpm-sock
31
32
-Then launch QEMU with:
33
+Then launch QEMU with some additional arguments to link a TPM device to the backend:
34
+
35
+.. code-block:: bash
36
37
- ...
38
+ $ qemu-system-riscv64 \
39
+ ... other args .... \
40
-chardev socket,id=chrtpm,path=swtpm-sock \
41
-tpmdev emulator,id=tpm0,chardev=chrtpm \
42
-device tpm-tis-device,tpmdev=tpm0
43
--
44
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 04/22] target/riscv: Remove sideleg and sedeleg
1
From: Rahul Pathak <rpathak@ventanamicro.com>
1
2
3
sideleg and sedeleg csrs are not part of riscv isa spec
4
anymore, these csrs were part of N extension which
5
is removed from the riscv isa specification.
6
7
These commits removed all traces of these csrs from
8
riscv spec (https://github.com/riscv/riscv-isa-manual) -
9
10
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
11
commit b6cade07034d ("Remove N extension chapter for now")
12
13
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
14
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/cpu_bits.h | 2 --
20
disas/riscv.c | 2 --
21
2 files changed, 4 deletions(-)
22
23
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/cpu_bits.h
26
+++ b/target/riscv/cpu_bits.h
27
@@ -XXX,XX +XXX,XX @@
28
29
/* Supervisor Trap Setup */
30
#define CSR_SSTATUS 0x100
31
-#define CSR_SEDELEG 0x102
32
-#define CSR_SIDELEG 0x103
33
#define CSR_SIE 0x104
34
#define CSR_STVEC 0x105
35
#define CSR_SCOUNTEREN 0x106
36
diff --git a/disas/riscv.c b/disas/riscv.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/disas/riscv.c
39
+++ b/disas/riscv.c
40
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
41
case 0x0043: return "utval";
42
case 0x0044: return "uip";
43
case 0x0100: return "sstatus";
44
- case 0x0102: return "sedeleg";
45
- case 0x0103: return "sideleg";
46
case 0x0104: return "sie";
47
case 0x0105: return "stvec";
48
case 0x0106: return "scounteren";
49
--
50
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- modify check for mcounteren to work in all less-privilege mode
4
- modify check for scounteren to work only when S mode is enabled
5
- distinguish the exception type raised by check for scounteren between U
6
and VU mode
7
8
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/csr.c | 13 +++++++++----
15
1 file changed, 9 insertions(+), 4 deletions(-)
16
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
21
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
22
23
skip_ext_pmu_check:
24
25
- if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) ||
26
- ((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask)))) {
27
+ if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
28
return RISCV_EXCP_ILLEGAL_INST;
29
}
30
31
if (riscv_cpu_virt_enabled(env)) {
32
- if (!get_field(env->hcounteren, ctr_mask) &&
33
- get_field(env->mcounteren, ctr_mask)) {
34
+ if (!get_field(env->hcounteren, ctr_mask) ||
35
+ (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
36
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
37
}
38
}
39
+
40
+ if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
41
+ !get_field(env->scounteren, ctr_mask)) {
42
+ return RISCV_EXCP_ILLEGAL_INST;
43
+ }
44
+
45
#endif
46
return RISCV_EXCP_NONE;
47
}
48
--
49
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml
1
From: Andrew Burgess <aburgess@redhat.com>
1
2
3
While testing some changes to GDB's handling for the RISC-V registers
4
fcsr, fflags, and frm, I spotted that QEMU includes these registers
5
twice in the target description it sends to GDB, once in the fpu
6
feature, and once in the csr feature.
7
8
Right now things basically work OK, QEMU maps these registers onto two
9
different register numbers, e.g. fcsr maps to both 68 and 73, and GDB
10
can use either of these to access the register.
11
12
However, GDB's target descriptions don't really work this way, each
13
register should appear just once in a target description, mapping the
14
register name onto the number GDB should use when accessing the
15
register on the target. Duplicate register names actually result in
16
duplicate registers on the GDB side, however, as the registers have
17
the same name, the user can only access one of these registers.
18
19
Currently GDB has a hack in place, specifically for RISC-V, to spot
20
the duplicate copies of these three registers, and hide them from the
21
user, ensuring the user only ever sees a single copy of each.
22
23
In this commit I propose fixing this issue on the QEMU side, and in
24
the process, simplify the fpu register handling a little.
25
26
I think we should, remove fflags, frm, and fcsr from the two (32-bit
27
and 64-bit) fpu feature xml files. These files will only contain the
28
32 core floating point register f0 to f31. The fflags, frm, and fcsr
29
registers will continue to be advertised in the csr feature as they
30
currently are.
31
32
With that change made, I will simplify riscv_gdb_get_fpu and
33
riscv_gdb_set_fpu, removing the extra handling for the 3 status
34
registers.
35
36
Signed-off-by: Andrew Burgess <aburgess@redhat.com>
37
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
38
Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com>
39
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
40
---
41
target/riscv/gdbstub.c | 32 ++------------------------------
42
gdb-xml/riscv-32bit-fpu.xml | 4 ----
43
gdb-xml/riscv-64bit-fpu.xml | 4 ----
44
3 files changed, 2 insertions(+), 38 deletions(-)
45
46
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/gdbstub.c
49
+++ b/target/riscv/gdbstub.c
50
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
51
if (env->misa_ext & RVF) {
52
return gdb_get_reg32(buf, env->fpr[n]);
53
}
54
- /* there is hole between ft11 and fflags in fpu.xml */
55
- } else if (n < 36 && n > 32) {
56
- target_ulong val = 0;
57
- int result;
58
- /*
59
- * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
60
- * register 33, so we recalculate the map index.
61
- * This also works for CSR_FRM and CSR_FCSR.
62
- */
63
- result = riscv_csrrw_debug(env, n - 32, &val,
64
- 0, 0);
65
- if (result == RISCV_EXCP_NONE) {
66
- return gdb_get_regl(buf, val);
67
- }
68
}
69
return 0;
70
}
71
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
72
if (n < 32) {
73
env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
74
return sizeof(uint64_t);
75
- /* there is hole between ft11 and fflags in fpu.xml */
76
- } else if (n < 36 && n > 32) {
77
- target_ulong val = ldtul_p(mem_buf);
78
- int result;
79
- /*
80
- * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
81
- * register 33, so we recalculate the map index.
82
- * This also works for CSR_FRM and CSR_FCSR.
83
- */
84
- result = riscv_csrrw_debug(env, n - 32, NULL,
85
- val, -1);
86
- if (result == RISCV_EXCP_NONE) {
87
- return sizeof(target_ulong);
88
- }
89
}
90
return 0;
91
}
92
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
93
CPURISCVState *env = &cpu->env;
94
if (env->misa_ext & RVD) {
95
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
96
- 36, "riscv-64bit-fpu.xml", 0);
97
+ 32, "riscv-64bit-fpu.xml", 0);
98
} else if (env->misa_ext & RVF) {
99
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
100
- 36, "riscv-32bit-fpu.xml", 0);
101
+ 32, "riscv-32bit-fpu.xml", 0);
102
}
103
if (env->misa_ext & RVV) {
104
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
105
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
106
index XXXXXXX..XXXXXXX 100644
107
--- a/gdb-xml/riscv-32bit-fpu.xml
108
+++ b/gdb-xml/riscv-32bit-fpu.xml
109
@@ -XXX,XX +XXX,XX @@
110
<reg name="ft9" bitsize="32" type="ieee_single"/>
111
<reg name="ft10" bitsize="32" type="ieee_single"/>
112
<reg name="ft11" bitsize="32" type="ieee_single"/>
113
-
114
- <reg name="fflags" bitsize="32" type="int" regnum="66"/>
115
- <reg name="frm" bitsize="32" type="int" regnum="67"/>
116
- <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
117
</feature>
118
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
119
index XXXXXXX..XXXXXXX 100644
120
--- a/gdb-xml/riscv-64bit-fpu.xml
121
+++ b/gdb-xml/riscv-64bit-fpu.xml
122
@@ -XXX,XX +XXX,XX @@
123
<reg name="ft9" bitsize="64" type="riscv_double"/>
124
<reg name="ft10" bitsize="64" type="riscv_double"/>
125
<reg name="ft11" bitsize="64" type="riscv_double"/>
126
-
127
- <reg name="fflags" bitsize="32" type="int" regnum="66"/>
128
- <reg name="frm" bitsize="32" type="int" regnum="67"/>
129
- <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
130
</feature>
131
--
132
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files
1
From: Andrew Burgess <aburgess@redhat.com>
1
2
3
The fixed register numbering in the various GDB feature files for
4
RISC-V only exists because these files were originally copied from the
5
GDB source tree.
6
7
However, the fixed numbering only exists in the GDB source tree so
8
that GDB, when it connects to a target that doesn't provide a target
9
description, will use a specific numbering scheme.
10
11
That numbering scheme is designed to be compatible with the first
12
versions of QEMU (for RISC-V), that didn't send a target description,
13
and relied on a fixed numbering scheme.
14
15
Because of the way that QEMU manages its target descriptions,
16
recording the number of registers in each feature, and just relying on
17
GDB's numbering starting from 0, then I propose that we remove all the
18
fixed numbering from the RISC-V feature xml files, and just rely on
19
the standard numbering scheme. Plenty of other targets manage their
20
xml files this way, e.g. ARM, AArch64, Loongarch, m68k, rx, and s390.
21
22
Signed-off-by: Andrew Burgess <aburgess@redhat.com>
23
Acked-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
25
Message-Id: <6069395f90e6fc24dac92197be815fedf42f5974.1661934573.git.aburgess@redhat.com>
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
---
28
gdb-xml/riscv-32bit-cpu.xml | 6 +-----
29
gdb-xml/riscv-32bit-fpu.xml | 6 +-----
30
gdb-xml/riscv-64bit-cpu.xml | 6 +-----
31
gdb-xml/riscv-64bit-fpu.xml | 6 +-----
32
4 files changed, 4 insertions(+), 20 deletions(-)
33
34
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
35
index XXXXXXX..XXXXXXX 100644
36
--- a/gdb-xml/riscv-32bit-cpu.xml
37
+++ b/gdb-xml/riscv-32bit-cpu.xml
38
@@ -XXX,XX +XXX,XX @@
39
are permitted in any medium without royalty provided the copyright
40
notice and this notice are preserved. -->
41
42
-<!-- Register numbers are hard-coded in order to maintain backward
43
- compatibility with older versions of tools that didn't use xml
44
- register descriptions. -->
45
-
46
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
47
<feature name="org.gnu.gdb.riscv.cpu">
48
- <reg name="zero" bitsize="32" type="int" regnum="0"/>
49
+ <reg name="zero" bitsize="32" type="int"/>
50
<reg name="ra" bitsize="32" type="code_ptr"/>
51
<reg name="sp" bitsize="32" type="data_ptr"/>
52
<reg name="gp" bitsize="32" type="data_ptr"/>
53
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
54
index XXXXXXX..XXXXXXX 100644
55
--- a/gdb-xml/riscv-32bit-fpu.xml
56
+++ b/gdb-xml/riscv-32bit-fpu.xml
57
@@ -XXX,XX +XXX,XX @@
58
are permitted in any medium without royalty provided the copyright
59
notice and this notice are preserved. -->
60
61
-<!-- Register numbers are hard-coded in order to maintain backward
62
- compatibility with older versions of tools that didn't use xml
63
- register descriptions. -->
64
-
65
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
66
<feature name="org.gnu.gdb.riscv.fpu">
67
- <reg name="ft0" bitsize="32" type="ieee_single" regnum="33"/>
68
+ <reg name="ft0" bitsize="32" type="ieee_single"/>
69
<reg name="ft1" bitsize="32" type="ieee_single"/>
70
<reg name="ft2" bitsize="32" type="ieee_single"/>
71
<reg name="ft3" bitsize="32" type="ieee_single"/>
72
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
73
index XXXXXXX..XXXXXXX 100644
74
--- a/gdb-xml/riscv-64bit-cpu.xml
75
+++ b/gdb-xml/riscv-64bit-cpu.xml
76
@@ -XXX,XX +XXX,XX @@
77
are permitted in any medium without royalty provided the copyright
78
notice and this notice are preserved. -->
79
80
-<!-- Register numbers are hard-coded in order to maintain backward
81
- compatibility with older versions of tools that didn't use xml
82
- register descriptions. -->
83
-
84
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
85
<feature name="org.gnu.gdb.riscv.cpu">
86
- <reg name="zero" bitsize="64" type="int" regnum="0"/>
87
+ <reg name="zero" bitsize="64" type="int"/>
88
<reg name="ra" bitsize="64" type="code_ptr"/>
89
<reg name="sp" bitsize="64" type="data_ptr"/>
90
<reg name="gp" bitsize="64" type="data_ptr"/>
91
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
92
index XXXXXXX..XXXXXXX 100644
93
--- a/gdb-xml/riscv-64bit-fpu.xml
94
+++ b/gdb-xml/riscv-64bit-fpu.xml
95
@@ -XXX,XX +XXX,XX @@
96
are permitted in any medium without royalty provided the copyright
97
notice and this notice are preserved. -->
98
99
-<!-- Register numbers are hard-coded in order to maintain backward
100
- compatibility with older versions of tools that didn't use xml
101
- register descriptions. -->
102
-
103
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
104
<feature name="org.gnu.gdb.riscv.fpu">
105
106
@@ -XXX,XX +XXX,XX @@
107
<field name="double" type="ieee_double"/>
108
</union>
109
110
- <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
111
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
112
<reg name="ft1" bitsize="64" type="riscv_double"/>
113
<reg name="ft2" bitsize="64" type="riscv_double"/>
114
<reg name="ft3" bitsize="64" type="riscv_double"/>
115
--
116
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 08/22] target/riscv: Set the CPU resetvec directly
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
Instead of using our properties to set a config value which then might
4
be used to set the resetvec (depending on your timing), let's instead
5
just set the resetvec directly in the env struct.
6
7
This allows us to set the reset vec from the command line with:
8
-global driver=riscv.hart_array,property=resetvec,value=0x20000400
9
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-Id: <20220914101108.82571-2-alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 3 +--
16
target/riscv/cpu.c | 13 +++----------
17
target/riscv/machine.c | 6 +++---
18
3 files changed, 7 insertions(+), 15 deletions(-)
19
20
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/cpu.h
23
+++ b/target/riscv/cpu.h
24
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
25
/* This contains QEMU specific information about the virt state. */
26
target_ulong virt;
27
target_ulong geilen;
28
- target_ulong resetvec;
29
+ uint64_t resetvec;
30
31
target_ulong mhartid;
32
/*
33
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
34
bool pmp;
35
bool epmp;
36
bool debug;
37
- uint64_t resetvec;
38
39
bool short_isa_string;
40
};
41
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/riscv/cpu.c
44
+++ b/target/riscv/cpu.c
45
@@ -XXX,XX +XXX,XX @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
46
env->vext_ver = vext_ver;
47
}
48
49
-static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
50
-{
51
-#ifndef CONFIG_USER_ONLY
52
- env->resetvec = resetvec;
53
-#endif
54
-}
55
-
56
static void riscv_any_cpu_init(Object *obj)
57
{
58
CPURISCVState *env = &RISCV_CPU(obj)->env;
59
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
60
61
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
62
set_priv_version(env, PRIV_VERSION_1_10_0);
63
- set_resetvec(env, DEFAULT_RSTVEC);
64
cpu->cfg.mmu = false;
65
}
66
#endif
67
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
68
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
69
}
70
71
- set_resetvec(env, cpu->cfg.resetvec);
72
73
#ifndef CONFIG_USER_ONLY
74
if (cpu->cfg.ext_sstc) {
75
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
76
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
77
DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
78
79
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
80
+#ifndef CONFIG_USER_ONLY
81
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
82
+#endif
83
84
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
85
86
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/riscv/machine.c
89
+++ b/target/riscv/machine.c
90
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = {
91
92
const VMStateDescription vmstate_riscv_cpu = {
93
.name = "cpu",
94
- .version_id = 4,
95
- .minimum_version_id = 4,
96
+ .version_id = 5,
97
+ .minimum_version_id = 5,
98
.post_load = riscv_cpu_post_load,
99
.fields = (VMStateField[]) {
100
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
101
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
102
VMSTATE_UINT32(env.features, RISCVCPU),
103
VMSTATE_UINTTL(env.priv, RISCVCPU),
104
VMSTATE_UINTTL(env.virt, RISCVCPU),
105
- VMSTATE_UINTTL(env.resetvec, RISCVCPU),
106
+ VMSTATE_UINT64(env.resetvec, RISCVCPU),
107
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
108
VMSTATE_UINT64(env.mstatus, RISCVCPU),
109
VMSTATE_UINT64(env.mip, RISCVCPU),
110
--
111
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
The resetvec for the OpenTitan machine ended up being set to an out of
4
date value, so let's fix that and bump it to the correct start address
5
(after the boot ROM)
6
7
Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220914101108.82571-3-alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/riscv/opentitan.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/opentitan.c
18
+++ b/hw/riscv/opentitan.c
19
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
20
&error_abort);
21
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
22
&error_abort);
23
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
24
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
25
&error_abort);
26
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
27
28
--
29
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
4
QEMU we don't run the ROM code and instead just jump to the next stage.
5
This means we need to be a little more flexible about what the resetvec
6
is.
7
8
This patch allows us to set the resetvec from the command line with
9
something like this:
10
-global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
11
12
This way as the next stage changes we can update the resetvec.
13
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
include/hw/riscv/opentitan.h | 2 ++
20
hw/riscv/opentitan.c | 8 +++++++-
21
2 files changed, 9 insertions(+), 1 deletion(-)
22
23
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/riscv/opentitan.h
26
+++ b/include/hw/riscv/opentitan.h
27
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
28
IbexTimerState timer;
29
IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
30
31
+ uint32_t resetvec;
32
+
33
MemoryRegion flash_mem;
34
MemoryRegion rom;
35
MemoryRegion flash_alias;
36
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/riscv/opentitan.c
39
+++ b/hw/riscv/opentitan.c
40
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
41
&error_abort);
42
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
43
&error_abort);
44
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
45
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
46
&error_abort);
47
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
48
49
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
50
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
51
}
52
53
+static Property lowrisc_ibex_soc_props[] = {
54
+ DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
55
+ DEFINE_PROP_END_OF_LIST()
56
+};
57
+
58
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
59
{
60
DeviceClass *dc = DEVICE_CLASS(oc);
61
62
+ device_class_set_props(dc, lowrisc_ibex_soc_props);
63
dc->realize = lowrisc_ibex_soc_realize;
64
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
65
dc->user_creatable = false;
66
--
67
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
After RISCVException enum is introduced, riscv_csrrw_debug() returns
4
RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
5
should check the result against RISCV_EXCP_NONE instead of value 0.
6
Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
7
when using "info reg vector" GDB command.
8
9
Signed-off-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Jim Shu <jim.shu@sifive.com>
11
Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
14
Message-Id: <20220918083245.13028-1-frank.chang@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/gdbstub.c | 4 ++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
19
20
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/gdbstub.c
23
+++ b/target/riscv/gdbstub.c
24
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
25
target_ulong val = 0;
26
int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
27
28
- if (result == 0) {
29
+ if (result == RISCV_EXCP_NONE) {
30
return gdb_get_regl(buf, val);
31
}
32
33
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
34
target_ulong val = ldtul_p(mem_buf);
35
int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
36
37
- if (result == 0) {
38
+ if (result == RISCV_EXCP_NONE) {
39
return sizeof(target_ulong);
40
}
41
42
--
43
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
4
inherit from TYPE_MACHINE. This is an inconsistency which can cause
5
undefined behavior such as memory corruption.
6
7
Change SiFiveEState to inherit from MachineState since it is registered
8
as a machine.
9
10
Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")
11
12
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-Id: <20220922075232.33653-1-shentey@gmail.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
include/hw/riscv/sifive_e.h | 3 ++-
19
1 file changed, 2 insertions(+), 1 deletion(-)
20
21
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/riscv/sifive_e.h
24
+++ b/include/hw/riscv/sifive_e.h
25
@@ -XXX,XX +XXX,XX @@
26
#include "hw/riscv/riscv_hart.h"
27
#include "hw/riscv/sifive_cpu.h"
28
#include "hw/gpio/sifive_gpio.h"
29
+#include "hw/boards.h"
30
31
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
32
#define RISCV_E_SOC(obj) \
33
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveESoCState {
34
35
typedef struct SiFiveEState {
36
/*< private >*/
37
- SysBusDevice parent_obj;
38
+ MachineState parent_obj;
39
40
/*< public >*/
41
SiFiveESoCState soc;
42
--
43
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
Current RISC-V debug assumes that only type 2 trigger is supported.
4
To allow more types of triggers to be supported in the future
5
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
6
functionality), we should determine the trigger type from tdata1.type.
7
8
RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM.
9
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
13
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
14
[bmeng: fixed MXL_RV128 case, and moved macros to the following patch]
15
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
16
Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/cpu.h | 2 +-
20
target/riscv/debug.h | 13 +--
21
target/riscv/csr.c | 2 +-
22
target/riscv/debug.c | 188 +++++++++++++++++++++++++++++------------
23
target/riscv/machine.c | 2 +-
24
5 files changed, 140 insertions(+), 67 deletions(-)
25
26
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.h
29
+++ b/target/riscv/cpu.h
30
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
31
32
/* trigger module */
33
target_ulong trigger_cur;
34
- type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
35
+ type2_trigger_t type2_trig[RV_MAX_TRIGGERS];
36
37
/* machine specific rdtime callback */
38
uint64_t (*rdtime_fn)(void *);
39
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/debug.h
42
+++ b/target/riscv/debug.h
43
@@ -XXX,XX +XXX,XX @@
44
#ifndef RISCV_DEBUG_H
45
#define RISCV_DEBUG_H
46
47
-/* trigger indexes implemented */
48
-enum {
49
- TRIGGER_TYPE2_IDX_0 = 0,
50
- TRIGGER_TYPE2_IDX_1,
51
- TRIGGER_TYPE2_NUM,
52
- TRIGGER_NUM = TRIGGER_TYPE2_NUM
53
-};
54
+#define RV_MAX_TRIGGERS 2
55
56
/* register index of tdata CSRs */
57
enum {
58
@@ -XXX,XX +XXX,XX @@ typedef enum {
59
TRIGGER_TYPE_EXCP = 5, /* exception trigger */
60
TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */
61
TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */
62
- TRIGGER_TYPE_UNAVAIL = 15 /* trigger exists, but unavailable */
63
+ TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */
64
+ TRIGGER_TYPE_NUM
65
} trigger_type_t;
66
67
typedef struct {
68
@@ -XXX,XX +XXX,XX @@ typedef struct {
69
struct CPUWatchpoint *wp;
70
} type2_trigger_t;
71
72
-/* tdata field masks */
73
+/* tdata1 field masks */
74
75
#define RV32_TYPE(t) ((uint32_t)(t) << 28)
76
#define RV32_TYPE_MASK (0xf << 28)
77
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/csr.c
80
+++ b/target/riscv/csr.c
81
@@ -XXX,XX +XXX,XX @@ static RISCVException read_tdata(CPURISCVState *env, int csrno,
82
target_ulong *val)
83
{
84
/* return 0 in tdata1 to end the trigger enumeration */
85
- if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
86
+ if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) {
87
*val = 0;
88
return RISCV_EXCP_NONE;
89
}
90
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/riscv/debug.c
93
+++ b/target/riscv/debug.c
94
@@ -XXX,XX +XXX,XX @@
95
/* tdata availability of a trigger */
96
typedef bool tdata_avail[TDATA_NUM];
97
98
-static tdata_avail tdata_mapping[TRIGGER_NUM] = {
99
- [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = { true, true, false },
100
+static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] = {
101
+ [TRIGGER_TYPE_NO_EXIST] = { false, false, false },
102
+ [TRIGGER_TYPE_AD_MATCH] = { true, true, true },
103
+ [TRIGGER_TYPE_INST_CNT] = { true, false, true },
104
+ [TRIGGER_TYPE_INT] = { true, true, true },
105
+ [TRIGGER_TYPE_EXCP] = { true, true, true },
106
+ [TRIGGER_TYPE_AD_MATCH6] = { true, true, true },
107
+ [TRIGGER_TYPE_EXT_SRC] = { true, false, false },
108
+ [TRIGGER_TYPE_UNAVAIL] = { true, true, true }
109
};
110
111
/* only breakpoint size 1/2/4/8 supported */
112
@@ -XXX,XX +XXX,XX @@ static int access_size[SIZE_NUM] = {
113
[6 ... 15] = -1,
114
};
115
116
+static inline target_ulong extract_trigger_type(CPURISCVState *env,
117
+ target_ulong tdata1)
118
+{
119
+ switch (riscv_cpu_mxl(env)) {
120
+ case MXL_RV32:
121
+ return extract32(tdata1, 28, 4);
122
+ case MXL_RV64:
123
+ case MXL_RV128:
124
+ return extract64(tdata1, 60, 4);
125
+ default:
126
+ g_assert_not_reached();
127
+ }
128
+}
129
+
130
+static inline target_ulong get_trigger_type(CPURISCVState *env,
131
+ target_ulong trigger_index)
132
+{
133
+ target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol;
134
+ return extract_trigger_type(env, tdata1);
135
+}
136
+
137
static inline target_ulong trigger_type(CPURISCVState *env,
138
trigger_type_t type)
139
{
140
@@ -XXX,XX +XXX,XX @@ static inline target_ulong trigger_type(CPURISCVState *env,
141
142
bool tdata_available(CPURISCVState *env, int tdata_index)
143
{
144
+ int trigger_type = get_trigger_type(env, env->trigger_cur);
145
+
146
if (unlikely(tdata_index >= TDATA_NUM)) {
147
return false;
148
}
149
150
- if (unlikely(env->trigger_cur >= TRIGGER_NUM)) {
151
+ if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
152
return false;
153
}
154
155
- return tdata_mapping[env->trigger_cur][tdata_index];
156
+ return tdata_mapping[trigger_type][tdata_index];
157
}
158
159
target_ulong tselect_csr_read(CPURISCVState *env)
160
@@ -XXX,XX +XXX,XX @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
161
qemu_log_mask(LOG_GUEST_ERROR,
162
"ignoring type write to tdata1 register\n");
163
}
164
+
165
if (dmode != 0) {
166
qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n");
167
}
168
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
169
}
170
171
static target_ulong type2_reg_read(CPURISCVState *env,
172
- target_ulong trigger_index, int tdata_index)
173
+ target_ulong index, int tdata_index)
174
{
175
- uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0;
176
target_ulong tdata;
177
178
switch (tdata_index) {
179
@@ -XXX,XX +XXX,XX @@ static target_ulong type2_reg_read(CPURISCVState *env,
180
return tdata;
181
}
182
183
-static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index,
184
+static void type2_reg_write(CPURISCVState *env, target_ulong index,
185
int tdata_index, target_ulong val)
186
{
187
- uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0;
188
target_ulong new_val;
189
190
switch (tdata_index) {
191
@@ -XXX,XX +XXX,XX @@ static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index,
192
return;
193
}
194
195
-typedef target_ulong (*tdata_read_func)(CPURISCVState *env,
196
- target_ulong trigger_index,
197
- int tdata_index);
198
-
199
-static tdata_read_func trigger_read_funcs[TRIGGER_NUM] = {
200
- [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_read,
201
-};
202
-
203
-typedef void (*tdata_write_func)(CPURISCVState *env,
204
- target_ulong trigger_index,
205
- int tdata_index,
206
- target_ulong val);
207
-
208
-static tdata_write_func trigger_write_funcs[TRIGGER_NUM] = {
209
- [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_write,
210
-};
211
-
212
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
213
{
214
- tdata_read_func read_func = trigger_read_funcs[env->trigger_cur];
215
+ int trigger_type = get_trigger_type(env, env->trigger_cur);
216
+
217
+ switch (trigger_type) {
218
+ case TRIGGER_TYPE_AD_MATCH:
219
+ return type2_reg_read(env, env->trigger_cur, tdata_index);
220
+ break;
221
+ case TRIGGER_TYPE_INST_CNT:
222
+ case TRIGGER_TYPE_INT:
223
+ case TRIGGER_TYPE_EXCP:
224
+ case TRIGGER_TYPE_AD_MATCH6:
225
+ case TRIGGER_TYPE_EXT_SRC:
226
+ qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
227
+ trigger_type);
228
+ break;
229
+ case TRIGGER_TYPE_NO_EXIST:
230
+ case TRIGGER_TYPE_UNAVAIL:
231
+ qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
232
+ trigger_type);
233
+ break;
234
+ default:
235
+ g_assert_not_reached();
236
+ }
237
238
- return read_func(env, env->trigger_cur, tdata_index);
239
+ return 0;
240
}
241
242
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
243
{
244
- tdata_write_func write_func = trigger_write_funcs[env->trigger_cur];
245
+ int trigger_type;
246
247
- return write_func(env, env->trigger_cur, tdata_index, val);
248
+ if (tdata_index == TDATA1) {
249
+ trigger_type = extract_trigger_type(env, val);
250
+ } else {
251
+ trigger_type = get_trigger_type(env, env->trigger_cur);
252
+ }
253
+
254
+ switch (trigger_type) {
255
+ case TRIGGER_TYPE_AD_MATCH:
256
+ type2_reg_write(env, env->trigger_cur, tdata_index, val);
257
+ break;
258
+ case TRIGGER_TYPE_INST_CNT:
259
+ case TRIGGER_TYPE_INT:
260
+ case TRIGGER_TYPE_EXCP:
261
+ case TRIGGER_TYPE_AD_MATCH6:
262
+ case TRIGGER_TYPE_EXT_SRC:
263
+ qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
264
+ trigger_type);
265
+ break;
266
+ case TRIGGER_TYPE_NO_EXIST:
267
+ case TRIGGER_TYPE_UNAVAIL:
268
+ qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
269
+ trigger_type);
270
+ break;
271
+ default:
272
+ g_assert_not_reached();
273
+ }
274
}
275
276
void riscv_cpu_debug_excp_handler(CPUState *cs)
277
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
278
CPUBreakpoint *bp;
279
target_ulong ctrl;
280
target_ulong pc;
281
+ int trigger_type;
282
int i;
283
284
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
285
- for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
286
- ctrl = env->type2_trig[i].mcontrol;
287
- pc = env->type2_trig[i].maddress;
288
-
289
- if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
290
- /* check U/S/M bit against current privilege level */
291
- if ((ctrl >> 3) & BIT(env->priv)) {
292
- return true;
293
+ for (i = 0; i < RV_MAX_TRIGGERS; i++) {
294
+ trigger_type = get_trigger_type(env, i);
295
+
296
+ switch (trigger_type) {
297
+ case TRIGGER_TYPE_AD_MATCH:
298
+ ctrl = env->type2_trig[i].mcontrol;
299
+ pc = env->type2_trig[i].maddress;
300
+
301
+ if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
302
+ /* check U/S/M bit against current privilege level */
303
+ if ((ctrl >> 3) & BIT(env->priv)) {
304
+ return true;
305
+ }
306
}
307
+ break;
308
+ default:
309
+ /* other trigger types are not supported or irrelevant */
310
+ break;
311
}
312
}
313
}
314
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
315
CPURISCVState *env = &cpu->env;
316
target_ulong ctrl;
317
target_ulong addr;
318
+ int trigger_type;
319
int flags;
320
int i;
321
322
- for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
323
- ctrl = env->type2_trig[i].mcontrol;
324
- addr = env->type2_trig[i].maddress;
325
- flags = 0;
326
+ for (i = 0; i < RV_MAX_TRIGGERS; i++) {
327
+ trigger_type = get_trigger_type(env, i);
328
329
- if (ctrl & TYPE2_LOAD) {
330
- flags |= BP_MEM_READ;
331
- }
332
- if (ctrl & TYPE2_STORE) {
333
- flags |= BP_MEM_WRITE;
334
- }
335
+ switch (trigger_type) {
336
+ case TRIGGER_TYPE_AD_MATCH:
337
+ ctrl = env->type2_trig[i].mcontrol;
338
+ addr = env->type2_trig[i].maddress;
339
+ flags = 0;
340
341
- if ((wp->flags & flags) && (wp->vaddr == addr)) {
342
- /* check U/S/M bit against current privilege level */
343
- if ((ctrl >> 3) & BIT(env->priv)) {
344
- return true;
345
+ if (ctrl & TYPE2_LOAD) {
346
+ flags |= BP_MEM_READ;
347
+ }
348
+ if (ctrl & TYPE2_STORE) {
349
+ flags |= BP_MEM_WRITE;
350
+ }
351
+
352
+ if ((wp->flags & flags) && (wp->vaddr == addr)) {
353
+ /* check U/S/M bit against current privilege level */
354
+ if ((ctrl >> 3) & BIT(env->priv)) {
355
+ return true;
356
+ }
357
}
358
+ break;
359
+ default:
360
+ /* other trigger types are not supported */
361
+ break;
362
}
363
}
364
365
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
366
367
void riscv_trigger_init(CPURISCVState *env)
368
{
369
- target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
370
+ target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
371
int i;
372
373
- /* type 2 triggers */
374
- for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
375
+ /* init to type 2 triggers */
376
+ for (i = 0; i < RV_MAX_TRIGGERS; i++) {
377
/*
378
* type = TRIGGER_TYPE_AD_MATCH
379
* dmode = 0 (both debug and M-mode can write tdata)
380
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
381
* chain = 0 (unimplemented, always 0)
382
* match = 0 (always 0, when any compare value equals tdata2)
383
*/
384
- env->type2_trig[i].mcontrol = type2;
385
+ env->type2_trig[i].mcontrol = tdata1;
386
env->type2_trig[i].maddress = 0;
387
env->type2_trig[i].bp = NULL;
388
env->type2_trig[i].wp = NULL;
389
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
390
index XXXXXXX..XXXXXXX 100644
391
--- a/target/riscv/machine.c
392
+++ b/target/riscv/machine.c
393
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_debug = {
394
.needed = debug_needed,
395
.fields = (VMStateField[]) {
396
VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
397
- VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
398
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS,
399
0, vmstate_debug_type2, type2_trigger_t),
400
VMSTATE_END_OF_LIST()
401
}
402
--
403
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
Introduce build_tdata1() to build tdata1 register content, which can be
4
shared among all types of triggers.
5
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
[bmeng: moved RV{32,64}_DATA_MASK definition to this patch]
11
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220909134215.1843865-3-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/debug.h | 2 ++
16
target/riscv/debug.c | 15 ++++++++++-----
17
2 files changed, 12 insertions(+), 5 deletions(-)
18
19
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/debug.h
22
+++ b/target/riscv/debug.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
#define RV32_TYPE(t) ((uint32_t)(t) << 28)
25
#define RV32_TYPE_MASK (0xf << 28)
26
#define RV32_DMODE BIT(27)
27
+#define RV32_DATA_MASK 0x7ffffff
28
#define RV64_TYPE(t) ((uint64_t)(t) << 60)
29
#define RV64_TYPE_MASK (0xfULL << 60)
30
#define RV64_DMODE BIT_ULL(59)
31
+#define RV64_DATA_MASK 0x7ffffffffffffff
32
33
/* mcontrol field masks */
34
35
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/debug.c
38
+++ b/target/riscv/debug.c
39
@@ -XXX,XX +XXX,XX @@ static inline target_ulong get_trigger_type(CPURISCVState *env,
40
return extract_trigger_type(env, tdata1);
41
}
42
43
-static inline target_ulong trigger_type(CPURISCVState *env,
44
- trigger_type_t type)
45
+static inline target_ulong build_tdata1(CPURISCVState *env,
46
+ trigger_type_t type,
47
+ bool dmode, target_ulong data)
48
{
49
target_ulong tdata1;
50
51
switch (riscv_cpu_mxl(env)) {
52
case MXL_RV32:
53
- tdata1 = RV32_TYPE(type);
54
+ tdata1 = RV32_TYPE(type) |
55
+ (dmode ? RV32_DMODE : 0) |
56
+ (data & RV32_DATA_MASK);
57
break;
58
case MXL_RV64:
59
case MXL_RV128:
60
- tdata1 = RV64_TYPE(type);
61
+ tdata1 = RV64_TYPE(type) |
62
+ (dmode ? RV64_DMODE : 0) |
63
+ (data & RV64_DATA_MASK);
64
break;
65
default:
66
g_assert_not_reached();
67
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
68
69
void riscv_trigger_init(CPURISCVState *env)
70
{
71
- target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
72
+ target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
73
int i;
74
75
/* init to type 2 triggers */
76
--
77
2.37.3
diff view generated by jsdifflib
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
[PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
3
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
4
which allows us to support more types of triggers in the future.
4
5
5
Do not re-initialize the OTP content in the DeviceReset handler,
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
6
initialize it once in the DeviceRealize one.
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
8
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
12
---
14
hw/misc/sifive_u_otp.c | 13 +++++--------
13
target/riscv/cpu.h | 6 ++-
15
1 file changed, 5 insertions(+), 8 deletions(-)
14
target/riscv/debug.h | 7 ---
15
target/riscv/debug.c | 103 +++++++++++++++--------------------------
16
target/riscv/machine.c | 20 ++------
17
4 files changed, 48 insertions(+), 88 deletions(-)
16
18
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
21
--- a/target/riscv/cpu.h
20
+++ b/hw/misc/sifive_u_otp.c
22
+++ b/target/riscv/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
23
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
22
24
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
25
/* trigger module */
24
error_setg(errp, "failed to read the initial flash content");
26
target_ulong trigger_cur;
25
+ return;
27
- type2_trigger_t type2_trig[RV_MAX_TRIGGERS];
26
}
28
+ target_ulong tdata1[RV_MAX_TRIGGERS];
29
+ target_ulong tdata2[RV_MAX_TRIGGERS];
30
+ target_ulong tdata3[RV_MAX_TRIGGERS];
31
+ struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
32
+ struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
33
34
/* machine specific rdtime callback */
35
uint64_t (*rdtime_fn)(void *);
36
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/debug.h
39
+++ b/target/riscv/debug.h
40
@@ -XXX,XX +XXX,XX @@ typedef enum {
41
TRIGGER_TYPE_NUM
42
} trigger_type_t;
43
44
-typedef struct {
45
- target_ulong mcontrol;
46
- target_ulong maddress;
47
- struct CPUBreakpoint *bp;
48
- struct CPUWatchpoint *wp;
49
-} type2_trigger_t;
50
-
51
/* tdata1 field masks */
52
53
#define RV32_TYPE(t) ((uint32_t)(t) << 28)
54
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/riscv/debug.c
57
+++ b/target/riscv/debug.c
58
@@ -XXX,XX +XXX,XX @@ static inline target_ulong extract_trigger_type(CPURISCVState *env,
59
static inline target_ulong get_trigger_type(CPURISCVState *env,
60
target_ulong trigger_index)
61
{
62
- target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol;
63
- return extract_trigger_type(env, tdata1);
64
+ return extract_trigger_type(env, env->tdata1[trigger_index]);
65
}
66
67
static inline target_ulong build_tdata1(CPURISCVState *env,
68
@@ -XXX,XX +XXX,XX @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
69
}
70
}
71
72
+/* type 2 trigger */
73
+
74
static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
75
{
76
uint32_t size, sizelo, sizehi = 0;
77
@@ -XXX,XX +XXX,XX @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
78
79
static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
80
{
81
- target_ulong ctrl = env->type2_trig[index].mcontrol;
82
- target_ulong addr = env->type2_trig[index].maddress;
83
+ target_ulong ctrl = env->tdata1[index];
84
+ target_ulong addr = env->tdata2[index];
85
bool enabled = type2_breakpoint_enabled(ctrl);
86
CPUState *cs = env_cpu(env);
87
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
88
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
89
}
90
91
if (ctrl & TYPE2_EXEC) {
92
- cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp);
93
+ cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
94
}
95
96
if (ctrl & TYPE2_LOAD) {
97
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
98
size = type2_breakpoint_size(env, ctrl);
99
if (size != 0) {
100
cpu_watchpoint_insert(cs, addr, size, flags,
101
- &env->type2_trig[index].wp);
102
+ &env->cpu_watchpoint[index]);
103
} else {
104
cpu_watchpoint_insert(cs, addr, 8, flags,
105
- &env->type2_trig[index].wp);
106
+ &env->cpu_watchpoint[index]);
27
}
107
}
28
}
108
}
109
}
110
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
111
{
112
CPUState *cs = env_cpu(env);
113
114
- if (env->type2_trig[index].bp) {
115
- cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp);
116
- env->type2_trig[index].bp = NULL;
117
+ if (env->cpu_breakpoint[index]) {
118
+ cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
119
+ env->cpu_breakpoint[index] = NULL;
120
}
121
122
- if (env->type2_trig[index].wp) {
123
- cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp);
124
- env->type2_trig[index].wp = NULL;
125
+ if (env->cpu_watchpoint[index]) {
126
+ cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
127
+ env->cpu_watchpoint[index] = NULL;
128
}
129
}
130
131
-static target_ulong type2_reg_read(CPURISCVState *env,
132
- target_ulong index, int tdata_index)
133
-{
134
- target_ulong tdata;
135
-
136
- switch (tdata_index) {
137
- case TDATA1:
138
- tdata = env->type2_trig[index].mcontrol;
139
- break;
140
- case TDATA2:
141
- tdata = env->type2_trig[index].maddress;
142
- break;
143
- default:
144
- g_assert_not_reached();
145
- }
146
-
147
- return tdata;
29
-}
148
-}
30
-
149
-
31
-static void sifive_u_otp_reset(DeviceState *dev)
150
static void type2_reg_write(CPURISCVState *env, target_ulong index,
32
-{
151
int tdata_index, target_ulong val)
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
152
{
34
153
@@ -XXX,XX +XXX,XX @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
35
/* Initialize all fuses' initial value to 0xFFs */
154
switch (tdata_index) {
36
memset(s->fuse, 0xff, sizeof(s->fuse));
155
case TDATA1:
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
156
new_val = type2_mcontrol_validate(env, val);
38
serial_data = s->serial;
157
- if (new_val != env->type2_trig[index].mcontrol) {
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
158
- env->type2_trig[index].mcontrol = new_val;
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
159
+ if (new_val != env->tdata1[index]) {
41
- error_report("write error index<%d>", index);
160
+ env->tdata1[index] = new_val;
42
+ error_setg(errp, "failed to write index<%d>", index);
161
type2_breakpoint_remove(env, index);
43
+ return;
162
type2_breakpoint_insert(env, index);
44
}
163
}
45
164
break;
46
serial_data = ~(s->serial);
165
case TDATA2:
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
166
- if (val != env->type2_trig[index].maddress) {
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
167
- env->type2_trig[index].maddress = val;
49
- error_report("write error index<%d>", index + 1);
168
+ if (val != env->tdata2[index]) {
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
169
+ env->tdata2[index] = val;
51
+ return;
170
type2_breakpoint_remove(env, index);
171
type2_breakpoint_insert(env, index);
52
}
172
}
53
}
173
break;
54
174
+ case TDATA3:
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
175
+ qemu_log_mask(LOG_UNIMP,
56
176
+ "tdata3 is not supported for type 2 trigger\n");
57
device_class_set_props(dc, sifive_u_otp_properties);
177
+ break;
58
dc->realize = sifive_u_otp_realize;
178
default:
59
- dc->reset = sifive_u_otp_reset;
179
g_assert_not_reached();
60
}
180
}
61
181
@@ -XXX,XX +XXX,XX @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
62
static const TypeInfo sifive_u_otp_info = {
182
183
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
184
{
185
- int trigger_type = get_trigger_type(env, env->trigger_cur);
186
-
187
- switch (trigger_type) {
188
- case TRIGGER_TYPE_AD_MATCH:
189
- return type2_reg_read(env, env->trigger_cur, tdata_index);
190
- break;
191
- case TRIGGER_TYPE_INST_CNT:
192
- case TRIGGER_TYPE_INT:
193
- case TRIGGER_TYPE_EXCP:
194
- case TRIGGER_TYPE_AD_MATCH6:
195
- case TRIGGER_TYPE_EXT_SRC:
196
- qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
197
- trigger_type);
198
- break;
199
- case TRIGGER_TYPE_NO_EXIST:
200
- case TRIGGER_TYPE_UNAVAIL:
201
- qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
202
- trigger_type);
203
- break;
204
+ switch (tdata_index) {
205
+ case TDATA1:
206
+ return env->tdata1[env->trigger_cur];
207
+ case TDATA2:
208
+ return env->tdata2[env->trigger_cur];
209
+ case TDATA3:
210
+ return env->tdata3[env->trigger_cur];
211
default:
212
g_assert_not_reached();
213
}
214
-
215
- return 0;
216
}
217
218
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
219
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
220
221
switch (trigger_type) {
222
case TRIGGER_TYPE_AD_MATCH:
223
- ctrl = env->type2_trig[i].mcontrol;
224
- pc = env->type2_trig[i].maddress;
225
+ ctrl = env->tdata1[i];
226
+ pc = env->tdata2[i];
227
228
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
229
/* check U/S/M bit against current privilege level */
230
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
231
232
switch (trigger_type) {
233
case TRIGGER_TYPE_AD_MATCH:
234
- ctrl = env->type2_trig[i].mcontrol;
235
- addr = env->type2_trig[i].maddress;
236
+ ctrl = env->tdata1[i];
237
+ addr = env->tdata2[i];
238
flags = 0;
239
240
if (ctrl & TYPE2_LOAD) {
241
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
242
* chain = 0 (unimplemented, always 0)
243
* match = 0 (always 0, when any compare value equals tdata2)
244
*/
245
- env->type2_trig[i].mcontrol = tdata1;
246
- env->type2_trig[i].maddress = 0;
247
- env->type2_trig[i].bp = NULL;
248
- env->type2_trig[i].wp = NULL;
249
+ env->tdata1[i] = tdata1;
250
+ env->tdata2[i] = 0;
251
+ env->tdata3[i] = 0;
252
+ env->cpu_breakpoint[i] = NULL;
253
+ env->cpu_watchpoint[i] = NULL;
254
}
255
}
256
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
257
index XXXXXXX..XXXXXXX 100644
258
--- a/target/riscv/machine.c
259
+++ b/target/riscv/machine.c
260
@@ -XXX,XX +XXX,XX @@ static bool debug_needed(void *opaque)
261
return riscv_feature(env, RISCV_FEATURE_DEBUG);
262
}
263
264
-static const VMStateDescription vmstate_debug_type2 = {
265
- .name = "cpu/debug/type2",
266
- .version_id = 1,
267
- .minimum_version_id = 1,
268
- .fields = (VMStateField[]) {
269
- VMSTATE_UINTTL(mcontrol, type2_trigger_t),
270
- VMSTATE_UINTTL(maddress, type2_trigger_t),
271
- VMSTATE_END_OF_LIST()
272
- }
273
-};
274
-
275
static const VMStateDescription vmstate_debug = {
276
.name = "cpu/debug",
277
- .version_id = 1,
278
- .minimum_version_id = 1,
279
+ .version_id = 2,
280
+ .minimum_version_id = 2,
281
.needed = debug_needed,
282
.fields = (VMStateField[]) {
283
VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
284
- VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS,
285
- 0, vmstate_debug_type2, type2_trigger_t),
286
+ VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
287
+ VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
288
+ VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
289
VMSTATE_END_OF_LIST()
290
}
291
};
63
--
292
--
64
2.31.1
293
2.37.3
65
66
diff view generated by jsdifflib
New patch
[PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
The value of tselect CSR can be written should be limited within the
4
range of supported triggers number.
5
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
Message-Id: <20220909134215.1843865-5-bmeng.cn@gmail.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/debug.c | 9 +++------
14
1 file changed, 3 insertions(+), 6 deletions(-)
15
16
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/debug.c
19
+++ b/target/riscv/debug.c
20
@@ -XXX,XX +XXX,XX @@ bool tdata_available(CPURISCVState *env, int tdata_index)
21
return false;
22
}
23
24
- if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
25
- return false;
26
- }
27
-
28
return tdata_mapping[trigger_type][tdata_index];
29
}
30
31
@@ -XXX,XX +XXX,XX @@ target_ulong tselect_csr_read(CPURISCVState *env)
32
33
void tselect_csr_write(CPURISCVState *env, target_ulong val)
34
{
35
- /* all target_ulong bits of tselect are implemented */
36
- env->trigger_cur = val;
37
+ if (val < RV_MAX_TRIGGERS) {
38
+ env->trigger_cur = val;
39
+ }
40
}
41
42
static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
43
--
44
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
tinfo.info:
4
One bit for each possible type enumerated in tdata1.
5
If the bit is set, then that type is supported by the currently
6
selected trigger.
7
8
Signed-off-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
11
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
12
Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu_bits.h | 1 +
16
target/riscv/debug.h | 2 ++
17
target/riscv/csr.c | 8 ++++++++
18
target/riscv/debug.c | 10 +++++++---
19
4 files changed, 18 insertions(+), 3 deletions(-)
20
21
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_bits.h
24
+++ b/target/riscv/cpu_bits.h
25
@@ -XXX,XX +XXX,XX @@
26
#define CSR_TDATA1 0x7a1
27
#define CSR_TDATA2 0x7a2
28
#define CSR_TDATA3 0x7a3
29
+#define CSR_TINFO 0x7a4
30
31
/* Debug Mode Registers */
32
#define CSR_DCSR 0x7b0
33
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/debug.h
36
+++ b/target/riscv/debug.h
37
@@ -XXX,XX +XXX,XX @@ void tselect_csr_write(CPURISCVState *env, target_ulong val);
38
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
39
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
40
41
+target_ulong tinfo_csr_read(CPURISCVState *env);
42
+
43
void riscv_cpu_debug_excp_handler(CPUState *cs);
44
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
45
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
46
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/csr.c
49
+++ b/target/riscv/csr.c
50
@@ -XXX,XX +XXX,XX @@ static RISCVException write_tdata(CPURISCVState *env, int csrno,
51
return RISCV_EXCP_NONE;
52
}
53
54
+static RISCVException read_tinfo(CPURISCVState *env, int csrno,
55
+ target_ulong *val)
56
+{
57
+ *val = tinfo_csr_read(env);
58
+ return RISCV_EXCP_NONE;
59
+}
60
+
61
/*
62
* Functions to access Pointer Masking feature registers
63
* We have to check if current priv lvl could modify
64
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
65
[CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
66
[CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
67
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
68
+ [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
69
70
/* User Pointer Masking */
71
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
72
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/riscv/debug.c
75
+++ b/target/riscv/debug.c
76
@@ -XXX,XX +XXX,XX @@
77
* - tdata1
78
* - tdata2
79
* - tdata3
80
- *
81
- * We don't support writable 'type' field in the tdata1 register, so there is
82
- * no need to implement the "tinfo" CSR.
83
+ * - tinfo
84
*
85
* The following triggers are implemented:
86
*
87
@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
88
}
89
}
90
91
+target_ulong tinfo_csr_read(CPURISCVState *env)
92
+{
93
+ /* assume all triggers support the same types of triggers */
94
+ return BIT(TRIGGER_TYPE_AD_MATCH);
95
+}
96
+
97
void riscv_cpu_debug_excp_handler(CPUState *cs)
98
{
99
RISCVCPU *cpu = RISCV_CPU(cs);
100
--
101
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 18/22] target/riscv: debug: Create common trigger actions function
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
Trigger actions are shared among all triggers. Extract to a common
4
function.
5
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
[bmeng: handle the DBG_ACTION_NONE case]
11
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220909134215.1843865-7-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/debug.h | 13 ++++++++++
16
target/riscv/debug.c | 59 ++++++++++++++++++++++++++++++++++++++++++--
17
2 files changed, 70 insertions(+), 2 deletions(-)
18
19
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/debug.h
22
+++ b/target/riscv/debug.h
23
@@ -XXX,XX +XXX,XX @@ typedef enum {
24
TRIGGER_TYPE_NUM
25
} trigger_type_t;
26
27
+/* actions */
28
+typedef enum {
29
+ DBG_ACTION_NONE = -1, /* sentinel value */
30
+ DBG_ACTION_BP = 0,
31
+ DBG_ACTION_DBG_MODE,
32
+ DBG_ACTION_TRACE0,
33
+ DBG_ACTION_TRACE1,
34
+ DBG_ACTION_TRACE2,
35
+ DBG_ACTION_TRACE3,
36
+ DBG_ACTION_EXT_DBG0 = 8,
37
+ DBG_ACTION_EXT_DBG1
38
+} trigger_action_t;
39
+
40
/* tdata1 field masks */
41
42
#define RV32_TYPE(t) ((uint32_t)(t) << 28)
43
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/debug.c
46
+++ b/target/riscv/debug.c
47
@@ -XXX,XX +XXX,XX @@ static inline target_ulong get_trigger_type(CPURISCVState *env,
48
return extract_trigger_type(env, env->tdata1[trigger_index]);
49
}
50
51
+static trigger_action_t get_trigger_action(CPURISCVState *env,
52
+ target_ulong trigger_index)
53
+{
54
+ target_ulong tdata1 = env->tdata1[trigger_index];
55
+ int trigger_type = get_trigger_type(env, trigger_index);
56
+ trigger_action_t action = DBG_ACTION_NONE;
57
+
58
+ switch (trigger_type) {
59
+ case TRIGGER_TYPE_AD_MATCH:
60
+ action = (tdata1 & TYPE2_ACTION) >> 12;
61
+ break;
62
+ case TRIGGER_TYPE_INST_CNT:
63
+ case TRIGGER_TYPE_INT:
64
+ case TRIGGER_TYPE_EXCP:
65
+ case TRIGGER_TYPE_AD_MATCH6:
66
+ case TRIGGER_TYPE_EXT_SRC:
67
+ qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
68
+ trigger_type);
69
+ break;
70
+ case TRIGGER_TYPE_NO_EXIST:
71
+ case TRIGGER_TYPE_UNAVAIL:
72
+ qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
73
+ trigger_type);
74
+ break;
75
+ default:
76
+ g_assert_not_reached();
77
+ }
78
+
79
+ return action;
80
+}
81
+
82
static inline target_ulong build_tdata1(CPURISCVState *env,
83
trigger_type_t type,
84
bool dmode, target_ulong data)
85
@@ -XXX,XX +XXX,XX @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
86
}
87
}
88
89
+static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
90
+{
91
+ trigger_action_t action = get_trigger_action(env, trigger_index);
92
+
93
+ switch (action) {
94
+ case DBG_ACTION_NONE:
95
+ break;
96
+ case DBG_ACTION_BP:
97
+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
98
+ break;
99
+ case DBG_ACTION_DBG_MODE:
100
+ case DBG_ACTION_TRACE0:
101
+ case DBG_ACTION_TRACE1:
102
+ case DBG_ACTION_TRACE2:
103
+ case DBG_ACTION_TRACE3:
104
+ case DBG_ACTION_EXT_DBG0:
105
+ case DBG_ACTION_EXT_DBG1:
106
+ qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action);
107
+ break;
108
+ default:
109
+ g_assert_not_reached();
110
+ }
111
+}
112
+
113
/* type 2 trigger */
114
115
static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
116
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
117
if (cs->watchpoint_hit) {
118
if (cs->watchpoint_hit->flags & BP_CPU) {
119
cs->watchpoint_hit = NULL;
120
- riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
121
+ do_trigger_action(env, DBG_ACTION_BP);
122
}
123
} else {
124
if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
125
- riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
126
+ do_trigger_action(env, DBG_ACTION_BP);
127
}
128
}
129
}
130
--
131
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
Type 2 trigger cannot be fired in VU/VS modes.
4
5
Signed-off-by: Frank Chang <frank.chang@sifive.com>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
8
Message-Id: <20220909134215.1843865-8-bmeng.cn@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/debug.c | 10 ++++++++++
12
1 file changed, 10 insertions(+)
13
14
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/debug.c
17
+++ b/target/riscv/debug.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
19
20
switch (trigger_type) {
21
case TRIGGER_TYPE_AD_MATCH:
22
+ /* type 2 trigger cannot be fired in VU/VS mode */
23
+ if (riscv_cpu_virt_enabled(env)) {
24
+ return false;
25
+ }
26
+
27
ctrl = env->tdata1[i];
28
pc = env->tdata2[i];
29
30
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
31
32
switch (trigger_type) {
33
case TRIGGER_TYPE_AD_MATCH:
34
+ /* type 2 trigger cannot be fired in VU/VS mode */
35
+ if (riscv_cpu_virt_enabled(env)) {
36
+ return false;
37
+ }
38
+
39
ctrl = env->tdata1[i];
40
addr = env->tdata2[i];
41
flags = 0;
42
--
43
2.37.3
diff view generated by jsdifflib
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
[PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger
1
From: Thomas Huth <thuth@redhat.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
Configuring a drive with "if=none" is meant for creation of a backend
3
Type 6 trigger is similar to a type 2 trigger, but provides additional
4
only, it should not get automatically assigned to a device frontend.
4
functionality and should be used instead of type 2 in newer
5
Use "if=pflash" for the One-Time-Programmable device instead (like
5
implementations.
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
7
6
8
Since the old way of configuring the device has already been published
7
Signed-off-by: Frank Chang <frank.chang@sifive.com>
9
with the previous QEMU versions, we cannot remove this immediately, but
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
have to deprecate it and support it for at least two more releases.
9
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
11
10
Message-Id: <20220909134215.1843865-9-bmeng.cn@gmail.com>
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
12
---
19
docs/about/deprecated.rst | 6 ++++++
13
target/riscv/debug.h | 18 +++++
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
14
target/riscv/debug.c | 174 ++++++++++++++++++++++++++++++++++++++++++-
21
2 files changed, 14 insertions(+), 1 deletion(-)
15
2 files changed, 188 insertions(+), 4 deletions(-)
22
16
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
17
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/about/deprecated.rst
19
--- a/target/riscv/debug.h
26
+++ b/docs/about/deprecated.rst
20
+++ b/target/riscv/debug.h
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
21
@@ -XXX,XX +XXX,XX @@ typedef enum {
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
22
#define TYPE2_HIT BIT(20)
29
form is preferred.
23
#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */
30
24
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
25
+/* mcontrol6 field masks */
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
26
+
33
+
27
+#define TYPE6_LOAD BIT(0)
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
28
+#define TYPE6_STORE BIT(1)
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
29
+#define TYPE6_EXEC BIT(2)
36
+
30
+#define TYPE6_U BIT(3)
37
31
+#define TYPE6_S BIT(4)
38
QEMU Machine Protocol (QMP) commands
32
+#define TYPE6_M BIT(6)
39
------------------------------------
33
+#define TYPE6_MATCH (0xf << 7)
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
34
+#define TYPE6_CHAIN BIT(11)
35
+#define TYPE6_ACTION (0xf << 12)
36
+#define TYPE6_SIZE (0xf << 16)
37
+#define TYPE6_TIMING BIT(20)
38
+#define TYPE6_SELECT BIT(21)
39
+#define TYPE6_HIT BIT(22)
40
+#define TYPE6_VU BIT(23)
41
+#define TYPE6_VS BIT(24)
42
+
43
/* access size */
44
enum {
45
SIZE_ANY = 0,
46
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
41
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
48
--- a/target/riscv/debug.c
43
+++ b/hw/misc/sifive_u_otp.c
49
+++ b/target/riscv/debug.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
50
@@ -XXX,XX +XXX,XX @@
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
51
* - tdata3
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
52
* - tinfo
47
53
*
48
- dinfo = drive_get_next(IF_NONE);
54
- * The following triggers are implemented:
49
+ dinfo = drive_get_next(IF_PFLASH);
55
+ * The following triggers are initialized by default:
50
+ if (!dinfo) {
56
*
51
+ dinfo = drive_get_next(IF_NONE);
57
* Index | Type | tdata mapping | Description
52
+ if (dinfo) {
58
* ------+------+------------------------+------------
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
59
@@ -XXX,XX +XXX,XX @@ static trigger_action_t get_trigger_action(CPURISCVState *env,
54
+ "use \"-drive if=pflash\" instead.");
60
case TRIGGER_TYPE_AD_MATCH:
61
action = (tdata1 & TYPE2_ACTION) >> 12;
62
break;
63
+ case TRIGGER_TYPE_AD_MATCH6:
64
+ action = (tdata1 & TYPE6_ACTION) >> 12;
65
+ break;
66
case TRIGGER_TYPE_INST_CNT:
67
case TRIGGER_TYPE_INT:
68
case TRIGGER_TYPE_EXCP:
69
- case TRIGGER_TYPE_AD_MATCH6:
70
case TRIGGER_TYPE_EXT_SRC:
71
qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
72
trigger_type);
73
@@ -XXX,XX +XXX,XX @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
74
return;
75
}
76
77
+/* type 6 trigger */
78
+
79
+static inline bool type6_breakpoint_enabled(target_ulong ctrl)
80
+{
81
+ bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M));
82
+ bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
83
+
84
+ return mode && rwx;
85
+}
86
+
87
+static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
88
+ target_ulong ctrl)
89
+{
90
+ target_ulong val;
91
+ uint32_t size;
92
+
93
+ /* validate the generic part first */
94
+ val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);
95
+
96
+ /* validate unimplemented (always zero) bits */
97
+ warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
98
+ warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
99
+ warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
100
+ warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
101
+ warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
102
+ warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
103
+
104
+ /* validate size encoding */
105
+ size = extract32(ctrl, 16, 4);
106
+ if (access_size[size] == -1) {
107
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
108
+ size);
109
+ } else {
110
+ val |= (ctrl & TYPE6_SIZE);
111
+ }
112
+
113
+ /* keep the mode and attribute bits */
114
+ val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M |
115
+ TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
116
+
117
+ return val;
118
+}
119
+
120
+static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index)
121
+{
122
+ target_ulong ctrl = env->tdata1[index];
123
+ target_ulong addr = env->tdata2[index];
124
+ bool enabled = type6_breakpoint_enabled(ctrl);
125
+ CPUState *cs = env_cpu(env);
126
+ int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
127
+ uint32_t size;
128
+
129
+ if (!enabled) {
130
+ return;
131
+ }
132
+
133
+ if (ctrl & TYPE6_EXEC) {
134
+ cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
135
+ }
136
+
137
+ if (ctrl & TYPE6_LOAD) {
138
+ flags |= BP_MEM_READ;
139
+ }
140
+
141
+ if (ctrl & TYPE6_STORE) {
142
+ flags |= BP_MEM_WRITE;
143
+ }
144
+
145
+ if (flags & BP_MEM_ACCESS) {
146
+ size = extract32(ctrl, 16, 4);
147
+ if (size != 0) {
148
+ cpu_watchpoint_insert(cs, addr, size, flags,
149
+ &env->cpu_watchpoint[index]);
150
+ } else {
151
+ cpu_watchpoint_insert(cs, addr, 8, flags,
152
+ &env->cpu_watchpoint[index]);
55
+ }
153
+ }
56
+ }
154
+ }
57
if (dinfo) {
155
+}
58
int ret;
156
+
59
uint64_t perm;
157
+static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index)
158
+{
159
+ type2_breakpoint_remove(env, index);
160
+}
161
+
162
+static void type6_reg_write(CPURISCVState *env, target_ulong index,
163
+ int tdata_index, target_ulong val)
164
+{
165
+ target_ulong new_val;
166
+
167
+ switch (tdata_index) {
168
+ case TDATA1:
169
+ new_val = type6_mcontrol6_validate(env, val);
170
+ if (new_val != env->tdata1[index]) {
171
+ env->tdata1[index] = new_val;
172
+ type6_breakpoint_remove(env, index);
173
+ type6_breakpoint_insert(env, index);
174
+ }
175
+ break;
176
+ case TDATA2:
177
+ if (val != env->tdata2[index]) {
178
+ env->tdata2[index] = val;
179
+ type6_breakpoint_remove(env, index);
180
+ type6_breakpoint_insert(env, index);
181
+ }
182
+ break;
183
+ case TDATA3:
184
+ qemu_log_mask(LOG_UNIMP,
185
+ "tdata3 is not supported for type 6 trigger\n");
186
+ break;
187
+ default:
188
+ g_assert_not_reached();
189
+ }
190
+
191
+ return;
192
+}
193
+
194
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
195
{
196
switch (tdata_index) {
197
@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
198
case TRIGGER_TYPE_AD_MATCH:
199
type2_reg_write(env, env->trigger_cur, tdata_index, val);
200
break;
201
+ case TRIGGER_TYPE_AD_MATCH6:
202
+ type6_reg_write(env, env->trigger_cur, tdata_index, val);
203
+ break;
204
case TRIGGER_TYPE_INST_CNT:
205
case TRIGGER_TYPE_INT:
206
case TRIGGER_TYPE_EXCP:
207
- case TRIGGER_TYPE_AD_MATCH6:
208
case TRIGGER_TYPE_EXT_SRC:
209
qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
210
trigger_type);
211
@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
212
target_ulong tinfo_csr_read(CPURISCVState *env)
213
{
214
/* assume all triggers support the same types of triggers */
215
- return BIT(TRIGGER_TYPE_AD_MATCH);
216
+ return BIT(TRIGGER_TYPE_AD_MATCH) |
217
+ BIT(TRIGGER_TYPE_AD_MATCH6);
218
}
219
220
void riscv_cpu_debug_excp_handler(CPUState *cs)
221
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
222
}
223
}
224
break;
225
+ case TRIGGER_TYPE_AD_MATCH6:
226
+ ctrl = env->tdata1[i];
227
+ pc = env->tdata2[i];
228
+
229
+ if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
230
+ if (riscv_cpu_virt_enabled(env)) {
231
+ /* check VU/VS bit against current privilege level */
232
+ if ((ctrl >> 23) & BIT(env->priv)) {
233
+ return true;
234
+ }
235
+ } else {
236
+ /* check U/S/M bit against current privilege level */
237
+ if ((ctrl >> 3) & BIT(env->priv)) {
238
+ return true;
239
+ }
240
+ }
241
+ }
242
+ break;
243
default:
244
/* other trigger types are not supported or irrelevant */
245
break;
246
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
247
}
248
}
249
break;
250
+ case TRIGGER_TYPE_AD_MATCH6:
251
+ ctrl = env->tdata1[i];
252
+ addr = env->tdata2[i];
253
+ flags = 0;
254
+
255
+ if (ctrl & TYPE6_LOAD) {
256
+ flags |= BP_MEM_READ;
257
+ }
258
+ if (ctrl & TYPE6_STORE) {
259
+ flags |= BP_MEM_WRITE;
260
+ }
261
+
262
+ if ((wp->flags & flags) && (wp->vaddr == addr)) {
263
+ if (riscv_cpu_virt_enabled(env)) {
264
+ /* check VU/VS bit against current privilege level */
265
+ if ((ctrl >> 23) & BIT(env->priv)) {
266
+ return true;
267
+ }
268
+ } else {
269
+ /* check U/S/M bit against current privilege level */
270
+ if ((ctrl >> 3) & BIT(env->priv)) {
271
+ return true;
272
+ }
273
+ }
274
+ }
275
+ break;
276
default:
277
/* other trigger types are not supported */
278
break;
60
--
279
--
61
2.31.1
280
2.37.3
62
63
diff view generated by jsdifflib
New patch
[PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code
1
From: Yang Liu <liuyang22@iscas.ac.cn>
1
2
3
Remove duplicate code by wrapping vfwredsum_vs's OP function.
4
5
Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Message-Id: <20220817074802.20765-1-liuyang22@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/vector_helper.c | 56 +++++++-----------------------------
12
1 file changed, 10 insertions(+), 46 deletions(-)
13
14
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/vector_helper.c
17
+++ b/target/riscv/vector_helper.c
18
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number)
19
GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number)
20
GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number)
21
22
-/* Vector Widening Floating-Point Reduction Instructions */
23
-/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
24
-void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
25
- void *vs2, CPURISCVState *env, uint32_t desc)
26
+/* Vector Widening Floating-Point Add Instructions */
27
+static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
28
{
29
- uint32_t vm = vext_vm(desc);
30
- uint32_t vl = env->vl;
31
- uint32_t esz = sizeof(uint32_t);
32
- uint32_t vlenb = simd_maxsz(desc);
33
- uint32_t vta = vext_vta(desc);
34
- uint32_t i;
35
- uint32_t s1 = *((uint32_t *)vs1 + H4(0));
36
-
37
- for (i = env->vstart; i < vl; i++) {
38
- uint16_t s2 = *((uint16_t *)vs2 + H2(i));
39
- if (!vm && !vext_elem_mask(v0, i)) {
40
- continue;
41
- }
42
- s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
43
- &env->fp_status);
44
- }
45
- *((uint32_t *)vd + H4(0)) = s1;
46
- env->vstart = 0;
47
- /* set tail elements to 1s */
48
- vext_set_elems_1s(vd, vta, esz, vlenb);
49
+ return float32_add(a, float16_to_float32(b, true, s), s);
50
}
51
52
-void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
53
- void *vs2, CPURISCVState *env, uint32_t desc)
54
+static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s)
55
{
56
- uint32_t vm = vext_vm(desc);
57
- uint32_t vl = env->vl;
58
- uint32_t esz = sizeof(uint64_t);
59
- uint32_t vlenb = simd_maxsz(desc);
60
- uint32_t vta = vext_vta(desc);
61
- uint32_t i;
62
- uint64_t s1 = *((uint64_t *)vs1);
63
-
64
- for (i = env->vstart; i < vl; i++) {
65
- uint32_t s2 = *((uint32_t *)vs2 + H4(i));
66
- if (!vm && !vext_elem_mask(v0, i)) {
67
- continue;
68
- }
69
- s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
70
- &env->fp_status);
71
- }
72
- *((uint64_t *)vd) = s1;
73
- env->vstart = 0;
74
- /* set tail elements to 1s */
75
- vext_set_elems_1s(vd, vta, esz, vlenb);
76
+ return float64_add(a, float32_to_float64(b, s), s);
77
}
78
79
+/* Vector Widening Floating-Point Reduction Instructions */
80
+/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
81
+GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
82
+GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
83
+
84
/*
85
*** Vector Mask Operations
86
*/
87
--
88
2.37.3
diff view generated by jsdifflib
New patch
[PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
1
From: Yang Liu <liuyang22@iscas.ac.cn>
1
2
3
Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed
4
to vf[w]redusum_vs. The distinction between ordered and unordered is also
5
more consistent with other instructions, although there is no difference
6
in implementation between the two for QEMU.
7
8
Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Frank Chang <frank.chang@sifive.com>
11
Message-Id: <20220817074802.20765-2-liuyang22@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/helper.h | 15 ++++++++++-----
15
target/riscv/insn32.decode | 6 ++++--
16
target/riscv/vector_helper.c | 19 +++++++++++++------
17
target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
18
4 files changed, 31 insertions(+), 15 deletions(-)
19
20
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/helper.h
23
+++ b/target/riscv/helper.h
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
25
DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
26
DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
27
28
-DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
29
-DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
30
-DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
31
+DEF_HELPER_6(vfredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
32
+DEF_HELPER_6(vfredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
33
+DEF_HELPER_6(vfredusum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
34
+DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
35
+DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
36
+DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
37
DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
38
DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
39
DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
40
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
41
DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
42
DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
43
44
-DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
45
-DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
46
+DEF_HELPER_6(vfwredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
47
+DEF_HELPER_6(vfwredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
48
+DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
49
+DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
50
51
DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
52
DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
53
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/insn32.decode
56
+++ b/target/riscv/insn32.decode
57
@@ -XXX,XX +XXX,XX @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
58
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
59
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
60
# Vector ordered and unordered reduction sum
61
-vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
62
+vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
63
+vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
64
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
65
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
66
# Vector widening ordered and unordered float reduction sum
67
-vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
68
+vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
69
+vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
70
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
71
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
72
vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
73
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/vector_helper.c
76
+++ b/target/riscv/vector_helper.c
77
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
78
}
79
80
/* Unordered sum */
81
-GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add)
82
-GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
83
-GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
84
+GEN_VEXT_FRED(vfredusum_vs_h, uint16_t, uint16_t, H2, H2, float16_add)
85
+GEN_VEXT_FRED(vfredusum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
86
+GEN_VEXT_FRED(vfredusum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
87
+
88
+/* Ordered sum */
89
+GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, float16_add)
90
+GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
91
+GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
92
93
/* Maximum value */
94
GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number)
95
@@ -XXX,XX +XXX,XX @@ static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s)
96
}
97
98
/* Vector Widening Floating-Point Reduction Instructions */
99
-/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
100
-GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
101
-GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
102
+/* Ordered/unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
103
+GEN_VEXT_FRED(vfwredusum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
104
+GEN_VEXT_FRED(vfwredusum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
105
+GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
106
+GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
107
108
/*
109
*** Vector Mask Operations
110
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/riscv/insn_trans/trans_rvv.c.inc
113
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
114
@@ -XXX,XX +XXX,XX @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
115
require_zve64f(s);
116
}
117
118
-GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
119
+GEN_OPFVV_TRANS(vfredusum_vs, freduction_check)
120
+GEN_OPFVV_TRANS(vfredosum_vs, freduction_check)
121
GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
122
GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
123
124
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
125
(s->sew != MO_8);
126
}
127
128
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check)
129
+GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
130
+GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check)
131
132
/*
133
*** Vector Mask Operations
134
--
135
2.37.3
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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