[PULL 0/2] riscv-to-apply queue
[PULL v2 00/19] riscv-to-apply queue
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
3
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
4
4
5
Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
5
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging (2022-06-30 22:04:12 +0530)
6
6
7
are available in the Git repository at:
7
are available in the Git repository at:
8
8
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220703-1
10
10
11
for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
11
for you to fetch changes up to 435774992e82d2d16f025afbb20b4f7be9b242b0:
12
12
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
13
target/riscv: Update default priority table for local interrupts (2022-07-03 10:03:20 +1000)
14
14
15
----------------------------------------------------------------
15
----------------------------------------------------------------
16
Seventh RISC-V PR for QEMU 6.2
16
Fifth RISC-V PR for QEMU 7.1
17
17
18
- Deprecate IF_NONE for SiFive OTP
18
* Fix register zero guarding for auipc and lui
19
- Don't reset SiFive OTP content
19
* Ensure bins (mtval) is set correctly
20
* Minimize the calls to decode_save_opc
21
* Guard against PMP ranges with a negative size
22
* Implement mcountinhibit CSR
23
* Add support for hpmcounters/hpmevents
24
* Improve PMU implenentation
25
* Support mcycle/minstret write operation
26
* Fixup MSECCFG minimum priv check
27
* Ibex (OpenTitan) fixup priv version
28
* Fix bug resulting in always using latest priv spec
29
* Reduce FDT address alignment constraints
30
* Set minumum priv spec version for mcountinhibit
31
* AIA update to v0.3 of the spec
20
32
21
----------------------------------------------------------------
33
----------------------------------------------------------------
22
Philippe Mathieu-Daudé (1):
34
Alistair Francis (3):
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
35
target/riscv: Fixup MSECCFG minimum priv check
36
target/riscv: Ibex: Support priv version 1.11
37
hw/riscv: boot: Reduce FDT address alignment constraints
24
38
25
Thomas Huth (1):
39
Anup Patel (4):
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
40
target/riscv: Don't force update priv spec version to latest
41
target/riscv: Set minumum priv spec version for mcountinhibit
42
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
43
target/riscv: Update default priority table for local interrupts
27
44
28
docs/about/deprecated.rst | 6 ++++++
45
Atish Patra (7):
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
46
target/riscv: Fix PMU CSR predicate function
30
2 files changed, 19 insertions(+), 9 deletions(-)
47
target/riscv: Implement PMU CSR predicate function for S-mode
48
target/riscv: pmu: Rename the counters extension to pmu
49
target/riscv: pmu: Make number of counters configurable
50
target/riscv: Implement mcountinhibit CSR
51
target/riscv: Add support for hpmcounters/hpmevents
52
target/riscv: Support mcycle/minstret write operation
31
53
54
Nicolas Pitre (1):
55
target/riscv/pmp: guard against PMP ranges with a negative size
56
57
Richard Henderson (3):
58
target/riscv: Set env->bins in gen_exception_illegal
59
target/riscv: Remove generate_exception_mtval
60
target/riscv: Minimize the calls to decode_save_opc
61
62
Víctor Colombo (1):
63
target/riscv: Remove condition guarding register zero for auipc and lui
64
65
target/riscv/cpu.h | 24 +-
66
target/riscv/cpu_bits.h | 30 +-
67
target/riscv/pmu.h | 28 +
68
hw/riscv/boot.c | 4 +-
69
target/riscv/cpu.c | 17 +-
70
target/riscv/cpu_helper.c | 134 ++--
71
target/riscv/csr.c | 857 +++++++++++++++----------
72
target/riscv/machine.c | 25 +
73
target/riscv/pmp.c | 3 +
74
target/riscv/pmu.c | 32 +
75
target/riscv/translate.c | 31 +-
76
target/riscv/insn_trans/trans_privileged.c.inc | 4 +
77
target/riscv/insn_trans/trans_rvh.c.inc | 2 +
78
target/riscv/insn_trans/trans_rvi.c.inc | 10 +-
79
target/riscv/meson.build | 3 +-
80
tests/tcg/riscv64/Makefile.softmmu-target | 21 +
81
tests/tcg/riscv64/issue1060.S | 53 ++
82
tests/tcg/riscv64/semihost.ld | 21 +
83
18 files changed, 843 insertions(+), 456 deletions(-)
84
create mode 100644 target/riscv/pmu.h
85
create mode 100644 target/riscv/pmu.c
86
create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
87
create mode 100644 tests/tcg/riscv64/issue1060.S
88
create mode 100644 tests/tcg/riscv64/semihost.ld
diff view generated by jsdifflib
New patch
[PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui
1
From: Víctor Colombo <victor.colombo@eldorado.org.br>
1
2
3
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
4
a check for if the destination register is 'zero'. The check in auipc
5
and lui are then redundant. This patch removes those checks.
6
7
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
14
1 file changed, 2 insertions(+), 6 deletions(-)
15
16
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn_trans/trans_rvi.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
21
22
static bool trans_lui(DisasContext *ctx, arg_lui *a)
23
{
24
- if (a->rd != 0) {
25
- gen_set_gpri(ctx, a->rd, a->imm);
26
- }
27
+ gen_set_gpri(ctx, a->rd, a->imm);
28
return true;
29
}
30
31
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
32
{
33
- if (a->rd != 0) {
34
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
35
- }
36
+ gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
37
return true;
38
}
39
40
--
41
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
While we set env->bins when unwinding for ILLEGAL_INST,
4
from e.g. csrrw, we weren't setting it for immediately
5
illegal instructions.
6
7
Add a testcase for mtval via both exception paths.
8
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/translate.c | 2 +
16
tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++
17
tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++++++
18
tests/tcg/riscv64/semihost.ld | 21 +++++++++
19
4 files changed, 97 insertions(+)
20
create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
21
create mode 100644 tests/tcg/riscv64/issue1060.S
22
create mode 100644 tests/tcg/riscv64/semihost.ld
23
24
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/translate.c
27
+++ b/target/riscv/translate.c
28
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
29
30
static void gen_exception_illegal(DisasContext *ctx)
31
{
32
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
33
+ offsetof(CPURISCVState, bins));
34
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
35
}
36
37
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
38
new file mode 100644
39
index XXXXXXX..XXXXXXX
40
--- /dev/null
41
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
42
@@ -XXX,XX +XXX,XX @@
43
+#
44
+# RISC-V system tests
45
+#
46
+
47
+TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
48
+VPATH += $(TEST_SRC)
49
+
50
+LINK_SCRIPT = $(TEST_SRC)/semihost.ld
51
+LDFLAGS = -T $(LINK_SCRIPT)
52
+CFLAGS += -g -Og
53
+
54
+%.o: %.S
55
+    $(CC) $(CFLAGS) $< -c -o $@
56
+%: %.o $(LINK_SCRIPT)
57
+    $(LD) $(LDFLAGS) $< -o $@
58
+
59
+QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
60
+
61
+EXTRA_RUNS += run-issue1060
62
+run-issue1060: issue1060
63
+    $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
64
diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/tests/tcg/riscv64/issue1060.S
69
@@ -XXX,XX +XXX,XX @@
70
+    .option    norvc
71
+
72
+    .text
73
+    .global _start
74
+_start:
75
+    lla    t0, trap
76
+    csrw    mtvec, t0
77
+
78
+    # These are all illegal instructions
79
+    csrw    time, x0
80
+    .insn    i CUSTOM_0, 0, x0, x0, 0x321
81
+    csrw    time, x0
82
+    .insn    i CUSTOM_0, 0, x0, x0, 0x123
83
+    csrw    cycle, x0
84
+
85
+    # Success!
86
+    li    a0, 0
87
+    j    _exit
88
+
89
+trap:
90
+    # When an instruction traps, compare it to the insn in memory.
91
+    csrr    t0, mepc
92
+    csrr    t1, mtval
93
+    lwu    t2, 0(t0)
94
+    bne    t1, t2, fail
95
+
96
+    # Skip the insn and continue.
97
+    addi    t0, t0, 4
98
+    csrw    mepc, t0
99
+    mret
100
+
101
+fail:
102
+    li    a0, 1
103
+
104
+# Exit code in a0
105
+_exit:
106
+    lla    a1, semiargs
107
+    li    t0, 0x20026    # ADP_Stopped_ApplicationExit
108
+    sd    t0, 0(a1)
109
+    sd    a0, 8(a1)
110
+    li    a0, 0x20    # TARGET_SYS_EXIT_EXTENDED
111
+
112
+    # Semihosting call sequence
113
+    .balign    16
114
+    slli    zero, zero, 0x1f
115
+    ebreak
116
+    srai    zero, zero, 0x7
117
+    j    .
118
+
119
+    .data
120
+    .balign    16
121
+semiargs:
122
+    .space    16
123
diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld
124
new file mode 100644
125
index XXXXXXX..XXXXXXX
126
--- /dev/null
127
+++ b/tests/tcg/riscv64/semihost.ld
128
@@ -XXX,XX +XXX,XX @@
129
+ENTRY(_start)
130
+
131
+SECTIONS
132
+{
133
+ /* virt machine, RAM starts at 2gb */
134
+ . = 0x80000000;
135
+ .text : {
136
+ *(.text)
137
+ }
138
+ .rodata : {
139
+ *(.rodata)
140
+ }
141
+ /* align r/w section to next 2mb */
142
+ . = ALIGN(1 << 21);
143
+ .data : {
144
+ *(.data)
145
+ }
146
+ .bss : {
147
+ *(.bss)
148
+ }
149
+}
150
--
151
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 03/19] target/riscv: Remove generate_exception_mtval
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The function doesn't set mtval, it sets badaddr. Move the set
4
of badaddr directly into gen_exception_inst_addr_mis and use
5
generate_exception.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/translate.c | 11 ++---------
13
1 file changed, 2 insertions(+), 9 deletions(-)
14
15
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/translate.c
18
+++ b/target/riscv/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
20
ctx->base.is_jmp = DISAS_NORETURN;
21
}
22
23
-static void generate_exception_mtval(DisasContext *ctx, int excp)
24
-{
25
- gen_set_pc_imm(ctx, ctx->base.pc_next);
26
- tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
27
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
28
- ctx->base.is_jmp = DISAS_NORETURN;
29
-}
30
-
31
static void gen_exception_illegal(DisasContext *ctx)
32
{
33
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
34
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
35
36
static void gen_exception_inst_addr_mis(DisasContext *ctx)
37
{
38
- generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
39
+ tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
40
+ generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
41
}
42
43
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
44
--
45
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The set of instructions that require decode_save_opc for
4
unwinding is really fairly small -- only insns that can
5
raise ILLEGAL_INSN at runtime. This includes CSR, anything
6
that uses a *new* fp rounding mode, and many privileged insns.
7
8
Since unwind info is stored as the difference from the
9
previous insn, storing a 0 for most insns minimizes the
10
size of the unwind info.
11
12
Booting a debian kernel image to the missing rootfs panic yields
13
14
- gen code size 22226819/1026886656
15
+ gen code size 21601907/1026886656
16
17
on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.
18
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
21
Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
22
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
23
---
24
target/riscv/translate.c | 18 +++++++++---------
25
target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
26
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
27
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
28
4 files changed, 17 insertions(+), 9 deletions(-)
29
30
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/translate.c
33
+++ b/target/riscv/translate.c
34
@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
35
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
36
}
37
38
+static void decode_save_opc(DisasContext *ctx)
39
+{
40
+ assert(ctx->insn_start != NULL);
41
+ tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
42
+ ctx->insn_start = NULL;
43
+}
44
+
45
static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
46
{
47
if (get_xl(ctx) == MXL_RV32) {
48
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
49
return;
50
}
51
52
+ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
53
+ decode_save_opc(ctx);
54
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
55
}
56
57
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
58
/* Include decoders for factored-out extensions */
59
#include "decode-XVentanaCondOps.c.inc"
60
61
-static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
62
-{
63
- assert(ctx->insn_start != NULL);
64
- tcg_set_insn_start_param(ctx->insn_start, 1, opc);
65
- ctx->insn_start = NULL;
66
-}
67
-
68
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
69
{
70
/*
71
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
72
73
/* Check for compressed insn */
74
if (extract16(opcode, 0, 2) != 3) {
75
- decode_save_opc(ctx, opcode);
76
if (!has_ext(ctx, RVC)) {
77
gen_exception_illegal(ctx);
78
} else {
79
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
80
opcode32 = deposit32(opcode32, 16, 16,
81
translator_lduw(env, &ctx->base,
82
ctx->base.pc_next + 2));
83
- decode_save_opc(ctx, opcode32);
84
ctx->opcode = opcode32;
85
ctx->pc_succ_insn = ctx->base.pc_next + 4;
86
87
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/riscv/insn_trans/trans_privileged.c.inc
90
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
91
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
92
{
93
#ifndef CONFIG_USER_ONLY
94
if (has_ext(ctx, RVS)) {
95
+ decode_save_opc(ctx);
96
gen_helper_sret(cpu_pc, cpu_env);
97
tcg_gen_exit_tb(NULL, 0); /* no chaining */
98
ctx->base.is_jmp = DISAS_NORETURN;
99
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
100
static bool trans_mret(DisasContext *ctx, arg_mret *a)
101
{
102
#ifndef CONFIG_USER_ONLY
103
+ decode_save_opc(ctx);
104
gen_helper_mret(cpu_pc, cpu_env);
105
tcg_gen_exit_tb(NULL, 0); /* no chaining */
106
ctx->base.is_jmp = DISAS_NORETURN;
107
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
108
static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
109
{
110
#ifndef CONFIG_USER_ONLY
111
+ decode_save_opc(ctx);
112
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
113
gen_helper_wfi(cpu_env);
114
return true;
115
@@ -XXX,XX +XXX,XX @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
116
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
117
{
118
#ifndef CONFIG_USER_ONLY
119
+ decode_save_opc(ctx);
120
gen_helper_tlb_flush(cpu_env);
121
return true;
122
#endif
123
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
124
index XXXXXXX..XXXXXXX 100644
125
--- a/target/riscv/insn_trans/trans_rvh.c.inc
126
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
127
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
128
{
129
REQUIRE_EXT(ctx, RVH);
130
#ifndef CONFIG_USER_ONLY
131
+ decode_save_opc(ctx);
132
gen_helper_hyp_gvma_tlb_flush(cpu_env);
133
return true;
134
#endif
135
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
136
{
137
REQUIRE_EXT(ctx, RVH);
138
#ifndef CONFIG_USER_ONLY
139
+ decode_save_opc(ctx);
140
gen_helper_hyp_tlb_flush(cpu_env);
141
return true;
142
#endif
143
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
144
index XXXXXXX..XXXXXXX 100644
145
--- a/target/riscv/insn_trans/trans_rvi.c.inc
146
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
147
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
148
149
static bool do_csr_post(DisasContext *ctx)
150
{
151
+ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
152
+ decode_save_opc(ctx);
153
/* We may have changed important cpu state -- exit to main loop. */
154
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
155
tcg_gen_exit_tb(NULL, 0);
156
--
157
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size
1
From: Nicolas Pitre <nico@fluxnic.net>
1
2
3
For a TOR entry to match, the stard address must be lower than the end
4
address. Normally this is always the case, but correct code might still
5
run into the following scenario:
6
7
Initial state:
8
9
    pmpaddr3 = 0x2000    pmp3cfg = OFF
10
    pmpaddr4 = 0x3000    pmp4cfg = TOR
11
12
Execution:
13
14
    1. write 0x40ff to pmpaddr3
15
    2. write 0x32ff to pmpaddr4
16
    3. set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0
17
    4. set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1
18
19
When (2) is emulated, a call to pmp_update_rule() creates a negative
20
range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated,
21
a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return
22
a very creatively large TLB size for pmp4. This, in turn, may result in
23
accesses to non-existent/unitialized memory regions and a fault, so that
24
(4) ends up never being executed.
25
26
This is in m-mode with MPRV unset, meaning that unlocked PMP entries
27
should have no effect. Therefore such a behavior based on PMP content
28
is very unexpected.
29
30
Make sure no negative PMP range can be created, whether explicitly by
31
the emulated code or implicitly like the above.
32
33
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
35
Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg>
36
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
37
---
38
target/riscv/pmp.c | 3 +++
39
1 file changed, 3 insertions(+)
40
41
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/riscv/pmp.c
44
+++ b/target/riscv/pmp.c
45
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
46
case PMP_AMATCH_TOR:
47
sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
48
ea = (this_addr << 2) - 1u;
49
+ if (sa > ea) {
50
+ sa = ea = 0u;
51
+ }
52
break;
53
54
case PMP_AMATCH_NA4:
55
--
56
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 06/19] target/riscv: Fix PMU CSR predicate function
1
From: Atish Patra <atish.patra@wdc.com>
1
2
3
The predicate function calculates the counter index incorrectly for
4
hpmcounterx. Fix the counter index to reflect correct CSR number.
5
6
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Signed-off-by: Atish Patra <atish.patra@wdc.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/csr.c | 11 +++++++----
15
1 file changed, 7 insertions(+), 4 deletions(-)
16
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
21
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
22
#if !defined(CONFIG_USER_ONLY)
23
CPUState *cs = env_cpu(env);
24
RISCVCPU *cpu = RISCV_CPU(cs);
25
+ int ctr_index;
26
27
if (!cpu->cfg.ext_counters) {
28
/* The Counters extensions is not enabled */
29
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
30
}
31
break;
32
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
33
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
34
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
35
+ ctr_index = csrno - CSR_CYCLE;
36
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
37
+ get_field(env->mcounteren, 1 << ctr_index)) {
38
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
39
}
40
break;
41
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
42
}
43
break;
44
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
45
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
46
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
47
+ ctr_index = csrno - CSR_CYCLEH;
48
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
49
+ get_field(env->mcounteren, 1 << ctr_index)) {
50
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
51
}
52
break;
53
--
54
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode
1
From: Atish Patra <atish.patra@wdc.com>
1
2
3
Currently, the predicate function for PMU related CSRs only works if
4
virtualization is enabled. It also does not check mcounteren bits before
5
before cycle/minstret/hpmcounterx access.
6
7
Support supervisor mode access in the predicate function as well.
8
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Signed-off-by: Atish Patra <atish.patra@wdc.com>
12
Signed-off-by: Atish Patra <atishp@rivosinc.com>
13
Message-Id: <20220620231603.2547260-3-atishp@rivosinc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
17
1 file changed, 51 insertions(+)
18
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
23
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
24
return RISCV_EXCP_ILLEGAL_INST;
25
}
26
27
+ if (env->priv == PRV_S) {
28
+ switch (csrno) {
29
+ case CSR_CYCLE:
30
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
31
+ return RISCV_EXCP_ILLEGAL_INST;
32
+ }
33
+ break;
34
+ case CSR_TIME:
35
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
36
+ return RISCV_EXCP_ILLEGAL_INST;
37
+ }
38
+ break;
39
+ case CSR_INSTRET:
40
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
41
+ return RISCV_EXCP_ILLEGAL_INST;
42
+ }
43
+ break;
44
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
45
+ ctr_index = csrno - CSR_CYCLE;
46
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
47
+ return RISCV_EXCP_ILLEGAL_INST;
48
+ }
49
+ break;
50
+ }
51
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
52
+ switch (csrno) {
53
+ case CSR_CYCLEH:
54
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
55
+ return RISCV_EXCP_ILLEGAL_INST;
56
+ }
57
+ break;
58
+ case CSR_TIMEH:
59
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
60
+ return RISCV_EXCP_ILLEGAL_INST;
61
+ }
62
+ break;
63
+ case CSR_INSTRETH:
64
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
65
+ return RISCV_EXCP_ILLEGAL_INST;
66
+ }
67
+ break;
68
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
69
+ ctr_index = csrno - CSR_CYCLEH;
70
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
71
+ return RISCV_EXCP_ILLEGAL_INST;
72
+ }
73
+ break;
74
+ }
75
+ }
76
+ }
77
+
78
if (riscv_cpu_virt_enabled(env)) {
79
switch (csrno) {
80
case CSR_CYCLE:
81
--
82
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu
1
From: Atish Patra <atish.patra@wdc.com>
1
2
3
The PMU counters are supported via cpu config "Counters" which doesn't
4
indicate the correct purpose of those counters.
5
6
Rename the config property to pmu to indicate that these counters
7
are performance monitoring counters. This aligns with cpu options for
8
ARM architecture as well.
9
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Atish Patra <atish.patra@wdc.com>
13
Signed-off-by: Atish Patra <atishp@rivosinc.com>
14
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.h | 2 +-
18
target/riscv/cpu.c | 4 ++--
19
target/riscv/csr.c | 4 ++--
20
3 files changed, 5 insertions(+), 5 deletions(-)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
27
bool ext_zksed;
28
bool ext_zksh;
29
bool ext_zkt;
30
- bool ext_counters;
31
+ bool ext_pmu;
32
bool ext_ifencei;
33
bool ext_icsr;
34
bool ext_svinval;
35
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu.c
38
+++ b/target/riscv/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
40
{
41
RISCVCPU *cpu = RISCV_CPU(obj);
42
43
- cpu->cfg.ext_counters = true;
44
+ cpu->cfg.ext_pmu = true;
45
cpu->cfg.ext_ifencei = true;
46
cpu->cfg.ext_icsr = true;
47
cpu->cfg.mmu = true;
48
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
49
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
50
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
51
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
52
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
53
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
54
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
55
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
56
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
57
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/csr.c
60
+++ b/target/riscv/csr.c
61
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
62
RISCVCPU *cpu = RISCV_CPU(cs);
63
int ctr_index;
64
65
- if (!cpu->cfg.ext_counters) {
66
- /* The Counters extensions is not enabled */
67
+ if (!cpu->cfg.ext_pmu) {
68
+ /* The PMU extension is not enabled */
69
return RISCV_EXCP_ILLEGAL_INST;
70
}
71
72
--
73
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 09/19] target/riscv: pmu: Make number of counters configurable
1
From: Atish Patra <atishp@rivosinc.com>
1
2
3
The RISC-V privilege specification provides flexibility to implement
4
any number of counters from 29 programmable counters. However, the QEMU
5
implements all the counters.
6
7
Make it configurable through pmu config parameter which now will indicate
8
how many programmable counters should be implemented by the cpu.
9
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Atish Patra <atish.patra@wdc.com>
13
Signed-off-by: Atish Patra <atishp@rivosinc.com>
14
Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.h | 2 +-
18
target/riscv/cpu.c | 3 +-
19
target/riscv/csr.c | 94 ++++++++++++++++++++++++++++++----------------
20
3 files changed, 63 insertions(+), 36 deletions(-)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
27
bool ext_zksed;
28
bool ext_zksh;
29
bool ext_zkt;
30
- bool ext_pmu;
31
bool ext_ifencei;
32
bool ext_icsr;
33
bool ext_svinval;
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
35
/* Vendor-specific custom extensions */
36
bool ext_XVentanaCondOps;
37
38
+ uint8_t pmu_num;
39
char *priv_spec;
40
char *user_spec;
41
char *bext_spec;
42
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/riscv/cpu.c
45
+++ b/target/riscv/cpu.c
46
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
47
{
48
RISCVCPU *cpu = RISCV_CPU(obj);
49
50
- cpu->cfg.ext_pmu = true;
51
cpu->cfg.ext_ifencei = true;
52
cpu->cfg.ext_icsr = true;
53
cpu->cfg.mmu = true;
54
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
55
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
56
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
57
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
58
- DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
59
+ DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
60
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
61
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
62
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
63
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/riscv/csr.c
66
+++ b/target/riscv/csr.c
67
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
68
CPUState *cs = env_cpu(env);
69
RISCVCPU *cpu = RISCV_CPU(cs);
70
int ctr_index;
71
+ int base_csrno = CSR_HPMCOUNTER3;
72
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
73
74
- if (!cpu->cfg.ext_pmu) {
75
- /* The PMU extension is not enabled */
76
+ if (rv32 && csrno >= CSR_CYCLEH) {
77
+ /* Offset for RV32 hpmcounternh counters */
78
+ base_csrno += 0x80;
79
+ }
80
+ ctr_index = csrno - base_csrno;
81
+
82
+ if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num)) {
83
+ /* No counter is enabled in PMU or the counter is out of range */
84
return RISCV_EXCP_ILLEGAL_INST;
85
}
86
87
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
88
}
89
break;
90
}
91
- if (riscv_cpu_mxl(env) == MXL_RV32) {
92
+ if (rv32) {
93
switch (csrno) {
94
case CSR_CYCLEH:
95
if (!get_field(env->mcounteren, COUNTEREN_CY)) {
96
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
97
}
98
break;
99
}
100
- if (riscv_cpu_mxl(env) == MXL_RV32) {
101
+ if (rv32) {
102
switch (csrno) {
103
case CSR_CYCLEH:
104
if (!get_field(env->hcounteren, COUNTEREN_CY) &&
105
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
106
}
107
108
#if !defined(CONFIG_USER_ONLY)
109
+static RISCVException mctr(CPURISCVState *env, int csrno)
110
+{
111
+ CPUState *cs = env_cpu(env);
112
+ RISCVCPU *cpu = RISCV_CPU(cs);
113
+ int ctr_index;
114
+ int base_csrno = CSR_MHPMCOUNTER3;
115
+
116
+ if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) {
117
+ /* Offset for RV32 mhpmcounternh counters */
118
+ base_csrno += 0x80;
119
+ }
120
+ ctr_index = csrno - base_csrno;
121
+ if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
122
+ /* The PMU is not enabled or counter is out of range*/
123
+ return RISCV_EXCP_ILLEGAL_INST;
124
+ }
125
+
126
+ return RISCV_EXCP_NONE;
127
+}
128
+
129
static RISCVException any(CPURISCVState *env, int csrno)
130
{
131
return RISCV_EXCP_NONE;
132
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
133
[CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
134
[CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
135
136
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
137
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
138
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
139
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
140
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
141
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
142
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
143
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
144
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
145
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
146
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
147
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
148
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
149
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
150
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
151
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
152
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
153
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
154
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
155
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
156
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
157
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
158
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
159
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
160
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
161
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
162
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
163
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
164
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
165
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
166
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
167
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
168
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
169
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
170
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
171
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
172
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
173
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
174
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
175
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
176
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
177
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
178
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
179
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
180
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
181
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
182
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
183
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
184
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
185
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
186
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
187
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
188
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
189
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
190
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
191
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
192
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
193
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
194
195
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
196
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
197
--
198
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 10/19] target/riscv: Implement mcountinhibit CSR
1
From: Atish Patra <atish.patra@wdc.com>
1
2
3
As per the privilege specification v1.11, mcountinhibit allows to start/stop
4
a pmu counter selectively.
5
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Atish Patra <atish.patra@wdc.com>
9
Signed-off-by: Atish Patra <atishp@rivosinc.com>
10
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu.h | 2 ++
14
target/riscv/cpu_bits.h | 4 ++++
15
target/riscv/csr.c | 25 +++++++++++++++++++++++++
16
target/riscv/machine.c | 1 +
17
4 files changed, 32 insertions(+)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
24
target_ulong scounteren;
25
target_ulong mcounteren;
26
27
+ target_ulong mcountinhibit;
28
+
29
target_ulong sscratch;
30
target_ulong mscratch;
31
32
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/cpu_bits.h
35
+++ b/target/riscv/cpu_bits.h
36
@@ -XXX,XX +XXX,XX @@
37
#define CSR_MHPMCOUNTER29 0xb1d
38
#define CSR_MHPMCOUNTER30 0xb1e
39
#define CSR_MHPMCOUNTER31 0xb1f
40
+
41
+/* Machine counter-inhibit register */
42
+#define CSR_MCOUNTINHIBIT 0x320
43
+
44
#define CSR_MHPMEVENT3 0x323
45
#define CSR_MHPMEVENT4 0x324
46
#define CSR_MHPMEVENT5 0x325
47
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/csr.c
50
+++ b/target/riscv/csr.c
51
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
52
return RISCV_EXCP_NONE;
53
}
54
55
+static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
56
+ target_ulong *val)
57
+{
58
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
59
+ return RISCV_EXCP_ILLEGAL_INST;
60
+ }
61
+
62
+ *val = env->mcountinhibit;
63
+ return RISCV_EXCP_NONE;
64
+}
65
+
66
+static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
67
+ target_ulong val)
68
+{
69
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
70
+ return RISCV_EXCP_ILLEGAL_INST;
71
+ }
72
+
73
+ env->mcountinhibit = val;
74
+ return RISCV_EXCP_NONE;
75
+}
76
+
77
static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
78
target_ulong *val)
79
{
80
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
81
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
82
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
83
84
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
85
+ write_mcountinhibit },
86
+
87
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
88
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
89
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
90
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/riscv/machine.c
93
+++ b/target/riscv/machine.c
94
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
95
VMSTATE_UINTTL(env.siselect, RISCVCPU),
96
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
97
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
98
+ VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
99
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
100
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
101
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
102
--
103
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents
1
From: Atish Patra <atish.patra@wdc.com>
1
2
3
With SBI PMU extension, user can use any of the available hpmcounters to
4
track any perf events based on the value written to mhpmevent csr.
5
Add read/write functionality for these csrs.
6
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Signed-off-by: Atish Patra <atish.patra@wdc.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu.h | 11 +
15
target/riscv/csr.c | 469 ++++++++++++++++++++++++++++-------------
16
target/riscv/machine.c | 3 +
17
3 files changed, 331 insertions(+), 152 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState CPURISCVState;
24
#endif
25
26
#define RV_VLEN_MAX 1024
27
+#define RV_MAX_MHPMEVENTS 29
28
+#define RV_MAX_MHPMCOUNTERS 32
29
30
FIELD(VTYPE, VLMUL, 0, 3)
31
FIELD(VTYPE, VSEW, 3, 3)
32
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
33
34
target_ulong mcountinhibit;
35
36
+ /* PMU counter configured values */
37
+ target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
38
+
39
+ /* for RV32 */
40
+ target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
41
+
42
+ /* PMU event selector configured values */
43
+ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
44
+
45
target_ulong sscratch;
46
target_ulong mscratch;
47
48
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/csr.c
51
+++ b/target/riscv/csr.c
52
@@ -XXX,XX +XXX,XX @@ static RISCVException mctr(CPURISCVState *env, int csrno)
53
return RISCV_EXCP_NONE;
54
}
55
56
+static RISCVException mctr32(CPURISCVState *env, int csrno)
57
+{
58
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
59
+ return RISCV_EXCP_ILLEGAL_INST;
60
+ }
61
+
62
+ return mctr(env, csrno);
63
+}
64
+
65
static RISCVException any(CPURISCVState *env, int csrno)
66
{
67
return RISCV_EXCP_NONE;
68
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
69
70
#else /* CONFIG_USER_ONLY */
71
72
+static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
73
+{
74
+ int evt_index = csrno - CSR_MHPMEVENT3;
75
+
76
+ *val = env->mhpmevent_val[evt_index];
77
+
78
+ return RISCV_EXCP_NONE;
79
+}
80
+
81
+static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
82
+{
83
+ int evt_index = csrno - CSR_MHPMEVENT3;
84
+
85
+ env->mhpmevent_val[evt_index] = val;
86
+
87
+ return RISCV_EXCP_NONE;
88
+}
89
+
90
+static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
91
+{
92
+ int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
93
+
94
+ env->mhpmcounter_val[ctr_index] = val;
95
+
96
+ return RISCV_EXCP_NONE;
97
+}
98
+
99
+static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
100
+{
101
+ int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
102
+
103
+ env->mhpmcounterh_val[ctr_index] = val;
104
+
105
+ return RISCV_EXCP_NONE;
106
+}
107
+
108
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
109
+{
110
+ int ctr_index;
111
+
112
+ if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
113
+ ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
114
+ } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
115
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
116
+ } else {
117
+ return RISCV_EXCP_ILLEGAL_INST;
118
+ }
119
+ *val = env->mhpmcounter_val[ctr_index];
120
+
121
+ return RISCV_EXCP_NONE;
122
+}
123
+
124
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
125
+{
126
+ int ctr_index;
127
+
128
+ if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
129
+ ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
130
+ } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
131
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
132
+ } else {
133
+ return RISCV_EXCP_ILLEGAL_INST;
134
+ }
135
+ *val = env->mhpmcounterh_val[ctr_index];
136
+
137
+ return RISCV_EXCP_NONE;
138
+}
139
+
140
+
141
static RISCVException read_time(CPURISCVState *env, int csrno,
142
target_ulong *val)
143
{
144
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
145
[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
146
147
/* Performance Counters */
148
- [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
149
- [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
150
- [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
151
- [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
152
- [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
153
- [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
154
- [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
155
- [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
156
- [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
157
- [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
158
- [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
159
- [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
160
- [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
161
- [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
162
- [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
163
- [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
164
- [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
165
- [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
166
- [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
167
- [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
168
- [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
169
- [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
170
- [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
171
- [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
172
- [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
173
- [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
174
- [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
175
- [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
176
- [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
177
-
178
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
179
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
180
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
181
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
182
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
183
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
184
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
185
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
186
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
187
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
188
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
189
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
190
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
191
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
192
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
193
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
194
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
195
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
196
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
197
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
198
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
199
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
200
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
201
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
202
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
203
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
204
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
205
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
206
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
207
-
208
- [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
209
- write_mcountinhibit },
210
-
211
- [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
212
- [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
213
- [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
214
- [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
215
- [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
216
- [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
217
- [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
218
- [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
219
- [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
220
- [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
221
- [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
222
- [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
223
- [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
224
- [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
225
- [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
226
- [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
227
- [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
228
- [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
229
- [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
230
- [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
231
- [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
232
- [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
233
- [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
234
- [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
235
- [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
236
- [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
237
- [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
238
- [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
239
- [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
240
-
241
- [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
242
- [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
243
- [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
244
- [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
245
- [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
246
- [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
247
- [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
248
- [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
249
- [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
250
- [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
251
- [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
252
- [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
253
- [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
254
- [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
255
- [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
256
- [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
257
- [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
258
- [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
259
- [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
260
- [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
261
- [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
262
- [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
263
- [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
264
- [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
265
- [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
266
- [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
267
- [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
268
- [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
269
- [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
270
-
271
- [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
272
- [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
273
- [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
274
- [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
275
- [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
276
- [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
277
- [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
278
- [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
279
- [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
280
- [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
281
- [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
282
- [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
283
- [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
284
- [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
285
- [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
286
- [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
287
- [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
288
- [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
289
- [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
290
- [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
291
- [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
292
- [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
293
- [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
294
- [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
295
- [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
296
- [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
297
- [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
298
- [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
299
- [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
300
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
301
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
302
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter },
303
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter },
304
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter },
305
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter },
306
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter },
307
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter },
308
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter },
309
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter },
310
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter },
311
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter },
312
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter },
313
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter },
314
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter },
315
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter },
316
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter },
317
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter },
318
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter },
319
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter },
320
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter },
321
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter },
322
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter },
323
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter },
324
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter },
325
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter },
326
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter },
327
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter },
328
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter },
329
+
330
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter,
331
+ write_mhpmcounter },
332
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter,
333
+ write_mhpmcounter },
334
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter,
335
+ write_mhpmcounter },
336
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter,
337
+ write_mhpmcounter },
338
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter,
339
+ write_mhpmcounter },
340
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter,
341
+ write_mhpmcounter },
342
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter,
343
+ write_mhpmcounter },
344
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter,
345
+ write_mhpmcounter },
346
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter,
347
+ write_mhpmcounter },
348
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter,
349
+ write_mhpmcounter },
350
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter,
351
+ write_mhpmcounter },
352
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter,
353
+ write_mhpmcounter },
354
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter,
355
+ write_mhpmcounter },
356
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter,
357
+ write_mhpmcounter },
358
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter,
359
+ write_mhpmcounter },
360
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter,
361
+ write_mhpmcounter },
362
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter,
363
+ write_mhpmcounter },
364
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter,
365
+ write_mhpmcounter },
366
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter,
367
+ write_mhpmcounter },
368
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter,
369
+ write_mhpmcounter },
370
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter,
371
+ write_mhpmcounter },
372
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter,
373
+ write_mhpmcounter },
374
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter,
375
+ write_mhpmcounter },
376
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter,
377
+ write_mhpmcounter },
378
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter,
379
+ write_mhpmcounter },
380
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter,
381
+ write_mhpmcounter },
382
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter,
383
+ write_mhpmcounter },
384
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter,
385
+ write_mhpmcounter },
386
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter,
387
+ write_mhpmcounter },
388
+
389
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
390
+ write_mcountinhibit },
391
+
392
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
393
+ write_mhpmevent },
394
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent,
395
+ write_mhpmevent },
396
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,
397
+ write_mhpmevent },
398
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent,
399
+ write_mhpmevent },
400
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent,
401
+ write_mhpmevent },
402
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent,
403
+ write_mhpmevent },
404
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent,
405
+ write_mhpmevent },
406
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent,
407
+ write_mhpmevent },
408
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent,
409
+ write_mhpmevent },
410
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent,
411
+ write_mhpmevent },
412
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent,
413
+ write_mhpmevent },
414
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent,
415
+ write_mhpmevent },
416
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent,
417
+ write_mhpmevent },
418
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent,
419
+ write_mhpmevent },
420
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent,
421
+ write_mhpmevent },
422
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent,
423
+ write_mhpmevent },
424
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent,
425
+ write_mhpmevent },
426
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent,
427
+ write_mhpmevent },
428
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent,
429
+ write_mhpmevent },
430
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent,
431
+ write_mhpmevent },
432
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent,
433
+ write_mhpmevent },
434
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent,
435
+ write_mhpmevent },
436
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent,
437
+ write_mhpmevent },
438
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent,
439
+ write_mhpmevent },
440
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent,
441
+ write_mhpmevent },
442
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,
443
+ write_mhpmevent },
444
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent,
445
+ write_mhpmevent },
446
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent,
447
+ write_mhpmevent },
448
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
449
+ write_mhpmevent },
450
+
451
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
452
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
453
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
454
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh },
455
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh },
456
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh },
457
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh },
458
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh },
459
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh },
460
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh },
461
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh },
462
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh },
463
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh },
464
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh },
465
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh },
466
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh },
467
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh },
468
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh },
469
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh },
470
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh },
471
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh },
472
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh },
473
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh },
474
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh },
475
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh },
476
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh },
477
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh },
478
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh },
479
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh },
480
+
481
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh,
482
+ write_mhpmcounterh },
483
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh,
484
+ write_mhpmcounterh },
485
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh,
486
+ write_mhpmcounterh },
487
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh,
488
+ write_mhpmcounterh },
489
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh,
490
+ write_mhpmcounterh },
491
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh,
492
+ write_mhpmcounterh },
493
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh,
494
+ write_mhpmcounterh },
495
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh,
496
+ write_mhpmcounterh },
497
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh,
498
+ write_mhpmcounterh },
499
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh,
500
+ write_mhpmcounterh },
501
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh,
502
+ write_mhpmcounterh },
503
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh,
504
+ write_mhpmcounterh },
505
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
506
+ write_mhpmcounterh },
507
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
508
+ write_mhpmcounterh },
509
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
510
+ write_mhpmcounterh },
511
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
512
+ write_mhpmcounterh },
513
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
514
+ write_mhpmcounterh },
515
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
516
+ write_mhpmcounterh },
517
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
518
+ write_mhpmcounterh },
519
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
520
+ write_mhpmcounterh },
521
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
522
+ write_mhpmcounterh },
523
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
524
+ write_mhpmcounterh },
525
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
526
+ write_mhpmcounterh },
527
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
528
+ write_mhpmcounterh },
529
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
530
+ write_mhpmcounterh },
531
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
532
+ write_mhpmcounterh },
533
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
534
+ write_mhpmcounterh },
535
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
536
+ write_mhpmcounterh },
537
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
538
+ write_mhpmcounterh },
539
#endif /* !CONFIG_USER_ONLY */
540
};
541
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
542
index XXXXXXX..XXXXXXX 100644
543
--- a/target/riscv/machine.c
544
+++ b/target/riscv/machine.c
545
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
546
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
547
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
548
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
549
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
550
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
551
+ VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
552
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
553
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
554
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
555
--
556
2.36.1
diff view generated by jsdifflib
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
[PULL v2 12/19] target/riscv: Support mcycle/minstret write operation
1
From: Thomas Huth <thuth@redhat.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
Configuring a drive with "if=none" is meant for creation of a backend
3
mcycle/minstret are actually WARL registers and can be written with any
4
only, it should not get automatically assigned to a device frontend.
4
given value. With SBI PMU extension, it will be used to store a initial
5
Use "if=pflash" for the One-Time-Programmable device instead (like
5
value provided from supervisor OS. The Qemu also need prohibit the counter
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
6
increment if mcountinhibit is set.
7
7
8
Since the old way of configuring the device has already been published
8
Support mcycle/minstret through generic counter infrastructure.
9
with the previous QEMU versions, we cannot remove this immediately, but
10
have to deprecate it and support it for at least two more releases.
11
9
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
11
Signed-off-by: Atish Patra <atish.patra@wdc.com>
12
Signed-off-by: Atish Patra <atishp@rivosinc.com>
13
Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
15
---
19
docs/about/deprecated.rst | 6 ++++++
16
target/riscv/cpu.h | 23 ++++--
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
17
target/riscv/pmu.h | 28 +++++++
21
2 files changed, 14 insertions(+), 1 deletion(-)
18
target/riscv/csr.c | 155 ++++++++++++++++++++++++++++-----------
19
target/riscv/machine.c | 25 ++++++-
20
target/riscv/pmu.c | 32 ++++++++
21
target/riscv/meson.build | 3 +-
22
6 files changed, 213 insertions(+), 53 deletions(-)
23
create mode 100644 target/riscv/pmu.h
24
create mode 100644 target/riscv/pmu.c
22
25
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
26
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/about/deprecated.rst
28
--- a/target/riscv/cpu.h
26
+++ b/docs/about/deprecated.rst
29
+++ b/target/riscv/cpu.h
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
30
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState CPURISCVState;
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
31
#endif
29
form is preferred.
32
30
33
#define RV_VLEN_MAX 1024
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
34
-#define RV_MAX_MHPMEVENTS 29
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
35
+#define RV_MAX_MHPMEVENTS 32
33
+
36
#define RV_MAX_MHPMCOUNTERS 32
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
37
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
38
FIELD(VTYPE, VLMUL, 0, 3)
36
+
39
@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, VMA, 7, 1)
37
40
FIELD(VTYPE, VEDIV, 8, 2)
38
QEMU Machine Protocol (QMP) commands
41
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
39
------------------------------------
42
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
43
+typedef struct PMUCTRState {
44
+ /* Current value of a counter */
45
+ target_ulong mhpmcounter_val;
46
+ /* Current value of a counter in RV32*/
47
+ target_ulong mhpmcounterh_val;
48
+ /* Snapshot values of counter */
49
+ target_ulong mhpmcounter_prev;
50
+ /* Snapshort value of a counter in RV32 */
51
+ target_ulong mhpmcounterh_prev;
52
+ bool started;
53
+} PMUCTRState;
54
+
55
struct CPUArchState {
56
target_ulong gpr[32];
57
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
58
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
59
60
target_ulong mcountinhibit;
61
62
- /* PMU counter configured values */
63
- target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
64
-
65
- /* for RV32 */
66
- target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
67
+ /* PMU counter state */
68
+ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
69
70
- /* PMU event selector configured values */
71
+ /* PMU event selector configured values. First three are unused*/
72
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
73
74
target_ulong sscratch;
75
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
76
new file mode 100644
77
index XXXXXXX..XXXXXXX
78
--- /dev/null
79
+++ b/target/riscv/pmu.h
80
@@ -XXX,XX +XXX,XX @@
81
+/*
82
+ * RISC-V PMU header file.
83
+ *
84
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
85
+ *
86
+ * This program is free software; you can redistribute it and/or modify it
87
+ * under the terms and conditions of the GNU General Public License,
88
+ * version 2 or later, as published by the Free Software Foundation.
89
+ *
90
+ * This program is distributed in the hope it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
93
+ * more details.
94
+ *
95
+ * You should have received a copy of the GNU General Public License along with
96
+ * this program. If not, see <http://www.gnu.org/licenses/>.
97
+ */
98
+
99
+#include "qemu/osdep.h"
100
+#include "qemu/log.h"
101
+#include "cpu.h"
102
+#include "qemu/main-loop.h"
103
+#include "exec/exec-all.h"
104
+
105
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
106
+ uint32_t target_ctr);
107
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
108
+ uint32_t target_ctr);
109
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
41
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
111
--- a/target/riscv/csr.c
43
+++ b/hw/misc/sifive_u_otp.c
112
+++ b/target/riscv/csr.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
113
@@ -XXX,XX +XXX,XX @@
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
114
#include "qemu/log.h"
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
115
#include "qemu/timer.h"
47
116
#include "cpu.h"
48
- dinfo = drive_get_next(IF_NONE);
117
+#include "pmu.h"
49
+ dinfo = drive_get_next(IF_PFLASH);
118
#include "qemu/main-loop.h"
50
+ if (!dinfo) {
119
#include "exec/exec-all.h"
51
+ dinfo = drive_get_next(IF_NONE);
120
#include "sysemu/cpu-timers.h"
52
+ if (dinfo) {
121
@@ -XXX,XX +XXX,XX @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
122
}
54
+ "use \"-drive if=pflash\" instead.");
123
124
/* User Timers and Counters */
125
-static RISCVException read_instret(CPURISCVState *env, int csrno,
126
- target_ulong *val)
127
+static target_ulong get_ticks(bool shift)
128
{
129
+ int64_t val;
130
+ target_ulong result;
131
+
132
#if !defined(CONFIG_USER_ONLY)
133
if (icount_enabled()) {
134
- *val = icount_get();
135
+ val = icount_get();
136
} else {
137
- *val = cpu_get_host_ticks();
138
+ val = cpu_get_host_ticks();
139
}
140
#else
141
- *val = cpu_get_host_ticks();
142
+ val = cpu_get_host_ticks();
143
#endif
144
- return RISCV_EXCP_NONE;
145
-}
146
147
-static RISCVException read_instreth(CPURISCVState *env, int csrno,
148
- target_ulong *val)
149
-{
150
-#if !defined(CONFIG_USER_ONLY)
151
- if (icount_enabled()) {
152
- *val = icount_get() >> 32;
153
+ if (shift) {
154
+ result = val >> 32;
155
} else {
156
- *val = cpu_get_host_ticks() >> 32;
157
+ result = val;
158
}
159
-#else
160
- *val = cpu_get_host_ticks() >> 32;
161
-#endif
162
- return RISCV_EXCP_NONE;
163
+
164
+ return result;
165
}
166
167
#if defined(CONFIG_USER_ONLY)
168
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
169
return RISCV_EXCP_NONE;
170
}
171
172
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
173
+{
174
+ *val = get_ticks(false);
175
+ return RISCV_EXCP_NONE;
176
+}
177
+
178
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
179
+{
180
+ *val = get_ticks(true);
181
+ return RISCV_EXCP_NONE;
182
+}
183
+
184
#else /* CONFIG_USER_ONLY */
185
186
static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
187
{
188
- int evt_index = csrno - CSR_MHPMEVENT3;
189
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
190
191
*val = env->mhpmevent_val[evt_index];
192
193
@@ -XXX,XX +XXX,XX @@ static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
194
195
static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
196
{
197
- int evt_index = csrno - CSR_MHPMEVENT3;
198
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
199
200
env->mhpmevent_val[evt_index] = val;
201
202
@@ -XXX,XX +XXX,XX @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
203
204
static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
205
{
206
- int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
207
+ int ctr_idx = csrno - CSR_MCYCLE;
208
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
209
210
- env->mhpmcounter_val[ctr_index] = val;
211
+ counter->mhpmcounter_val = val;
212
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
213
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
214
+ counter->mhpmcounter_prev = get_ticks(false);
215
+ } else {
216
+ /* Other counters can keep incrementing from the given value */
217
+ counter->mhpmcounter_prev = val;
218
+ }
219
220
return RISCV_EXCP_NONE;
221
}
222
223
static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
224
{
225
- int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
226
+ int ctr_idx = csrno - CSR_MCYCLEH;
227
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
228
229
- env->mhpmcounterh_val[ctr_index] = val;
230
+ counter->mhpmcounterh_val = val;
231
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
232
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
233
+ counter->mhpmcounterh_prev = get_ticks(true);
234
+ } else {
235
+ counter->mhpmcounterh_prev = val;
236
+ }
237
+
238
+ return RISCV_EXCP_NONE;
239
+}
240
+
241
+static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
242
+ bool upper_half, uint32_t ctr_idx)
243
+{
244
+ PMUCTRState counter = env->pmu_ctrs[ctr_idx];
245
+ target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev :
246
+ counter.mhpmcounter_prev;
247
+ target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val :
248
+ counter.mhpmcounter_val;
249
+
250
+ if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
251
+ /**
252
+ * Counter should not increment if inhibit bit is set. We can't really
253
+ * stop the icount counting. Just return the counter value written by
254
+ * the supervisor to indicate that counter was not incremented.
255
+ */
256
+ if (!counter.started) {
257
+ *val = ctr_val;
258
+ return RISCV_EXCP_NONE;
259
+ } else {
260
+ /* Mark that the counter has been stopped */
261
+ counter.started = false;
55
+ }
262
+ }
56
+ }
263
+ }
57
if (dinfo) {
264
+
58
int ret;
265
+ /**
59
uint64_t perm;
266
+ * The kernel computes the perf delta by subtracting the current value from
267
+ * the value it initialized previously (ctr_val).
268
+ */
269
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
270
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
271
+ *val = get_ticks(upper_half) - ctr_prev + ctr_val;
272
+ } else {
273
+ *val = ctr_val;
274
+ }
275
276
return RISCV_EXCP_NONE;
277
}
278
279
static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
280
{
281
- int ctr_index;
282
+ uint16_t ctr_index;
283
284
if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
285
- ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
286
+ ctr_index = csrno - CSR_MCYCLE;
287
} else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
288
- ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
289
+ ctr_index = csrno - CSR_CYCLE;
290
} else {
291
return RISCV_EXCP_ILLEGAL_INST;
292
}
293
- *val = env->mhpmcounter_val[ctr_index];
294
295
- return RISCV_EXCP_NONE;
296
+ return riscv_pmu_read_ctr(env, val, false, ctr_index);
297
}
298
299
static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
300
{
301
- int ctr_index;
302
+ uint16_t ctr_index;
303
304
if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
305
- ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
306
+ ctr_index = csrno - CSR_MCYCLEH;
307
} else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
308
- ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
309
+ ctr_index = csrno - CSR_CYCLEH;
310
} else {
311
return RISCV_EXCP_ILLEGAL_INST;
312
}
313
- *val = env->mhpmcounterh_val[ctr_index];
314
315
- return RISCV_EXCP_NONE;
316
+ return riscv_pmu_read_ctr(env, val, true, ctr_index);
317
}
318
319
-
320
static RISCVException read_time(CPURISCVState *env, int csrno,
321
target_ulong *val)
322
{
323
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
324
static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
325
target_ulong val)
326
{
327
+ int cidx;
328
+ PMUCTRState *counter;
329
+
330
if (env->priv_ver < PRIV_VERSION_1_11_0) {
331
return RISCV_EXCP_ILLEGAL_INST;
332
}
333
334
env->mcountinhibit = val;
335
+
336
+ /* Check if any other counter is also monitoring cycles/instructions */
337
+ for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
338
+ if (!get_field(env->mcountinhibit, BIT(cidx))) {
339
+ counter = &env->pmu_ctrs[cidx];
340
+ counter->started = true;
341
+ }
342
+ }
343
+
344
return RISCV_EXCP_NONE;
345
}
346
347
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
348
[CSR_VLENB] = { "vlenb", vs, read_vlenb,
349
.min_priv_ver = PRIV_VERSION_1_12_0 },
350
/* User Timers and Counters */
351
- [CSR_CYCLE] = { "cycle", ctr, read_instret },
352
- [CSR_INSTRET] = { "instret", ctr, read_instret },
353
- [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
354
- [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
355
+ [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
356
+ [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
357
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh },
358
+ [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh },
359
360
/*
361
* In privileged mode, the monitor will have to emulate TIME CSRs only if
362
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
363
364
#if !defined(CONFIG_USER_ONLY)
365
/* Machine Timers and Counters */
366
- [CSR_MCYCLE] = { "mcycle", any, read_instret },
367
- [CSR_MINSTRET] = { "minstret", any, read_instret },
368
- [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
369
- [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
370
+ [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
371
+ [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
372
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
373
+ [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
374
375
/* Machine Information Registers */
376
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
377
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
378
index XXXXXXX..XXXXXXX 100644
379
--- a/target/riscv/machine.c
380
+++ b/target/riscv/machine.c
381
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_envcfg = {
382
VMSTATE_UINT64(env.menvcfg, RISCVCPU),
383
VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
384
VMSTATE_UINT64(env.henvcfg, RISCVCPU),
385
+ VMSTATE_END_OF_LIST()
386
+ }
387
+};
388
+
389
+static bool pmu_needed(void *opaque)
390
+{
391
+ RISCVCPU *cpu = opaque;
392
393
+ return cpu->cfg.pmu_num;
394
+}
395
+
396
+static const VMStateDescription vmstate_pmu_ctr_state = {
397
+ .name = "cpu/pmu",
398
+ .version_id = 1,
399
+ .minimum_version_id = 1,
400
+ .needed = pmu_needed,
401
+ .fields = (VMStateField[]) {
402
+ VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
403
+ VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
404
+ VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
405
+ VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
406
+ VMSTATE_BOOL(started, PMUCTRState),
407
VMSTATE_END_OF_LIST()
408
}
409
};
410
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
411
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
412
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
413
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
414
- VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
415
- VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
416
+ VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
417
+ vmstate_pmu_ctr_state, PMUCTRState),
418
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
419
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
420
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
421
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
422
new file mode 100644
423
index XXXXXXX..XXXXXXX
424
--- /dev/null
425
+++ b/target/riscv/pmu.c
426
@@ -XXX,XX +XXX,XX @@
427
+/*
428
+ * RISC-V PMU file.
429
+ *
430
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
431
+ *
432
+ * This program is free software; you can redistribute it and/or modify it
433
+ * under the terms and conditions of the GNU General Public License,
434
+ * version 2 or later, as published by the Free Software Foundation.
435
+ *
436
+ * This program is distributed in the hope it will be useful, but WITHOUT
437
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
438
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
439
+ * more details.
440
+ *
441
+ * You should have received a copy of the GNU General Public License along with
442
+ * this program. If not, see <http://www.gnu.org/licenses/>.
443
+ */
444
+
445
+#include "qemu/osdep.h"
446
+#include "cpu.h"
447
+#include "pmu.h"
448
+
449
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
450
+ uint32_t target_ctr)
451
+{
452
+ return (target_ctr == 0) ? true : false;
453
+}
454
+
455
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
456
+{
457
+ return (target_ctr == 2) ? true : false;
458
+}
459
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
460
index XXXXXXX..XXXXXXX 100644
461
--- a/target/riscv/meson.build
462
+++ b/target/riscv/meson.build
463
@@ -XXX,XX +XXX,XX @@ riscv_softmmu_ss.add(files(
464
'pmp.c',
465
'debug.c',
466
'monitor.c',
467
- 'machine.c'
468
+ 'machine.c',
469
+ 'pmu.c'
470
))
471
472
target_arch += {'riscv': riscv_ss}
60
--
473
--
61
2.31.1
474
2.36.1
62
63
diff view generated by jsdifflib
New patch
[PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
There is nothing in the RISC-V spec that mandates version 1.12 is
4
required for ePMP and there is currently hardware [1] that implements
5
ePMP (a draft version though) with the 1.11 priv spec.
6
7
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
8
9
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.")
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>
13
---
14
target/riscv/csr.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
21
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
22
23
/* Physical Memory Protection */
24
[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
25
- .min_priv_ver = PRIV_VERSION_1_12_0 },
26
+ .min_priv_ver = PRIV_VERSION_1_11_0 },
27
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
28
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
29
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
30
--
31
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
The Ibex CPU supports version 1.11 of the priv spec [1], so let's
4
correct that in QEMU as well.
5
6
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
7
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Message-Id: <20220629233102.275181-3-alistair.francis@opensource.wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.c
19
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
21
RISCVCPU *cpu = RISCV_CPU(obj);
22
23
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
24
- set_priv_version(env, PRIV_VERSION_1_10_0);
25
+ set_priv_version(env, PRIV_VERSION_1_11_0);
26
cpu->cfg.mmu = false;
27
cpu->cfg.epmp = true;
28
}
29
--
30
2.36.1
diff view generated by jsdifflib
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
[PULL v2 15/19] target/riscv: Don't force update priv spec version to latest
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
3
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
4
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
5
value of priv spec v1.10 is zero.
4
6
5
Do not re-initialize the OTP content in the DeviceReset handler,
7
Due to above issue, the sifive_u machine will see priv spec v1.12
6
initialize it once in the DeviceRealize one.
8
instead of priv spec v1.10.
7
9
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
10
To fix this issue, we set latest priv spec version (i.e. v1.12)
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
12
spec version only when "cpu->cfg.priv_spec != NULL".
13
14
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
15
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
16
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
18
Reviewed-by: Atish Patra <atishp@rivosinc.com>
19
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
20
Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
22
---
14
hw/misc/sifive_u_otp.c | 13 +++++--------
23
target/riscv/cpu.c | 12 ++++++++----
15
1 file changed, 5 insertions(+), 8 deletions(-)
24
1 file changed, 8 insertions(+), 4 deletions(-)
16
25
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
28
--- a/target/riscv/cpu.c
20
+++ b/hw/misc/sifive_u_otp.c
29
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
30
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
22
31
/* We set this in the realise function */
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
32
set_misa(env, MXL_RV64, 0);
24
error_setg(errp, "failed to read the initial flash content");
33
register_cpu_props(DEVICE(obj));
25
+ return;
34
+ /* Set latest version of privileged specification */
26
}
35
+ set_priv_version(env, PRIV_VERSION_1_12_0);
36
}
37
38
static void rv64_sifive_u_cpu_init(Object *obj)
39
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
40
/* We set this in the realise function */
41
set_misa(env, MXL_RV128, 0);
42
register_cpu_props(DEVICE(obj));
43
+ /* Set latest version of privileged specification */
44
+ set_priv_version(env, PRIV_VERSION_1_12_0);
45
}
46
#else
47
static void rv32_base_cpu_init(Object *obj)
48
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
49
/* We set this in the realise function */
50
set_misa(env, MXL_RV32, 0);
51
register_cpu_props(DEVICE(obj));
52
+ /* Set latest version of privileged specification */
53
+ set_priv_version(env, PRIV_VERSION_1_12_0);
54
}
55
56
static void rv32_sifive_u_cpu_init(Object *obj)
57
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
58
CPURISCVState *env = &cpu->env;
59
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
60
CPUClass *cc = CPU_CLASS(mcc);
61
- int priv_version = 0;
62
+ int priv_version = -1;
63
Error *local_err = NULL;
64
65
cpu_exec_realizefn(cs, &local_err);
66
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
27
}
67
}
28
}
68
}
29
-}
69
30
-
70
- if (priv_version) {
31
-static void sifive_u_otp_reset(DeviceState *dev)
71
+ if (priv_version >= PRIV_VERSION_1_10_0) {
32
-{
72
set_priv_version(env, priv_version);
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
73
- } else if (!env->priv_ver) {
34
74
- set_priv_version(env, PRIV_VERSION_1_12_0);
35
/* Initialize all fuses' initial value to 0xFFs */
36
memset(s->fuse, 0xff, sizeof(s->fuse));
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
38
serial_data = s->serial;
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
41
- error_report("write error index<%d>", index);
42
+ error_setg(errp, "failed to write index<%d>", index);
43
+ return;
44
}
45
46
serial_data = ~(s->serial);
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
49
- error_report("write error index<%d>", index + 1);
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
51
+ return;
52
}
53
}
75
}
54
76
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
77
if (cpu->cfg.mmu) {
56
57
device_class_set_props(dc, sifive_u_otp_properties);
58
dc->realize = sifive_u_otp_realize;
59
- dc->reset = sifive_u_otp_reset;
60
}
61
62
static const TypeInfo sifive_u_otp_info = {
63
--
78
--
64
2.31.1
79
2.36.1
65
66
diff view generated by jsdifflib
New patch
[PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
We previously stored the device tree at a 16MB alignment from the end of
4
memory (or 3GB). This means we need at least 16MB of memory to be able
5
to do this. We don't actually need the FDT to be 16MB aligned, so let's
6
drop it down to 2MB so that we can support systems with less memory,
7
while also allowing FDT size expansion.
8
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Atish Patra <atishp@rivosinc.com>
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
13
Tested-by: Bin Meng <bin.meng@windriver.com>
14
Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
hw/riscv/boot.c | 4 ++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
19
20
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/riscv/boot.c
23
+++ b/hw/riscv/boot.c
24
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
25
/*
26
* We should put fdt as far as possible to avoid kernel/initrd overwriting
27
* its content. But it should be addressable by 32 bit system as well.
28
- * Thus, put it at an 16MB aligned address that less than fdt size from the
29
+ * Thus, put it at an 2MB aligned address that less than fdt size from the
30
* end of dram or 3GB whichever is lesser.
31
*/
32
temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
33
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
34
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
35
36
ret = fdt_pack(fdt);
37
/* Should only fail if we've built a corrupted tree */
38
--
39
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit
1
From: Anup Patel <apatel@ventanamicro.com>
1
2
3
The minimum priv spec versino for mcountinhibit to v1.11 so that it
4
is not available for v1.10 (or lower).
5
6
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
7
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/csr.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/csr.c
18
+++ b/target/riscv/csr.c
19
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
20
write_mhpmcounter },
21
22
[CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
23
- write_mcountinhibit },
24
+ write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 },
25
26
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
27
write_mhpmevent },
28
--
29
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
1
1
From: Anup Patel <apatel@ventanamicro.com>
2
3
Based on architecture review committee feedback, the [m|s|vs]seteienum,
4
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
5
removed in the latest AIA draft v0.3.0 specification.
6
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
7
8
These CSRs were mostly for software convenience and software can always
9
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
10
file bits.
11
12
We update the IMSIC CSR emulation as-per above to match the latest AIA
13
draft specification.
14
15
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
target/riscv/cpu_bits.h | 24 +------
21
target/riscv/csr.c | 150 +---------------------------------------
22
2 files changed, 6 insertions(+), 168 deletions(-)
23
24
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu_bits.h
27
+++ b/target/riscv/cpu_bits.h
28
@@ -XXX,XX +XXX,XX @@
29
#define CSR_MIREG 0x351
30
31
/* Machine-Level Interrupts (AIA) */
32
-#define CSR_MTOPI 0xfb0
33
-
34
-/* Machine-Level IMSIC Interface (AIA) */
35
-#define CSR_MSETEIPNUM 0x358
36
-#define CSR_MCLREIPNUM 0x359
37
-#define CSR_MSETEIENUM 0x35a
38
-#define CSR_MCLREIENUM 0x35b
39
#define CSR_MTOPEI 0x35c
40
+#define CSR_MTOPI 0xfb0
41
42
/* Virtual Interrupts for Supervisor Level (AIA) */
43
#define CSR_MVIEN 0x308
44
@@ -XXX,XX +XXX,XX @@
45
#define CSR_SIREG 0x151
46
47
/* Supervisor-Level Interrupts (AIA) */
48
-#define CSR_STOPI 0xdb0
49
-
50
-/* Supervisor-Level IMSIC Interface (AIA) */
51
-#define CSR_SSETEIPNUM 0x158
52
-#define CSR_SCLREIPNUM 0x159
53
-#define CSR_SSETEIENUM 0x15a
54
-#define CSR_SCLREIENUM 0x15b
55
#define CSR_STOPEI 0x15c
56
+#define CSR_STOPI 0xdb0
57
58
/* Supervisor-Level High-Half CSRs (AIA) */
59
#define CSR_SIEH 0x114
60
@@ -XXX,XX +XXX,XX @@
61
#define CSR_VSIREG 0x251
62
63
/* VS-Level Interrupts (H-extension with AIA) */
64
-#define CSR_VSTOPI 0xeb0
65
-
66
-/* VS-Level IMSIC Interface (H-extension with AIA) */
67
-#define CSR_VSSETEIPNUM 0x258
68
-#define CSR_VSCLREIPNUM 0x259
69
-#define CSR_VSSETEIENUM 0x25a
70
-#define CSR_VSCLREIENUM 0x25b
71
#define CSR_VSTOPEI 0x25c
72
+#define CSR_VSTOPI 0xeb0
73
74
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
75
#define CSR_HIDELEGH 0x613
76
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/riscv/csr.c
79
+++ b/target/riscv/csr.c
80
@@ -XXX,XX +XXX,XX @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
81
return CSR_VSISELECT;
82
case CSR_SIREG:
83
return CSR_VSIREG;
84
- case CSR_SSETEIPNUM:
85
- return CSR_VSSETEIPNUM;
86
- case CSR_SCLREIPNUM:
87
- return CSR_VSCLREIPNUM;
88
- case CSR_SSETEIENUM:
89
- return CSR_VSSETEIENUM;
90
- case CSR_SCLREIENUM:
91
- return CSR_VSCLREIENUM;
92
case CSR_STOPEI:
93
return CSR_VSTOPEI;
94
default:
95
@@ -XXX,XX +XXX,XX @@ done:
96
return RISCV_EXCP_NONE;
97
}
98
99
-static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
100
- target_ulong new_val, target_ulong wr_mask)
101
-{
102
- int ret = -EINVAL;
103
- bool set, pend, virt;
104
- target_ulong priv, isel, vgein, xlen, nval, wmask;
105
-
106
- /* Translate CSR number for VS-mode */
107
- csrno = aia_xlate_vs_csrno(env, csrno);
108
-
109
- /* Decode register details from CSR number */
110
- virt = set = pend = false;
111
- switch (csrno) {
112
- case CSR_MSETEIPNUM:
113
- priv = PRV_M;
114
- set = true;
115
- pend = true;
116
- break;
117
- case CSR_MCLREIPNUM:
118
- priv = PRV_M;
119
- pend = true;
120
- break;
121
- case CSR_MSETEIENUM:
122
- priv = PRV_M;
123
- set = true;
124
- break;
125
- case CSR_MCLREIENUM:
126
- priv = PRV_M;
127
- break;
128
- case CSR_SSETEIPNUM:
129
- priv = PRV_S;
130
- set = true;
131
- pend = true;
132
- break;
133
- case CSR_SCLREIPNUM:
134
- priv = PRV_S;
135
- pend = true;
136
- break;
137
- case CSR_SSETEIENUM:
138
- priv = PRV_S;
139
- set = true;
140
- break;
141
- case CSR_SCLREIENUM:
142
- priv = PRV_S;
143
- break;
144
- case CSR_VSSETEIPNUM:
145
- priv = PRV_S;
146
- virt = true;
147
- set = true;
148
- pend = true;
149
- break;
150
- case CSR_VSCLREIPNUM:
151
- priv = PRV_S;
152
- virt = true;
153
- pend = true;
154
- break;
155
- case CSR_VSSETEIENUM:
156
- priv = PRV_S;
157
- virt = true;
158
- set = true;
159
- break;
160
- case CSR_VSCLREIENUM:
161
- priv = PRV_S;
162
- virt = true;
163
- break;
164
- default:
165
- goto done;
166
- };
167
-
168
- /* IMSIC CSRs only available when machine implements IMSIC. */
169
- if (!env->aia_ireg_rmw_fn[priv]) {
170
- goto done;
171
- }
172
-
173
- /* Find the selected guest interrupt file */
174
- vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
175
-
176
- /* Selected guest interrupt file should be valid */
177
- if (virt && (!vgein || env->geilen < vgein)) {
178
- goto done;
179
- }
180
-
181
- /* Set/Clear CSRs always read zero */
182
- if (val) {
183
- *val = 0;
184
- }
185
-
186
- if (wr_mask) {
187
- /* Get interrupt number */
188
- new_val &= wr_mask;
189
-
190
- /* Find target interrupt pending/enable register */
191
- xlen = riscv_cpu_mxl_bits(env);
192
- isel = (new_val / xlen);
193
- isel *= (xlen / IMSIC_EIPx_BITS);
194
- isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
195
-
196
- /* Find the interrupt bit to be set/clear */
197
- wmask = ((target_ulong)1) << (new_val % xlen);
198
- nval = (set) ? wmask : 0;
199
-
200
- /* Call machine specific IMSIC register emulation */
201
- ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
202
- AIA_MAKE_IREG(isel, priv, virt,
203
- vgein, xlen),
204
- NULL, nval, wmask);
205
- } else {
206
- ret = 0;
207
- }
208
-
209
-done:
210
- if (ret) {
211
- return (riscv_cpu_virt_enabled(env) && virt) ?
212
- RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
213
- }
214
- return RISCV_EXCP_NONE;
215
-}
216
-
217
static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
218
target_ulong new_val, target_ulong wr_mask)
219
{
220
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
221
[CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
222
223
/* Machine-Level Interrupts (AIA) */
224
- [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
225
-
226
- /* Machine-Level IMSIC Interface (AIA) */
227
- [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
228
- [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
229
- [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
230
- [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
231
[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
232
+ [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
233
234
/* Virtual Interrupts for Supervisor Level (AIA) */
235
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
236
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
237
[CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
238
239
/* Supervisor-Level Interrupts (AIA) */
240
- [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
241
-
242
- /* Supervisor-Level IMSIC Interface (AIA) */
243
- [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
244
- [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
245
- [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
246
- [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
247
[CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
248
+ [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
249
250
/* Supervisor-Level High-Half CSRs (AIA) */
251
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
252
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
253
[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
254
255
/* VS-Level Interrupts (H-extension with AIA) */
256
- [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
257
-
258
- /* VS-Level IMSIC Interface (H-extension with AIA) */
259
- [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
260
- [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
261
- [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
262
- [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
263
[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
264
+ [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
265
266
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
267
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
268
--
269
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 19/19] target/riscv: Update default priority table for local interrupts
1
1
From: Anup Patel <apatel@ventanamicro.com>
2
3
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
4
default priority assignments where:
5
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
6
and have implementation specific default priority.
7
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
8
(not mandatory) priority assignments.
9
10
We update the default priority table and hviprio mapping as-per above.
11
12
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu_bits.h | 2 +-
18
target/riscv/cpu_helper.c | 134 ++++++++++++++++++--------------------
19
2 files changed, 66 insertions(+), 70 deletions(-)
20
21
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_bits.h
24
+++ b/target/riscv/cpu_bits.h
25
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
26
#define IPRIO_IRQ_BITS 8
27
#define IPRIO_MMAXIPRIO 255
28
#define IPRIO_DEFAULT_UPPER 4
29
-#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24)
30
+#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12)
31
#define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE
32
#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3)
33
#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3)
34
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu_helper.c
37
+++ b/target/riscv/cpu_helper.c
38
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_update_mask(CPURISCVState *env)
39
* 14 "
40
* 15 "
41
* 16 "
42
- * 18 Debug/trace interrupt
43
- * 20 (Reserved interrupt)
44
+ * 17 "
45
+ * 18 "
46
+ * 19 "
47
+ * 20 "
48
+ * 21 "
49
* 22 "
50
- * 24 "
51
- * 26 "
52
- * 28 "
53
- * 30 (Reserved for standard reporting of bus or system errors)
54
+ * 23 "
55
*/
56
57
static const int hviprio_index2irq[] = {
58
- 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
59
+ 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
60
static const int hviprio_index2rdzero[] = {
61
1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
62
63
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
64
* Default |
65
* Priority | Major Interrupt Numbers
66
* ----------------------------------------------------------------
67
- * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c),
68
- * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38),
69
- * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34),
70
- * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30)
71
+ * Highest | 47, 23, 46, 45, 22, 44,
72
+ * | 43, 21, 42, 41, 20, 40
73
* |
74
* | 11 (0b), 3 (03), 7 (07)
75
* | 9 (09), 1 (01), 5 (05)
76
* | 12 (0c)
77
* | 10 (0a), 2 (02), 6 (06)
78
* |
79
- * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c),
80
- * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28),
81
- * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24),
82
- * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20)
83
+ * | 39, 19, 38, 37, 18, 36,
84
+ * Lowest | 35, 17, 34, 33, 16, 32
85
* ----------------------------------------------------------------
86
*/
87
static const uint8_t default_iprio[64] = {
88
- [63] = IPRIO_DEFAULT_UPPER,
89
- [62] = IPRIO_DEFAULT_UPPER + 1,
90
- [31] = IPRIO_DEFAULT_UPPER + 2,
91
- [30] = IPRIO_DEFAULT_UPPER + 3,
92
- [61] = IPRIO_DEFAULT_UPPER + 4,
93
- [60] = IPRIO_DEFAULT_UPPER + 5,
94
-
95
- [59] = IPRIO_DEFAULT_UPPER + 6,
96
- [58] = IPRIO_DEFAULT_UPPER + 7,
97
- [29] = IPRIO_DEFAULT_UPPER + 8,
98
- [28] = IPRIO_DEFAULT_UPPER + 9,
99
- [57] = IPRIO_DEFAULT_UPPER + 10,
100
- [56] = IPRIO_DEFAULT_UPPER + 11,
101
-
102
- [55] = IPRIO_DEFAULT_UPPER + 12,
103
- [54] = IPRIO_DEFAULT_UPPER + 13,
104
- [27] = IPRIO_DEFAULT_UPPER + 14,
105
- [26] = IPRIO_DEFAULT_UPPER + 15,
106
- [53] = IPRIO_DEFAULT_UPPER + 16,
107
- [52] = IPRIO_DEFAULT_UPPER + 17,
108
-
109
- [51] = IPRIO_DEFAULT_UPPER + 18,
110
- [50] = IPRIO_DEFAULT_UPPER + 19,
111
- [25] = IPRIO_DEFAULT_UPPER + 20,
112
- [24] = IPRIO_DEFAULT_UPPER + 21,
113
- [49] = IPRIO_DEFAULT_UPPER + 22,
114
- [48] = IPRIO_DEFAULT_UPPER + 23,
115
+ /* Custom interrupts 48 to 63 */
116
+ [63] = IPRIO_MMAXIPRIO,
117
+ [62] = IPRIO_MMAXIPRIO,
118
+ [61] = IPRIO_MMAXIPRIO,
119
+ [60] = IPRIO_MMAXIPRIO,
120
+ [59] = IPRIO_MMAXIPRIO,
121
+ [58] = IPRIO_MMAXIPRIO,
122
+ [57] = IPRIO_MMAXIPRIO,
123
+ [56] = IPRIO_MMAXIPRIO,
124
+ [55] = IPRIO_MMAXIPRIO,
125
+ [54] = IPRIO_MMAXIPRIO,
126
+ [53] = IPRIO_MMAXIPRIO,
127
+ [52] = IPRIO_MMAXIPRIO,
128
+ [51] = IPRIO_MMAXIPRIO,
129
+ [50] = IPRIO_MMAXIPRIO,
130
+ [49] = IPRIO_MMAXIPRIO,
131
+ [48] = IPRIO_MMAXIPRIO,
132
+
133
+ /* Custom interrupts 24 to 31 */
134
+ [31] = IPRIO_MMAXIPRIO,
135
+ [30] = IPRIO_MMAXIPRIO,
136
+ [29] = IPRIO_MMAXIPRIO,
137
+ [28] = IPRIO_MMAXIPRIO,
138
+ [27] = IPRIO_MMAXIPRIO,
139
+ [26] = IPRIO_MMAXIPRIO,
140
+ [25] = IPRIO_MMAXIPRIO,
141
+ [24] = IPRIO_MMAXIPRIO,
142
+
143
+ [47] = IPRIO_DEFAULT_UPPER,
144
+ [23] = IPRIO_DEFAULT_UPPER + 1,
145
+ [46] = IPRIO_DEFAULT_UPPER + 2,
146
+ [45] = IPRIO_DEFAULT_UPPER + 3,
147
+ [22] = IPRIO_DEFAULT_UPPER + 4,
148
+ [44] = IPRIO_DEFAULT_UPPER + 5,
149
+
150
+ [43] = IPRIO_DEFAULT_UPPER + 6,
151
+ [21] = IPRIO_DEFAULT_UPPER + 7,
152
+ [42] = IPRIO_DEFAULT_UPPER + 8,
153
+ [41] = IPRIO_DEFAULT_UPPER + 9,
154
+ [20] = IPRIO_DEFAULT_UPPER + 10,
155
+ [40] = IPRIO_DEFAULT_UPPER + 11,
156
157
[11] = IPRIO_DEFAULT_M,
158
[3] = IPRIO_DEFAULT_M + 1,
159
@@ -XXX,XX +XXX,XX @@ static const uint8_t default_iprio[64] = {
160
[2] = IPRIO_DEFAULT_VS + 1,
161
[6] = IPRIO_DEFAULT_VS + 2,
162
163
- [47] = IPRIO_DEFAULT_LOWER,
164
- [46] = IPRIO_DEFAULT_LOWER + 1,
165
- [23] = IPRIO_DEFAULT_LOWER + 2,
166
- [22] = IPRIO_DEFAULT_LOWER + 3,
167
- [45] = IPRIO_DEFAULT_LOWER + 4,
168
- [44] = IPRIO_DEFAULT_LOWER + 5,
169
-
170
- [43] = IPRIO_DEFAULT_LOWER + 6,
171
- [42] = IPRIO_DEFAULT_LOWER + 7,
172
- [21] = IPRIO_DEFAULT_LOWER + 8,
173
- [20] = IPRIO_DEFAULT_LOWER + 9,
174
- [41] = IPRIO_DEFAULT_LOWER + 10,
175
- [40] = IPRIO_DEFAULT_LOWER + 11,
176
-
177
- [39] = IPRIO_DEFAULT_LOWER + 12,
178
- [38] = IPRIO_DEFAULT_LOWER + 13,
179
- [19] = IPRIO_DEFAULT_LOWER + 14,
180
- [18] = IPRIO_DEFAULT_LOWER + 15,
181
- [37] = IPRIO_DEFAULT_LOWER + 16,
182
- [36] = IPRIO_DEFAULT_LOWER + 17,
183
-
184
- [35] = IPRIO_DEFAULT_LOWER + 18,
185
- [34] = IPRIO_DEFAULT_LOWER + 19,
186
- [17] = IPRIO_DEFAULT_LOWER + 20,
187
- [16] = IPRIO_DEFAULT_LOWER + 21,
188
- [33] = IPRIO_DEFAULT_LOWER + 22,
189
- [32] = IPRIO_DEFAULT_LOWER + 23,
190
+ [39] = IPRIO_DEFAULT_LOWER,
191
+ [19] = IPRIO_DEFAULT_LOWER + 1,
192
+ [38] = IPRIO_DEFAULT_LOWER + 2,
193
+ [37] = IPRIO_DEFAULT_LOWER + 3,
194
+ [18] = IPRIO_DEFAULT_LOWER + 4,
195
+ [36] = IPRIO_DEFAULT_LOWER + 5,
196
+
197
+ [35] = IPRIO_DEFAULT_LOWER + 6,
198
+ [17] = IPRIO_DEFAULT_LOWER + 7,
199
+ [34] = IPRIO_DEFAULT_LOWER + 8,
200
+ [33] = IPRIO_DEFAULT_LOWER + 9,
201
+ [16] = IPRIO_DEFAULT_LOWER + 10,
202
+ [32] = IPRIO_DEFAULT_LOWER + 11,
203
};
204
205
uint8_t riscv_cpu_default_priority(int irq)
206
--
207
2.36.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.