Series comparison

-[PULL 0/2] riscv-to-apply queue
+[PULL 00/23] riscv-to-apply queue
 From: Alistair Francis <alistair.francis@wdc.com>
-The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
+The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
-  Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
+  Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220525
-for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
+for you to fetch changes up to 8fe63fe8e512d77583d6798acd2164f1fa1e40ab:
-  hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
+  hw/core: loader: Set is_linux to true for VxWorks uImage (2022-05-24 10:38:50 +1000)
 ----------------------------------------------------------------
-Seventh RISC-V PR for QEMU 6.2
+Third RISC-V PR for QEMU 7.1
- - Deprecate IF_NONE for SiFive OTP
+ * Fixes for accessing VS hypervisor CSRs
- - Don't reset SiFive OTP content
+ * Improvements for RISC-V Vector extension
  * Fixes for accessing mtimecmp
  * Add new short-isa-string CPU option
  * Improvements to RISC-V machine error handling
  * Disable the "G" extension by default internally, no functional change
  * Enforce floating point extension requirements
  * Cleanup ISA extension checks
  * Resolve redundant property accessors
  * Fix typo of mimpid cpu option
  * Improvements for virtulisation
  * Add zicsr/zifencei to isa_string
  * Support for VxWorks uImage
 ----------------------------------------------------------------
-Philippe Mathieu-Daudé (1):
+Anup Patel (4):
-      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
+      target/riscv: Fix csr number based privilege checking
       target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
       target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
       hw/riscv: virt: Fix interrupt parent for dynamic platform devices
-Thomas Huth (1):
+Atish Patra (1):
-      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
+      hw/intc: Pass correct hartid while updating mtimecmp
- docs/about/deprecated.rst |  6 ++++++
+Bernhard Beschow (2):
- hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
+      hw/vfio/pci-quirks: Resolve redundant property getters
-files changed, 19 insertions(+), 9 deletions(-)
+      hw/riscv/sifive_u: Resolve redundant property accessors
+Bin Meng (2):
+      hw/core: Sync uboot_image.h from U-Boot v2022.01
+      hw/core: loader: Set is_linux to true for VxWorks uImage
+Dylan Reid (1):
+      target/riscv: Fix VS mode hypervisor CSR access
+Frank Chang (1):
+      target/riscv: Fix typo of mimpid cpu option
+Hongren (Zenithal) Zheng (1):
+      target/riscv: add zicsr/zifencei to isa_string
+Tsukasa OI (9):
+      target/riscv: Move Zhinx* extensions on ISA string
+      target/riscv: Add short-isa-string option
+      hw/riscv: Make CPU config error handling generous (virt/spike)
+      hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
+      target/riscv: Fix coding style on "G" expansion
+      target/riscv: Disable "G" by default
+      target/riscv: Change "G" expansion
+      target/riscv: FP extension requirements
+      target/riscv: Move/refactor ISA extension checks
+Weiwei Li (1):
+      target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
+eopXD (1):
+      target/riscv: rvv: Fix early exit condition for whole register load/store
+ hw/core/uboot_image.h                   | 213 +++++++++++++++++++++-----------
+ target/riscv/cpu.h                      |  12 +-
+ hw/core/loader.c                        |  15 +++
+ hw/intc/riscv_aclint.c                  |   3 +-
+ hw/riscv/opentitan.c                    |   2 +-
+ hw/riscv/sifive_e.c                     |   2 +-
+ hw/riscv/sifive_u.c                     |  28 +----
+ hw/riscv/spike.c                        |   2 +-
+ hw/riscv/virt.c                         |  27 ++--
+ hw/vfio/pci-quirks.c                    |  34 ++---
+ target/riscv/cpu.c                      |  91 ++++++++++----
+ target/riscv/cpu_helper.c               |   4 +-
+ target/riscv/csr.c                      |  26 ++--
+ target/riscv/translate.c                |  17 ++-
+ target/riscv/insn_trans/trans_rvv.c.inc |  58 +++++----
+files changed, 325 insertions(+), 209 deletions(-)

-New patch
+[PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access
+From: Dylan Reid <dylan@rivosinc.com>
+VS mode access to hypervisor CSRs should generate virtual, not illegal,
+instruction exceptions.
+Don't return early and indicate an illegal instruction exception when
+accessing a hypervisor CSR from VS mode. Instead, fall through to the
+`hmode` predicate to return the correct virtual instruction exception.
+Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/csr.c | 10 +++++-----
+file changed, 5 insertions(+), 5 deletions(-)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+ #if !defined(CONFIG_USER_ONLY)
+     int effective_priv = env->priv;
+-    if (riscv_has_ext(env, RVH) &&
+-        env->priv == PRV_S &&
+-        !riscv_cpu_virt_enabled(env)) {
++    if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
+         /*
+-         * We are in S mode without virtualisation, therefore we are in HS Mode.
++         * We are in either HS or VS mode.
+          * Add 1 to the effective privledge level to allow us to access the
+-         * Hypervisor CSRs.
++         * Hypervisor CSRs. The `hmode` predicate will determine if access
++         * should be allowed(HS) or if a virtual instruction exception should be
++         * raised(VS).
+          */
+         effective_priv++;
+     }
+--
+.35.3

-New patch
+[PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store
+From: eopXD <eop.chen@sifive.com>
+Vector whole register load instructions have EEW encoded in the opcode,
+so we shouldn't take SEW here. Vector whole register store instructions
+are always EEW=8.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++------------
+file changed, 31 insertions(+), 27 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
+ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
+ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
+-                             gen_helper_ldst_whole *fn, DisasContext *s,
+-                             bool is_store)
++                             uint32_t width, gen_helper_ldst_whole *fn,
++                             DisasContext *s, bool is_store)
+ {
+-    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
++    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
+     TCGLabel *over = gen_new_label();
+     tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
+@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
+  * load and store whole register instructions ignore vtype and vl setting.
+  * Thus, we don't need to check vill bit. (Section 7.9)
+  */
+-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE)                      \
++#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE)               \
+ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)                 \
+ {                                                                         \
+     if (require_rvv(s) &&                                                 \
+         QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                                 \
+-        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
+-                                s, IS_STORE);                             \
++        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH,             \
++                                gen_helper_##NAME, s, IS_STORE);          \
+     }                                                                     \
+     return false;                                                         \
+ }
+-GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
+-
+-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
+-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
+-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
+-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
++GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, 1, false)
++GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
++GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
++GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
++GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, 1, false)
++GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
++GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
++GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
++GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, 1, false)
++GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
++GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
++GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
++GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, 1, false)
++GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
++GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
++GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
++
++/*
++ * The vector whole register store instructions are encoded similar to
++ * unmasked unit-stride store of elements with EEW=8.
++ */
++GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
++GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
++GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
++GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
+ /*
+  *** Vector Integer Arithmetic Instructions
+--
+.35.3

-New patch
+[PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp
+From: Atish Patra <atishp@rivosinc.com>
+timecmp update function should be invoked with hartid for which
+timecmp is being updated. The following patch passes the incorrect
+hartid to the update function.
+Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
+Signed-off-by: Atish Patra <atishp@rivosinc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Anup Patel <anup@brainfault.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/riscv_aclint.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aclint.c
++++ b/hw/intc/riscv_aclint.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
+                 continue;
+             }
+             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
+-                                              i, env->timecmp);
++                                              mtimer->hartid_base + i,
++                                              env->timecmp);
+         }
+         return;
+     }
+--
+.35.3

-New patch
+[PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
+Because extension category ordering of "H" is going to be after "V",
+their ordering is going to be valid (on canonical order).
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+         ISA_EDATA_ENTRY(zfh, ext_zfh),
+         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+         ISA_EDATA_ENTRY(zdinx, ext_zdinx),
+         ISA_EDATA_ENTRY(zba, ext_zba),
+         ISA_EDATA_ENTRY(zbb, ext_zbb),
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+         ISA_EDATA_ENTRY(zkt, ext_zkt),
+         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
+         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
++        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
++        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+         ISA_EDATA_ENTRY(svinval, ext_svinval),
+         ISA_EDATA_ENTRY(svnapot, ext_svnapot),
+         ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+--
+.35.3

-New patch
+[PULL 05/23] target/riscv: Add short-isa-string option
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+Because some operating systems don't correctly parse long ISA extension
+string, this commit adds short-isa-string boolean option to disable
+generating long ISA extension strings on Device Tree.
+For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
+earlier) with FPU support caused a kernel panic.
+Operating Systems which short-isa-string might be helpful:
+.  Linux (5.17 or earlier)
+.  FreeBSD (at least 14.0-CURRENT)
+.  OpenBSD (at least current development version)
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 2 ++
+ target/riscv/cpu.c | 6 +++++-
+files changed, 7 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool aia;
+     bool debug;
+     uint64_t resetvec;
++
++    bool short_isa_string;
+ };
+ typedef struct RISCVCPUConfig RISCVCPUConfig;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
+     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
++
++    DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
+         }
+     }
+     *p = '\0';
+-    riscv_isa_string_ext(cpu, &isa_str, maxlen);
++    if (!cpu->cfg.short_isa_string) {
++        riscv_isa_string_ext(cpu, &isa_str, maxlen);
++    }
+     return isa_str;
+ }
+--
+.35.3

-New patch
+[PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike)
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+If specified CPU configuration is not valid, not just it prints error
+message, it aborts and generates core dumps (depends on the operating
+system).  This kind of error handling should be used only when a serious
+runtime error occurs.
+This commit makes error handling on CPU configuration more generous on
+virt/spike machines.  It now just prints error message and quits (without
+coredumps and aborts).
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/spike.c | 2 +-
+ hw/riscv/virt.c  | 2 +-
+files changed, 2 insertions(+), 2 deletions(-)
+diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/spike.c
++++ b/hw/riscv/spike.c
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+                                 base_hartid, &error_abort);
+         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                 hart_count, &error_abort);
+-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
++        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
+         /* Core Local Interruptor (timer and IPI) for each socket */
+         riscv_aclint_swi_create(
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+                                 base_hartid, &error_abort);
+         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                 hart_count, &error_abort);
+-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
++        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
+         if (!kvm_enabled()) {
+             if (s->have_aclint) {
+--
+.35.3

-New patch
+[PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+If specified CPU configuration is not valid, not just it prints error
+message, it aborts and generates core dumps (depends on the operating
+system).  This kind of error handling should be used only when a serious
+runtime error occurs.
+This commit makes error handling on CPU configuration more generous on
+sifive_e/u and opentitan machines.  It now just prints error message and
+quits (without coredumps and aborts).
+This is separate from spike/virt because it involves different type
+(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/opentitan.c | 2 +-
+ hw/riscv/sifive_e.c  | 2 +-
+ hw/riscv/sifive_u.c  | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+                             &error_abort);
+     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
+     /* Boot ROM */
+     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
+diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_e.c
++++ b/hw/riscv/sifive_e.c
+@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
+     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
+                             &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
+     /* Mask ROM */
+     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_u.c
++++ b/hw/riscv/sifive_u.c
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
+     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
++    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
+     /*
+      * The cluster must be realized after the RISC-V hart array container,
+      * as the container's CPU object is only created on realize, and the
+--
+.35.3

-New patch
+[PULL 08/23] target/riscv: Fix coding style on "G" expansion
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+Because ext_? members are boolean variables, operator `&&' should be
+used instead of `&'.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
+Message-Id: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             return;
+         }
+-        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+-                                cpu->cfg.ext_a & cpu->cfg.ext_f &
++        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
++                                cpu->cfg.ext_a && cpu->cfg.ext_f &&
+                                 cpu->cfg.ext_d)) {
+             warn_report("Setting G will also set IMAFD");
+             cpu->cfg.ext_i = true;
+--
+.35.3

-New patch
+[PULL 09/23] target/riscv: Disable "G" by default
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+Because "G" virtual extension expands to "IMAFD", we cannot separately
+disable extensions like "F" or "D" without disabling "G".  Because all
+"IMAFD" are enabled by default, it's harmless to disable "G" by default.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     /* Defaults for standard extensions */
+     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
+     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
+-    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
++    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
+     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
+     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
+     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
+--
+.35.3

-New patch
+[PULL 10/23] target/riscv: Change "G" expansion
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
+Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
+be (virtually) enabled as well, it should be safe to change its expansion.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 7 +++++--
+file changed, 5 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+         if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+                                 cpu->cfg.ext_a && cpu->cfg.ext_f &&
+-                                cpu->cfg.ext_d)) {
+-            warn_report("Setting G will also set IMAFD");
++                                cpu->cfg.ext_d &&
++                                cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
++            warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+             cpu->cfg.ext_i = true;
+             cpu->cfg.ext_m = true;
+             cpu->cfg.ext_a = true;
+             cpu->cfg.ext_f = true;
+             cpu->cfg.ext_d = true;
++            cpu->cfg.ext_icsr = true;
++            cpu->cfg.ext_ifencei = true;
+         }
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+--
+.35.3

-New patch
+[PULL 11/23] target/riscv: FP extension requirements
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+QEMU allowed inconsistent configurations that made floating point
+arithmetic effectively unusable.
+This commit adds certain checks for consistent FP arithmetic:
+-   F requires Zicsr
+-   Zfinx requires Zicsr
+-   Zfh/Zfhmin require F
+-   D requires F
+-   V requires D
+Because F/D/Zicsr are enabled by default (and an error will not occur unless
+we manually disable one or more of prerequisites), this commit just enforces
+the user to give consistent combinations.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 25 +++++++++++++++++++++++++
+file changed, 25 insertions(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_ifencei = true;
+         }
++        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
++            error_setg(errp, "F extension requires Zicsr");
++            return;
++        }
++
++        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
++            error_setg(errp, "Zfh/Zfhmin extensions require F extension");
++            return;
++        }
++
++        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
++            error_setg(errp, "D extension requires F extension");
++            return;
++        }
++
++        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
++            error_setg(errp, "V extension requires D extension");
++            return;
++        }
++
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+             cpu->cfg.ext_zhinxmin) {
+             cpu->cfg.ext_zfinx = true;
+         }
++        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
++            error_setg(errp, "Zfinx extension requires Zicsr");
++            return;
++        }
++
+         if (cpu->cfg.ext_zk) {
+             cpu->cfg.ext_zkn = true;
+             cpu->cfg.ext_zkr = true;
+--
+.35.3

-New patch
+[PULL 12/23] target/riscv: Move/refactor ISA extension checks
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+We should separate "check" and "configure" steps as possible.
+This commit separates both steps except vector/Zfinx-related checks.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 31 ++++++++++++++++---------------
+file changed, 16 insertions(+), 15 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             return;
+         }
++        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
++            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
++            return;
++        }
++
++        /* Set the ISA extensions, checks should have happened above */
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+             cpu->cfg.ext_zhinxmin) {
+             cpu->cfg.ext_zfinx = true;
+         }
+-        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
+-            error_setg(errp, "Zfinx extension requires Zicsr");
+-            return;
++        if (cpu->cfg.ext_zfinx) {
++            if (!cpu->cfg.ext_icsr) {
++                error_setg(errp, "Zfinx extension requires Zicsr");
++                return;
++            }
++            if (cpu->cfg.ext_f) {
++                error_setg(errp,
++                    "Zfinx cannot be supported together with F extension");
++                return;
++            }
+         }
+         if (cpu->cfg.ext_zk) {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_zksh = true;
+         }
+-        /* Set the ISA extensions, checks should have happened above */
+         if (cpu->cfg.ext_i) {
+             ext |= RVI;
+         }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             }
+             set_vext_version(env, vext_version);
+         }
+-        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+-            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
+-            return;
+-        }
+         if (cpu->cfg.ext_j) {
+             ext |= RVJ;
+         }
+-        if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
+-                                   cpu->cfg.ext_zfhmin)) {
+-            error_setg(errp,
+-                    "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
+-                    " 'Zfhmin'");
+-            return;
+-        }
+         set_misa(env, env->misa_mxl, ext);
+     }
+--
+.35.3

-New patch
+[PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters
+From: Bernhard Beschow <shentey@gmail.com>
+The QOM API already provides getters for uint64 and uint32 values, so reuse
+them.
+Signed-off-by: Bernhard Beschow <shentey@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-Id: <20220301225220.239065-2-shentey@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/vfio/pci-quirks.c | 34 +++++++++-------------------------
+file changed, 9 insertions(+), 25 deletions(-)
+diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/vfio/pci-quirks.c
++++ b/hw/vfio/pci-quirks.c
+@@ -XXX,XX +XXX,XX @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
+     return 0;
+ }
+-static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
+-                                     const char *name,
+-                                     void *opaque, Error **errp)
+-{
+-    uint64_t tgt = (uintptr_t) opaque;
+-    visit_type_uint64(v, name, &tgt, errp);
+-}
+-
+-static void vfio_pci_nvlink2_get_link_speed(Object *obj, Visitor *v,
+-                                                 const char *name,
+-                                                 void *opaque, Error **errp)
+-{
+-    uint32_t link_speed = (uint32_t)(uintptr_t) opaque;
+-    visit_type_uint32(v, name, &link_speed, errp);
+-}
+-
+ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
+ {
+     int ret;
+@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
+                                nv2reg->size, p);
+     QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
+-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
+-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
+-                        (void *) (uintptr_t) cap->tgt);
++    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
++                                   (uint64_t *) &cap->tgt,
++                                   OBJ_PROP_FLAG_READ);
+     trace_vfio_pci_nvidia_gpu_setup_quirk(vdev->vbasedev.name, cap->tgt,
+                                           nv2reg->size);
+ free_exit:
+@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp)
+         QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
+     }
+-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
+-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
+-                        (void *) (uintptr_t) captgt->tgt);
++    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
++                                   (uint64_t *) &captgt->tgt,
++                                   OBJ_PROP_FLAG_READ);
+     trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev->vbasedev.name, captgt->tgt,
+                                               atsdreg->size);
+-    object_property_add(OBJECT(vdev), "nvlink2-link-speed", "uint32",
+-                        vfio_pci_nvlink2_get_link_speed, NULL, NULL,
+-                        (void *) (uintptr_t) capspeed->link_speed);
++    object_property_add_uint32_ptr(OBJECT(vdev), "nvlink2-link-speed",
++                                   &capspeed->link_speed,
++                                   OBJ_PROP_FLAG_READ);
+     trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev->vbasedev.name,
+                                               capspeed->link_speed);
+ free_exit:
+--
+.35.3

-[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
+[PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Bernhard Beschow <shentey@gmail.com>
-Once a "One Time Programmable" is programmed, it shouldn't be reset.
+The QOM API already provides accessors for uint32 values, so reuse them.
-Do not re-initialize the OTP content in the DeviceReset handler,
+Signed-off-by: Bernhard Beschow <shentey@gmail.com>
-initialize it once in the DeviceRealize one.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
+Message-Id: <20220301225220.239065-3-shentey@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/misc/sifive_u_otp.c | 13 +++++--------
+ hw/riscv/sifive_u.c | 24 ++++--------------------
-file changed, 5 insertions(+), 8 deletions(-)
+file changed, 4 insertions(+), 20 deletions(-)
-diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/sifive_u_otp.c
+--- a/hw/riscv/sifive_u.c
-+++ b/hw/misc/sifive_u_otp.c
++++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
+     s->start_in_flash = value;
-             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
+ }
-                 error_setg(errp, "failed to read the initial flash content");
-+                return;
+-static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
-             }
+-                                             const char *name, void *opaque,
-         }
+-                                             Error **errp)
-     }
+-{
 -    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
 -}
 -
--static void sifive_u_otp_reset(DeviceState *dev)
+-static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
 -                                             const char *name, void *opaque,
 -                                             Error **errp)
 -{
--    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
+-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+-}
-     /* Initialize all fuses' initial value to 0xFFs */
+-
-     memset(s->fuse, 0xff, sizeof(s->fuse));
+ static void sifive_u_machine_instance_init(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
+ {
-         serial_data = s->serial;
+     SiFiveUState *s = RISCV_U_MACHINE(obj);
-         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
-                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
+     s->start_in_flash = false;
--            error_report("write error index<%d>", index);
+     s->msel = 0;
-+            error_setg(errp, "failed to write index<%d>", index);
+-    object_property_add(obj, "msel", "uint32",
-+            return;
+-                        sifive_u_machine_get_uint32_prop,
-         }
+-                        sifive_u_machine_set_uint32_prop, NULL, &s->msel);
++    object_property_add_uint32_ptr(obj, "msel", &s->msel,
-         serial_data = ~(s->serial);
++                                   OBJ_PROP_FLAG_READWRITE);
-         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
+     object_property_set_description(obj, "msel",
-                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
+                                     "Mode Select (MSEL[3:0]) pin state");
--            error_report("write error index<%d>", index + 1);
-+            error_setg(errp, "failed to write index<%d>", index + 1);
+     s->serial = OTP_SERIAL;
-+            return;
+-    object_property_add(obj, "serial", "uint32",
-         }
+-                        sifive_u_machine_get_uint32_prop,
-     }
+-                        sifive_u_machine_set_uint32_prop, NULL, &s->serial);
++    object_property_add_uint32_ptr(obj, "serial", &s->serial,
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
++                                   OBJ_PROP_FLAG_READWRITE);
+     object_property_set_description(obj, "serial", "Board serial number");
      device_class_set_props(dc, sifive_u_otp_properties);
      dc->realize = sifive_u_otp_realize;
 -    dc->reset = sifive_u_otp_reset;
  }
- static const TypeInfo sifive_u_otp_info = {
 --
-.31.1
+.35.3

-New patch
+[PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
+From: Weiwei Li <liweiwei@iscas.ac.cn>
+ - setting ext_g will implicitly set ext_i
+Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 24 ++++++++++++------------
+file changed, 12 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+         uint32_t ext = 0;
+         /* Do some ISA extension error checking */
+-        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+-            error_setg(errp,
+-                       "I and E extensions are incompatible");
+-            return;
+-        }
+-
+-        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+-            error_setg(errp,
+-                       "Either I or E extension must be set");
+-            return;
+-        }
+-
+         if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+                                 cpu->cfg.ext_a && cpu->cfg.ext_f &&
+                                 cpu->cfg.ext_d &&
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_ifencei = true;
+         }
++        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
++            error_setg(errp,
++                       "I and E extensions are incompatible");
++            return;
++        }
++
++        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
++            error_setg(errp,
++                       "Either I or E extension must be set");
++            return;
++        }
++
+         if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+             error_setg(errp, "F extension requires Zicsr");
+             return;
+--
+.35.3

-New patch
+[PULL 16/23] target/riscv: Fix typo of mimpid cpu option
+From: Frank Chang <frank.chang@sifive.com>
+"mimpid" cpu option was mistyped to "mipid".
+Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values")
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 2 +-
+ target/riscv/cpu.c | 4 ++--
+ target/riscv/csr.c | 8 ++++----
+files changed, 7 insertions(+), 7 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     uint32_t mvendorid;
+     uint64_t marchid;
+-    uint64_t mipid;
++    uint64_t mimpid;
+     /* Vendor-specific custom extensions */
+     bool ext_XVentanaCondOps;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@
+ #define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
+                              (QEMU_VERSION_MINOR << 8)  | \
+                              (QEMU_VERSION_MICRO))
+-#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
++#define RISCV_CPU_MIMPID    RISCV_CPU_MARCHID
+ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+-    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
++    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
+     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
+     return RISCV_EXCP_NONE;
+ }
+-static RISCVException read_mipid(CPURISCVState *env, int csrno,
+-                                 target_ulong *val)
++static RISCVException read_mimpid(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     CPUState *cs = env_cpu(env);
+     RISCVCPU *cpu = RISCV_CPU(cs);
+-    *val = cpu->cfg.mipid;
++    *val = cpu->cfg.mimpid;
+     return RISCV_EXCP_NONE;
+ }
+@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
+     /* Machine Information Registers */
+     [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
+     [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
+-    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
++    [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
+     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
+     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
+--
+.35.3

-New patch
+[PULL 17/23] target/riscv: Fix csr number based privilege checking
+From: Anup Patel <apatel@ventanamicro.com>
+When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
+the riscv_csrrw_check() function should generate virtual instruction
+trap instead illegal instruction trap.
+Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/csr.c | 8 ++++++--
+file changed, 6 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+     int read_only = get_field(csrno, 0xC00) == 3;
+     int csr_min_priv = csr_ops[csrno].min_priv_ver;
+ #if !defined(CONFIG_USER_ONLY)
+-    int effective_priv = env->priv;
++    int csr_priv, effective_priv = env->priv;
+     if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
+         /*
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+         effective_priv++;
+     }
+-    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
++    csr_priv = get_field(csrno, 0x300);
++    if (!env->debugger && (effective_priv < csr_priv)) {
++        if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
++            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++        }
+         return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+--
+.35.3

-New patch
+[PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
+From: Anup Patel <apatel@ventanamicro.com>
+Currently, QEMU does not set hstatus.GVA bit for traps taken from
+HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
+on QEMU. This was working previously.
+This patch updates riscv_cpu_do_interrupt() to fix the above issue.
+Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 3 +--
+file changed, 1 insertion(+), 2 deletions(-)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+         case RISCV_EXCP_INST_PAGE_FAULT:
+         case RISCV_EXCP_LOAD_PAGE_FAULT:
+         case RISCV_EXCP_STORE_PAGE_FAULT:
+-            write_gva = true;
++            write_gva = env->two_stage_lookup;
+             tval = env->badaddr;
+             break;
+         case RISCV_EXCP_ILLEGAL_INST:
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+                 /* Trap into HS mode */
+                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
+                 htval = env->guest_phys_fault_addr;
+-                write_gva = false;
+             }
+             env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
+         }
+--
+.35.3

-New patch
+[PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
+From: Anup Patel <apatel@ventanamicro.com>
+Currently, the [m|s]tval CSRs are set with trapping instruction encoding
+only for illegal instruction traps taken at the time of instruction
+decoding.
+In RISC-V world, a valid instructions might also trap as illegal or
+virtual instruction based to trapping bits in various CSRs (such as
+mstatus.TVM or hstatus.VTVM).
+We improve setting of [m|s]tval CSRs for all types of illegal and
+virtual instruction traps.
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h        |  8 +++++++-
+ target/riscv/cpu.c        |  2 ++
+ target/riscv/cpu_helper.c |  1 +
+ target/riscv/translate.c  | 17 +++++++++++++----
+files changed, 23 insertions(+), 5 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ #define TCG_GUEST_DEFAULT_MO 0
++/*
++ * RISC-V-specific extra insn start words:
++ * 1: Original instruction opcode
++ */
++#define TARGET_INSN_START_EXTRA_WORDS 1
++
+ #define TYPE_RISCV_CPU "riscv-cpu"
+ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
+@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
+     target_ulong frm;
+     target_ulong badaddr;
+-    uint32_t bins;
++    target_ulong bins;
+     target_ulong guest_phys_fault_addr;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
+     } else {
+         env->pc = data[0];
+     }
++    env->bins = data[1];
+ }
+ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+     env->mcause = 0;
+     env->miclaim = MIP_SGEIP;
+     env->pc = env->resetvec;
++    env->bins = 0;
+     env->two_stage_lookup = false;
+     /* Initialized default priorities of local interrupts. */
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+             tval = env->badaddr;
+             break;
+         case RISCV_EXCP_ILLEGAL_INST:
++        case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
+             tval = env->bins;
+             break;
+         default:
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     /* PointerMasking extension */
+     bool pm_mask_enabled;
+     bool pm_base_enabled;
++    /* TCG of the current insn_start */
++    TCGOp *insn_start;
+ } DisasContext;
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
+ static void gen_exception_illegal(DisasContext *ctx)
+ {
+-    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+-                   offsetof(CPURISCVState, bins));
+-
+     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+ }
+@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+ /* Include decoders for factored-out extensions */
+ #include "decode-XVentanaCondOps.c.inc"
++static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
++{
++    assert(ctx->insn_start != NULL);
++    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
++    ctx->insn_start = NULL;
++}
++
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+ {
+     /*
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+     /* Check for compressed insn */
+     if (extract16(opcode, 0, 2) != 3) {
++        decode_save_opc(ctx, opcode);
+         if (!has_ext(ctx, RVC)) {
+             gen_exception_illegal(ctx);
+         } else {
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+         opcode32 = deposit32(opcode32, 16, 16,
+                              translator_lduw(env, &ctx->base,
+                                              ctx->base.pc_next + 2));
++        decode_save_opc(ctx, opcode32);
+         ctx->opcode = opcode32;
+         ctx->pc_succ_insn = ctx->base.pc_next + 4;
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
+ {
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+-    tcg_gen_insn_start(ctx->base.pc_next);
++    tcg_gen_insn_start(ctx->base.pc_next, 0);
++    ctx->insn_start = tcg_last_op();
+ }
+ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+--
+.35.3

-New patch
+[PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices
+From: Anup Patel <apatel@ventanamicro.com>
+When both APLIC and IMSIC are present in virt machine, the APLIC should
+be used as parent interrupt controller for dynamic platform devices.
+In case of  multiple sockets, we should prefer interrupt controller of
+socket0 for dynamic platform devices.
+Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
+platform FDT entries")
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/virt.c | 25 ++++++++++++-------------
+file changed, 12 insertions(+), 13 deletions(-)
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
+     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+         plic_phandles[socket]);
+-    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+-                                   memmap[VIRT_PLATFORM_BUS].base,
+-                                   memmap[VIRT_PLATFORM_BUS].size,
+-                                   VIRT_PLATFORM_BUS_IRQ);
++    if (!socket) {
++        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
++                                       memmap[VIRT_PLATFORM_BUS].base,
++                                       memmap[VIRT_PLATFORM_BUS].size,
++                                       VIRT_PLATFORM_BUS_IRQ);
++    }
+     g_free(plic_name);
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+     }
+     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+-    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
+-                                   memmap[VIRT_PLATFORM_BUS].base,
+-                                   memmap[VIRT_PLATFORM_BUS].size,
+-                                   VIRT_PLATFORM_BUS_IRQ);
+-
+     g_free(imsic_name);
+     /* S-level IMSIC node */
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
+     riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+-    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+-                                   memmap[VIRT_PLATFORM_BUS].base,
+-                                   memmap[VIRT_PLATFORM_BUS].size,
+-                                   VIRT_PLATFORM_BUS_IRQ);
++    if (!socket) {
++        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
++                                       memmap[VIRT_PLATFORM_BUS].base,
++                                       memmap[VIRT_PLATFORM_BUS].size,
++                                       VIRT_PLATFORM_BUS_IRQ);
++    }
+     g_free(aplic_name);
+--
+.35.3

-New patch
+[PULL 21/23] target/riscv: add zicsr/zifencei to isa_string
+From: "Hongren (Zenithal) Zheng" <i@zenithal.me>
+Zicsr/Zifencei is not in 'I' since ISA version 20190608,
+thus to fully express the capability of the CPU,
+they should be exposed in isa_string.
+Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
+Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <YoTqwpfrodveJ7CR@Sun>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 2 ++
+file changed, 2 insertions(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+      *    extensions by an underscore.
+      */
+     struct isa_ext_data isa_edata_arr[] = {
++        ISA_EDATA_ENTRY(zicsr, ext_icsr),
++        ISA_EDATA_ENTRY(zifencei, ext_ifencei),
+         ISA_EDATA_ENTRY(zfh, ext_zfh),
+         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+--
+.35.3

-New patch
+[PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01
+From: Bin Meng <bin.meng@windriver.com>
 Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
 [1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  hw/core/uboot_image.h | 213 ++++++++++++++++++++++++++++--------------
 file changed, 142 insertions(+), 71 deletions(-)
 diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/uboot_image.h
 +++ b/hw/core/uboot_image.h
@@ -XXX,XX +XXX,XX @@
 +/* SPDX-License-Identifier: GPL-2.0+ */
  /*
 + * (C) Copyright 2008 Semihalf
 + *
   * (C) Copyright 2000-2005
   * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 - *
 - * See file CREDITS for list of people who contributed to this
 - * project.
 - *
 - * This program is free software; you can redistribute it and/or
 - * modify it under the terms of the GNU General Public License as
 - * published by the Free Software Foundation; either version 2 of
 - * the License, or (at your option) any later version.
 - *
 - * This program is distributed in the hope that it will be useful,
 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     See the
 - * GNU General Public License for more details.
 - *
 - * You should have received a copy of the GNU General Public License along
 - * with this program; if not, see <http://www.gnu.org/licenses/>.
 - *
   ********************************************************************
   * NOTE: This header file defines an interface to U-Boot. Including
   * this (unmodified) header file in another file is considered normal
@@ -XXX,XX +XXX,XX @@
  /*
   * Operating System Codes
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_OS_INVALID        0    /* Invalid OS    */
 -#define IH_OS_OPENBSD        1    /* OpenBSD    */
 -#define IH_OS_NETBSD        2    /* NetBSD    */
 -#define IH_OS_FREEBSD        3    /* FreeBSD    */
 -#define IH_OS_4_4BSD        4    /* 4.4BSD    */
 -#define IH_OS_LINUX        5    /* Linux    */
 -#define IH_OS_SVR4        6    /* SVR4        */
 -#define IH_OS_ESIX        7    /* Esix        */
 -#define IH_OS_SOLARIS        8    /* Solaris    */
 -#define IH_OS_IRIX        9    /* Irix        */
 -#define IH_OS_SCO        10    /* SCO        */
 -#define IH_OS_DELL        11    /* Dell        */
 -#define IH_OS_NCR        12    /* NCR        */
 -#define IH_OS_LYNXOS        13    /* LynxOS    */
 -#define IH_OS_VXWORKS        14    /* VxWorks    */
 -#define IH_OS_PSOS        15    /* pSOS        */
 -#define IH_OS_QNX        16    /* QNX        */
 -#define IH_OS_U_BOOT        17    /* Firmware    */
 -#define IH_OS_RTEMS        18    /* RTEMS    */
 -#define IH_OS_ARTOS        19    /* ARTOS    */
 -#define IH_OS_UNITY        20    /* Unity OS    */
 +enum {
 +    IH_OS_INVALID        = 0,    /* Invalid OS    */
 +    IH_OS_OPENBSD,            /* OpenBSD    */
 +    IH_OS_NETBSD,            /* NetBSD    */
 +    IH_OS_FREEBSD,            /* FreeBSD    */
 +    IH_OS_4_4BSD,            /* 4.4BSD    */
 +    IH_OS_LINUX,            /* Linux    */
 +    IH_OS_SVR4,            /* SVR4        */
 +    IH_OS_ESIX,            /* Esix        */
 +    IH_OS_SOLARIS,            /* Solaris    */
 +    IH_OS_IRIX,            /* Irix        */
 +    IH_OS_SCO,            /* SCO        */
 +    IH_OS_DELL,            /* Dell        */
 +    IH_OS_NCR,            /* NCR        */
 +    IH_OS_LYNXOS,            /* LynxOS    */
 +    IH_OS_VXWORKS,            /* VxWorks    */
 +    IH_OS_PSOS,            /* pSOS        */
 +    IH_OS_QNX,            /* QNX        */
 +    IH_OS_U_BOOT,            /* Firmware    */
 +    IH_OS_RTEMS,            /* RTEMS    */
 +    IH_OS_ARTOS,            /* ARTOS    */
 +    IH_OS_UNITY,            /* Unity OS    */
 +    IH_OS_INTEGRITY,        /* INTEGRITY    */
 +    IH_OS_OSE,            /* OSE        */
 +    IH_OS_PLAN9,            /* Plan 9    */
 +    IH_OS_OPENRTOS,        /* OpenRTOS    */
 +    IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
 +    IH_OS_TEE,            /* Trusted Execution Environment */
 +    IH_OS_OPENSBI,            /* RISC-V OpenSBI */
 +    IH_OS_EFI,            /* EFI Firmware (e.g. GRUB2) */
 +
 +    IH_OS_COUNT,
 +};
  /*
   * CPU Architecture Codes (supported by Linux)
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_CPU_INVALID        0    /* Invalid CPU    */
 -#define IH_CPU_ALPHA        1    /* Alpha    */
 -#define IH_CPU_ARM        2    /* ARM        */
 -#define IH_CPU_I386        3    /* Intel x86    */
 -#define IH_CPU_IA64        4    /* IA64        */
 -#define IH_CPU_MIPS        5    /* MIPS        */
 -#define IH_CPU_MIPS64        6    /* MIPS     64 Bit */
 -#define IH_CPU_PPC        7    /* PowerPC    */
 -#define IH_CPU_S390        8    /* IBM S390    */
 -#define IH_CPU_SH        9    /* SuperH    */
 -#define IH_CPU_SPARC        10    /* Sparc    */
 -#define IH_CPU_SPARC64        11    /* Sparc 64 Bit */
 -#define IH_CPU_M68K        12    /* M68K        */
 -#define IH_CPU_NIOS        13    /* Nios-32    */
 -#define IH_CPU_MICROBLAZE    14    /* MicroBlaze   */
 -#define IH_CPU_NIOS2        15    /* Nios-II    */
 -#define IH_CPU_BLACKFIN        16    /* Blackfin    */
 -#define IH_CPU_AVR32        17    /* AVR32    */
 +enum {
 +    IH_ARCH_INVALID        = 0,    /* Invalid CPU    */
 +    IH_ARCH_ALPHA,            /* Alpha    */
 +    IH_ARCH_ARM,            /* ARM        */
 +    IH_ARCH_I386,            /* Intel x86    */
 +    IH_ARCH_IA64,            /* IA64        */
 +    IH_ARCH_MIPS,            /* MIPS        */
 +    IH_ARCH_MIPS64,            /* MIPS     64 Bit */
 +    IH_ARCH_PPC,            /* PowerPC    */
 +    IH_ARCH_S390,            /* IBM S390    */
 +    IH_ARCH_SH,            /* SuperH    */
 +    IH_ARCH_SPARC,            /* Sparc    */
 +    IH_ARCH_SPARC64,        /* Sparc 64 Bit */
 +    IH_ARCH_M68K,            /* M68K        */
 +    IH_ARCH_NIOS,            /* Nios-32    */
 +    IH_ARCH_MICROBLAZE,        /* MicroBlaze   */
 +    IH_ARCH_NIOS2,            /* Nios-II    */
 +    IH_ARCH_BLACKFIN,        /* Blackfin    */
 +    IH_ARCH_AVR32,            /* AVR32    */
 +    IH_ARCH_ST200,            /* STMicroelectronics ST200  */
 +    IH_ARCH_SANDBOX,        /* Sandbox architecture (test only) */
 +    IH_ARCH_NDS32,            /* ANDES Technology - NDS32  */
 +    IH_ARCH_OPENRISC,        /* OpenRISC 1000  */
 +    IH_ARCH_ARM64,            /* ARM64    */
 +    IH_ARCH_ARC,            /* Synopsys DesignWare ARC */
 +    IH_ARCH_X86_64,            /* AMD x86_64, Intel and Via */
 +    IH_ARCH_XTENSA,            /* Xtensa    */
 +    IH_ARCH_RISCV,            /* RISC-V */
 +
 +    IH_ARCH_COUNT,
 +};
  /*
   * Image Types
@@ -XXX,XX +XXX,XX @@
   *    U-Boot's command interpreter; this feature is especially
   *    useful when you configure U-Boot to use a real shell (hush)
   *    as command interpreter (=> Shell Scripts).
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_TYPE_INVALID        0    /* Invalid Image        */
 -#define IH_TYPE_STANDALONE    1    /* Standalone Program        */
 -#define IH_TYPE_KERNEL        2    /* OS Kernel Image        */
 -#define IH_TYPE_RAMDISK        3    /* RAMDisk Image        */
 -#define IH_TYPE_MULTI        4    /* Multi-File Image        */
 -#define IH_TYPE_FIRMWARE    5    /* Firmware Image        */
 -#define IH_TYPE_SCRIPT        6    /* Script file            */
 -#define IH_TYPE_FILESYSTEM    7    /* Filesystem Image (any type)    */
 -#define IH_TYPE_FLATDT        8    /* Binary Flat Device Tree Blob    */
 -#define IH_TYPE_KERNEL_NOLOAD  14    /* OS Kernel Image (noload)    */
 +enum {
 +    IH_TYPE_INVALID        = 0,    /* Invalid Image        */
 +    IH_TYPE_STANDALONE,        /* Standalone Program        */
 +    IH_TYPE_KERNEL,            /* OS Kernel Image        */
 +    IH_TYPE_RAMDISK,        /* RAMDisk Image        */
 +    IH_TYPE_MULTI,            /* Multi-File Image        */
 +    IH_TYPE_FIRMWARE,        /* Firmware Image        */
 +    IH_TYPE_SCRIPT,            /* Script file            */
 +    IH_TYPE_FILESYSTEM,        /* Filesystem Image (any type)    */
 +    IH_TYPE_FLATDT,            /* Binary Flat Device Tree Blob    */
 +    IH_TYPE_KWBIMAGE,        /* Kirkwood Boot Image        */
 +    IH_TYPE_IMXIMAGE,        /* Freescale IMXBoot Image    */
 +    IH_TYPE_UBLIMAGE,        /* Davinci UBL Image        */
 +    IH_TYPE_OMAPIMAGE,        /* TI OMAP Config Header Image    */
 +    IH_TYPE_AISIMAGE,        /* TI Davinci AIS Image        */
 +    /* OS Kernel Image, can run from any load address */
 +    IH_TYPE_KERNEL_NOLOAD,
 +    IH_TYPE_PBLIMAGE,        /* Freescale PBL Boot Image    */
 +    IH_TYPE_MXSIMAGE,        /* Freescale MXSBoot Image    */
 +    IH_TYPE_GPIMAGE,        /* TI Keystone GPHeader Image    */
 +    IH_TYPE_ATMELIMAGE,        /* ATMEL ROM bootable Image    */
 +    IH_TYPE_SOCFPGAIMAGE,        /* Altera SOCFPGA CV/AV Preloader */
 +    IH_TYPE_X86_SETUP,        /* x86 setup.bin Image        */
 +    IH_TYPE_LPC32XXIMAGE,        /* x86 setup.bin Image        */
 +    IH_TYPE_LOADABLE,        /* A list of typeless images    */
 +    IH_TYPE_RKIMAGE,        /* Rockchip Boot Image        */
 +    IH_TYPE_RKSD,            /* Rockchip SD card        */
 +    IH_TYPE_RKSPI,            /* Rockchip SPI image        */
 +    IH_TYPE_ZYNQIMAGE,        /* Xilinx Zynq Boot Image */
 +    IH_TYPE_ZYNQMPIMAGE,        /* Xilinx ZynqMP Boot Image */
 +    IH_TYPE_ZYNQMPBIF,        /* Xilinx ZynqMP Boot Image (bif) */
 +    IH_TYPE_FPGA,            /* FPGA Image */
 +    IH_TYPE_VYBRIDIMAGE,    /* VYBRID .vyb Image */
 +    IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
 +    IH_TYPE_FIRMWARE_IVT,        /* Firmware Image with HABv4 IVT */
 +    IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
 +    IH_TYPE_STM32IMAGE,        /* STMicroelectronics STM32 Image */
 +    IH_TYPE_SOCFPGAIMAGE_V1,    /* Altera SOCFPGA A10 Preloader    */
 +    IH_TYPE_MTKIMAGE,        /* MediaTek BootROM loadable Image */
 +    IH_TYPE_IMX8MIMAGE,        /* Freescale IMX8MBoot Image    */
 +    IH_TYPE_IMX8IMAGE,        /* Freescale IMX8Boot Image    */
 +    IH_TYPE_COPRO,            /* Coprocessor Image for remoteproc*/
 +    IH_TYPE_SUNXI_EGON,        /* Allwinner eGON Boot Image */
 +
 +    IH_TYPE_COUNT,            /* Number of image types */
 +};
  /*
   * Compression Types
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_COMP_NONE        0    /*  No     Compression Used    */
 -#define IH_COMP_GZIP        1    /* gzip     Compression Used    */
 -#define IH_COMP_BZIP2        2    /* bzip2 Compression Used    */
 +enum {
 +    IH_COMP_NONE        = 0,    /*  No     Compression Used    */
 +    IH_COMP_GZIP,            /* gzip     Compression Used    */
 +    IH_COMP_BZIP2,            /* bzip2 Compression Used    */
 +    IH_COMP_LZMA,            /* lzma  Compression Used    */
 +    IH_COMP_LZO,            /* lzo   Compression Used    */
 +    IH_COMP_LZ4,            /* lz4   Compression Used    */
 +    IH_COMP_ZSTD,            /* zstd   Compression Used    */
 +
 +    IH_COMP_COUNT,
 +};
  #define IH_MAGIC    0x27051956    /* Image Magic Number        */
  #define IH_NMLEN        32    /* Image Name Length        */
  /*
 - * all data in network byte order (aka natural aka bigendian)
 + * Legacy format image header,
 + * all data in network byte order (aka natural aka bigendian).
   */
 -
  typedef struct uboot_image_header {
      uint32_t    ih_magic;    /* Image Header Magic Number    */
      uint32_t    ih_hcrc;    /* Image Header CRC Checksum    */
 --
 .35.3

-[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
+[PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage
-From: Thomas Huth <thuth@redhat.com>
+From: Bin Meng <bin.meng@windriver.com>
-Configuring a drive with "if=none" is meant for creation of a backend
+VxWorks 7 uses the same boot interface as the Linux kernel on Arm
-only, it should not get automatically assigned to a device frontend.
+(64-bit only), PowerPC and RISC-V architectures. Add logic to set
-Use "if=pflash" for the One-Time-Programmable device instead (like
+is_linux to true for VxWorks uImage for these architectures in
-it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
+load_uboot_image().
-Since the old way of configuring the device has already been published
+Signed-off-by: Bin Meng <bin.meng@windriver.com>
-with the previous QEMU versions, we cannot remove this immediately, but
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 have to deprecate it and support it for at least two more releases.
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20211119102549.217755-1-thuth@redhat.com
+Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/about/deprecated.rst | 6 ++++++
+ hw/core/loader.c | 15 +++++++++++++++
- hw/misc/sifive_u_otp.c    | 9 ++++++++-
+file changed, 15 insertions(+)
 files changed, 14 insertions(+), 1 deletion(-)
-diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
+diff --git a/hw/core/loader.c b/hw/core/loader.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
+--- a/hw/core/loader.c
-+++ b/docs/about/deprecated.rst
++++ b/hw/core/loader.c
-@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
+@@ -XXX,XX +XXX,XX @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
- However, short-form booleans are deprecated and full explicit ``arg_name=on``
+         if (is_linux) {
- form is preferred.
+             if (hdr->ih_os == IH_OS_LINUX) {
+                 *is_linux = 1;
-+``-drive if=none`` for the sifive_u OTP device (since 6.2)
++            } else if (hdr->ih_os == IH_OS_VXWORKS) {
-+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
++                /*
-+
++                 * VxWorks 7 uses the same boot interface as the Linux kernel
-+Using ``-drive if=none`` to configure the OTP device of the sifive_u
++                 * on Arm (64-bit only), PowerPC and RISC-V architectures.
-+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
++                 */
-+
++                switch (hdr->ih_arch) {
++                case IH_ARCH_ARM64:
- QEMU Machine Protocol (QMP) commands
++                case IH_ARCH_PPC:
- ------------------------------------
++                case IH_ARCH_RISCV:
-diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
++                    *is_linux = 1;
-index XXXXXXX..XXXXXXX 100644
++                    break;
---- a/hw/misc/sifive_u_otp.c
++                default:
-+++ b/hw/misc/sifive_u_otp.c
++                    *is_linux = 0;
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
++                    break;
-                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
++                }
-     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+             } else {
+                 *is_linux = 0;
--    dinfo = drive_get_next(IF_NONE);
+             }
 +    dinfo = drive_get_next(IF_PFLASH);
 +    if (!dinfo) {
 +        dinfo = drive_get_next(IF_NONE);
 +        if (dinfo) {
 +            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
 +                        "use \"-drive if=pflash\" instead.");
 +        }
 +    }
      if (dinfo) {
          int ret;
          uint64_t perm;
 --
-.31.1
+.35.3

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:

Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122

for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:

hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 6.2

- Deprecate IF_NONE for SiFive OTP
 - Don't reset SiFive OTP content

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset

Thomas Huth (1):
      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE

docs/about/deprecated.rst |  6 ++++++
 hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

From: Thomas Huth <thuth@redhat.com>

Configuring a drive with "if=none" is meant for creation of a backend
only, it should not get automatically assigned to a device frontend.
Use "if=pflash" for the One-Time-Programmable device instead (like
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).

Since the old way of configuring the device has already been published
with the previous QEMU versions, we cannot remove this immediately, but
have to deprecate it and support it for at least two more releases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211119102549.217755-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 6 ++++++
 hw/misc/sifive_u_otp.c    | 9 ++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
 However, short-form booleans are deprecated and full explicit ``arg_name=on``
 form is preferred.
 
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
+
 
 QEMU Machine Protocol (QMP) commands
 ------------------------------------
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 
-    dinfo = drive_get_next(IF_NONE);
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!dinfo) {
+        dinfo = drive_get_next(IF_NONE);
+        if (dinfo) {
+            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
+                        "use \"-drive if=pflash\" instead.");
+        }
+    }
     if (dinfo) {
         int ret;
         uint64_t perm;
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Once a "One Time Programmable" is programmed, it shouldn't be reset.

Do not re-initialize the OTP content in the DeviceReset handler,
initialize it once in the DeviceRealize one.

Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_u_otp.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
 
             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
                 error_setg(errp, "failed to read the initial flash content");
+                return;
             }
         }
     }
-}
-
-static void sifive_u_otp_reset(DeviceState *dev)
-{
-    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
 
     /* Initialize all fuses' initial value to 0xFFs */
     memset(s->fuse, 0xff, sizeof(s->fuse));
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
         serial_data = s->serial;
         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index);
+            error_setg(errp, "failed to write index<%d>", index);
+            return;
         }
 
         serial_data = ~(s->serial);
         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index + 1);
+            error_setg(errp, "failed to write index<%d>", index + 1);
+            return;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
 
     device_class_set_props(dc, sifive_u_otp_properties);
     dc->realize = sifive_u_otp_realize;
-    dc->reset = sifive_u_otp_reset;
 }
 
 static const TypeInfo sifive_u_otp_info = {
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:

Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220525

for you to fetch changes up to 8fe63fe8e512d77583d6798acd2164f1fa1e40ab:

hw/core: loader: Set is_linux to true for VxWorks uImage (2022-05-24 10:38:50 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.1

* Fixes for accessing VS hypervisor CSRs
 * Improvements for RISC-V Vector extension
 * Fixes for accessing mtimecmp
 * Add new short-isa-string CPU option
 * Improvements to RISC-V machine error handling
 * Disable the "G" extension by default internally, no functional change
 * Enforce floating point extension requirements
 * Cleanup ISA extension checks
 * Resolve redundant property accessors
 * Fix typo of mimpid cpu option
 * Improvements for virtulisation
 * Add zicsr/zifencei to isa_string
 * Support for VxWorks uImage

----------------------------------------------------------------
Anup Patel (4):
      target/riscv: Fix csr number based privilege checking
      target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
      target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
      hw/riscv: virt: Fix interrupt parent for dynamic platform devices

Atish Patra (1):
      hw/intc: Pass correct hartid while updating mtimecmp

Bernhard Beschow (2):
      hw/vfio/pci-quirks: Resolve redundant property getters
      hw/riscv/sifive_u: Resolve redundant property accessors

Bin Meng (2):
      hw/core: Sync uboot_image.h from U-Boot v2022.01
      hw/core: loader: Set is_linux to true for VxWorks uImage

Dylan Reid (1):
      target/riscv: Fix VS mode hypervisor CSR access

Frank Chang (1):
      target/riscv: Fix typo of mimpid cpu option

Hongren (Zenithal) Zheng (1):
      target/riscv: add zicsr/zifencei to isa_string

Tsukasa OI (9):
      target/riscv: Move Zhinx* extensions on ISA string
      target/riscv: Add short-isa-string option
      hw/riscv: Make CPU config error handling generous (virt/spike)
      hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
      target/riscv: Fix coding style on "G" expansion
      target/riscv: Disable "G" by default
      target/riscv: Change "G" expansion
      target/riscv: FP extension requirements
      target/riscv: Move/refactor ISA extension checks

Weiwei Li (1):
      target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

eopXD (1):
      target/riscv: rvv: Fix early exit condition for whole register load/store

From: Dylan Reid <dylan@rivosinc.com>

VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.

Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.

Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
 #if !defined(CONFIG_USER_ONLY)
     int effective_priv = env->priv;
 
-    if (riscv_has_ext(env, RVH) &&
-        env->priv == PRV_S &&
-        !riscv_cpu_virt_enabled(env)) {
+    if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
         /*
-         * We are in S mode without virtualisation, therefore we are in HS Mode.
+         * We are in either HS or VS mode.
          * Add 1 to the effective privledge level to allow us to access the
-         * Hypervisor CSRs.
+         * Hypervisor CSRs. The `hmode` predicate will determine if access
+         * should be allowed(HS) or if a virtual instruction exception should be
+         * raised(VS).
          */
         effective_priv++;
     }
-- 
2.35.3

From: eopXD <eop.chen@sifive.com>

Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++------------
 1 file changed, 31 insertions(+), 27 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
 typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
 
 static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
-                             gen_helper_ldst_whole *fn, DisasContext *s,
-                             bool is_store)
+                             uint32_t width, gen_helper_ldst_whole *fn,
+                             DisasContext *s, bool is_store)
 {
-    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
+    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
  * load and store whole register instructions ignore vtype and vl setting.
  * Thus, we don't need to check vill bit. (Section 7.9)
  */
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE)                      \
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE)               \
 static bool trans_##NAME(DisasContext *s, arg_##NAME * a)                 \
 {                                                                         \
     if (require_rvv(s) &&                                                 \
         QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                                 \
-        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
-                                s, IS_STORE);                             \
+        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH,             \
+                                gen_helper_##NAME, s, IS_STORE);          \
     }                                                                     \
     return false;                                                         \
 }
 
-GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, false)
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, false)
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, false)
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, false)
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
-
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
+GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, 1, false)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
+GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, 1, false)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
+GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, 1, false)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
+GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, 1, false)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
+
+/*
+ * The vector whole register store instructions are encoded similar to
+ * unmasked unit-stride store of elements with EEW=8.
+ */
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
 
 /*
  *** Vector Integer Arithmetic Instructions
-- 
2.35.3

From: Atish Patra <atishp@rivosinc.com>

timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.

Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aclint.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
                 continue;
             }
             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
-                                              i, env->timecmp);
+                                              mtimer->hartid_base + i,
+                                              env->timecmp);
         }
         return;
     }
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
         ISA_EDATA_ENTRY(zfh, ext_zfh),
         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
         ISA_EDATA_ENTRY(zdinx, ext_zdinx),
         ISA_EDATA_ENTRY(zba, ext_zba),
         ISA_EDATA_ENTRY(zbb, ext_zbb),
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
         ISA_EDATA_ENTRY(zkt, ext_zkt),
         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
         ISA_EDATA_ENTRY(svinval, ext_svinval),
         ISA_EDATA_ENTRY(svnapot, ext_svnapot),
         ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.

For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier) with FPU support caused a kernel panic.

Operating Systems which short-isa-string might be helpful:

1.  Linux (5.17 or earlier)
2.  FreeBSD (at least 14.0-CURRENT)
3.  OpenBSD (at least current development version)

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool aia;
     bool debug;
     uint64_t resetvec;
+
+    bool short_isa_string;
 };
 
 typedef struct RISCVCPUConfig RISCVCPUConfig;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
 
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+
+    DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
         }
     }
     *p = '\0';
-    riscv_isa_string_ext(cpu, &isa_str, maxlen);
+    if (!cpu->cfg.short_isa_string) {
+        riscv_isa_string_ext(cpu, &isa_str, maxlen);
+    }
     return isa_str;
 }
 
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
virt/spike machines.  It now just prints error message and quits (without
coredumps and aborts).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 2 +-
 hw/riscv/virt.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                 base_hartid, &error_abort);
         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
                                 hart_count, &error_abort);
-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
 
         /* Core Local Interruptor (timer and IPI) for each socket */
         riscv_aclint_swi_create(
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                 base_hartid, &error_abort);
         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
                                 hart_count, &error_abort);
-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
 
         if (!kvm_enabled()) {
             if (s->have_aclint) {
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines.  It now just prints error message and
quits (without coredumps and aborts).

This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 hw/riscv/sifive_e.c  | 2 +-
 hw/riscv/sifive_u.c  | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
     /* Boot ROM */
     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 
     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
                             &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
     /* Mask ROM */
     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
+    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
     /*
      * The cluster must be realized after the RISC-V hart array container,
      * as the container's CPU object is only created on realize, and the
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G".  Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     /* Defaults for standard extensions */
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
-    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
+    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.

This commit adds certain checks for consistent FP arithmetic:

-   F requires Zicsr
-   Zfinx requires Zicsr
-   Zfh/Zfhmin require F
-   D requires F
-   V requires D

Because F/D/Zicsr are enabled by default (and an error will not occur unless
we manually disable one or more of prerequisites), this commit just enforces
the user to give consistent combinations.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+
+        /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
             cpu->cfg.ext_zhinxmin) {
             cpu->cfg.ext_zfinx = true;
         }
 
-        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
-            error_setg(errp, "Zfinx extension requires Zicsr");
-            return;
+        if (cpu->cfg.ext_zfinx) {
+            if (!cpu->cfg.ext_icsr) {
+                error_setg(errp, "Zfinx extension requires Zicsr");
+                return;
+            }
+            if (cpu->cfg.ext_f) {
+                error_setg(errp,
+                    "Zfinx cannot be supported together with F extension");
+                return;
+            }
         }
 
         if (cpu->cfg.ext_zk) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_zksh = true;
         }
 
-        /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
             ext |= RVI;
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
-        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
-            return;
-        }
         if (cpu->cfg.ext_j) {
             ext |= RVJ;
         }
-        if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
-                                   cpu->cfg.ext_zfhmin)) {
-            error_setg(errp,
-                    "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
-                    " 'Zfhmin'");
-            return;
-        }
 
         set_misa(env, env->misa_mxl, ext);
     }
-- 
2.35.3

From: Bernhard Beschow <shentey@gmail.com>

The QOM API already provides getters for uint64 and uint32 values, so reuse
them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301225220.239065-2-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/vfio/pci-quirks.c | 34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -XXX,XX +XXX,XX @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
     return 0;
 }
 
-static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
-                                     const char *name,
-                                     void *opaque, Error **errp)
-{
-    uint64_t tgt = (uintptr_t) opaque;
-    visit_type_uint64(v, name, &tgt, errp);
-}
-
-static void vfio_pci_nvlink2_get_link_speed(Object *obj, Visitor *v,
-                                                 const char *name,
-                                                 void *opaque, Error **errp)
-{
-    uint32_t link_speed = (uint32_t)(uintptr_t) opaque;
-    visit_type_uint32(v, name, &link_speed, errp);
-}
-
 int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
 {
     int ret;
@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
                                nv2reg->size, p);
     QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
 
-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
-                        (void *) (uintptr_t) cap->tgt);
+    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
+                                   (uint64_t *) &cap->tgt,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvidia_gpu_setup_quirk(vdev->vbasedev.name, cap->tgt,
                                           nv2reg->size);
 free_exit:
@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp)
         QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
     }
 
-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
-                        (void *) (uintptr_t) captgt->tgt);
+    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
+                                   (uint64_t *) &captgt->tgt,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev->vbasedev.name, captgt->tgt,
                                               atsdreg->size);
 
-    object_property_add(OBJECT(vdev), "nvlink2-link-speed", "uint32",
-                        vfio_pci_nvlink2_get_link_speed, NULL, NULL,
-                        (void *) (uintptr_t) capspeed->link_speed);
+    object_property_add_uint32_ptr(OBJECT(vdev), "nvlink2-link-speed",
+                                   &capspeed->link_speed,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev->vbasedev.name,
                                               capspeed->link_speed);
 free_exit:
-- 
2.35.3

From: Bernhard Beschow <shentey@gmail.com>

The QOM API already provides accessors for uint32 values, so reuse them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220301225220.239065-3-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 24 ++++--------------------
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
     s->start_in_flash = value;
 }
 
-static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
-                                             const char *name, void *opaque,
-                                             Error **errp)
-{
-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
-static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
-                                             const char *name, void *opaque,
-                                             Error **errp)
-{
-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
 static void sifive_u_machine_instance_init(Object *obj)
 {
     SiFiveUState *s = RISCV_U_MACHINE(obj);
 
     s->start_in_flash = false;
     s->msel = 0;
-    object_property_add(obj, "msel", "uint32",
-                        sifive_u_machine_get_uint32_prop,
-                        sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+    object_property_add_uint32_ptr(obj, "msel", &s->msel,
+                                   OBJ_PROP_FLAG_READWRITE);
     object_property_set_description(obj, "msel",
                                     "Mode Select (MSEL[3:0]) pin state");
 
     s->serial = OTP_SERIAL;
-    object_property_add(obj, "serial", "uint32",
-                        sifive_u_machine_get_uint32_prop,
-                        sifive_u_machine_set_uint32_prop, NULL, &s->serial);
+    object_property_add_uint32_ptr(obj, "serial", &s->serial,
+                                   OBJ_PROP_FLAG_READWRITE);
     object_property_set_description(obj, "serial", "Board serial number");
 }
 
-- 
2.35.3

From: Weiwei Li <liweiwei@iscas.ac.cn>

- setting ext_g will implicitly set ext_i

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

"mimpid" cpu option was mistyped to "mipid".

Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 +-
 target/riscv/cpu.c | 4 ++--
 target/riscv/csr.c | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
 
     uint32_t mvendorid;
     uint64_t marchid;
-    uint64_t mipid;
+    uint64_t mimpid;
 
     /* Vendor-specific custom extensions */
     bool ext_XVentanaCondOps;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
                              (QEMU_VERSION_MINOR << 8)  | \
                              (QEMU_VERSION_MICRO))
-#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
+#define RISCV_CPU_MIMPID    RISCV_CPU_MARCHID
 
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
-    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
 
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_mipid(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+static RISCVException read_mimpid(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     CPUState *cs = env_cpu(env);
     RISCVCPU *cpu = RISCV_CPU(cs);
 
-    *val = cpu->cfg.mipid;
+    *val = cpu->cfg.mimpid;
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Machine Information Registers */
     [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
     [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
-    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
+    [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
 
     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.

Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     int read_only = get_field(csrno, 0xC00) == 3;
     int csr_min_priv = csr_ops[csrno].min_priv_ver;
 #if !defined(CONFIG_USER_ONLY)
-    int effective_priv = env->priv;
+    int csr_priv, effective_priv = env->priv;
 
     if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
         /*
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
         effective_priv++;
     }
 
-    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
+    csr_priv = get_field(csrno, 0x300);
+    if (!env->debugger && (effective_priv < csr_priv)) {
+        if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         case RISCV_EXCP_INST_PAGE_FAULT:
         case RISCV_EXCP_LOAD_PAGE_FAULT:
         case RISCV_EXCP_STORE_PAGE_FAULT:
-            write_gva = true;
+            write_gva = env->two_stage_lookup;
             tval = env->badaddr;
             break;
         case RISCV_EXCP_ILLEGAL_INST:
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 /* Trap into HS mode */
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
-                write_gva = false;
             }
             env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
         }
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.

In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM or hstatus.VTVM).

We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  8 +++++++-
 target/riscv/cpu.c        |  2 ++
 target/riscv/cpu_helper.c |  1 +
 target/riscv/translate.c  | 17 +++++++++++++----
 4 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 
 #define TCG_GUEST_DEFAULT_MO 0
 
+/*
+ * RISC-V-specific extra insn start words:
+ * 1: Original instruction opcode
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #define TYPE_RISCV_CPU "riscv-cpu"
 
 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
     target_ulong frm;
 
     target_ulong badaddr;
-    uint32_t bins;
+    target_ulong bins;
 
     target_ulong guest_phys_fault_addr;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
     } else {
         env->pc = data[0];
     }
+    env->bins = data[1];
 }
 
 static void riscv_cpu_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mcause = 0;
     env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
+    env->bins = 0;
     env->two_stage_lookup = false;
 
     /* Initialized default priorities of local interrupts. */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->badaddr;
             break;
         case RISCV_EXCP_ILLEGAL_INST:
+        case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
             tval = env->bins;
             break;
         default:
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* PointerMasking extension */
     bool pm_mask_enabled;
     bool pm_base_enabled;
+    /* TCG of the current insn_start */
+    TCGOp *insn_start;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
 
 static void gen_exception_illegal(DisasContext *ctx)
 {
-    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
-                   offsetof(CPURISCVState, bins));
-
     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 }
 
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 /* Include decoders for factored-out extensions */
 #include "decode-XVentanaCondOps.c.inc"
 
+static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
+{
+    assert(ctx->insn_start != NULL);
+    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
+    ctx->insn_start = NULL;
+}
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 
     /* Check for compressed insn */
     if (extract16(opcode, 0, 2) != 3) {
+        decode_save_opc(ctx, opcode);
         if (!has_ext(ctx, RVC)) {
             gen_exception_illegal(ctx);
         } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         opcode32 = deposit32(opcode32, 16, 16,
                              translator_lduw(env, &ctx->base,
                                              ctx->base.pc_next + 2));
+        decode_save_opc(ctx, opcode32);
         ctx->opcode = opcode32;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next);
+    tcg_gen_insn_start(ctx->base.pc_next, 0);
+    ctx->insn_start = tcg_last_op();
 }
 
 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.

In case of  multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.

Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
platform FDT entries")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
+    if (!socket) {
+        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+                                       memmap[VIRT_PLATFORM_BUS].base,
+                                       memmap[VIRT_PLATFORM_BUS].size,
+                                       VIRT_PLATFORM_BUS_IRQ);
+    }
 
     g_free(plic_name);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     }
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
-
     g_free(imsic_name);
 
     /* S-level IMSIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
+    if (!socket) {
+        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+                                       memmap[VIRT_PLATFORM_BUS].base,
+                                       memmap[VIRT_PLATFORM_BUS].size,
+                                       VIRT_PLATFORM_BUS_IRQ);
+    }
 
     g_free(aplic_name);
 
-- 
2.35.3

From: "Hongren (Zenithal) Zheng" <i@zenithal.me>

Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
      *    extensions by an underscore.
      */
     struct isa_ext_data isa_edata_arr[] = {
+        ISA_EDATA_ENTRY(zicsr, ext_icsr),
+        ISA_EDATA_ENTRY(zifencei, ext_ifencei),
         ISA_EDATA_ENTRY(zfh, ext_zfh),
         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-- 
2.35.3

From: Bin Meng <bin.meng@windriver.com>

Sync uboot_image.h from upstream U-Boot v2022.01 release [1].

[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/core/uboot_image.h | 213 ++++++++++++++++++++++++++++--------------
 1 file changed, 142 insertions(+), 71 deletions(-)

diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/uboot_image.h
+++ b/hw/core/uboot_image.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * (C) Copyright 2008 Semihalf
+ *
  * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
  ********************************************************************
  * NOTE: This header file defines an interface to U-Boot. Including
  * this (unmodified) header file in another file is considered normal
@@ -XXX,XX +XXX,XX @@
 
 /*
  * Operating System Codes
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_OS_INVALID		0	/* Invalid OS	*/
-#define IH_OS_OPENBSD		1	/* OpenBSD	*/
-#define IH_OS_NETBSD		2	/* NetBSD	*/
-#define IH_OS_FREEBSD		3	/* FreeBSD	*/
-#define IH_OS_4_4BSD		4	/* 4.4BSD	*/
-#define IH_OS_LINUX		5	/* Linux	*/
-#define IH_OS_SVR4		6	/* SVR4		*/
-#define IH_OS_ESIX		7	/* Esix		*/
-#define IH_OS_SOLARIS		8	/* Solaris	*/
-#define IH_OS_IRIX		9	/* Irix		*/
-#define IH_OS_SCO		10	/* SCO		*/
-#define IH_OS_DELL		11	/* Dell		*/
-#define IH_OS_NCR		12	/* NCR		*/
-#define IH_OS_LYNXOS		13	/* LynxOS	*/
-#define IH_OS_VXWORKS		14	/* VxWorks	*/
-#define IH_OS_PSOS		15	/* pSOS		*/
-#define IH_OS_QNX		16	/* QNX		*/
-#define IH_OS_U_BOOT		17	/* Firmware	*/
-#define IH_OS_RTEMS		18	/* RTEMS	*/
-#define IH_OS_ARTOS		19	/* ARTOS	*/
-#define IH_OS_UNITY		20	/* Unity OS	*/
+enum {
+	IH_OS_INVALID		= 0,	/* Invalid OS	*/
+	IH_OS_OPENBSD,			/* OpenBSD	*/
+	IH_OS_NETBSD,			/* NetBSD	*/
+	IH_OS_FREEBSD,			/* FreeBSD	*/
+	IH_OS_4_4BSD,			/* 4.4BSD	*/
+	IH_OS_LINUX,			/* Linux	*/
+	IH_OS_SVR4,			/* SVR4		*/
+	IH_OS_ESIX,			/* Esix		*/
+	IH_OS_SOLARIS,			/* Solaris	*/
+	IH_OS_IRIX,			/* Irix		*/
+	IH_OS_SCO,			/* SCO		*/
+	IH_OS_DELL,			/* Dell		*/
+	IH_OS_NCR,			/* NCR		*/
+	IH_OS_LYNXOS,			/* LynxOS	*/
+	IH_OS_VXWORKS,			/* VxWorks	*/
+	IH_OS_PSOS,			/* pSOS		*/
+	IH_OS_QNX,			/* QNX		*/
+	IH_OS_U_BOOT,			/* Firmware	*/
+	IH_OS_RTEMS,			/* RTEMS	*/
+	IH_OS_ARTOS,			/* ARTOS	*/
+	IH_OS_UNITY,			/* Unity OS	*/
+	IH_OS_INTEGRITY,		/* INTEGRITY	*/
+	IH_OS_OSE,			/* OSE		*/
+	IH_OS_PLAN9,			/* Plan 9	*/
+	IH_OS_OPENRTOS,		/* OpenRTOS	*/
+	IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
+	IH_OS_TEE,			/* Trusted Execution Environment */
+	IH_OS_OPENSBI,			/* RISC-V OpenSBI */
+	IH_OS_EFI,			/* EFI Firmware (e.g. GRUB2) */
+
+	IH_OS_COUNT,
+};
 
 /*
  * CPU Architecture Codes (supported by Linux)
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_CPU_INVALID		0	/* Invalid CPU	*/
-#define IH_CPU_ALPHA		1	/* Alpha	*/
-#define IH_CPU_ARM		2	/* ARM		*/
-#define IH_CPU_I386		3	/* Intel x86	*/
-#define IH_CPU_IA64		4	/* IA64		*/
-#define IH_CPU_MIPS		5	/* MIPS		*/
-#define IH_CPU_MIPS64		6	/* MIPS	 64 Bit */
-#define IH_CPU_PPC		7	/* PowerPC	*/
-#define IH_CPU_S390		8	/* IBM S390	*/
-#define IH_CPU_SH		9	/* SuperH	*/
-#define IH_CPU_SPARC		10	/* Sparc	*/
-#define IH_CPU_SPARC64		11	/* Sparc 64 Bit */
-#define IH_CPU_M68K		12	/* M68K		*/
-#define IH_CPU_NIOS		13	/* Nios-32	*/
-#define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
-#define IH_CPU_NIOS2		15	/* Nios-II	*/
-#define IH_CPU_BLACKFIN		16	/* Blackfin	*/
-#define IH_CPU_AVR32		17	/* AVR32	*/
+enum {
+	IH_ARCH_INVALID		= 0,	/* Invalid CPU	*/
+	IH_ARCH_ALPHA,			/* Alpha	*/
+	IH_ARCH_ARM,			/* ARM		*/
+	IH_ARCH_I386,			/* Intel x86	*/
+	IH_ARCH_IA64,			/* IA64		*/
+	IH_ARCH_MIPS,			/* MIPS		*/
+	IH_ARCH_MIPS64,			/* MIPS	 64 Bit */
+	IH_ARCH_PPC,			/* PowerPC	*/
+	IH_ARCH_S390,			/* IBM S390	*/
+	IH_ARCH_SH,			/* SuperH	*/
+	IH_ARCH_SPARC,			/* Sparc	*/
+	IH_ARCH_SPARC64,		/* Sparc 64 Bit */
+	IH_ARCH_M68K,			/* M68K		*/
+	IH_ARCH_NIOS,			/* Nios-32	*/
+	IH_ARCH_MICROBLAZE,		/* MicroBlaze   */
+	IH_ARCH_NIOS2,			/* Nios-II	*/
+	IH_ARCH_BLACKFIN,		/* Blackfin	*/
+	IH_ARCH_AVR32,			/* AVR32	*/
+	IH_ARCH_ST200,			/* STMicroelectronics ST200  */
+	IH_ARCH_SANDBOX,		/* Sandbox architecture (test only) */
+	IH_ARCH_NDS32,			/* ANDES Technology - NDS32  */
+	IH_ARCH_OPENRISC,		/* OpenRISC 1000  */
+	IH_ARCH_ARM64,			/* ARM64	*/
+	IH_ARCH_ARC,			/* Synopsys DesignWare ARC */
+	IH_ARCH_X86_64,			/* AMD x86_64, Intel and Via */
+	IH_ARCH_XTENSA,			/* Xtensa	*/
+	IH_ARCH_RISCV,			/* RISC-V */
+
+	IH_ARCH_COUNT,
+};
 
 /*
  * Image Types
@@ -XXX,XX +XXX,XX @@
  *	U-Boot's command interpreter; this feature is especially
  *	useful when you configure U-Boot to use a real shell (hush)
  *	as command interpreter (=> Shell Scripts).
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
 
-#define IH_TYPE_INVALID		0	/* Invalid Image		*/
-#define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
-#define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
-#define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
-#define IH_TYPE_MULTI		4	/* Multi-File Image		*/
-#define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
-#define IH_TYPE_SCRIPT		6	/* Script file			*/
-#define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
-#define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
-#define IH_TYPE_KERNEL_NOLOAD  14	/* OS Kernel Image (noload)	*/
+enum {
+	IH_TYPE_INVALID		= 0,	/* Invalid Image		*/
+	IH_TYPE_STANDALONE,		/* Standalone Program		*/
+	IH_TYPE_KERNEL,			/* OS Kernel Image		*/
+	IH_TYPE_RAMDISK,		/* RAMDisk Image		*/
+	IH_TYPE_MULTI,			/* Multi-File Image		*/
+	IH_TYPE_FIRMWARE,		/* Firmware Image		*/
+	IH_TYPE_SCRIPT,			/* Script file			*/
+	IH_TYPE_FILESYSTEM,		/* Filesystem Image (any type)	*/
+	IH_TYPE_FLATDT,			/* Binary Flat Device Tree Blob	*/
+	IH_TYPE_KWBIMAGE,		/* Kirkwood Boot Image		*/
+	IH_TYPE_IMXIMAGE,		/* Freescale IMXBoot Image	*/
+	IH_TYPE_UBLIMAGE,		/* Davinci UBL Image		*/
+	IH_TYPE_OMAPIMAGE,		/* TI OMAP Config Header Image	*/
+	IH_TYPE_AISIMAGE,		/* TI Davinci AIS Image		*/
+	/* OS Kernel Image, can run from any load address */
+	IH_TYPE_KERNEL_NOLOAD,
+	IH_TYPE_PBLIMAGE,		/* Freescale PBL Boot Image	*/
+	IH_TYPE_MXSIMAGE,		/* Freescale MXSBoot Image	*/
+	IH_TYPE_GPIMAGE,		/* TI Keystone GPHeader Image	*/
+	IH_TYPE_ATMELIMAGE,		/* ATMEL ROM bootable Image	*/
+	IH_TYPE_SOCFPGAIMAGE,		/* Altera SOCFPGA CV/AV Preloader */
+	IH_TYPE_X86_SETUP,		/* x86 setup.bin Image		*/
+	IH_TYPE_LPC32XXIMAGE,		/* x86 setup.bin Image		*/
+	IH_TYPE_LOADABLE,		/* A list of typeless images	*/
+	IH_TYPE_RKIMAGE,		/* Rockchip Boot Image		*/
+	IH_TYPE_RKSD,			/* Rockchip SD card		*/
+	IH_TYPE_RKSPI,			/* Rockchip SPI image		*/
+	IH_TYPE_ZYNQIMAGE,		/* Xilinx Zynq Boot Image */
+	IH_TYPE_ZYNQMPIMAGE,		/* Xilinx ZynqMP Boot Image */
+	IH_TYPE_ZYNQMPBIF,		/* Xilinx ZynqMP Boot Image (bif) */
+	IH_TYPE_FPGA,			/* FPGA Image */
+	IH_TYPE_VYBRIDIMAGE,	/* VYBRID .vyb Image */
+	IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
+	IH_TYPE_FIRMWARE_IVT,		/* Firmware Image with HABv4 IVT */
+	IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
+	IH_TYPE_STM32IMAGE,		/* STMicroelectronics STM32 Image */
+	IH_TYPE_SOCFPGAIMAGE_V1,	/* Altera SOCFPGA A10 Preloader	*/
+	IH_TYPE_MTKIMAGE,		/* MediaTek BootROM loadable Image */
+	IH_TYPE_IMX8MIMAGE,		/* Freescale IMX8MBoot Image	*/
+	IH_TYPE_IMX8IMAGE,		/* Freescale IMX8Boot Image	*/
+	IH_TYPE_COPRO,			/* Coprocessor Image for remoteproc*/
+	IH_TYPE_SUNXI_EGON,		/* Allwinner eGON Boot Image */
+
+	IH_TYPE_COUNT,			/* Number of image types */
+};
 
 /*
  * Compression Types
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_COMP_NONE		0	/*  No	 Compression Used	*/
-#define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
-#define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
+enum {
+	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
+	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
+	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
+	IH_COMP_LZMA,			/* lzma  Compression Used	*/
+	IH_COMP_LZO,			/* lzo   Compression Used	*/
+	IH_COMP_LZ4,			/* lz4   Compression Used	*/
+	IH_COMP_ZSTD,			/* zstd   Compression Used	*/
+
+	IH_COMP_COUNT,
+};
 
 #define IH_MAGIC	0x27051956	/* Image Magic Number		*/
 #define IH_NMLEN		32	/* Image Name Length		*/
 
 /*
- * all data in network byte order (aka natural aka bigendian)
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
  */
-
 typedef struct uboot_image_header {
 	uint32_t	ih_magic;	/* Image Header Magic Number	*/
 	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
-- 
2.35.3

From: Bin Meng <bin.meng@windriver.com>

VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/core/loader.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
         if (is_linux) {
             if (hdr->ih_os == IH_OS_LINUX) {
                 *is_linux = 1;
+            } else if (hdr->ih_os == IH_OS_VXWORKS) {
+                /*
+                 * VxWorks 7 uses the same boot interface as the Linux kernel
+                 * on Arm (64-bit only), PowerPC and RISC-V architectures.
+                 */
+                switch (hdr->ih_arch) {
+                case IH_ARCH_ARM64:
+                case IH_ARCH_PPC:
+                case IH_ARCH_RISCV:
+                    *is_linux = 1;
+                    break;
+                default:
+                    *is_linux = 0;
+                    break;
+                }
             } else {
                 *is_linux = 0;
             }
-- 
2.35.3