Series comparison

-[PULL 0/2] riscv-to-apply queue
+[PULL v3 00/42] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit e4f3ede95ce813d5705c65e1c0e1c80c70739ebb:
-The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
+  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' into staging (2021-05-10 19:55:06 +0100)
   Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210511
-for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
+for you to fetch changes up to c30a0757f094c107e491820e3d35224eb68859c7:
-  hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
+  target/riscv: Fix the RV64H decode comment (2021-05-11 20:02:07 +1000)
 ----------------------------------------------------------------
-Seventh RISC-V PR for QEMU 6.2
+A large collection of RISC-V fixes, improvements and features
- - Deprecate IF_NONE for SiFive OTP
+ - Clenaup some left over v1.9 code
- - Don't reset SiFive OTP content
+ - Documentation improvements
  - Support for the shakti_c machine
  - Internal cleanup of the CSR accesses
  - Updates to the OpenTitan platform
  - Support for the virtio-vga
  - Fix for the saturate subtract in vector extensions
  - Experimental support for the ePMP spec
  - A range of other internal code cleanups and bug fixes
 ----------------------------------------------------------------
-Philippe Mathieu-Daudé (1):
+Alexander Wagner (1):
-      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
+      hw/riscv: Fix OT IBEX reset vector
-Thomas Huth (1):
+Alistair Francis (22):
-      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
+      target/riscv: Convert the RISC-V exceptions to an enum
       target/riscv: Use the RISCVException enum for CSR predicates
       target/riscv: Fix 32-bit HS mode access permissions
       target/riscv: Use the RISCVException enum for CSR operations
       target/riscv: Use RISCVException enum for CSR access
       MAINTAINERS: Update the RISC-V CPU Maintainers
       hw/opentitan: Update the interrupt layout
       hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
       target/riscv: Fix the PMP is locked check when using TOR
       target/riscv: Add the ePMP feature
       target/riscv/pmp: Remove outdated comment
       target/riscv: Add ePMP support for the Ibex CPU
       target/riscv: Remove the hardcoded RVXLEN macro
       target/riscv: Remove the hardcoded SSTATUS_SD macro
       target/riscv: Remove the hardcoded HGATP_MODE macro
       target/riscv: Remove the hardcoded MSTATUS_SD macro
       target/riscv: Remove the hardcoded SATP_MODE macro
       target/riscv: Remove the unused HSTATUS_WPRI macro
       target/riscv: Remove an unused CASE_OP_32_64 macro
       target/riscv: Consolidate RV32/64 32-bit instructions
       target/riscv: Consolidate RV32/64 16-bit instructions
       target/riscv: Fix the RV64H decode comment
- docs/about/deprecated.rst |  6 ++++++
+Atish Patra (1):
- hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
+      target/riscv: Remove privilege v1.9 specific CSR related code
 files changed, 19 insertions(+), 9 deletions(-)
+Axel Heider (1):
+      docs/system/generic-loader.rst: Fix style
+Bin Meng (1):
+      hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
+Dylan Jhong (1):
+      target/riscv: Align the data type of reset vector address
+Emmanuel Blot (2):
+      target/riscv: fix exception index on instruction access fault
+      target/riscv: fix a typo with interrupt names
+Frank Chang (2):
+      target/riscv: fix vrgather macro index variable type bug
+      fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
+Hou Weiying (4):
+      target/riscv: Define ePMP mseccfg
+      target/riscv: Add ePMP CSR access functions
+      target/riscv: Implementation of enhanced PMP (ePMP)
+      target/riscv: Add a config option for ePMP
+Jade Fink (1):
+      riscv: don't look at SUM when accessing memory from a debugger context
+LIU Zhiwei (1):
+      target/riscv: Fixup saturate subtract function
+Vijai Kumar K (5):
+      target/riscv: Add Shakti C class CPU
+      riscv: Add initial support for Shakti C machine
+      hw/char: Add Shakti UART emulation
+      hw/riscv: Connect Shakti UART to Shakti platform
+      docs: Add documentation for shakti_c machine
+ docs/system/generic-loader.rst              |   9 +-
+ docs/system/riscv/shakti-c.rst              |  82 +++
+ docs/system/target-riscv.rst                |   1 +
+ default-configs/devices/riscv64-softmmu.mak |   1 +
+ include/hw/char/shakti_uart.h               |  74 +++
+ include/hw/riscv/opentitan.h                |  16 +-
+ include/hw/riscv/shakti_c.h                 |  75 +++
+ target/riscv/cpu.h                          |  42 +-
+ target/riscv/cpu_bits.h                     | 114 +---
+ target/riscv/helper.h                       |  18 +-
+ target/riscv/pmp.h                          |  14 +
+ target/riscv/insn16-32.decode               |  28 -
+ target/riscv/insn16-64.decode               |  36 --
+ target/riscv/insn16.decode                  |  30 +
+ target/riscv/insn32-64.decode               |  88 ---
+ target/riscv/insn32.decode                  |  67 ++-
+ hw/char/shakti_uart.c                       | 185 +++++++
+ hw/intc/ibex_plic.c                         |  20 +-
+ hw/riscv/opentitan.c                        |  10 +-
+ hw/riscv/shakti_c.c                         | 181 ++++++
+ hw/riscv/sifive_e.c                         |   2 +-
+ target/riscv/cpu.c                          |  26 +-
+ target/riscv/cpu_helper.c                   |  88 ++-
+ target/riscv/csr.c                          | 824 +++++++++++++++++-----------
+ target/riscv/fpu_helper.c                   |  16 +-
+ target/riscv/gdbstub.c                      |   8 +-
+ target/riscv/machine.c                      |   8 +-
+ target/riscv/monitor.c                      |  22 +-
+ target/riscv/op_helper.c                    |  18 +-
+ target/riscv/pmp.c                          | 218 +++++++-
+ target/riscv/translate.c                    |  38 +-
+ target/riscv/vector_helper.c                |  18 +-
+ fpu/softfloat-specialize.c.inc              |   6 +
+ target/riscv/insn_trans/trans_rva.c.inc     |  14 +-
+ target/riscv/insn_trans/trans_rvd.c.inc     |  17 +-
+ target/riscv/insn_trans/trans_rvf.c.inc     |   6 +-
+ target/riscv/insn_trans/trans_rvh.c.inc     |   8 +-
+ target/riscv/insn_trans/trans_rvi.c.inc     |  22 +-
+ target/riscv/insn_trans/trans_rvm.c.inc     |  12 +-
+ target/riscv/insn_trans/trans_rvv.c.inc     |  39 +-
+ MAINTAINERS                                 |  14 +-
+ hw/char/meson.build                         |   1 +
+ hw/char/trace-events                        |   4 +
+ hw/riscv/Kconfig                            |  11 +
+ hw/riscv/meson.build                        |   1 +
+ target/riscv/meson.build                    |  13 +-
+ target/riscv/trace-events                   |   3 +
+files changed, 1759 insertions(+), 789 deletions(-)
+ create mode 100644 docs/system/riscv/shakti-c.rst
+ create mode 100644 include/hw/char/shakti_uart.h
+ create mode 100644 include/hw/riscv/shakti_c.h
+ delete mode 100644 target/riscv/insn16-32.decode
+ delete mode 100644 target/riscv/insn16-64.decode
+ delete mode 100644 target/riscv/insn32-64.decode
+ create mode 100644 hw/char/shakti_uart.c
+ create mode 100644 hw/riscv/shakti_c.c

-New patch
+[PULL v3 01/42] target/riscv: Remove privilege v1.9 specific CSR related code
+From: Atish Patra <atish.patra@wdc.com>
 Qemu doesn't support RISC-V privilege specification v1.9. Remove the
 remaining v1.9 specific references from the implementation.
 Signed-off-by: Atish Patra <atish.patra@wdc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
 [Changes by AF:
  - Rebase on latest patches
  - Bump the vmstate_riscv_cpu version_id and minimum_version_id
  ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.h        |  4 +---
  target/riscv/cpu_bits.h   | 23 ---------------------
  target/riscv/cpu.c        |  2 +-
  target/riscv/cpu_helper.c | 12 +++++------
  target/riscv/csr.c        | 42 ++++++++++-----------------------------
  target/riscv/machine.c    |  8 +++-----
  target/riscv/translate.c  |  4 ++--
 files changed, 23 insertions(+), 72 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
      target_ulong mie;
      target_ulong mideleg;
 -    target_ulong sptbr;  /* until: priv-1.9.1 */
      target_ulong satp;   /* since: priv-1.10.0 */
 -    target_ulong sbadaddr;
 -    target_ulong mbadaddr;
 +    target_ulong stval;
      target_ulong medeleg;
      target_ulong stvec;
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
  /* 32-bit only */
  #define CSR_MSTATUSH        0x310
 -/* Legacy Counter Setup (priv v1.9.1) */
 -/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
 -#define CSR_MUCOUNTEREN     0x320
 -#define CSR_MSCOUNTEREN     0x321
 -#define CSR_MHCOUNTEREN     0x322
 -
  /* Machine Trap Handling */
  #define CSR_MSCRATCH        0x340
  #define CSR_MEPC            0x341
@@ -XXX,XX +XXX,XX @@
  #define CSR_MTVAL           0x343
  #define CSR_MIP             0x344
 -/* Legacy Machine Trap Handling (priv v1.9.1) */
 -#define CSR_MBADADDR        0x343
 -
  /* Supervisor Trap Setup */
  #define CSR_SSTATUS         0x100
  #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
  #define CSR_STVAL           0x143
  #define CSR_SIP             0x144
 -/* Legacy Supervisor Trap Handling (priv v1.9.1) */
 -#define CSR_SBADADDR        0x143
 -
  /* Supervisor Protection and Translation */
  #define CSR_SPTBR           0x180
  #define CSR_SATP            0x180
@@ -XXX,XX +XXX,XX @@
  #define CSR_MHPMCOUNTER30H  0xb9e
  #define CSR_MHPMCOUNTER31H  0xb9f
 -/* Legacy Machine Protection and Translation (priv v1.9.1) */
 -#define CSR_MBASE           0x380
 -#define CSR_MBOUND          0x381
 -#define CSR_MIBASE          0x382
 -#define CSR_MIBOUND         0x383
 -#define CSR_MDBASE          0x384
 -#define CSR_MDBOUND         0x385
 -
  /* mstatus CSR bits */
  #define MSTATUS_UIE         0x00000001
  #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@
  #define MSTATUS_FS          0x00006000
  #define MSTATUS_XS          0x00018000
  #define MSTATUS_MPRV        0x00020000
 -#define MSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
  #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
  #define MSTATUS_MXR         0x00080000
 -#define MSTATUS_VM          0x1F000000 /* until: priv-1.9.1 */
  #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
  #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
  #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
@@ -XXX,XX +XXX,XX @@
  #define SSTATUS_SPP         0x00000100
  #define SSTATUS_FS          0x00006000
  #define SSTATUS_XS          0x00018000
 -#define SSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
  #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
  #define SSTATUS_MXR         0x00080000
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
          qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
      }
      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 +    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
      if (riscv_has_ext(env, RVH)) {
          qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
          qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
          env->vscause = env->scause;
          env->scause = env->scause_hs;
 -        env->vstval = env->sbadaddr;
 -        env->sbadaddr = env->stval_hs;
 +        env->vstval = env->stval;
 +        env->stval = env->stval_hs;
          env->vsatp = env->satp;
          env->satp = env->satp_hs;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
          env->scause_hs = env->scause;
          env->scause = env->vscause;
 -        env->stval_hs = env->sbadaddr;
 -        env->sbadaddr = env->vstval;
 +        env->stval_hs = env->stval;
 +        env->stval = env->vstval;
          env->satp_hs = env->satp;
          env->satp = env->vsatp;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          env->mstatus = s;
          env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
          env->sepc = env->pc;
 -        env->sbadaddr = tval;
 +        env->stval = tval;
          env->htval = htval;
          env->pc = (env->stvec >> 2 << 2) +
              ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          env->mstatus = s;
          env->mcause = cause | ~(((target_ulong)-1) >> async);
          env->mepc = env->pc;
 -        env->mbadaddr = tval;
 +        env->mtval = tval;
          env->mtval2 = mtval2;
          env->pc = (env->mtvec >> 2 << 2) +
              ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 -static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 -{
 -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 -    }
 -    *val = env->mcounteren;
 -    return 0;
 -}
 -
 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 -static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 -{
 -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 -    }
 -    env->mcounteren = val;
 -    return 0;
 -}
 -
  /* Machine Trap Handling */
  static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
  {
@@ -XXX,XX +XXX,XX @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 +static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
  {
 -    *val = env->mbadaddr;
 +    *val = env->mtval;
      return 0;
  }
 -static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    env->mbadaddr = val;
 +    env->mtval = val;
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 +static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
  {
 -    *val = env->sbadaddr;
 +    *val = env->stval;
      return 0;
  }
 -static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    env->sbadaddr = val;
 +    env->stval = val;
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
 -    [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
 -
      /* Machine Trap Handling */
      [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
      [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
      [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
 -    [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
 +    [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
      [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
      /* Supervisor Trap Setup */
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
      [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
      [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
 -    [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
 +    [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
      [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
      /* Supervisor Protection and Translation */
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINT32(env.miclaim, RISCVCPU),
          VMSTATE_UINTTL(env.mie, RISCVCPU),
          VMSTATE_UINTTL(env.mideleg, RISCVCPU),
 -        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
          VMSTATE_UINTTL(env.satp, RISCVCPU),
 -        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
 -        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
 +        VMSTATE_UINTTL(env.stval, RISCVCPU),
          VMSTATE_UINTTL(env.medeleg, RISCVCPU),
          VMSTATE_UINTTL(env.stvec, RISCVCPU),
          VMSTATE_UINTTL(env.sepc, RISCVCPU),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
 -static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
 +static void generate_exception_mtval(DisasContext *ctx, int excp)
  {
      tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
      tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
  static void gen_exception_inst_addr_mis(DisasContext *ctx)
  {
 -    generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
 +    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
  }
  static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 --
 .31.1

-New patch
+[PULL v3 02/42] docs/system/generic-loader.rst: Fix style
+From: Axel Heider <axelheider@gmx.de>
+Fix style to have a proper description of the parameter 'force-raw'.
+Signed-off-by: Axel Heider <axelheider@gmx.de>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ docs/system/generic-loader.rst | 9 ++++++---
+file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/generic-loader.rst
++++ b/docs/system/generic-loader.rst
+@@ -XXX,XX +XXX,XX @@ shown below:
+   specified in the executable format header. This option should only
+   be used for the boot image. This will also cause the image to be
+   written to the specified CPU's address space. If not specified, the
+-  default is CPU 0. <force-raw> - Setting force-raw=on forces the file
+-  to be treated as a raw image. This can be used to load supported
+-  executable formats as if they were raw.
++  default is CPU 0.
++
++``<force-raw>``
++  Setting 'force-raw=on' forces the file to be treated as a raw image.
++  This can be used to load supported executable formats as if they
++  were raw.
+ All values are parsed using the standard QemuOpts parsing. This allows the user
+ to specify any values in any format supported. By default the values
+--
+.31.1

-New patch
+[PULL v3 03/42] target/riscv: Align the data type of reset vector address
+From: Dylan Jhong <dylan@andestech.com>
+Use target_ulong to instead of uint64_t on reset vector address
+to adapt on both 32/64 machine.
+Signed-off-by: Dylan Jhong <dylan@andestech.com>
+Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210329034801.22667-1-dylan@andestech.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void set_feature(CPURISCVState *env, int feature)
+     env->features |= (1ULL << feature);
+ }
+-static void set_resetvec(CPURISCVState *env, int resetvec)
++static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
+ {
+ #ifndef CONFIG_USER_ONLY
+     env->resetvec = resetvec;
+--
+.31.1

-New patch
+[PULL v3 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
+From: Bin Meng <bmeng.cn@gmail.com>
+This was accidentally dropped before. Add it back.
+Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
+Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/sifive_e.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_e.c
++++ b/hw/riscv/sifive_e.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/arch_init.h"
+ #include "sysemu/sysemu.h"
+-static MemMapEntry sifive_e_memmap[] = {
++static const MemMapEntry sifive_e_memmap[] = {
+     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
+     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
+     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
+--
+.31.1

-New patch
+[PULL v3 05/42] target/riscv: Add Shakti C class CPU
+From: Vijai Kumar K <vijai@behindbytes.com>
+C-Class is a member of the SHAKTI family of processors from IIT-M.
+It is an extremely configurable and commercial-grade 5-stage in-order
+core supporting the standard RV64GCSUN ISA extensions.
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210401181457.73039-2-vijai@behindbytes.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 1 +
+ target/riscv/cpu.c | 1 +
+files changed, 2 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
+ #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
+ #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
++#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
+ #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
+ #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
+ #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
+     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
+     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
+     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
++    DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
+ #endif
+ };
+--
+.31.1

-New patch
+[PULL v3 06/42] riscv: Add initial support for Shakti C machine
+From: Vijai Kumar K <vijai@behindbytes.com>
 Add support for emulating Shakti reference platform based on C-class
 running on arty-100T board.
 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
 Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210401181457.73039-3-vijai@behindbytes.com
 [Changes by AF:
  - Check for mstate->firmware before loading it
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  default-configs/devices/riscv64-softmmu.mak |   1 +
  include/hw/riscv/shakti_c.h                 |  73 +++++++++
  hw/riscv/shakti_c.c                         | 173 ++++++++++++++++++++
  MAINTAINERS                                 |   7 +
  hw/riscv/Kconfig                            |  10 ++
  hw/riscv/meson.build                        |   1 +
 files changed, 265 insertions(+)
  create mode 100644 include/hw/riscv/shakti_c.h
  create mode 100644 hw/riscv/shakti_c.c
 diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/devices/riscv64-softmmu.mak
 +++ b/default-configs/devices/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SIFIVE_E=y
  CONFIG_SIFIVE_U=y
  CONFIG_RISCV_VIRT=y
  CONFIG_MICROCHIP_PFSOC=y
 +CONFIG_SHAKTI_C=y
 diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Shakti C-class SoC emulation
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef HW_SHAKTI_H
 +#define HW_SHAKTI_H
 +
 +#include "hw/riscv/riscv_hart.h"
 +#include "hw/boards.h"
 +
 +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
 +#define RISCV_SHAKTI_SOC(obj) \
 +    OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
 +
 +typedef struct ShaktiCSoCState {
 +    /*< private >*/
 +    DeviceState parent_obj;
 +
 +    /*< public >*/
 +    RISCVHartArrayState cpus;
 +    DeviceState *plic;
 +    MemoryRegion rom;
 +
 +} ShaktiCSoCState;
 +
 +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
 +#define RISCV_SHAKTI_MACHINE(obj) \
 +    OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
 +typedef struct ShaktiCMachineState {
 +    /*< private >*/
 +    MachineState parent_obj;
 +
 +    /*< public >*/
 +    ShaktiCSoCState soc;
 +} ShaktiCMachineState;
 +
 +enum {
 +    SHAKTI_C_ROM,
 +    SHAKTI_C_RAM,
 +    SHAKTI_C_UART,
 +    SHAKTI_C_GPIO,
 +    SHAKTI_C_PLIC,
 +    SHAKTI_C_CLINT,
 +    SHAKTI_C_I2C,
 +};
 +
 +#define SHAKTI_C_PLIC_HART_CONFIG "MS"
 +/* Including Interrupt ID 0 (no interrupt)*/
 +#define SHAKTI_C_PLIC_NUM_SOURCES 28
 +/* Excluding Priority 0 */
 +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
 +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
 +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
 +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
 +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
 +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
 +
 +#endif
 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Shakti C-class SoC emulation
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/boards.h"
 +#include "hw/riscv/shakti_c.h"
 +#include "qapi/error.h"
 +#include "hw/intc/sifive_plic.h"
 +#include "hw/intc/sifive_clint.h"
 +#include "sysemu/sysemu.h"
 +#include "hw/qdev-properties.h"
 +#include "exec/address-spaces.h"
 +#include "hw/riscv/boot.h"
 +
 +
 +static const struct MemmapEntry {
 +    hwaddr base;
 +    hwaddr size;
 +} shakti_c_memmap[] = {
 +    [SHAKTI_C_ROM]   =  {  0x00001000,  0x2000   },
 +    [SHAKTI_C_RAM]   =  {  0x80000000,  0x0      },
 +    [SHAKTI_C_UART]  =  {  0x00011300,  0x00040  },
 +    [SHAKTI_C_GPIO]  =  {  0x020d0000,  0x00100  },
 +    [SHAKTI_C_PLIC]  =  {  0x0c000000,  0x20000  },
 +    [SHAKTI_C_CLINT] =  {  0x02000000,  0xc0000  },
 +    [SHAKTI_C_I2C]   =  {  0x20c00000,  0x00100  },
 +};
 +
 +static void shakti_c_machine_state_init(MachineState *mstate)
 +{
 +    ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +
 +    /* Allow only Shakti C CPU for this platform */
 +    if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
 +        error_report("This board can only be used with Shakti C CPU");
 +        exit(1);
 +    }
 +
 +    /* Initialize SoC */
 +    object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
 +                            TYPE_RISCV_SHAKTI_SOC);
 +    qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
 +
 +    /* register RAM */
 +    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
 +                           mstate->ram_size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                shakti_c_memmap[SHAKTI_C_RAM].base,
 +                                main_mem);
 +
 +    /* ROM reset vector */
 +    riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
 +                              shakti_c_memmap[SHAKTI_C_RAM].base,
 +                              shakti_c_memmap[SHAKTI_C_ROM].base,
 +                              shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
 +                              NULL);
 +    if (mstate->firmware) {
 +        riscv_load_firmware(mstate->firmware,
 +                            shakti_c_memmap[SHAKTI_C_RAM].base,
 +                            NULL);
 +    }
 +}
 +
 +static void shakti_c_machine_instance_init(Object *obj)
 +{
 +}
 +
 +static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(klass);
 +    mc->desc = "RISC-V Board compatible with Shakti SDK";
 +    mc->init = shakti_c_machine_state_init;
 +    mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
 +}
 +
 +static const TypeInfo shakti_c_machine_type_info = {
 +    .name = TYPE_RISCV_SHAKTI_MACHINE,
 +    .parent = TYPE_MACHINE,
 +    .class_init = shakti_c_machine_class_init,
 +    .instance_init = shakti_c_machine_instance_init,
 +    .instance_size = sizeof(ShaktiCMachineState),
 +};
 +
 +static void shakti_c_machine_type_info_register(void)
 +{
 +    type_register_static(&shakti_c_machine_type_info);
 +}
 +type_init(shakti_c_machine_type_info_register)
 +
 +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
 +{
 +    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
 +    MemoryRegion *system_memory = get_system_memory();
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
 +
 +    sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
 +        (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
 +        SHAKTI_C_PLIC_NUM_SOURCES,
 +        SHAKTI_C_PLIC_NUM_PRIORITIES,
 +        SHAKTI_C_PLIC_PRIORITY_BASE,
 +        SHAKTI_C_PLIC_PENDING_BASE,
 +        SHAKTI_C_PLIC_ENABLE_BASE,
 +        SHAKTI_C_PLIC_ENABLE_STRIDE,
 +        SHAKTI_C_PLIC_CONTEXT_BASE,
 +        SHAKTI_C_PLIC_CONTEXT_STRIDE,
 +        shakti_c_memmap[SHAKTI_C_PLIC].size);
 +
 +    sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
 +        shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
 +        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 +        SIFIVE_CLINT_TIMEBASE_FREQ, false);
 +
 +    /* ROM */
 +    memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
 +                           shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +        shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
 +}
 +
 +static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->realize = shakti_c_soc_state_realize;
 +}
 +
 +static void shakti_c_soc_instance_init(Object *obj)
 +{
 +    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
 +
 +    object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
 +
 +    /*
 +     * CPU type is fixed and we are not supporting passing from commandline yet.
 +     * So let it be in instance_init. When supported should use ms->cpu_type
 +     * instead of TYPE_RISCV_CPU_SHAKTI_C
 +     */
 +    object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
 +                            TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
 +    object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
 +                            &error_abort);
 +}
 +
 +static const TypeInfo shakti_c_type_info = {
 +    .name = TYPE_RISCV_SHAKTI_SOC,
 +    .parent = TYPE_DEVICE,
 +    .class_init = shakti_c_soc_class_init,
 +    .instance_init = shakti_c_soc_instance_init,
 +    .instance_size = sizeof(ShaktiCSoCState),
 +};
 +
 +static void shakti_c_type_info_register(void)
 +{
 +    type_register_static(&shakti_c_type_info);
 +}
 +type_init(shakti_c_type_info_register)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_dmc.h
  F: include/hw/misc/mchp_pfsoc_ioscb.h
  F: include/hw/misc/mchp_pfsoc_sysreg.h
 +Shakti C class SoC
 +M: Vijai Kumar K <vijai@behindbytes.com>
 +L: qemu-riscv@nongnu.org
 +S: Supported
 +F: hw/riscv/shakti_c.c
 +F: include/hw/riscv/shakti_c.h
 +
  SiFive Machines
  M: Alistair Francis <Alistair.Francis@wdc.com>
  M: Bin Meng <bin.meng@windriver.com>
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
      select IBEX
      select UNIMP
 +config SHAKTI
 +    bool
 +
 +config SHAKTI_C
 +    bool
 +    select UNIMP
 +    select SHAKTI
 +    select SIFIVE_CLINT
 +    select SIFIVE_PLIC
 +
  config RISCV_VIRT
      bool
      imply PCI_DEVICES
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 --
 .31.1

-New patch
+[PULL v3 07/42] hw/char: Add Shakti UART emulation
+From: Vijai Kumar K <vijai@behindbytes.com>
 This is the initial implementation of Shakti UART.
 Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210401181457.73039-4-vijai@behindbytes.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/char/shakti_uart.h |  74 ++++++++++++++
  hw/char/shakti_uart.c         | 185 ++++++++++++++++++++++++++++++++++
  MAINTAINERS                   |   2 +
  hw/char/meson.build           |   1 +
  hw/char/trace-events          |   4 +
 files changed, 266 insertions(+)
  create mode 100644 include/hw/char/shakti_uart.h
  create mode 100644 hw/char/shakti_uart.c
 diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/char/shakti_uart.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SHAKTI UART
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_SHAKTI_UART_H
 +#define HW_SHAKTI_UART_H
 +
 +#include "hw/sysbus.h"
 +#include "chardev/char-fe.h"
 +
 +#define SHAKTI_UART_BAUD        0x00
 +#define SHAKTI_UART_TX          0x04
 +#define SHAKTI_UART_RX          0x08
 +#define SHAKTI_UART_STATUS      0x0C
 +#define SHAKTI_UART_DELAY       0x10
 +#define SHAKTI_UART_CONTROL     0x14
 +#define SHAKTI_UART_INT_EN      0x18
 +#define SHAKTI_UART_IQ_CYCLES   0x1C
 +#define SHAKTI_UART_RX_THRES    0x20
 +
 +#define SHAKTI_UART_STATUS_TX_EMPTY     (1 << 0)
 +#define SHAKTI_UART_STATUS_TX_FULL      (1 << 1)
 +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
 +#define SHAKTI_UART_STATUS_RX_FULL      (1 << 3)
 +/* 9600 8N1 is the default setting */
 +/* Reg value = (50000000 Hz)/(16 * 9600)*/
 +#define SHAKTI_UART_BAUD_DEFAULT    0x0145
 +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
 +
 +#define TYPE_SHAKTI_UART "shakti-uart"
 +#define SHAKTI_UART(obj) \
 +    OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
 +
 +typedef struct {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion mmio;
 +
 +    uint32_t uart_baud;
 +    uint32_t uart_tx;
 +    uint32_t uart_rx;
 +    uint32_t uart_status;
 +    uint32_t uart_delay;
 +    uint32_t uart_control;
 +    uint32_t uart_interrupt;
 +    uint32_t uart_iq_cycles;
 +    uint32_t uart_rx_threshold;
 +
 +    CharBackend chr;
 +} ShaktiUartState;
 +
 +#endif /* HW_SHAKTI_UART_H */
 diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/char/shakti_uart.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SHAKTI UART
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/char/shakti_uart.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/qdev-properties-system.h"
 +#include "qemu/log.h"
 +
 +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    switch (addr) {
 +    case SHAKTI_UART_BAUD:
 +        return s->uart_baud;
 +    case SHAKTI_UART_RX:
 +        qemu_chr_fe_accept_input(&s->chr);
 +        s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
 +        return s->uart_rx;
 +    case SHAKTI_UART_STATUS:
 +        return s->uart_status;
 +    case SHAKTI_UART_DELAY:
 +        return s->uart_delay;
 +    case SHAKTI_UART_CONTROL:
 +        return s->uart_control;
 +    case SHAKTI_UART_INT_EN:
 +        return s->uart_interrupt;
 +    case SHAKTI_UART_IQ_CYCLES:
 +        return s->uart_iq_cycles;
 +    case SHAKTI_UART_RX_THRES:
 +        return s->uart_rx_threshold;
 +    default:
 +        /* Also handles TX REG which is write only */
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +
 +    return 0;
 +}
 +
 +static void shakti_uart_write(void *opaque, hwaddr addr,
 +                              uint64_t data, unsigned size)
 +{
 +    ShaktiUartState *s = opaque;
 +    uint32_t value = data;
 +    uint8_t ch;
 +
 +    switch (addr) {
 +    case SHAKTI_UART_BAUD:
 +        s->uart_baud = value;
 +        break;
 +    case SHAKTI_UART_TX:
 +        ch = value;
 +        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 +        s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
 +        break;
 +    case SHAKTI_UART_STATUS:
 +        s->uart_status = value;
 +        break;
 +    case SHAKTI_UART_DELAY:
 +        s->uart_delay = value;
 +        break;
 +    case SHAKTI_UART_CONTROL:
 +        s->uart_control = value;
 +        break;
 +    case SHAKTI_UART_INT_EN:
 +        s->uart_interrupt = value;
 +        break;
 +    case SHAKTI_UART_IQ_CYCLES:
 +        s->uart_iq_cycles = value;
 +        break;
 +    case SHAKTI_UART_RX_THRES:
 +        s->uart_rx_threshold = value;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +}
 +
 +static const MemoryRegionOps shakti_uart_ops = {
 +    .read = shakti_uart_read,
 +    .write = shakti_uart_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl = {.min_access_size = 1, .max_access_size = 4},
 +    .valid = {.min_access_size = 1, .max_access_size = 4},
 +};
 +
 +static void shakti_uart_reset(DeviceState *dev)
 +{
 +    ShaktiUartState *s = SHAKTI_UART(dev);
 +
 +    s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
 +    s->uart_tx = 0x0;
 +    s->uart_rx = 0x0;
 +    s->uart_status = 0x0000;
 +    s->uart_delay = 0x0000;
 +    s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
 +    s->uart_interrupt = 0x0000;
 +    s->uart_iq_cycles = 0x00;
 +    s->uart_rx_threshold = 0x00;
 +}
 +
 +static int shakti_uart_can_receive(void *opaque)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
 +}
 +
 +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    s->uart_rx = *buf;
 +    s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
 +}
 +
 +static void shakti_uart_realize(DeviceState *dev, Error **errp)
 +{
 +    ShaktiUartState *sus = SHAKTI_UART(dev);
 +    qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
 +                             shakti_uart_receive, NULL, NULL, sus, NULL, true);
 +}
 +
 +static void shakti_uart_instance_init(Object *obj)
 +{
 +    ShaktiUartState *sus = SHAKTI_UART(obj);
 +    memory_region_init_io(&sus->mmio,
 +                          obj,
 +                          &shakti_uart_ops,
 +                          sus,
 +                          TYPE_SHAKTI_UART,
 +                          0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
 +}
 +
 +static Property shakti_uart_properties[] = {
 +    DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void shakti_uart_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->reset = shakti_uart_reset;
 +    dc->realize = shakti_uart_realize;
 +    device_class_set_props(dc, shakti_uart_properties);
 +}
 +
 +static const TypeInfo shakti_uart_info = {
 +    .name = TYPE_SHAKTI_UART,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(ShaktiUartState),
 +    .class_init = shakti_uart_class_init,
 +    .instance_init = shakti_uart_instance_init,
 +};
 +
 +static void shakti_uart_register_types(void)
 +{
 +    type_register_static(&shakti_uart_info);
 +}
 +type_init(shakti_uart_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Vijai Kumar K <vijai@behindbytes.com>
  L: qemu-riscv@nongnu.org
  S: Supported
  F: hw/riscv/shakti_c.c
 +F: hw/char/shakti_uart.c
  F: include/hw/riscv/shakti_c.h
 +F: include/hw/char/shakti_uart.h
  SiFive Machines
  M: Alistair Francis <Alistair.Francis@wdc.com>
 diff --git a/hw/char/meson.build b/hw/char/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/meson.build
 +++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
  softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
  softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
  softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
 +softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
  softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
  softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
  softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
 diff --git a/hw/char/trace-events b/hw/char/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/trace-events
 +++ b/hw/char/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
  nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
  nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 +# shakti_uart.c
 +shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
 +shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 +
  # exynos4210_uart.c
  exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
  exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
 --
 .31.1

-New patch
+[PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform
+From: Vijai Kumar K <vijai@behindbytes.com>
+Connect one shakti uart to the shakti_c machine.
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210401181457.73039-5-vijai@behindbytes.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/shakti_c.h | 2 ++
+ hw/riscv/shakti_c.c         | 8 ++++++++
+files changed, 10 insertions(+)
+diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/shakti_c.h
++++ b/include/hw/riscv/shakti_c.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/riscv/riscv_hart.h"
+ #include "hw/boards.h"
++#include "hw/char/shakti_uart.h"
+ #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+ #define RISCV_SHAKTI_SOC(obj) \
+@@ -XXX,XX +XXX,XX @@ typedef struct ShaktiCSoCState {
+     /*< public >*/
+     RISCVHartArrayState cpus;
+     DeviceState *plic;
++    ShaktiUartState uart;
+     MemoryRegion rom;
+ } ShaktiCSoCState;
+diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/shakti_c.c
++++ b/hw/riscv/shakti_c.c
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+         SIFIVE_CLINT_TIMEBASE_FREQ, false);
++    qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
++    if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
++        return;
++    }
++    sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
++                    shakti_c_memmap[SHAKTI_C_UART].base);
++
+     /* ROM */
+     memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+                            shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_instance_init(Object *obj)
+     ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+     object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
++    object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
+     /*
+      * CPU type is fixed and we are not supporting passing from commandline yet.
+--
+.31.1

-New patch
+[PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h   | 44 ++++++++++++++++++++-------------------
+ target/riscv/cpu.c        |  2 +-
+ target/riscv/cpu_helper.c |  4 ++--
+files changed, 26 insertions(+), 24 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define DEFAULT_RSTVEC      0x1000
+ /* Exception causes */
+-#define EXCP_NONE                                -1 /* sentinel value */
+-#define RISCV_EXCP_INST_ADDR_MIS                 0x0
+-#define RISCV_EXCP_INST_ACCESS_FAULT             0x1
+-#define RISCV_EXCP_ILLEGAL_INST                  0x2
+-#define RISCV_EXCP_BREAKPOINT                    0x3
+-#define RISCV_EXCP_LOAD_ADDR_MIS                 0x4
+-#define RISCV_EXCP_LOAD_ACCESS_FAULT             0x5
+-#define RISCV_EXCP_STORE_AMO_ADDR_MIS            0x6
+-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT        0x7
+-#define RISCV_EXCP_U_ECALL                       0x8
+-#define RISCV_EXCP_S_ECALL                      0x9
+-#define RISCV_EXCP_VS_ECALL                      0xa
+-#define RISCV_EXCP_M_ECALL                       0xb
+-#define RISCV_EXCP_INST_PAGE_FAULT               0xc /* since: priv-1.10.0 */
+-#define RISCV_EXCP_LOAD_PAGE_FAULT               0xd /* since: priv-1.10.0 */
+-#define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
+-#define RISCV_EXCP_SEMIHOST                      0x10
+-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
+-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
+-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
+-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
++typedef enum RISCVException {
++    RISCV_EXCP_NONE = -1, /* sentinel value */
++    RISCV_EXCP_INST_ADDR_MIS = 0x0,
++    RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
++    RISCV_EXCP_ILLEGAL_INST = 0x2,
++    RISCV_EXCP_BREAKPOINT = 0x3,
++    RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
++    RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
++    RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
++    RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
++    RISCV_EXCP_U_ECALL = 0x8,
++    RISCV_EXCP_S_ECALL = 0x9,
++    RISCV_EXCP_VS_ECALL = 0xa,
++    RISCV_EXCP_M_ECALL = 0xb,
++    RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
++    RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
++    RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
++    RISCV_EXCP_SEMIHOST = 0x10,
++    RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
++    RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
++    RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
++    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
++} RISCVException;
+ #define RISCV_EXCP_INT_FLAG                0x80000000
+ #define RISCV_EXCP_INT_MASK                0x7fffffff
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+     env->pc = env->resetvec;
+     env->two_stage_lookup = false;
+ #endif
+-    cs->exception_index = EXCP_NONE;
++    cs->exception_index = RISCV_EXCP_NONE;
+     env->load_res = -1;
+     set_default_nan_mode(1, &env->fp_status);
+ }
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
+     if (irqs) {
+         return ctz64(irqs); /* since non-zero */
+     } else {
+-        return EXCP_NONE; /* indicates no pending interrupt */
++        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
+     }
+ }
+ #endif
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+     env->two_stage_lookup = false;
+ #endif
+-    cs->exception_index = EXCP_NONE; /* mark handled to qemu */
++    cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
+ }
+--
+.31.1

-New patch
+[PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.h |  3 +-
+ target/riscv/csr.c | 80 +++++++++++++++++++++++++---------------------
+files changed, 46 insertions(+), 37 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
+     return val;
+ }
+-typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
++typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
++                                                 int csrno);
+ typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+     target_ulong *ret_value);
+ typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
+ }
+ /* Predicates */
+-static int fs(CPURISCVState *env, int csrno)
++static RISCVException fs(CPURISCVState *env, int csrno)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     /* loose check condition for fcsr in vector extension */
+     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int vs(CPURISCVState *env, int csrno)
++static RISCVException vs(CPURISCVState *env, int csrno)
+ {
+     if (env->misa & RVV) {
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+-    return -RISCV_EXCP_ILLEGAL_INST;
++    return RISCV_EXCP_ILLEGAL_INST;
+ }
+-static int ctr(CPURISCVState *env, int csrno)
++static RISCVException ctr(CPURISCVState *env, int csrno)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     CPUState *cs = env_cpu(env);
+@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
+     if (!cpu->cfg.ext_counters) {
+         /* The Counters extensions is not enabled */
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     if (riscv_cpu_virt_enabled(env)) {
+@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
+         case CSR_CYCLE:
+             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+             }
+             break;
+         case CSR_TIME:
+             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+             }
+             break;
+         case CSR_INSTRET:
+             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+             }
+             break;
+         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
+                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+             }
+             break;
+         }
+@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
+             case CSR_CYCLEH:
+                 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+                     get_field(env->mcounteren, HCOUNTEREN_CY)) {
+-                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+                 }
+                 break;
+             case CSR_TIMEH:
+                 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+                     get_field(env->mcounteren, HCOUNTEREN_TM)) {
+-                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+                 }
+                 break;
+             case CSR_INSTRETH:
+                 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+                     get_field(env->mcounteren, HCOUNTEREN_IR)) {
+-                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+                 }
+                 break;
+             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
+                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+-                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+                 }
+                 break;
+             }
+         }
+     }
+ #endif
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int ctr32(CPURISCVState *env, int csrno)
++static RISCVException ctr32(CPURISCVState *env, int csrno)
+ {
+     if (!riscv_cpu_is_32bit(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     return ctr(env, csrno);
+ }
+ #if !defined(CONFIG_USER_ONLY)
+-static int any(CPURISCVState *env, int csrno)
++static RISCVException any(CPURISCVState *env, int csrno)
+ {
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int any32(CPURISCVState *env, int csrno)
++static RISCVException any32(CPURISCVState *env, int csrno)
+ {
+     if (!riscv_cpu_is_32bit(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     return any(env, csrno);
+ }
+-static int smode(CPURISCVState *env, int csrno)
++static RISCVException smode(CPURISCVState *env, int csrno)
+ {
+-    return -!riscv_has_ext(env, RVS);
++    if (riscv_has_ext(env, RVS)) {
++        return RISCV_EXCP_NONE;
++    }
++
++    return RISCV_EXCP_ILLEGAL_INST;
+ }
+-static int hmode(CPURISCVState *env, int csrno)
++static RISCVException hmode(CPURISCVState *env, int csrno)
+ {
+     if (riscv_has_ext(env, RVS) &&
+         riscv_has_ext(env, RVH)) {
+         /* Hypervisor extension is supported */
+         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+             env->priv == PRV_M) {
+-            return 0;
++            return RISCV_EXCP_NONE;
+         } else {
+-            return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+         }
+     }
+-    return -RISCV_EXCP_ILLEGAL_INST;
++    return RISCV_EXCP_ILLEGAL_INST;
+ }
+-static int hmode32(CPURISCVState *env, int csrno)
++static RISCVException hmode32(CPURISCVState *env, int csrno)
+ {
+     if (!riscv_cpu_is_32bit(env)) {
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     return hmode(env, csrno);
+ }
+-static int pmp(CPURISCVState *env, int csrno)
++static RISCVException pmp(CPURISCVState *env, int csrno)
+ {
+-    return -!riscv_feature(env, RISCV_FEATURE_PMP);
++    if (riscv_feature(env, RISCV_FEATURE_PMP)) {
++        return RISCV_EXCP_NONE;
++    }
++
++    return RISCV_EXCP_ILLEGAL_INST;
+ }
+ #endif
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         return -RISCV_EXCP_ILLEGAL_INST;
+     }
+     ret = csr_ops[csrno].predicate(env, csrno);
+-    if (ret < 0) {
+-        return ret;
++    if (ret != RISCV_EXCP_NONE) {
++        return -ret;
+     }
+     /* execute combined read/write operation if it exists */
+--
+.31.1

-New patch
+[PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/csr.c | 6 +++++-
+file changed, 5 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
+ static RISCVException hmode32(CPURISCVState *env, int csrno)
+ {
+     if (!riscv_cpu_is_32bit(env)) {
+-        return RISCV_EXCP_NONE;
++        if (riscv_cpu_virt_enabled(env)) {
++            return RISCV_EXCP_ILLEGAL_INST;
++        } else {
++            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++        }
+     }
+     return hmode(env, csrno);
+--
+.31.1

-New patch
+[PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.h |  14 +-
+ target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------
+files changed, 382 insertions(+), 261 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
+ typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
+                                                  int csrno);
+-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+-    target_ulong *ret_value);
+-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+-    target_ulong new_value);
+-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+-    target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
++typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
++                                            target_ulong *ret_value);
++typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
++                                             target_ulong new_value);
++typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
++                                          target_ulong *ret_value,
++                                          target_ulong new_value,
++                                          target_ulong write_mask);
+ typedef struct {
+     const char *name;
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
+ #endif
+ /* User Floating-Point CSRs */
+-static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_fflags(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+     *val = riscv_cpu_get_fflags(env);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_fflags(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_frm(CPURISCVState *env, int csrno,
++                               target_ulong *val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+     *val = env->frm;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_frm(CPURISCVState *env, int csrno,
++                                target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_fcsr(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
+@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
+         *val |= (env->vxrm << FSR_VXRM_SHIFT)
+                 | (env->vxsat << FSR_VXSAT_SHIFT);
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_fcsr(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
+         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
+     }
+     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vtype(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->vtype;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vl(CPURISCVState *env, int csrno,
++                              target_ulong *val)
+ {
+     *val = env->vl;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vxrm(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     *val = env->vxrm;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vxrm(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+     env->vxrm = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vxsat(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->vxsat;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vxsat(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->vxsat = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vstart(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->vstart;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vstart(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->vstart = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* User Timers and Counters */
+-static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_instret(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (icount_enabled()) {
+@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
+ #else
+     *val = cpu_get_host_ticks();
+ #endif
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_instreth(CPURISCVState *env, int csrno,
++                                    target_ulong *val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+     if (icount_enabled()) {
+@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
+ #else
+     *val = cpu_get_host_ticks() >> 32;
+ #endif
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ #if defined(CONFIG_USER_ONLY)
+-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_time(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     *val = cpu_get_host_ticks();
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_timeh(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = cpu_get_host_ticks() >> 32;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ #else /* CONFIG_USER_ONLY */
+-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_time(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_timeh(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Machine constants */
+@@ -XXX,XX +XXX,XX @@ static const char valid_vm_1_10_64[16] = {
+ };
+ /* Machine Information Registers */
+-static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_zero(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+-    return *val = 0;
++    *val = 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mhartid(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->mhartid;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Machine Trap Setup */
+-static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mstatus(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->mstatus;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ static int validate_vm(CPURISCVState *env, target_ulong vm)
+@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
+     }
+ }
+-static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mstatus(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     uint64_t mstatus = env->mstatus;
+     uint64_t mask = 0;
+@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
+     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+     env->mstatus = mstatus;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mstatush(CPURISCVState *env, int csrno,
++                                    target_ulong *val)
+ {
+     *val = env->mstatus >> 32;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mstatush(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     uint64_t valh = (uint64_t)val << 32;
+     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
+@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
+     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_misa(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     *val = env->misa;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_misa(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+         /* drop write to misa */
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     /* 'I' or 'E' must be present */
+     if (!(val & (RVI | RVE))) {
+         /* It is not, drop write to misa */
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     /* 'E' excludes all other extensions */
+@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+         /* when we support 'E' we can do "val = RVE;" however
+          * for now we just drop writes if 'E' is present.
+          */
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     /* Mask extensions that are not supported by this hart */
+@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+     env->misa = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_medeleg(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->medeleg;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_medeleg(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mideleg(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->mideleg;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mideleg(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
+     if (riscv_has_ext(env, RVH)) {
+         env->mideleg |= VS_MODE_INTERRUPTS;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mie(CPURISCVState *env, int csrno,
++                               target_ulong *val)
+ {
+     *val = env->mie;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mie(CPURISCVState *env, int csrno,
++                                target_ulong val)
+ {
+     env->mie = (env->mie & ~all_ints) | (val & all_ints);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mtvec(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->mtvec;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mtvec(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+     if ((val & 3) < 2) {
+@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
+     } else {
+         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
++                                      target_ulong *val)
+ {
+     *val = env->mcounteren;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
++                                       target_ulong val)
+ {
+     env->mcounteren = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Machine Trap Handling */
+-static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mscratch(CPURISCVState *env, int csrno,
++                                    target_ulong *val)
+ {
+     *val = env->mscratch;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mscratch(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     env->mscratch = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mepc(CPURISCVState *env, int csrno,
++                                     target_ulong *val)
+ {
+     *val = env->mepc;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mepc(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     env->mepc = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mcause(CPURISCVState *env, int csrno,
++                                     target_ulong *val)
+ {
+     *val = env->mcause;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mcause(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     env->mcause = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mtval(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->mtval;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mtval(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->mtval = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                   target_ulong new_value, target_ulong write_mask)
++static RISCVException rmw_mip(CPURISCVState *env, int csrno,
++                              target_ulong *ret_value,
++                              target_ulong new_value, target_ulong write_mask)
+ {
+     RISCVCPU *cpu = env_archcpu(env);
+     /* Allow software control of delegable interrupts not claimed by hardware */
+@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         *ret_value = old_mip;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Supervisor Trap Setup */
+-static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_sstatus(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     target_ulong mask = (sstatus_v1_10_mask);
+     *val = env->mstatus & mask;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_sstatus(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     target_ulong mask = (sstatus_v1_10_mask);
+     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
+     return write_mstatus(env, CSR_MSTATUS, newval);
+ }
+-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vsie(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     /* Shift the VS bits to their S bit location in vsie */
+     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_sie(CPURISCVState *env, int csrno,
++                               target_ulong *val)
+ {
+     if (riscv_cpu_virt_enabled(env)) {
+         read_vsie(env, CSR_VSIE, val);
+     } else {
+         *val = env->mie & env->mideleg;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vsie(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+     /* Shift the S bits to their VS bit location in mie */
+     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+@@ -XXX,XX +XXX,XX @@ static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+         write_mie(env, CSR_MIE, newval);
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_stvec(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->stvec;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_stvec(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+     if ((val & 3) < 2) {
+@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
+     } else {
+         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_scounteren(CPURISCVState *env, int csrno,
++                                      target_ulong *val)
+ {
+     *val = env->scounteren;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_scounteren(CPURISCVState *env, int csrno,
++                                       target_ulong val)
+ {
+     env->scounteren = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Supervisor Trap Handling */
+-static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_sscratch(CPURISCVState *env, int csrno,
++                                    target_ulong *val)
+ {
+     *val = env->sscratch;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_sscratch(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     env->sscratch = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_sepc(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     *val = env->sepc;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_sepc(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+     env->sepc = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_scause(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->scause;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_scause(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->scause = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_stval(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->stval;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_stval(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->stval = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                    target_ulong new_value, target_ulong write_mask)
++static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
++                               target_ulong *ret_value,
++                               target_ulong new_value, target_ulong write_mask)
+ {
+     /* Shift the S bits to their VS bit location in mip */
+     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+@@ -XXX,XX +XXX,XX @@ static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+     return ret;
+ }
+-static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                   target_ulong new_value, target_ulong write_mask)
++static RISCVException rmw_sip(CPURISCVState *env, int csrno,
++                              target_ulong *ret_value,
++                              target_ulong new_value, target_ulong write_mask)
+ {
+     int ret;
+@@ -XXX,XX +XXX,XX @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ }
+ /* Supervisor Protection and Translation */
+-static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_satp(CPURISCVState *env, int csrno,
++                                target_ulong *val)
+ {
+     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+         *val = 0;
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     } else {
+         *val = env->satp;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_satp(CPURISCVState *env, int csrno,
++                                 target_ulong val)
+ {
+     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+-        return 0;
++        return RISCV_EXCP_NONE;
+     }
+     if (validate_vm(env, get_field(val, SATP_MODE)) &&
+         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
+     {
+         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+-            return -RISCV_EXCP_ILLEGAL_INST;
++            return RISCV_EXCP_ILLEGAL_INST;
+         } else {
+             if ((val ^ env->satp) & SATP_ASID) {
+                 tlb_flush(env_cpu(env));
+@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
+             env->satp = val;
+         }
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Hypervisor Extensions */
+-static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hstatus(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->hstatus;
+     if (!riscv_cpu_is_32bit(env)) {
+@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+     }
+     /* We only support little endian */
+     *val = set_field(*val, HSTATUS_VSBE, 0);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hstatus(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->hstatus = val;
+     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
+@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+     if (get_field(val, HSTATUS_VSBE) != 0) {
+         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->hedeleg;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->hedeleg = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hideleg(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->hideleg;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hideleg(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->hideleg = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                   target_ulong new_value, target_ulong write_mask)
++static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
++                               target_ulong *ret_value,
++                               target_ulong new_value, target_ulong write_mask)
+ {
+     int ret = rmw_mip(env, 0, ret_value, new_value,
+                       write_mask & hvip_writable_mask);
+@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+     return ret;
+ }
+-static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                   target_ulong new_value, target_ulong write_mask)
++static RISCVException rmw_hip(CPURISCVState *env, int csrno,
++                              target_ulong *ret_value,
++                              target_ulong new_value, target_ulong write_mask)
+ {
+     int ret = rmw_mip(env, 0, ret_value, new_value,
+                       write_mask & hip_writable_mask);
+@@ -XXX,XX +XXX,XX @@ static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+     return ret;
+ }
+-static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hie(CPURISCVState *env, int csrno,
++                               target_ulong *val)
+ {
+     *val = env->mie & VS_MODE_INTERRUPTS;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hie(CPURISCVState *env, int csrno,
++                                target_ulong val)
+ {
+     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
+     return write_mie(env, CSR_MIE, newval);
+ }
+-static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
++                                      target_ulong *val)
+ {
+     *val = env->hcounteren;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
++                                       target_ulong val)
+ {
+     env->hcounteren = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hgeie(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hgeie(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_htval(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->htval;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_htval(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->htval = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_htinst(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->htinst;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_htinst(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hgeip(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hgeip(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_hgatp(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->hgatp;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_hgatp(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->hgatp = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
++                                      target_ulong *val)
+ {
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     *val = env->htimedelta;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
++                                       target_ulong val)
+ {
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     if (riscv_cpu_is_32bit(env)) {
+@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
+     } else {
+         env->htimedelta = val;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
++                                       target_ulong *val)
+ {
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     *val = env->htimedelta >> 32;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
++                                        target_ulong val)
+ {
+     if (!env->rdtime_fn) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Virtual CSR Registers */
+-static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
++                                    target_ulong *val)
+ {
+     *val = env->vsstatus;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
++                                     target_ulong val)
+ {
+     uint64_t mask = (target_ulong)-1;
+     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
+ {
+     *val = env->vstvec;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vstvec(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->vstvec = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
++                                     target_ulong *val)
+ {
+     *val = env->vsscratch;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
++                                      target_ulong val)
+ {
+     env->vsscratch = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vsepc(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->vsepc;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vsepc(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->vsepc = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vscause(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = env->vscause;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vscause(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     env->vscause = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vstval(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->vstval;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vstval(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->vstval = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_vsatp(CPURISCVState *env, int csrno,
++                                 target_ulong *val)
+ {
+     *val = env->vsatp;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_vsatp(CPURISCVState *env, int csrno,
++                                  target_ulong val)
+ {
+     env->vsatp = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mtval2(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->mtval2;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mtval2(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->mtval2 = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_mtinst(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = env->mtinst;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_mtinst(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     env->mtinst = val;
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /* Physical Memory Protection */
+-static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
++                                  target_ulong *val)
+ {
+     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
++                                   target_ulong val)
+ {
+     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
++static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
+ {
+     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+-static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
++static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
++                                    target_ulong val)
+ {
+     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ #endif
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+     /* execute combined read/write operation if it exists */
+     if (csr_ops[csrno].op) {
+-        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
++        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
++        if (ret != RISCV_EXCP_NONE) {
++            return -ret;
++        }
++        return 0;
+     }
+     /* if no accessor exists then return failure */
+     if (!csr_ops[csrno].read) {
+         return -RISCV_EXCP_ILLEGAL_INST;
+     }
+-
+     /* read old value */
+     ret = csr_ops[csrno].read(env, csrno, &old_value);
+-    if (ret < 0) {
+-        return ret;
++    if (ret != RISCV_EXCP_NONE) {
++        return -ret;
+     }
+     /* write value if writable and write mask set, otherwise drop writes */
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         new_value = (old_value & ~write_mask) | (new_value & write_mask);
+         if (csr_ops[csrno].write) {
+             ret = csr_ops[csrno].write(env, csrno, new_value);
+-            if (ret < 0) {
+-                return ret;
++            if (ret != RISCV_EXCP_NONE) {
++                return -ret;
+             }
+         }
+     }
+--
+.31.1

-New patch
+[PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.h       | 11 +++++++----
+ target/riscv/csr.c       | 37 ++++++++++++++++++-------------------
+ target/riscv/gdbstub.c   |  8 ++++----
+ target/riscv/op_helper.c | 18 +++++++++---------
+files changed, 38 insertions(+), 36 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+     *pflags = flags;
+ }
+-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                target_ulong new_value, target_ulong write_mask);
+-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                      target_ulong new_value, target_ulong write_mask);
++RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
++                           target_ulong *ret_value,
++                           target_ulong new_value, target_ulong write_mask);
++RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
++                                 target_ulong *ret_value,
++                                 target_ulong new_value,
++                                 target_ulong write_mask);
+ static inline void riscv_csr_write(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
+  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
+  */
+-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                target_ulong new_value, target_ulong write_mask)
++RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
++                           target_ulong *ret_value,
++                           target_ulong new_value, target_ulong write_mask)
+ {
+-    int ret;
++    RISCVException ret;
+     target_ulong old_value;
+     RISCVCPU *cpu = env_archcpu(env);
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+     if ((write_mask && read_only) ||
+         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+ #endif
+     /* ensure the CSR extension is enabled. */
+     if (!cpu->cfg.ext_icsr) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     /* check predicate */
+     if (!csr_ops[csrno].predicate) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     ret = csr_ops[csrno].predicate(env, csrno);
+     if (ret != RISCV_EXCP_NONE) {
+-        return -ret;
++        return ret;
+     }
+     /* execute combined read/write operation if it exists */
+     if (csr_ops[csrno].op) {
+-        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+-        if (ret != RISCV_EXCP_NONE) {
+-            return -ret;
+-        }
+-        return 0;
++        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+     }
+     /* if no accessor exists then return failure */
+     if (!csr_ops[csrno].read) {
+-        return -RISCV_EXCP_ILLEGAL_INST;
++        return RISCV_EXCP_ILLEGAL_INST;
+     }
+     /* read old value */
+     ret = csr_ops[csrno].read(env, csrno, &old_value);
+     if (ret != RISCV_EXCP_NONE) {
+-        return -ret;
++        return ret;
+     }
+     /* write value if writable and write mask set, otherwise drop writes */
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         if (csr_ops[csrno].write) {
+             ret = csr_ops[csrno].write(env, csrno, new_value);
+             if (ret != RISCV_EXCP_NONE) {
+-                return -ret;
++                return ret;
+             }
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         *ret_value = old_value;
+     }
+-    return 0;
++    return RISCV_EXCP_NONE;
+ }
+ /*
+  * Debugger support.  If not in user mode, set env->debugger before the
+  * riscv_csrrw call and clear it after the call.
+  */
+-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-                target_ulong new_value, target_ulong write_mask)
++RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
++                                 target_ulong *ret_value,
++                                 target_ulong new_value,
++                                 target_ulong write_mask)
+ {
+-    int ret;
++    RISCVException ret;
+ #if !defined(CONFIG_USER_ONLY)
+     env->debugger = true;
+ #endif
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/gdbstub.c
++++ b/target/riscv/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
+          */
+         result = riscv_csrrw_debug(env, n - 32, &val,
+, 0);
+-        if (result == 0) {
++        if (result == RISCV_EXCP_NONE) {
+             return gdb_get_regl(buf, val);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+          */
+         result = riscv_csrrw_debug(env, n - 32, NULL,
+                                    val, -1);
+-        if (result == 0) {
++        if (result == RISCV_EXCP_NONE) {
+             return sizeof(target_ulong);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
+         int result;
+         result = riscv_csrrw_debug(env, n, &val, 0, 0);
+-        if (result == 0) {
++        if (result == RISCV_EXCP_NONE) {
+             return gdb_get_regl(buf, val);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+         int result;
+         result = riscv_csrrw_debug(env, n, NULL, val, -1);
+-        if (result == 0) {
++        if (result == RISCV_EXCP_NONE) {
+             return sizeof(target_ulong);
+         }
+     }
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/op_helper.c
++++ b/target/riscv/op_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
+         target_ulong csr)
+ {
+     target_ulong val = 0;
+-    int ret = riscv_csrrw(env, csr, &val, src, -1);
++    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
+-    if (ret < 0) {
+-        riscv_raise_exception(env, -ret, GETPC());
++    if (ret != RISCV_EXCP_NONE) {
++        riscv_raise_exception(env, ret, GETPC());
+     }
+     return val;
+ }
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
+         target_ulong csr, target_ulong rs1_pass)
+ {
+     target_ulong val = 0;
+-    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
++    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+-    if (ret < 0) {
+-        riscv_raise_exception(env, -ret, GETPC());
++    if (ret != RISCV_EXCP_NONE) {
++        riscv_raise_exception(env, ret, GETPC());
+     }
+     return val;
+ }
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
+         target_ulong csr, target_ulong rs1_pass)
+ {
+     target_ulong val = 0;
+-    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
++    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+-    if (ret < 0) {
+-        riscv_raise_exception(env, -ret, GETPC());
++    if (ret != RISCV_EXCP_NONE) {
++        riscv_raise_exception(env, ret, GETPC());
+     }
+     return val;
+ }
+--
+.31.1

-New patch
+[PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers
+Update the RISC-V maintainers by removing Sagar and Bastian who haven't
+been involved recently.
+Also add Bin who has been helping with reviews.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bin.meng@windriver.com>
+Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
+---
+ MAINTAINERS | 5 ++---
+file changed, 2 insertions(+), 3 deletions(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_ppc.py
+ RISC-V TCG CPUs
+ M: Palmer Dabbelt <palmer@dabbelt.com>
+-M: Alistair Francis <Alistair.Francis@wdc.com>
+-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
+-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
++M: Alistair Francis <alistair.francis@wdc.com>
++M: Bin Meng <bin.meng@windriver.com>
+ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/
+--
+.31.1

-New patch
+[PULL v3 15/42] hw/opentitan: Update the interrupt layout
+Update the OpenTitan interrupt layout to match the latest OpenTitan
+bitstreams. This involves changing the Ibex PLIC memory layout and the
+UART interrupts.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
+---
+ include/hw/riscv/opentitan.h | 16 ++++++++--------
+ hw/intc/ibex_plic.c          | 20 ++++++++++----------
+ hw/riscv/opentitan.c         |  8 ++++----
+files changed, 22 insertions(+), 22 deletions(-)
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/opentitan.h
++++ b/include/hw/riscv/opentitan.h
+@@ -XXX,XX +XXX,XX @@ enum {
+ };
+ enum {
+-    IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
+-    IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
+-    IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
+-    IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
+-    IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
+-    IBEX_UART_TX_EMPTY_IRQ = 0x23,
+-    IBEX_UART_RX_WATERMARK_IRQ = 0x22,
+-    IBEX_UART_TX_WATERMARK_IRQ = 0x21,
++    IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
++    IBEX_UART0_RX_TIMEOUT_IRQ = 7,
++    IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
++    IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
++    IBEX_UART0_RX_OVERFLOW_IRQ = 4,
++    IBEX_UART0_TX_EMPTY_IRQ = 3,
++    IBEX_UART0_RX_WATERMARK_IRQ = 2,
++    IBEX_UART0_TX_WATERMARK_IRQ = 1,
+ };
+ #endif
+diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/ibex_plic.c
++++ b/hw/intc/ibex_plic.c
+@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
+ static Property ibex_plic_properties[] = {
+     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
+-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
++    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
+     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
+-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
++    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
+-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
+-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
++    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
++    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
+-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
+-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
++    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
++    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
+-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
+-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
++    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
++    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
+-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
++    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
+-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
++    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_TX_WATERMARK_IRQ));
++                       IBEX_UART0_TX_WATERMARK_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_RX_WATERMARK_IRQ));
++                       IBEX_UART0_RX_WATERMARK_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_TX_EMPTY_IRQ));
++                       IBEX_UART0_TX_EMPTY_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_RX_OVERFLOW_IRQ));
++                       IBEX_UART0_RX_OVERFLOW_IRQ));
+     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
+         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
+--
+.31.1

-New patch
+[PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
+imply VIRTIO_VGA for the virt machine, this fixes the following error
+when specifying `-vga virtio` as a command line argument:
+qemu-system-riscv64: Virtio VGA not available
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
+---
+ hw/riscv/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/Kconfig
++++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ config SHAKTI_C
+ config RISCV_VIRT
+     bool
+     imply PCI_DEVICES
++    imply VIRTIO_VGA
+     imply TEST_DEVICES
+     select GOLDFISH_RTC
+     select MSI_NONBROKEN
+--
+.31.1

-[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
+[PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Jade Fink <qemu@jade.fyi>
-Once a "One Time Programmable" is programmed, it shouldn't be reset.
+Previously the qemu monitor and gdbstub looked at SUM and refused to
 perform accesses to user memory if it is off, which was an impediment to
 debugging.
-Do not re-initialize the OTP content in the DeviceReset handler,
+Signed-off-by: Jade Fink <qemu@jade.fyi>
 initialize it once in the DeviceRealize one.
 Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
+Message-id: 20210406113109.1031033-1-qemu@jade.fyi
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/misc/sifive_u_otp.c | 13 +++++--------
+ target/riscv/cpu_helper.c | 20 ++++++++++++--------
-file changed, 5 insertions(+), 8 deletions(-)
+file changed, 12 insertions(+), 8 deletions(-)
-diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/sifive_u_otp.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/misc/sifive_u_otp.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+  * @first_stage: Are we in first stage translation?
-             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
+  *               Second stage is used for hypervisor guest translation
-                 error_setg(errp, "failed to read the initial flash content");
+  * @two_stage: Are we going to perform two stage translation
-+                return;
++ * @is_debug: Is this access from a debugger or the monitor?
-             }
+  */
  static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                                  int *prot, target_ulong addr,
                                  target_ulong *fault_pte_addr,
                                  int access_type, int mmu_idx,
 -                                bool first_stage, bool two_stage)
 +                                bool first_stage, bool two_stage,
 +                                bool is_debug)
  {
      /* NOTE: the env->pc value visible here will not be
       * correct, but the value visible to the exception handler
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
          widened = 2;
      }
      /* status.SUM will be ignored if execute on background */
 -    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
 +    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
      switch (vm) {
      case VM_1_10_SV32:
        levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -XXX,XX +XXX,XX @@ restart:
              /* Do the second stage translation on the base PTE address. */
              int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
                                                   base, NULL, MMU_DATA_LOAD,
 -                                                 mmu_idx, false, true);
 +                                                 mmu_idx, false, true,
 +                                                 is_debug);
              if (vbase_ret != TRANSLATE_SUCCESS) {
                  if (fault_pte_addr) {
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
      int mmu_idx = cpu_mmu_index(&cpu->env, false);
      if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
 -                             true, riscv_cpu_virt_enabled(env))) {
 +                             true, riscv_cpu_virt_enabled(env), true)) {
          return -1;
      }
      if (riscv_cpu_virt_enabled(env)) {
          if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
 -                                 0, mmu_idx, false, true)) {
 +                                 0, mmu_idx, false, true, true)) {
              return -1;
          }
      }
--}
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--
+         /* Two stage lookup */
--static void sifive_u_otp_reset(DeviceState *dev)
+         ret = get_physical_address(env, &pa, &prot, address,
--{
+                                    &env->guest_phys_fault_addr, access_type,
--    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
+-                                   mmu_idx, true, true);
++                                   mmu_idx, true, true, false);
-     /* Initialize all fuses' initial value to 0xFFs */
-     memset(s->fuse, 0xff, sizeof(s->fuse));
+         /*
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
+          * A G-stage exception may be triggered during two state lookup.
-         serial_data = s->serial;
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
+             im_address = pa;
-                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
--            error_report("write error index<%d>", index);
+             ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
-+            error_setg(errp, "failed to write index<%d>", index);
+-                                       access_type, mmu_idx, false, true);
-+            return;
++                                       access_type, mmu_idx, false, true,
-         }
++                                       false);
-         serial_data = ~(s->serial);
+             qemu_log_mask(CPU_LOG_MMU,
-         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
+                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
-                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--            error_report("write error index<%d>", index + 1);
+     } else {
-+            error_setg(errp, "failed to write index<%d>", index + 1);
+         /* Single stage lookup */
-+            return;
+         ret = get_physical_address(env, &pa, &prot, address, NULL,
-         }
+-                                   access_type, mmu_idx, true, false);
-     }
++                                   access_type, mmu_idx, true, false, false);
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
+         qemu_log_mask(CPU_LOG_MMU,
+                       "%s address=%" VADDR_PRIx " ret %d physical "
      device_class_set_props(dc, sifive_u_otp_properties);
      dc->realize = sifive_u_otp_realize;
 -    dc->reset = sifive_u_otp_reset;
  }
  static const TypeInfo sifive_u_otp_info = {
 --
 .31.1

-New patch
+[PULL v3 18/42] target/riscv: Fixup saturate subtract function
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
+However, when the predication is ture and a is 0, it should return maximum.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 8 ++++----
+file changed, 4 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+ {
+     int8_t res = a - b;
+     if ((res ^ a) & (a ^ b) & INT8_MIN) {
+-        res = a > 0 ? INT8_MAX : INT8_MIN;
++        res = a >= 0 ? INT8_MAX : INT8_MIN;
+         env->vxsat = 0x1;
+     }
+     return res;
+@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+ {
+     int16_t res = a - b;
+     if ((res ^ a) & (a ^ b) & INT16_MIN) {
+-        res = a > 0 ? INT16_MAX : INT16_MIN;
++        res = a >= 0 ? INT16_MAX : INT16_MIN;
+         env->vxsat = 0x1;
+     }
+     return res;
+@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+ {
+     int32_t res = a - b;
+     if ((res ^ a) & (a ^ b) & INT32_MIN) {
+-        res = a > 0 ? INT32_MAX : INT32_MIN;
++        res = a >= 0 ? INT32_MAX : INT32_MIN;
+         env->vxsat = 0x1;
+     }
+     return res;
+@@ -XXX,XX +XXX,XX @@ static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+ {
+     int64_t res = a - b;
+     if ((res ^ a) & (a ^ b) & INT64_MIN) {
+-        res = a > 0 ? INT64_MAX : INT64_MIN;
++        res = a >= 0 ? INT64_MAX : INT64_MIN;
+         env->vxsat = 0x1;
+     }
+     return res;
+--
+.31.1

-New patch
+[PULL v3 19/42] docs: Add documentation for shakti_c machine
+From: Vijai Kumar K <vijai@behindbytes.com>
+Add documentation for Shakti C reference platform.
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210412174248.8668-1-vijai@behindbytes.com
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+[ Changes from Bin Meng:
+ - Add missing TOC
+ Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
+ docs/system/target-riscv.rst   |  1 +
+files changed, 83 insertions(+)
+ create mode 100644 docs/system/riscv/shakti-c.rst
+diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/docs/system/riscv/shakti-c.rst
+@@ -XXX,XX +XXX,XX @@
++Shakti C Reference Platform (``shakti_c``)
++==========================================
++
++Shakti C Reference Platform is a reference platform based on arty a7 100t
++for the Shakti SoC.
++
++Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
++is a 64bit RV64GCSUN processor core.
++
++For more details on Shakti SoC, please see:
++https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
++
++For more info on the Shakti C-class core, please see:
++https://c-class.readthedocs.io/en/latest/
++
++Supported devices
++-----------------
++
++The ``shakti_c`` machine supports the following devices:
++
++ * 1 C-class core
++ * Core Level Interruptor (CLINT)
++ * Platform-Level Interrupt Controller (PLIC)
++ * 1 UART
++
++Boot options
++------------
++
++The ``shakti_c`` machine can start using the standard -bios
++functionality for loading the baremetal application or opensbi.
++
++Boot the machine
++----------------
++
++Shakti SDK
++~~~~~~~~~~
++Shakti SDK can be used to generate the baremetal example UART applications.
++
++.. code-block:: bash
++
++   $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
++   $ cd shakti-sdk
++   $ make software PROGRAM=loopback TARGET=artix7_100t
++
++Binary would be generated in:
++  software/examples/uart_applns/loopback/output/loopback.shakti
++
++You could also download the precompiled example applicatons using below
++commands.
++
++.. code-block:: bash
++
++   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
++   $ unzip shakti_sdk_qemu.zip
++
++Then we can run the UART example using:
++
++.. code-block:: bash
++
++   $ qemu-system-riscv64 -M shakti_c -nographic \
++      -bios path/to/shakti_sdk_qemu/loopback.shakti
++
++OpenSBI
++~~~~~~~
++We can also run OpenSBI with Test Payload.
++
++.. code-block:: bash
++
++   $ git clone https://github.com/riscv/opensbi.git -b v0.9
++   $ cd opensbi
++   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
++   $ export CROSS_COMPILE=riscv64-unknown-elf-
++   $ export FW_FDT_PATH=./shakti.dtb
++   $ make PLATFORM=generic
++
++fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
++Boot it using the below qemu command.
++
++.. code-block:: bash
++
++   $ qemu-system-riscv64 -M shakti_c -nographic \
++      -bios path/to/fw_payload.elf
+diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/target-riscv.rst
++++ b/docs/system/target-riscv.rst
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+    :maxdepth: 1
+    riscv/microchip-icicle-kit
++   riscv/shakti-c
+    riscv/sifive_u
+ RISC-V CPU features
+--
+.31.1

-New patch
+[PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR
+The RISC-V spec says:
+    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
+    pmpaddri-1 are ignored.
+The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
+is incorrect.
+Update the pmp_is_locked() function to not check the supporting fields
+and instead enforce the lock functionality in the pmpaddr write operation.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
+---
+ target/riscv/pmp.c | 26 ++++++++++++++++----------
+file changed, 16 insertions(+), 10 deletions(-)
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/pmp.c
++++ b/target/riscv/pmp.c
+@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
+         return 0;
+     }
+-    /* In TOR mode, need to check the lock bit of the next pmp
+-     * (if there is a next)
+-     */
+-    const uint8_t a_field =
+-        pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
+-    if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
+-         (PMP_AMATCH_TOR == a_field)) {
+-        return 1;
+-    }
+-
+     return 0;
+ }
+@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+     target_ulong val)
+ {
+     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
++
+     if (addr_index < MAX_RISCV_PMPS) {
++        /*
++         * In TOR mode, need to check the lock bit of the next pmp
++         * (if there is a next).
++         */
++        if (addr_index + 1 < MAX_RISCV_PMPS) {
++            uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
++
++            if (pmp_cfg & PMP_LOCK &&
++                PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
++                qemu_log_mask(LOG_GUEST_ERROR,
++                              "ignoring pmpaddr write - pmpcfg + 1 locked\n");
++                return;
++            }
++        }
++
+         if (!pmp_is_locked(env, addr_index)) {
+             env->pmp_state.pmp[addr_index].addr_reg = val;
+             pmp_update_rule(env, addr_index);
+--
+.31.1

-New patch
+[PULL v3 21/42] target/riscv: Define ePMP mseccfg
+From: Hou Weiying <weiying_hou@outlook.com>
+Use address 0x390 and 0x391 for the ePMP CSRs.
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
+[ Changes by AF:
+ - Tidy up commit message
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ target/riscv/cpu_bits.h | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define CSR_MTINST          0x34a
+ #define CSR_MTVAL2          0x34b
++/* Enhanced Physical Memory Protection (ePMP) */
++#define CSR_MSECCFG         0x390
++#define CSR_MSECCFGH        0x391
+ /* Physical Memory Protection */
+ #define CSR_PMPCFG0         0x3a0
+ #define CSR_PMPCFG1         0x3a1
+--
+.31.1

-New patch
+[PULL v3 22/42] target/riscv: Add the ePMP feature
+The spec is avaliable at:
+https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.h | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ enum {
+     RISCV_FEATURE_MMU,
+     RISCV_FEATURE_PMP,
++    RISCV_FEATURE_EPMP,
+     RISCV_FEATURE_MISA
+ };
+--
+.31.1

-New patch
+[PULL v3 23/42] target/riscv: Add ePMP CSR access functions
+From: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
+[ Changes by AF:
+ - Rebase on master
+ - Fix build errors
+ - Fix some style issues
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ target/riscv/cpu.h        |  1 +
+ target/riscv/pmp.h        | 14 ++++++++++++++
+ target/riscv/csr.c        | 24 ++++++++++++++++++++++++
+ target/riscv/pmp.c        | 34 ++++++++++++++++++++++++++++++++++
+ target/riscv/trace-events |  3 +++
+files changed, 76 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     /* physical memory protection */
+     pmp_table_t pmp_state;
++    target_ulong mseccfg;
+     /* machine specific rdtime callback */
+     uint64_t (*rdtime_fn)(uint32_t);
+diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/pmp.h
++++ b/target/riscv/pmp.h
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
+ } pmp_am_t;
++typedef enum {
++    MSECCFG_MML  = 1 << 0,
++    MSECCFG_MMWP = 1 << 1,
++    MSECCFG_RLB  = 1 << 2
++} mseccfg_field_t;
++
+ typedef struct {
+     target_ulong addr_reg;
+     uint8_t  cfg_reg;
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
+     target_ulong val);
+ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
++
++void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
++target_ulong mseccfg_csr_read(CPURISCVState *env);
++
+ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+     target_ulong val);
+ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env);
+ uint32_t pmp_get_num_rules(CPURISCVState *env);
+ int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
++#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
++#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
++#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
++
+ #endif
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
+     return RISCV_EXCP_ILLEGAL_INST;
+ }
++
++static RISCVException epmp(CPURISCVState *env, int csrno)
++{
++    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
++        return RISCV_EXCP_NONE;
++    }
++
++    return RISCV_EXCP_ILLEGAL_INST;
++}
+ #endif
+ /* User Floating-Point CSRs */
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
+ }
+ /* Physical Memory Protection */
++static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
++                                   target_ulong *val)
++{
++    *val = mseccfg_csr_read(env);
++    return RISCV_EXCP_NONE;
++}
++
++static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
++                         target_ulong val)
++{
++    mseccfg_csr_write(env, val);
++    return RISCV_EXCP_NONE;
++}
++
+ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+ {
+@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
+     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
+     /* Physical Memory Protection */
++    [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
+     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
+     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
+     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/pmp.c
++++ b/target/riscv/pmp.c
+@@ -XXX,XX +XXX,XX @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
+     return val;
+ }
++/*
++ * Handle a write to a mseccfg CSR
++ */
++void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
++{
++    int i;
++
++    trace_mseccfg_csr_write(env->mhartid, val);
++
++    /* RLB cannot be enabled if it's already 0 and if any regions are locked */
++    if (!MSECCFG_RLB_ISSET(env)) {
++        for (i = 0; i < MAX_RISCV_PMPS; i++) {
++            if (pmp_is_locked(env, i)) {
++                val &= ~MSECCFG_RLB;
++                break;
++            }
++        }
++    }
++
++    /* Sticky bits */
++    val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
++
++    env->mseccfg = val;
++}
++
++/*
++ * Handle a read from a mseccfg CSR
++ */
++target_ulong mseccfg_csr_read(CPURISCVState *env)
++{
++    trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
++    return env->mseccfg;
++}
++
+ /*
+  * Calculate the TLB size if the start address or the end address of
+  * PMP entry is presented in thie TLB page.
+diff --git a/target/riscv/trace-events b/target/riscv/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/trace-events
++++ b/target/riscv/trace-events
+@@ -XXX,XX +XXX,XX @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
+ pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
+ pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
+ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
++
++mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
++mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
+--
+.31.1

-[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
+[PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP)
-From: Thomas Huth <thuth@redhat.com>
+From: Hou Weiying <weiying_hou@outlook.com>
-Configuring a drive with "if=none" is meant for creation of a backend
+This commit adds support for ePMP v0.9.1.
-only, it should not get automatically assigned to a device frontend.
-Use "if=pflash" for the One-Time-Programmable device instead (like
+The ePMP spec can be found in:
-it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
+https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
-Since the old way of configuring the device has already been published
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
-with the previous QEMU versions, we cannot remove this immediately, but
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
-have to deprecate it and support it for at least two more releases.
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Thomas Huth <thuth@redhat.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
-Reviewed-by: Markus Armbruster <armbru@redhat.com>
+[ Changes by AF:
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+ - Rebase on master
-Message-id: 20211119102549.217755-1-thuth@redhat.com
+ - Update to latest spec
  - Use a switch case to handle ePMP MML permissions
  - Fix a few bugs
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/about/deprecated.rst | 6 ++++++
+ target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
- hw/misc/sifive_u_otp.c    | 9 ++++++++-
+file changed, 146 insertions(+), 8 deletions(-)
-files changed, 14 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
+--- a/target/riscv/pmp.c
-+++ b/docs/about/deprecated.rst
++++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
+@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
- However, short-form booleans are deprecated and full explicit ``arg_name=on``
+ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
- form is preferred.
+ {
+     if (pmp_index < MAX_RISCV_PMPS) {
-+``-drive if=none`` for the sifive_u OTP device (since 6.2)
+-        if (!pmp_is_locked(env, pmp_index)) {
-+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+-            env->pmp_state.pmp[pmp_index].cfg_reg = val;
-+
+-            pmp_update_rule(env, pmp_index);
-+Using ``-drive if=none`` to configure the OTP device of the sifive_u
++        bool locked = true;
-+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
++
-+
++        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
++            /* mseccfg.RLB is set */
- QEMU Machine Protocol (QMP) commands
++            if (MSECCFG_RLB_ISSET(env)) {
- ------------------------------------
++                locked = false;
-diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
++            }
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/misc/sifive_u_otp.c
++            /* mseccfg.MML is not set */
-+++ b/hw/misc/sifive_u_otp.c
++            if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index)) {
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
++                locked = false;
-                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
++            }
-     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
++
++            /* mseccfg.MML is set */
--    dinfo = drive_get_next(IF_NONE);
++            if (MSECCFG_MML_ISSET(env)) {
-+    dinfo = drive_get_next(IF_PFLASH);
++                /* not adding execute bit */
-+    if (!dinfo) {
++                if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) {
-+        dinfo = drive_get_next(IF_NONE);
++                    locked = false;
-+        if (dinfo) {
++                }
-+            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
++                /* shared region and not adding X bit */
-+                        "use \"-drive if=pflash\" instead.");
++                if ((val & PMP_LOCK) != PMP_LOCK &&
 +                    (val & 0x7) != (PMP_WRITE | PMP_EXEC)) {
 +                    locked = false;
 +                }
 +            }
          } else {
 +            if (!pmp_is_locked(env, pmp_index)) {
 +                locked = false;
 +            }
 +        }
 +
 +        if (locked) {
              qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
 +        } else {
 +            env->pmp_state.pmp[pmp_index].cfg_reg = val;
 +            pmp_update_rule(env, pmp_index);
          }
      } else {
          qemu_log_mask(LOG_GUEST_ERROR,
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
  {
      bool ret;
 +    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
 +        if (MSECCFG_MMWP_ISSET(env)) {
 +            /*
 +             * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
 +             * so we default to deny all, even for M-mode.
 +             */
 +            *allowed_privs = 0;
 +            return false;
 +        } else if (MSECCFG_MML_ISSET(env)) {
 +            /*
 +             * The Machine Mode Lockdown (mseccfg.MML) bit is set
 +             * so we can only execute code in M-mode with an applicable
 +             * rule. Other modes are disabled.
 +             */
 +            if (mode == PRV_M && !(privs & PMP_EXEC)) {
 +                ret = true;
 +                *allowed_privs = PMP_READ | PMP_WRITE;
 +            } else {
 +                ret = false;
 +                *allowed_privs = 0;
 +            }
 +
 +            return ret;
 +        }
 +    }
-     if (dinfo) {
++
-         int ret;
+     if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-         uint64_t perm;
+         /*
           * Privileged spec v1.10 states if HW doesn't implement any PMP entry
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
              pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
          /*
 -         * If the PMP entry is not off and the address is in range, do the priv
 -         * check
 +         * Convert the PMP permissions to match the truth table in the
 +         * ePMP spec.
           */
 +        const uint8_t epmp_operation =
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
 +            (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
 +
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 -            if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +            /*
 +             * If the PMP entry is not off and the address is in range,
 +             * do the priv check
 +             */
 +            if (!MSECCFG_MML_ISSET(env)) {
 +                /*
 +                 * If mseccfg.MML Bit is not set, do pmp priv check
 +                 * This will always apply to regular PMP.
 +                 */
 +                *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +                if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 +                    *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                }
 +            } else {
 +                /*
 +                 * If mseccfg.MML Bit set, do the enhanced pmp priv check
 +                 */
 +                if (mode == PRV_M) {
 +                    switch (epmp_operation) {
 +                    case 0:
 +                    case 1:
 +                    case 4:
 +                    case 5:
 +                    case 6:
 +                    case 7:
 +                    case 8:
 +                        *allowed_privs = 0;
 +                        break;
 +                    case 2:
 +                    case 3:
 +                    case 14:
 +                        *allowed_privs = PMP_READ | PMP_WRITE;
 +                        break;
 +                    case 9:
 +                    case 10:
 +                        *allowed_privs = PMP_EXEC;
 +                        break;
 +                    case 11:
 +                    case 13:
 +                        *allowed_privs = PMP_READ | PMP_EXEC;
 +                        break;
 +                    case 12:
 +                    case 15:
 +                        *allowed_privs = PMP_READ;
 +                        break;
 +                    }
 +                } else {
 +                    switch (epmp_operation) {
 +                    case 0:
 +                    case 8:
 +                    case 9:
 +                    case 12:
 +                    case 13:
 +                    case 14:
 +                        *allowed_privs = 0;
 +                        break;
 +                    case 1:
 +                    case 10:
 +                    case 11:
 +                        *allowed_privs = PMP_EXEC;
 +                        break;
 +                    case 2:
 +                    case 4:
 +                    case 15:
 +                        *allowed_privs = PMP_READ;
 +                        break;
 +                    case 3:
 +                    case 6:
 +                        *allowed_privs = PMP_READ | PMP_WRITE;
 +                        break;
 +                    case 5:
 +                        *allowed_privs = PMP_READ | PMP_EXEC;
 +                        break;
 +                    case 7:
 +                        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +                        break;
 +                    }
 +                }
              }
              ret = ((privs & *allowed_privs) == privs);
 --
 .31.1

-New patch
+[PULL v3 25/42] target/riscv: Add a config option for ePMP
+From: Hou Weiying <weiying_hou@outlook.com>
+Add a config option to enable experimental support for ePMP. This
+is disabled by default and can be enabled with 'x-epmp=true'.
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ target/riscv/cpu.h |  1 +
+ target/riscv/cpu.c | 10 ++++++++++
+files changed, 11 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+         uint16_t elen;
+         bool mmu;
+         bool pmp;
++        bool epmp;
+         uint64_t resetvec;
+     } cfg;
+ };
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+     if (cpu->cfg.pmp) {
+         set_feature(env, RISCV_FEATURE_PMP);
++
++        /*
++         * Enhanced PMP should only be available
++         * on harts with PMP support
++         */
++        if (cpu->cfg.epmp) {
++            set_feature(env, RISCV_FEATURE_EPMP);
++        }
+     }
+     set_resetvec(env, cpu->cfg.resetvec);
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
++    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
++
+     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+--
+.31.1

-New patch
+[PULL v3 26/42] target/riscv/pmp: Remove outdated comment
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
+---
+ target/riscv/pmp.c | 4 ----
+file changed, 4 deletions(-)
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/pmp.c
++++ b/target/riscv/pmp.c
+@@ -XXX,XX +XXX,XX @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-/*
+- * PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
+- */
+-
+ #include "qemu/osdep.h"
+ #include "qemu/log.h"
+ #include "qapi/error.h"
+--
+.31.1

-New patch
+[PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU
+The physical Ibex CPU has ePMP support and it's enabled for the
+OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
+     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+     set_priv_version(env, PRIV_VERSION_1_10_0);
+     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
++    qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
+ }
+ static void rv32_imafcu_nommu_cpu_init(Object *obj)
+--
+.31.1

-New patch
+[PULL v3 28/42] target/riscv: fix vrgather macro index variable type bug
+From: Frank Chang <frank.chang@sifive.com>
+ETYPE may be type of uint64_t, thus index variable has to be declared as
+type of uint64_t, too. Otherwise the value read from vs1 register may be
+truncated to type of uint32_t.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210419060302.14075-1-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
+     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+     uint32_t vm = vext_vm(desc);                                          \
+     uint32_t vl = env->vl;                                                \
+-    uint32_t index, i;                                                    \
++    uint64_t index;                                                       \
++    uint32_t i;                                                           \
+                                                                           \
+     for (i = 0; i < vl; i++) {                                            \
+         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
+     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+     uint32_t vm = vext_vm(desc);                                          \
+     uint32_t vl = env->vl;                                                \
+-    uint32_t index = s1, i;                                               \
++    uint64_t index = s1;                                                  \
++    uint32_t i;                                                           \
+                                                                           \
+     for (i = 0; i < vl; i++) {                                            \
+         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+--
+.31.1

-New patch
+[PULL v3 29/42] target/riscv: fix exception index on instruction access fault
+From: Emmanuel Blot <emmanuel.blot@sifive.com>
+When no MMU is used and the guest code attempts to fetch an instruction
+from an invalid memory location, the exception index defaults to a data
+load access fault, rather an instruction access fault.
+Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 4 +++-
+file changed, 3 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+     if (access_type == MMU_DATA_STORE) {
+         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+-    } else {
++    } else if (access_type == MMU_DATA_LOAD) {
+         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
++    } else {
++        cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+     }
+     env->badaddr = addr;
+--
+.31.1

-New patch
+[PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector
+From: Alexander Wagner <alexander.wagner@ulal.de>
+The IBEX documentation [1] specifies the reset vector to be "the most
+significant 3 bytes of the boot address and the reset value (0x80) as
+the least significant byte".
+[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
+Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/opentitan.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+                             &error_abort);
+     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+                             &error_abort);
+-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
++    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
+     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+     /* Boot ROM */
+--
+.31.1

-New patch
+[PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
+From: Frank Chang <frank.chang@sifive.com>
+In IEEE 754-2008 spec:
+  Invalid operation exception is signaled when doing:
+  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
+  unless c is a quiet NaN; if c is a quiet NaN then it is
+  implementation defined whether the invalid operation exception
+  is signaled.
+In RISC-V Unprivileged ISA spec:
+  The fused multiply-add instructions must set the invalid
+  operation exception flag when the multiplicands are Inf and
+  zero, even when the addend is a quiet NaN.
+This commit set invalid operation execption flag for RISC-V when
+multiplicands of muladd instructions are Inf and zero.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210420013150.21992-1-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ fpu/softfloat-specialize.c.inc | 6 ++++++
+file changed, 6 insertions(+)
+diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/fpu/softfloat-specialize.c.inc
++++ b/fpu/softfloat-specialize.c.inc
+@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
+     } else {
+         return 1;
+     }
++#elif defined(TARGET_RISCV)
++    /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
++    if (infzero) {
++        float_raise(float_flag_invalid, status);
++    }
++    return 3; /* default NaN */
+ #elif defined(TARGET_XTENSA)
+     /*
+      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
+--
+.31.1

-New patch
+[PULL v3 32/42] target/riscv: fix a typo with interrupt names
+From: Emmanuel Blot <emmanuel.blot@sifive.com>
+Interrupt names have been swapped in 205377f8 and do not follow
+IRQ_*_EXT definition order.
+Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
+     "vs_timer",
+     "m_timer",
+     "u_external",
++    "s_external",
+     "vs_external",
+-    "h_external",
+     "m_external",
+     "reserved",
+     "reserved",
+--
+.31.1

-New patch
+[PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu.h | 6 ------
+ target/riscv/cpu.c | 6 +++++-
+files changed, 5 insertions(+), 7 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
+ #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
+-#if defined(TARGET_RISCV32)
+-#define RVXLEN RV32
+-#elif defined(TARGET_RISCV64)
+-#define RVXLEN RV64
+-#endif
+-
+ #define RV(x) ((target_ulong)1 << (x - 'A'))
+ #define RVI RV('I')
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
+ static void riscv_any_cpu_init(Object *obj)
+ {
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
++#if defined(TARGET_RISCV32)
++    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
++#elif defined(TARGET_RISCV64)
++    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
++#endif
+     set_priv_version(env, PRIV_VERSION_1_11_0);
+ }
+--
+.31.1

-New patch
+[PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro
+This also ensures that the SD bit is not writable.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h | 6 ------
+ target/riscv/csr.c      | 9 ++++++++-
+files changed, 8 insertions(+), 7 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define SSTATUS32_SD        0x80000000
+ #define SSTATUS64_SD        0x8000000000000000ULL
+-#if defined(TARGET_RISCV32)
+-#define SSTATUS_SD SSTATUS32_SD
+-#elif defined(TARGET_RISCV64)
+-#define SSTATUS_SD SSTATUS64_SD
+-#endif
+-
+ /* hstatus CSR bits */
+ #define HSTATUS_VSBE         0x00000020
+ #define HSTATUS_GVA          0x00000040
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
+     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
+ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+-    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
++    SSTATUS_SUM | SSTATUS_MXR;
+ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+ static const target_ulong hip_writable_mask = MIP_VSSIP;
+ static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
+ {
+     target_ulong mask = (sstatus_v1_10_mask);
++
++    if (riscv_cpu_is_32bit(env)) {
++        mask |= SSTATUS32_SD;
++    } else {
++        mask |= SSTATUS64_SD;
++    }
++
+     *val = env->mstatus & mask;
+     return RISCV_EXCP_NONE;
+ }
+--
+.31.1

-New patch
+[PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h   | 11 -----------
+ target/riscv/cpu_helper.c | 24 +++++++++++++++---------
+files changed, 15 insertions(+), 20 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define CSR_HTIMEDELTA      0x605
+ #define CSR_HTIMEDELTAH     0x615
+-#if defined(TARGET_RISCV32)
+-#define HGATP_MODE           SATP32_MODE
+-#define HGATP_VMID           SATP32_ASID
+-#define HGATP_PPN            SATP32_PPN
+-#endif
+-#if defined(TARGET_RISCV64)
+-#define HGATP_MODE           SATP64_MODE
+-#define HGATP_VMID           SATP64_ASID
+-#define HGATP_PPN            SATP64_PPN
+-#endif
+-
+ /* Virtual CSRs */
+ #define CSR_VSSTATUS        0x200
+ #define CSR_VSIE            0x204
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+         }
+         widened = 0;
+     } else {
+-        base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
+-        vm = get_field(env->hgatp, HGATP_MODE);
++        if (riscv_cpu_is_32bit(env)) {
++            base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
++            vm = get_field(env->hgatp, SATP32_MODE);
++        } else {
++            base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
++            vm = get_field(env->hgatp, SATP64_MODE);
++        }
+         widened = 2;
+     }
+     /* status.SUM will be ignored if execute on background */
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+                                 bool first_stage, bool two_stage)
+ {
+     CPUState *cs = env_cpu(env);
+-    int page_fault_exceptions;
++    int page_fault_exceptions, vm;
++
+     if (first_stage) {
+-        page_fault_exceptions =
+-            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+-            !pmp_violation;
++        vm = get_field(env->satp, SATP_MODE);
++    } else if (riscv_cpu_is_32bit(env)) {
++        vm = get_field(env->hgatp, SATP32_MODE);
+     } else {
+-        page_fault_exceptions =
+-            get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
+-            !pmp_violation;
++        vm = get_field(env->hgatp, SATP64_MODE);
+     }
++    page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
++
+     switch (access_type) {
+     case MMU_INST_FETCH:
+         if (riscv_cpu_virt_enabled(env) && !first_stage) {
+--
+.31.1

-New patch
+[PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h  | 10 ----------
+ target/riscv/csr.c       | 12 ++++++++++--
+ target/riscv/translate.c | 19 +++++++++++++++++--
+files changed, 27 insertions(+), 14 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define MXL_RV64            2
+ #define MXL_RV128           3
+-#if defined(TARGET_RISCV32)
+-#define MSTATUS_SD MSTATUS32_SD
+-#define MISA_MXL MISA32_MXL
+-#define MXL_VAL MXL_RV32
+-#elif defined(TARGET_RISCV64)
+-#define MSTATUS_SD MSTATUS64_SD
+-#define MISA_MXL MISA64_MXL
+-#define MXL_VAL MXL_RV64
+-#endif
+-
+ /* sstatus CSR bits */
+ #define SSTATUS_UIE         0x00000001
+ #define SSTATUS_SIE         0x00000002
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
+-    mstatus = set_field(mstatus, MSTATUS_SD, dirty);
++    if (riscv_cpu_is_32bit(env)) {
++        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
++    } else {
++        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
++    }
+     env->mstatus = mstatus;
+     return RISCV_EXCP_NONE;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
+     }
+     /* misa.MXL writes are not supported by QEMU */
+-    val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
++    if (riscv_cpu_is_32bit(env)) {
++        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
++    } else {
++        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
++    }
+     /* flush translation cache */
+     if (val != env->misa) {
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+     return ctx->misa & ext;
+ }
++#ifdef TARGET_RISCV32
++# define is_32bit(ctx)  true
++#elif defined(CONFIG_USER_ONLY)
++# define is_32bit(ctx)  false
++#else
++static inline bool is_32bit(DisasContext *ctx)
++{
++    return (ctx->misa & RV32) == RV32;
++}
++#endif
++
+ /*
+  * RISC-V requires NaN-boxing of narrower width floating point values.
+  * This applies when a 32-bit value is assigned to a 64-bit FP register.
+@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+ static void mark_fs_dirty(DisasContext *ctx)
+ {
+     TCGv tmp;
++    target_ulong sd;
++
+     if (ctx->mstatus_fs == MSTATUS_FS) {
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
+     ctx->mstatus_fs = MSTATUS_FS;
+     tmp = tcg_temp_new();
++    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
++
+     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
++    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+     if (ctx->virt_enabled) {
+         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
++        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+     }
+     tcg_temp_free(tmp);
+--
+.31.1

-New patch
+[PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h   | 11 -----------
+ target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
+ target/riscv/csr.c        | 19 +++++++++++++++----
+ target/riscv/monitor.c    | 22 +++++++++++++++++-----
+files changed, 56 insertions(+), 28 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define SATP64_ASID         0x0FFFF00000000000ULL
+ #define SATP64_PPN          0x00000FFFFFFFFFFFULL
+-#if defined(TARGET_RISCV32)
+-#define SATP_MODE           SATP32_MODE
+-#define SATP_ASID           SATP32_ASID
+-#define SATP_PPN            SATP32_PPN
+-#endif
+-#if defined(TARGET_RISCV64)
+-#define SATP_MODE           SATP64_MODE
+-#define SATP_ASID           SATP64_ASID
+-#define SATP_PPN            SATP64_PPN
+-#endif
+-
+ /* VM modes (mstatus.vm) privileged ISA 1.9.1 */
+ #define VM_1_09_MBARE       0
+ #define VM_1_09_MBB         1
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+     if (first_stage == true) {
+         if (use_background) {
+-            base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
+-            vm = get_field(env->vsatp, SATP_MODE);
++            if (riscv_cpu_is_32bit(env)) {
++                base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
++                vm = get_field(env->vsatp, SATP32_MODE);
++            } else {
++                base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
++                vm = get_field(env->vsatp, SATP64_MODE);
++            }
+         } else {
+-            base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+-            vm = get_field(env->satp, SATP_MODE);
++            if (riscv_cpu_is_32bit(env)) {
++                base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
++                vm = get_field(env->satp, SATP32_MODE);
++            } else {
++                base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
++                vm = get_field(env->satp, SATP64_MODE);
++            }
+         }
+         widened = 0;
+     } else {
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+ {
+     CPUState *cs = env_cpu(env);
+     int page_fault_exceptions, vm;
++    uint64_t stap_mode;
++
++    if (riscv_cpu_is_32bit(env)) {
++        stap_mode = SATP32_MODE;
++    } else {
++        stap_mode = SATP64_MODE;
++    }
+     if (first_stage) {
+-        vm = get_field(env->satp, SATP_MODE);
+-    } else if (riscv_cpu_is_32bit(env)) {
+-        vm = get_field(env->hgatp, SATP32_MODE);
++        vm = get_field(env->satp, stap_mode);
+     } else {
+-        vm = get_field(env->hgatp, SATP64_MODE);
++        vm = get_field(env->hgatp, stap_mode);
+     }
++
+     page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+     switch (access_type) {
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
+ static RISCVException write_satp(CPURISCVState *env, int csrno,
+                                  target_ulong val)
+ {
++    int vm, mask, asid;
++
+     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+         return RISCV_EXCP_NONE;
+     }
+-    if (validate_vm(env, get_field(val, SATP_MODE)) &&
+-        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
+-    {
++
++    if (riscv_cpu_is_32bit(env)) {
++        vm = validate_vm(env, get_field(val, SATP32_MODE));
++        mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
++        asid = (val ^ env->satp) & SATP32_ASID;
++    } else {
++        vm = validate_vm(env, get_field(val, SATP64_MODE));
++        mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
++        asid = (val ^ env->satp) & SATP64_ASID;
++    }
++
++    if (vm && mask) {
+         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+             return RISCV_EXCP_ILLEGAL_INST;
+         } else {
+-            if ((val ^ env->satp) & SATP_ASID) {
++            if (asid) {
+                 tlb_flush(env_cpu(env));
+             }
+             env->satp = val;
+diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/monitor.c
++++ b/target/riscv/monitor.c
+@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
+     target_ulong last_size;
+     int last_attr;
+-    base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
++    if (riscv_cpu_is_32bit(env)) {
++        base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
++        vm = get_field(env->satp, SATP32_MODE);
++    } else {
++        base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
++        vm = get_field(env->satp, SATP64_MODE);
++    }
+-    vm = get_field(env->satp, SATP_MODE);
+     switch (vm) {
+     case VM_1_10_SV32:
+         levels = 2;
+@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
+         return;
+     }
+-    if (!(env->satp & SATP_MODE)) {
+-        monitor_printf(mon, "No translation or protection\n");
+-        return;
++    if (riscv_cpu_is_32bit(env)) {
++        if (!(env->satp & SATP32_MODE)) {
++            monitor_printf(mon, "No translation or protection\n");
++            return;
++        }
++    } else {
++        if (!(env->satp & SATP64_MODE)) {
++            monitor_printf(mon, "No translation or protection\n");
++            return;
++        }
+     }
+     mem_info_svxx(mon, env);
+--
+.31.1

-New patch
+[PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h | 6 ------
+file changed, 6 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define HSTATUS32_WPRI       0xFF8FF87E
+ #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
+-#if defined(TARGET_RISCV32)
+-#define HSTATUS_WPRI HSTATUS32_WPRI
+-#elif defined(TARGET_RISCV64)
+-#define HSTATUS_WPRI HSTATUS64_WPRI
+-#endif
+-
+ #define HCOUNTEREN_CY        (1 << 0)
+ #define HCOUNTEREN_TM        (1 << 1)
+ #define HCOUNTEREN_IR        (1 << 2)
+--
+.31.1

-New patch
+[PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/translate.c | 6 ------
+file changed, 6 deletions(-)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     CPUState *cs;
+ } DisasContext;
+-#ifdef TARGET_RISCV64
+-#define CASE_OP_32_64(X) case X: case glue(X, W)
+-#else
+-#define CASE_OP_32_64(X) case X
+-#endif
+-
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+ {
+     return ctx->misa & ext;
+--
+.31.1

-New patch
+[PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions
+This patch removes the insn32-64.decode decode file and consolidates the
+instructions into the general RISC-V insn32.decode decode tree.
+This means that all of the instructions are avaliable in both the 32-bit
+and 64-bit builds. This also means that we run a check to ensure we are
+running a 64-bit softmmu before we execute the 64-bit only instructions.
+This allows us to include the 32-bit instructions in the 64-bit build,
+while also ensuring that 32-bit only software can not execute the
+instructions.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/helper.h                   | 18 +++--
+ target/riscv/insn32-64.decode           | 88 -------------------------
+ target/riscv/insn32.decode              | 67 ++++++++++++++++++-
+ target/riscv/fpu_helper.c               | 16 ++---
+ target/riscv/translate.c                |  9 ++-
+ target/riscv/vector_helper.c            |  4 --
+ target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
+ target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
+ target/riscv/insn_trans/trans_rvf.c.inc |  6 +-
+ target/riscv/insn_trans/trans_rvh.c.inc |  8 ++-
+ target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
+ target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
+ target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
+ target/riscv/meson.build                |  2 +-
+files changed, 166 insertions(+), 150 deletions(-)
+ delete mode 100644 target/riscv/insn32-64.decode
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/helper.h
++++ b/target/riscv/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
+ DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
+ DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
+ DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
+ DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
+ DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
+-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
++DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
+ DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
+ /* Floating Point - Double Precision */
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
+ DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
+ DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
+ DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
+ DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
+ DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
+-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
+-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
++DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
++DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
+ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+ /* Special functions */
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
+ DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
+ DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
+ DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
+-#ifdef TARGET_RISCV64
+ DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamoaddw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
+-#endif
+ DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamoaddw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
+ DEF_HELPER_6(vamoxorw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
+diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+--- a/target/riscv/insn32-64.decode
++++ /dev/null
+@@ -XXX,XX +XXX,XX @@
+-#
+-# RISC-V translation routines for the RV Instruction Set.
+-#
+-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+-#
+-# This program is free software; you can redistribute it and/or modify it
+-# under the terms and conditions of the GNU General Public License,
+-# version 2 or later, as published by the Free Software Foundation.
+-#
+-# This program is distributed in the hope it will be useful, but WITHOUT
+-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+-# more details.
+-#
+-# You should have received a copy of the GNU General Public License along with
+-# this program.  If not, see <http://www.gnu.org/licenses/>.
+-
+-# This is concatenated with insn32.decode for risc64 targets.
+-# Most of the fields and formats are there.
+-
+-%sh5    20:5
+-
+-@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
+-
+-# *** RV64I Base Instruction Set (in addition to RV32I) ***
+-lwu      ............   ..... 110 ..... 0000011 @i
+-ld       ............   ..... 011 ..... 0000011 @i
+-sd       ....... .....  ..... 011 ..... 0100011 @s
+-addiw    ............   ..... 000 ..... 0011011 @i
+-slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
+-srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
+-sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
+-addw     0000000 .....  ..... 000 ..... 0111011 @r
+-subw     0100000 .....  ..... 000 ..... 0111011 @r
+-sllw     0000000 .....  ..... 001 ..... 0111011 @r
+-srlw     0000000 .....  ..... 101 ..... 0111011 @r
+-sraw     0100000 .....  ..... 101 ..... 0111011 @r
+-
+-# *** RV64M Standard Extension (in addition to RV32M) ***
+-mulw     0000001 .....  ..... 000 ..... 0111011 @r
+-divw     0000001 .....  ..... 100 ..... 0111011 @r
+-divuw    0000001 .....  ..... 101 ..... 0111011 @r
+-remw     0000001 .....  ..... 110 ..... 0111011 @r
+-remuw    0000001 .....  ..... 111 ..... 0111011 @r
+-
+-# *** RV64A Standard Extension (in addition to RV32A) ***
+-lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+-sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
+-amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
+-amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
+-amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
+-amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
+-amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
+-amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
+-amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
+-amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
+-amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
+-
+-#*** Vector AMO operations (in addition to Zvamo) ***
+-vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+-
+-# *** RV64F Standard Extension (in addition to RV32F) ***
+-fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
+-fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
+-fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
+-fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
+-
+-# *** RV64D Standard Extension (in addition to RV32D) ***
+-fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
+-fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
+-fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
+-fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
+-fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
+-fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
+-
+-# *** RV32H Base Instruction Set ***
+-hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+-hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+-hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@
+ %rs2       20:5
+ %rs1       15:5
+ %rd        7:5
++%sh5       20:5
+ %sh10    20:10
+ %csr    20:12
+@@ -XXX,XX +XXX,XX @@
+ @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
+ @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
++# Formats 64:
++@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
+ # *** Privileged Instructions ***
+ ecall       000000000000     00000 000 00000 1110011
+@@ -XXX,XX +XXX,XX @@ csrrwi   ............     ..... 101 ..... 1110011 @csr
+ csrrsi   ............     ..... 110 ..... 1110011 @csr
+ csrrci   ............     ..... 111 ..... 1110011 @csr
++# *** RV64I Base Instruction Set (in addition to RV32I) ***
++lwu      ............   ..... 110 ..... 0000011 @i
++ld       ............   ..... 011 ..... 0000011 @i
++sd       ....... .....  ..... 011 ..... 0100011 @s
++addiw    ............   ..... 000 ..... 0011011 @i
++slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
++srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
++sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
++addw     0000000 .....  ..... 000 ..... 0111011 @r
++subw     0100000 .....  ..... 000 ..... 0111011 @r
++sllw     0000000 .....  ..... 001 ..... 0111011 @r
++srlw     0000000 .....  ..... 101 ..... 0111011 @r
++sraw     0100000 .....  ..... 101 ..... 0111011 @r
++
+ # *** RV32M Standard Extension ***
+ mul      0000001 .....  ..... 000 ..... 0110011 @r
+ mulh     0000001 .....  ..... 001 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ divu     0000001 .....  ..... 101 ..... 0110011 @r
+ rem      0000001 .....  ..... 110 ..... 0110011 @r
+ remu     0000001 .....  ..... 111 ..... 0110011 @r
++# *** RV64M Standard Extension (in addition to RV32M) ***
++mulw     0000001 .....  ..... 000 ..... 0111011 @r
++divw     0000001 .....  ..... 100 ..... 0111011 @r
++divuw    0000001 .....  ..... 101 ..... 0111011 @r
++remw     0000001 .....  ..... 110 ..... 0111011 @r
++remuw    0000001 .....  ..... 111 ..... 0111011 @r
++
+ # *** RV32A Standard Extension ***
+ lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
+ sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
+@@ -XXX,XX +XXX,XX @@ amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
+ amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
+ amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
++# *** RV64A Standard Extension (in addition to RV32A) ***
++lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
++sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
++amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
++amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
++amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
++amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
++amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
++amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
++amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
++amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
++amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
++
+ # *** RV32F Standard Extension ***
+ flw        ............   ..... 010 ..... 0000111 @i
+ fsw        .......  ..... ..... 010 ..... 0100111 @s
+@@ -XXX,XX +XXX,XX @@ fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
+ fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
+ fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
++# *** RV64F Standard Extension (in addition to RV32F) ***
++fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
++fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
++fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
++fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
++
+ # *** RV32D Standard Extension ***
+ fld        ............   ..... 011 ..... 0000111 @i
+ fsd        ....... .....  ..... 011 ..... 0100111 @s
+@@ -XXX,XX +XXX,XX @@ fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
+ fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
+ fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
++# *** RV64D Standard Extension (in addition to RV32D) ***
++fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
++fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
++fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
++fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
++fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
++fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
++
+ # *** RV32H Base Instruction Set ***
+ hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
+ hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
+@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
+ hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
+ hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
+-# *** RV32V Extension ***
++# *** RV32H Base Instruction Set ***
++hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
++hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
++hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+ # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
+ vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
+@@ -XXX,XX +XXX,XX @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
+ vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
+ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
++
++#*** Vector AMO operations (in addition to Zvamo) ***
++vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
++vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/fpu_helper.c
++++ b/target/riscv/fpu_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
+     return (int32_t)float32_to_uint32(frs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
++target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+ {
+     float32 frs1 = check_nanbox_s(rs1);
+     return float32_to_int64(frs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
++target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+ {
+     float32 frs1 = check_nanbox_s(rs1);
+     return float32_to_uint64(frs1, &env->fp_status);
+@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
+     return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
+ }
+-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
++uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
+ {
+     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
+ }
+-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
++uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
+ {
+     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
+ }
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
+     return (int32_t)float64_to_uint32(frs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
++target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+ {
+     return float64_to_int64(frs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
++target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+ {
+     return float64_to_uint64(frs1, &env->fp_status);
+ }
+@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
+     return uint32_to_float64((uint32_t)rs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
++uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
+ {
+     return int64_to_float64(rs1, &env->fp_status);
+ }
+-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
++uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
+ {
+     return uint64_to_float64(rs1, &env->fp_status);
+ }
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ EX_SH(12)
+     }                              \
+ } while (0)
++#define REQUIRE_64BIT(ctx) do { \
++    if (is_32bit(ctx)) {        \
++        return false;           \
++    }                           \
++} while (0)
++
+ static int ex_rvc_register(DisasContext *ctx, int reg)
+ {
+     return 8 + reg;
+@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
+     return true;
+ }
+-#ifdef TARGET_RISCV64
+ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
+ {
+     tcg_gen_add_tl(ret, arg1, arg2);
+@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
+     return true;
+ }
+-#endif
+-
+ static bool gen_arith(DisasContext *ctx, arg_r *a,
+                       void(*func)(TCGv, TCGv, TCGv))
+ {
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w,  32, 32, H4, DO_MIN,  l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w,  32, 32, H4, DO_MAX,  l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
+-#ifdef TARGET_RISCV64
+ GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d,  64, 32, H8, DO_ADD,  l)
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
+ GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
+-#endif
+ static inline void
+ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base,       \
+                       GETPC());                                 \
+ }
+-#ifdef TARGET_RISCV64
+ GEN_VEXT_AMO(vamoswapw_v_d, int32_t,  int64_t,  idx_d, clearq)
+ GEN_VEXT_AMO(vamoswapd_v_d, int64_t,  int64_t,  idx_d, clearq)
+ GEN_VEXT_AMO(vamoaddw_v_d,  int32_t,  int64_t,  idx_d, clearq)
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
+ GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
+ GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
+ GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
+-#endif
+ GEN_VEXT_AMO(vamoswapw_v_w, int32_t,  int32_t,  idx_w, clearl)
+ GEN_VEXT_AMO(vamoaddw_v_w,  int32_t,  int32_t,  idx_w, clearl)
+ GEN_VEXT_AMO(vamoxorw_v_w,  int32_t,  int32_t,  idx_w, clearl)
+diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rva.c.inc
++++ b/target/riscv/insn_trans/trans_rva.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+ }
+-#ifdef TARGET_RISCV64
+-
+ static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+ }
+ static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+ }
+ static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+ }
+-#endif
+diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvd.c.inc
++++ b/target/riscv/insn_trans/trans_rvd.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
+     return true;
+ }
+-#ifdef TARGET_RISCV64
+-
+ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
++#ifdef TARGET_RISCV64
+     gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+     return true;
++#else
++    qemu_build_not_reached();
++#endif
+ }
+ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVD);
++#ifdef TARGET_RISCV64
+     TCGv t0 = tcg_temp_new();
+     gen_get_gpr(t0, a->rs1);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+     tcg_temp_free(t0);
+     mark_fs_dirty(ctx);
+     return true;
+-}
++#else
++    qemu_build_not_reached();
+ #endif
++}
+diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvf.c.inc
++++ b/target/riscv/insn_trans/trans_rvf.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
+     return true;
+ }
+-#ifdef TARGET_RISCV64
+ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVF);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVF);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVF);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_FPU;
+     REQUIRE_EXT(ctx, RVF);
+@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+     tcg_temp_free(t0);
+     return true;
+ }
+-#endif
+diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvh.c.inc
++++ b/target/riscv/insn_trans/trans_rvh.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
+ #endif
+ }
+-#ifdef TARGET_RISCV64
+ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVH);
++
+ #ifndef CONFIG_USER_ONLY
+     TCGv t0 = tcg_temp_new();
+     TCGv t1 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVH);
++
+ #ifndef CONFIG_USER_ONLY
+     TCGv t0 = tcg_temp_new();
+     TCGv t1 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVH);
++
+ #ifndef CONFIG_USER_ONLY
+     TCGv t0 = tcg_temp_new();
+     TCGv dat = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+     return false;
+ #endif
+ }
+-#endif
+ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
+ {
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
+     return gen_store(ctx, a, MO_TESL);
+ }
+-#ifdef TARGET_RISCV64
+ static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_load(ctx, a, MO_TEUL);
+ }
+ static bool trans_ld(DisasContext *ctx, arg_ld *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_load(ctx, a, MO_TEQ);
+ }
+ static bool trans_sd(DisasContext *ctx, arg_sd *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_store(ctx, a, MO_TEQ);
+ }
+-#endif
+ static bool trans_addi(DisasContext *ctx, arg_addi *a)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
+     return gen_arith(ctx, a, &tcg_gen_and_tl);
+ }
+-#ifdef TARGET_RISCV64
+ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_arith_imm_tl(ctx, a, &gen_addw);
+ }
+ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv source1;
+     source1 = tcg_temp_new();
+     gen_get_gpr(source1, a->rs1);
+@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv t = tcg_temp_new();
+     gen_get_gpr(t, a->rs1);
+     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv t = tcg_temp_new();
+     gen_get_gpr(t, a->rs1);
+     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+ static bool trans_addw(DisasContext *ctx, arg_addw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_arith(ctx, a, &gen_addw);
+ }
+ static bool trans_subw(DisasContext *ctx, arg_subw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     return gen_arith(ctx, a, &gen_subw);
+ }
+ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv source1 = tcg_temp_new();
+     TCGv source2 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv source1 = tcg_temp_new();
+     TCGv source2 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     TCGv source1 = tcg_temp_new();
+     TCGv source2 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+     return true;
+ }
+-#endif
+ static bool trans_fence(DisasContext *ctx, arg_fence *a)
+ {
+diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvm.c.inc
++++ b/target/riscv/insn_trans/trans_rvm.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
+     return gen_arith(ctx, a, &gen_remu);
+ }
+-#ifdef TARGET_RISCV64
+ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVM);
++
+     return gen_arith(ctx, a, &gen_mulw);
+ }
+ static bool trans_divw(DisasContext *ctx, arg_divw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVM);
++
+     return gen_arith_div_w(ctx, a, &gen_div);
+ }
+ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVM);
++
+     return gen_arith_div_uw(ctx, a, &gen_divu);
+ }
+ static bool trans_remw(DisasContext *ctx, arg_remw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVM);
++
+     return gen_arith_div_w(ctx, a, &gen_rem);
+ }
+ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+ {
++    REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVM);
++
+     return gen_arith_div_uw(ctx, a, &gen_remu);
+ }
+-#endif
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+         gen_helper_vamominuw_v_w,
+         gen_helper_vamomaxuw_v_w
+     };
+-#ifdef TARGET_RISCV64
+     static gen_helper_amo *const fnsd[18] = {
+         gen_helper_vamoswapw_v_d,
+         gen_helper_vamoaddw_v_d,
+@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+         gen_helper_vamominud_v_d,
+         gen_helper_vamomaxud_v_d
+     };
+-#endif
+     if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+         gen_helper_exit_atomic(cpu_env);
+@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+         return true;
+     } else {
+         if (s->sew == 3) {
+-#ifdef TARGET_RISCV64
+-            fn = fnsd[seq];
+-#else
+-            /* Check done in amo_check(). */
+-            g_assert_not_reached();
+-#endif
++            if (!is_32bit(s)) {
++                fn = fnsd[seq];
++            } else {
++                /* Check done in amo_check(). */
++                g_assert_not_reached();
++            }
+         } else {
+             assert(seq < ARRAY_SIZE(fnsw));
+             fn = fnsw[seq];
+@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
+             ((1 << s->sew) >= 4));
+ }
++static bool amo_check64(DisasContext *s, arg_rwdvm* a)
++{
++    return !is_32bit(s) && amo_check(s, a);
++}
++
+ GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
+ GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
+ GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
+ GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
+ GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
+ GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
+-#ifdef TARGET_RISCV64
+-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
+-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+-#endif
++GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
++GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
+ /*
+  *** Vector Integer Arithmetic Instructions
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@ gen32 = [
+ gen64 = [
+   decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+-  decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
++  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+ ]
+ riscv_ss = ss.source_set()
+--
+.31.1

-New patch
+[PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions
+This patch removes the insn16-32.decode and insn16-64.decode decode
+files and consolidates the instructions into the general RISC-V
+insn16.decode decode tree.
+This means that all of the instructions are avaliable in both the 32-bit
+and 64-bit builds. This also means that we run a check to ensure we are
+running a 64-bit softmmu before we execute the 64-bit only instructions.
+This allows us to include the 32-bit instructions in the 64-bit build,
+while also ensuring that 32-bit only software can not execute the
+instructions.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/insn16-32.decode           | 28 -------------------
+ target/riscv/insn16-64.decode           | 36 -------------------------
+ target/riscv/insn16.decode              | 30 +++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvi.c.inc |  6 +++++
+ target/riscv/meson.build                | 11 +++-----
+files changed, 39 insertions(+), 72 deletions(-)
+ delete mode 100644 target/riscv/insn16-32.decode
+ delete mode 100644 target/riscv/insn16-64.decode
+diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+--- a/target/riscv/insn16-32.decode
++++ /dev/null
+@@ -XXX,XX +XXX,XX @@
+-#
+-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+-#
+-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+-#
+-# This program is free software; you can redistribute it and/or modify it
+-# under the terms and conditions of the GNU General Public License,
+-# version 2 or later, as published by the Free Software Foundation.
+-#
+-# This program is distributed in the hope it will be useful, but WITHOUT
+-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+-# more details.
+-#
+-# You should have received a copy of the GNU General Public License along with
+-# this program.  If not, see <http://www.gnu.org/licenses/>.
+-
+-# *** RV32C Standard Extension (Quadrant 0) ***
+-flw               011  ... ... .. ... 00 @cl_w
+-fsw               111  ... ... .. ... 00 @cs_w
+-
+-# *** RV32C Standard Extension (Quadrant 1) ***
+-jal               001     ........... 01 @cj    rd=1  # C.JAL
+-
+-# *** RV32C Standard Extension (Quadrant 2) ***
+-flw               011 .  .....  ..... 10 @c_lwsp
+-fsw               111 .  .....  ..... 10 @c_swsp
+diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+--- a/target/riscv/insn16-64.decode
++++ /dev/null
+@@ -XXX,XX +XXX,XX @@
+-#
+-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+-#
+-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+-#
+-# This program is free software; you can redistribute it and/or modify it
+-# under the terms and conditions of the GNU General Public License,
+-# version 2 or later, as published by the Free Software Foundation.
+-#
+-# This program is distributed in the hope it will be useful, but WITHOUT
+-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+-# more details.
+-#
+-# You should have received a copy of the GNU General Public License along with
+-# this program.  If not, see <http://www.gnu.org/licenses/>.
+-
+-# *** RV64C Standard Extension (Quadrant 0) ***
+-ld                011  ... ... .. ... 00 @cl_d
+-sd                111  ... ... .. ... 00 @cs_d
+-
+-# *** RV64C Standard Extension (Quadrant 1) ***
+-{
+-  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
+-  addiw           001 .  .....  ..... 01 @ci
+-}
+-subw              100 1 11 ... 00 ... 01 @cs_2
+-addw              100 1 11 ... 01 ... 01 @cs_2
+-
+-# *** RV64C Standard Extension (Quadrant 2) ***
+-{
+-  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
+-  ld              011 .  .....  ..... 10 @c_ldsp
+-}
+-sd                111 .  .....  ..... 10 @c_sdsp
+diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn16.decode
++++ b/target/riscv/insn16.decode
+@@ -XXX,XX +XXX,XX @@ lw                010  ... ... .. ... 00 @cl_w
+ fsd               101  ... ... .. ... 00 @cs_d
+ sw                110  ... ... .. ... 00 @cs_w
++# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
++{
++  ld              011  ... ... .. ... 00 @cl_d
++  flw             011  ... ... .. ... 00 @cl_w
++}
++{
++  sd              111  ... ... .. ... 00 @cs_d
++  fsw             111  ... ... .. ... 00 @cs_w
++}
++
+ # *** RV32/64C Standard Extension (Quadrant 1) ***
+ addi              000 .  .....  ..... 01 @ci
+ addi              010 .  .....  ..... 01 @c_li
+@@ -XXX,XX +XXX,XX @@ jal               101     ........... 01 @cj    rd=0  # C.J
+ beq               110  ... ...  ..... 01 @cb_z
+ bne               111  ... ...  ..... 01 @cb_z
++# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
++{
++  c64_illegal     001 -  00000  ----- 01 # c.addiw, RES rd=0
++  addiw           001 .  .....  ..... 01 @ci
++  jal             001     ........... 01 @cj    rd=1  # C.JAL
++}
++subw              100 1 11 ... 00 ... 01 @cs_2
++addw              100 1 11 ... 01 ... 01 @cs_2
++
+ # *** RV32/64C Standard Extension (Quadrant 2) ***
+ slli              000 .  .....  ..... 10 @c_shift2
+ fld               001 .  .....  ..... 10 @c_ldsp
+@@ -XXX,XX +XXX,XX @@ fld               001 .  .....  ..... 10 @c_ldsp
+ }
+ fsd               101   ......  ..... 10 @c_sdsp
+ sw                110 .  .....  ..... 10 @c_swsp
++
++# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
++{
++  c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
++  ld              011 .  .....  ..... 10 @c_ldsp
++  flw             011 .  .....  ..... 10 @c_lwsp
++}
++{
++  sd              111 .  .....  ..... 10 @c_sdsp
++  fsw             111 .  .....  ..... 10 @c_swsp
++}
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
+     return true;
+ }
++static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
++{
++     REQUIRE_64BIT(ctx);
++     return trans_illegal(ctx, a);
++}
++
+ static bool trans_lui(DisasContext *ctx, arg_lui *a)
+ {
+     if (a->rd != 0) {
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@
+ # FIXME extra_args should accept files()
+ dir = meson.current_source_dir()
+-gen32 = [
+-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+-  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+-]
+-gen64 = [
+-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
++gen = [
++  decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
+   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+ ]
+ riscv_ss = ss.source_set()
+-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
+-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
++riscv_ss.add(gen)
+ riscv_ss.add(files(
+   'cpu.c',
+   'cpu_helper.c',
+--
+.31.1

-New patch
+[PULL v3 42/42] target/riscv: Fix the RV64H decode comment
+BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/insn32.decode | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
+ hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
+ hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
+-# *** RV32H Base Instruction Set ***
++# *** RV64H Base Instruction Set ***
+ hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+ hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+--
+.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:

Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122

for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:

hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 6.2

- Deprecate IF_NONE for SiFive OTP
 - Don't reset SiFive OTP content

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset

Thomas Huth (1):
      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE

docs/about/deprecated.rst |  6 ++++++
 hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

From: Thomas Huth <thuth@redhat.com>

Configuring a drive with "if=none" is meant for creation of a backend
only, it should not get automatically assigned to a device frontend.
Use "if=pflash" for the One-Time-Programmable device instead (like
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).

Since the old way of configuring the device has already been published
with the previous QEMU versions, we cannot remove this immediately, but
have to deprecate it and support it for at least two more releases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211119102549.217755-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 6 ++++++
 hw/misc/sifive_u_otp.c    | 9 ++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
 However, short-form booleans are deprecated and full explicit ``arg_name=on``
 form is preferred.
 
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
+
 
 QEMU Machine Protocol (QMP) commands
 ------------------------------------
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 
-    dinfo = drive_get_next(IF_NONE);
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!dinfo) {
+        dinfo = drive_get_next(IF_NONE);
+        if (dinfo) {
+            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
+                        "use \"-drive if=pflash\" instead.");
+        }
+    }
     if (dinfo) {
         int ret;
         uint64_t perm;
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Once a "One Time Programmable" is programmed, it shouldn't be reset.

Do not re-initialize the OTP content in the DeviceReset handler,
initialize it once in the DeviceRealize one.

Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_u_otp.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
 
             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
                 error_setg(errp, "failed to read the initial flash content");
+                return;
             }
         }
     }
-}
-
-static void sifive_u_otp_reset(DeviceState *dev)
-{
-    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
 
     /* Initialize all fuses' initial value to 0xFFs */
     memset(s->fuse, 0xff, sizeof(s->fuse));
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
         serial_data = s->serial;
         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index);
+            error_setg(errp, "failed to write index<%d>", index);
+            return;
         }
 
         serial_data = ~(s->serial);
         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index + 1);
+            error_setg(errp, "failed to write index<%d>", index + 1);
+            return;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
 
     device_class_set_props(dc, sifive_u_otp_properties);
     dc->realize = sifive_u_otp_realize;
-    dc->reset = sifive_u_otp_reset;
 }
 
 static const TypeInfo sifive_u_otp_info = {
-- 
2.31.1

The following changes since commit e4f3ede95ce813d5705c65e1c0e1c80c70739ebb:

Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' into staging (2021-05-10 19:55:06 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210511

for you to fetch changes up to c30a0757f094c107e491820e3d35224eb68859c7:

target/riscv: Fix the RV64H decode comment (2021-05-11 20:02:07 +1000)

----------------------------------------------------------------
A large collection of RISC-V fixes, improvements and features

- Clenaup some left over v1.9 code
 - Documentation improvements
 - Support for the shakti_c machine
 - Internal cleanup of the CSR accesses
 - Updates to the OpenTitan platform
 - Support for the virtio-vga
 - Fix for the saturate subtract in vector extensions
 - Experimental support for the ePMP spec
 - A range of other internal code cleanups and bug fixes

----------------------------------------------------------------
Alexander Wagner (1):
      hw/riscv: Fix OT IBEX reset vector

Alistair Francis (22):
      target/riscv: Convert the RISC-V exceptions to an enum
      target/riscv: Use the RISCVException enum for CSR predicates
      target/riscv: Fix 32-bit HS mode access permissions
      target/riscv: Use the RISCVException enum for CSR operations
      target/riscv: Use RISCVException enum for CSR access
      MAINTAINERS: Update the RISC-V CPU Maintainers
      hw/opentitan: Update the interrupt layout
      hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
      target/riscv: Fix the PMP is locked check when using TOR
      target/riscv: Add the ePMP feature
      target/riscv/pmp: Remove outdated comment
      target/riscv: Add ePMP support for the Ibex CPU
      target/riscv: Remove the hardcoded RVXLEN macro
      target/riscv: Remove the hardcoded SSTATUS_SD macro
      target/riscv: Remove the hardcoded HGATP_MODE macro
      target/riscv: Remove the hardcoded MSTATUS_SD macro
      target/riscv: Remove the hardcoded SATP_MODE macro
      target/riscv: Remove the unused HSTATUS_WPRI macro
      target/riscv: Remove an unused CASE_OP_32_64 macro
      target/riscv: Consolidate RV32/64 32-bit instructions
      target/riscv: Consolidate RV32/64 16-bit instructions
      target/riscv: Fix the RV64H decode comment

Atish Patra (1):
      target/riscv: Remove privilege v1.9 specific CSR related code

Axel Heider (1):
      docs/system/generic-loader.rst: Fix style

Bin Meng (1):
      hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

Dylan Jhong (1):
      target/riscv: Align the data type of reset vector address

Emmanuel Blot (2):
      target/riscv: fix exception index on instruction access fault
      target/riscv: fix a typo with interrupt names

Frank Chang (2):
      target/riscv: fix vrgather macro index variable type bug
      fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

Hou Weiying (4):
      target/riscv: Define ePMP mseccfg
      target/riscv: Add ePMP CSR access functions
      target/riscv: Implementation of enhanced PMP (ePMP)
      target/riscv: Add a config option for ePMP

Jade Fink (1):
      riscv: don't look at SUM when accessing memory from a debugger context

LIU Zhiwei (1):
      target/riscv: Fixup saturate subtract function

Vijai Kumar K (5):
      target/riscv: Add Shakti C class CPU
      riscv: Add initial support for Shakti C machine
      hw/char: Add Shakti UART emulation
      hw/riscv: Connect Shakti UART to Shakti platform
      docs: Add documentation for shakti_c machine

docs/system/generic-loader.rst              |   9 +-
 docs/system/riscv/shakti-c.rst              |  82 +++
 docs/system/target-riscv.rst                |   1 +
 default-configs/devices/riscv64-softmmu.mak |   1 +
 include/hw/char/shakti_uart.h               |  74 +++
 include/hw/riscv/opentitan.h                |  16 +-
 include/hw/riscv/shakti_c.h                 |  75 +++
 target/riscv/cpu.h                          |  42 +-
 target/riscv/cpu_bits.h                     | 114 +---
 target/riscv/helper.h                       |  18 +-
 target/riscv/pmp.h                          |  14 +
 target/riscv/insn16-32.decode               |  28 -
 target/riscv/insn16-64.decode               |  36 --
 target/riscv/insn16.decode                  |  30 +
 target/riscv/insn32-64.decode               |  88 ---
 target/riscv/insn32.decode                  |  67 ++-
 hw/char/shakti_uart.c                       | 185 +++++++
 hw/intc/ibex_plic.c                         |  20 +-
 hw/riscv/opentitan.c                        |  10 +-
 hw/riscv/shakti_c.c                         | 181 ++++++
 hw/riscv/sifive_e.c                         |   2 +-
 target/riscv/cpu.c                          |  26 +-
 target/riscv/cpu_helper.c                   |  88 ++-
 target/riscv/csr.c                          | 824 +++++++++++++++++-----------
 target/riscv/fpu_helper.c                   |  16 +-
 target/riscv/gdbstub.c                      |   8 +-
 target/riscv/machine.c                      |   8 +-
 target/riscv/monitor.c                      |  22 +-
 target/riscv/op_helper.c                    |  18 +-
 target/riscv/pmp.c                          | 218 +++++++-
 target/riscv/translate.c                    |  38 +-
 target/riscv/vector_helper.c                |  18 +-
 fpu/softfloat-specialize.c.inc              |   6 +
 target/riscv/insn_trans/trans_rva.c.inc     |  14 +-
 target/riscv/insn_trans/trans_rvd.c.inc     |  17 +-
 target/riscv/insn_trans/trans_rvf.c.inc     |   6 +-
 target/riscv/insn_trans/trans_rvh.c.inc     |   8 +-
 target/riscv/insn_trans/trans_rvi.c.inc     |  22 +-
 target/riscv/insn_trans/trans_rvm.c.inc     |  12 +-
 target/riscv/insn_trans/trans_rvv.c.inc     |  39 +-
 MAINTAINERS                                 |  14 +-
 hw/char/meson.build                         |   1 +
 hw/char/trace-events                        |   4 +
 hw/riscv/Kconfig                            |  11 +
 hw/riscv/meson.build                        |   1 +
 target/riscv/meson.build                    |  13 +-
 target/riscv/trace-events                   |   3 +
 47 files changed, 1759 insertions(+), 789 deletions(-)
 create mode 100644 docs/system/riscv/shakti-c.rst
 create mode 100644 include/hw/char/shakti_uart.h
 create mode 100644 include/hw/riscv/shakti_c.h
 delete mode 100644 target/riscv/insn16-32.decode
 delete mode 100644 target/riscv/insn16-64.decode
 delete mode 100644 target/riscv/insn32-64.decode
 create mode 100644 hw/char/shakti_uart.c
 create mode 100644 hw/riscv/shakti_c.c

From: Atish Patra <atish.patra@wdc.com>

Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
 - Rebase on latest patches
 - Bump the vmstate_riscv_cpu version_id and minimum_version_id
 ]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 +---
 target/riscv/cpu_bits.h   | 23 ---------------------
 target/riscv/cpu.c        |  2 +-
 target/riscv/cpu_helper.c | 12 +++++------
 target/riscv/csr.c        | 42 ++++++++++-----------------------------
 target/riscv/machine.c    |  8 +++-----
 target/riscv/translate.c  |  4 ++--
 7 files changed, 23 insertions(+), 72 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong mie;
     target_ulong mideleg;
 
-    target_ulong sptbr;  /* until: priv-1.9.1 */
     target_ulong satp;   /* since: priv-1.10.0 */
-    target_ulong sbadaddr;
-    target_ulong mbadaddr;
+    target_ulong stval;
     target_ulong medeleg;
 
     target_ulong stvec;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 /* 32-bit only */
 #define CSR_MSTATUSH        0x310
 
-/* Legacy Counter Setup (priv v1.9.1) */
-/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
-#define CSR_MUCOUNTEREN     0x320
-#define CSR_MSCOUNTEREN     0x321
-#define CSR_MHCOUNTEREN     0x322
-
 /* Machine Trap Handling */
 #define CSR_MSCRATCH        0x340
 #define CSR_MEPC            0x341
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTVAL           0x343
 #define CSR_MIP             0x344
 
-/* Legacy Machine Trap Handling (priv v1.9.1) */
-#define CSR_MBADADDR        0x343
-
 /* Supervisor Trap Setup */
 #define CSR_SSTATUS         0x100
 #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
 #define CSR_STVAL           0x143
 #define CSR_SIP             0x144
 
-/* Legacy Supervisor Trap Handling (priv v1.9.1) */
-#define CSR_SBADADDR        0x143
-
 /* Supervisor Protection and Translation */
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
@@ -XXX,XX +XXX,XX @@
 #define CSR_MHPMCOUNTER30H  0xb9e
 #define CSR_MHPMCOUNTER31H  0xb9f
 
-/* Legacy Machine Protection and Translation (priv v1.9.1) */
-#define CSR_MBASE           0x380
-#define CSR_MBOUND          0x381
-#define CSR_MIBASE          0x382
-#define CSR_MIBOUND         0x383
-#define CSR_MDBASE          0x384
-#define CSR_MDBOUND         0x385
-
 /* mstatus CSR bits */
 #define MSTATUS_UIE         0x00000001
 #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
-#define MSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
 #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
 #define MSTATUS_MXR         0x00080000
-#define MSTATUS_VM          0x1F000000 /* until: priv-1.9.1 */
 #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
 #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
 #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
@@ -XXX,XX +XXX,XX @@
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
-#define SSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
 #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
 #define SSTATUS_MXR         0x00080000
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
     }
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
         env->vscause = env->scause;
         env->scause = env->scause_hs;
 
-        env->vstval = env->sbadaddr;
-        env->sbadaddr = env->stval_hs;
+        env->vstval = env->stval;
+        env->stval = env->stval_hs;
 
         env->vsatp = env->satp;
         env->satp = env->satp_hs;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
         env->scause_hs = env->scause;
         env->scause = env->vscause;
 
-        env->stval_hs = env->sbadaddr;
-        env->sbadaddr = env->vstval;
+        env->stval_hs = env->stval;
+        env->stval = env->vstval;
 
         env->satp_hs = env->satp;
         env->satp = env->vsatp;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         env->mstatus = s;
         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
         env->sepc = env->pc;
-        env->sbadaddr = tval;
+        env->stval = tval;
         env->htval = htval;
         env->pc = (env->stvec >> 2 << 2) +
             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         env->mstatus = s;
         env->mcause = cause | ~(((target_ulong)-1) >> async);
         env->mepc = env->pc;
-        env->mbadaddr = tval;
+        env->mtval = tval;
         env->mtval2 = mtval2;
         env->pc = (env->mtvec >> 2 << 2) +
             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-    *val = env->mcounteren;
-    return 0;
-}
-
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
-{
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-    env->mcounteren = val;
-    return 0;
-}
-
 /* Machine Trap Handling */
 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    *val = env->mbadaddr;
+    *val = env->mtval;
     return 0;
 }
 
-static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
 {
-    env->mbadaddr = val;
+    env->mtval = val;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    *val = env->sbadaddr;
+    *val = env->stval;
     return 0;
 }
 
-static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
 {
-    env->sbadaddr = val;
+    env->stval = val;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 
     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
 
-    [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
-
     /* Machine Trap Handling */
     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
-    [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
+    [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
     /* Supervisor Trap Setup */
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
-    [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
+    [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
 
     /* Supervisor Protection and Translation */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINT32(env.miclaim, RISCVCPU),
         VMSTATE_UINTTL(env.mie, RISCVCPU),
         VMSTATE_UINTTL(env.mideleg, RISCVCPU),
-        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
         VMSTATE_UINTTL(env.satp, RISCVCPU),
-        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
-        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.stval, RISCVCPU),
         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
         VMSTATE_UINTTL(env.stvec, RISCVCPU),
         VMSTATE_UINTTL(env.sepc, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
+static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 {
-    generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
+    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
-- 
2.31.1

From: Axel Heider <axelheider@gmx.de>

Fix style to have a proper description of the parameter 'force-raw'.

Signed-off-by: Axel Heider <axelheider@gmx.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/generic-loader.rst | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/generic-loader.rst
+++ b/docs/system/generic-loader.rst
@@ -XXX,XX +XXX,XX @@ shown below:
   specified in the executable format header. This option should only
   be used for the boot image. This will also cause the image to be
   written to the specified CPU's address space. If not specified, the
-  default is CPU 0. <force-raw> - Setting force-raw=on forces the file
-  to be treated as a raw image. This can be used to load supported
-  executable formats as if they were raw.
+  default is CPU 0.
+
+``<force-raw>``
+  Setting 'force-raw=on' forces the file to be treated as a raw image.
+  This can be used to load supported executable formats as if they
+  were raw.
 
 All values are parsed using the standard QemuOpts parsing. This allows the user
 to specify any values in any format supported. By default the values
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

This was accidentally dropped before. Add it back.

Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_e.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/arch_init.h"
 #include "sysemu/sysemu.h"
 
-static MemMapEntry sifive_e_memmap[] = {
+static const MemMapEntry sifive_e_memmap[] = {
     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 #endif
 };
 
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.

https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
[Changes by AF:
 - Check for mstate->firmware before loading it
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/devices/riscv64-softmmu.mak |   1 +
 include/hw/riscv/shakti_c.h                 |  73 +++++++++
 hw/riscv/shakti_c.c                         | 173 ++++++++++++++++++++
 MAINTAINERS                                 |   7 +
 hw/riscv/Kconfig                            |  10 ++
 hw/riscv/meson.build                        |   1 +
 6 files changed, 265 insertions(+)
 create mode 100644 include/hw/riscv/shakti_c.h
 create mode 100644 hw/riscv/shakti_c.c

diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/devices/riscv64-softmmu.mak
+++ b/default-configs/devices/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SHAKTI_H
+#define HW_SHAKTI_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/boards.h"
+
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+#define RISCV_SHAKTI_SOC(obj) \
+    OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
+
+typedef struct ShaktiCSoCState {
+    /*< private >*/
+    DeviceState parent_obj;
+
+    /*< public >*/
+    RISCVHartArrayState cpus;
+    DeviceState *plic;
+    MemoryRegion rom;
+
+} ShaktiCSoCState;
+
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
+#define RISCV_SHAKTI_MACHINE(obj) \
+    OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
+typedef struct ShaktiCMachineState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+    ShaktiCSoCState soc;
+} ShaktiCMachineState;
+
+enum {
+    SHAKTI_C_ROM,
+    SHAKTI_C_RAM,
+    SHAKTI_C_UART,
+    SHAKTI_C_GPIO,
+    SHAKTI_C_PLIC,
+    SHAKTI_C_CLINT,
+    SHAKTI_C_I2C,
+};
+
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
+/* Including Interrupt ID 0 (no interrupt)*/
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
+/* Excluding Priority 0 */
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/riscv/shakti_c.h"
+#include "qapi/error.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/intc/sifive_clint.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/riscv/boot.h"
+
+
+static const struct MemmapEntry {
+    hwaddr base;
+    hwaddr size;
+} shakti_c_memmap[] = {
+    [SHAKTI_C_ROM]   =  {  0x00001000,  0x2000   },
+    [SHAKTI_C_RAM]   =  {  0x80000000,  0x0      },
+    [SHAKTI_C_UART]  =  {  0x00011300,  0x00040  },
+    [SHAKTI_C_GPIO]  =  {  0x020d0000,  0x00100  },
+    [SHAKTI_C_PLIC]  =  {  0x0c000000,  0x20000  },
+    [SHAKTI_C_CLINT] =  {  0x02000000,  0xc0000  },
+    [SHAKTI_C_I2C]   =  {  0x20c00000,  0x00100  },
+};
+
+static void shakti_c_machine_state_init(MachineState *mstate)
+{
+    ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    /* Allow only Shakti C CPU for this platform */
+    if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
+        error_report("This board can only be used with Shakti C CPU");
+        exit(1);
+    }
+
+    /* Initialize SoC */
+    object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
+                            TYPE_RISCV_SHAKTI_SOC);
+    qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
+
+    /* register RAM */
+    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
+                           mstate->ram_size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                shakti_c_memmap[SHAKTI_C_RAM].base,
+                                main_mem);
+
+    /* ROM reset vector */
+    riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
+                              shakti_c_memmap[SHAKTI_C_RAM].base,
+                              shakti_c_memmap[SHAKTI_C_ROM].base,
+                              shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
+                              NULL);
+    if (mstate->firmware) {
+        riscv_load_firmware(mstate->firmware,
+                            shakti_c_memmap[SHAKTI_C_RAM].base,
+                            NULL);
+    }
+}
+
+static void shakti_c_machine_instance_init(Object *obj)
+{
+}
+
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(klass);
+    mc->desc = "RISC-V Board compatible with Shakti SDK";
+    mc->init = shakti_c_machine_state_init;
+    mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+}
+
+static const TypeInfo shakti_c_machine_type_info = {
+    .name = TYPE_RISCV_SHAKTI_MACHINE,
+    .parent = TYPE_MACHINE,
+    .class_init = shakti_c_machine_class_init,
+    .instance_init = shakti_c_machine_instance_init,
+    .instance_size = sizeof(ShaktiCMachineState),
+};
+
+static void shakti_c_machine_type_info_register(void)
+{
+    type_register_static(&shakti_c_machine_type_info);
+}
+type_init(shakti_c_machine_type_info_register)
+
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+{
+    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
+    MemoryRegion *system_memory = get_system_memory();
+
+    sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+
+    sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+        (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
+        SHAKTI_C_PLIC_NUM_SOURCES,
+        SHAKTI_C_PLIC_NUM_PRIORITIES,
+        SHAKTI_C_PLIC_PRIORITY_BASE,
+        SHAKTI_C_PLIC_PENDING_BASE,
+        SHAKTI_C_PLIC_ENABLE_BASE,
+        SHAKTI_C_PLIC_ENABLE_STRIDE,
+        SHAKTI_C_PLIC_CONTEXT_BASE,
+        SHAKTI_C_PLIC_CONTEXT_STRIDE,
+        shakti_c_memmap[SHAKTI_C_PLIC].size);
+
+    sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+        shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+
+    /* ROM */
+    memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+                           shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+        shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
+}
+
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->realize = shakti_c_soc_state_realize;
+}
+
+static void shakti_c_soc_instance_init(Object *obj)
+{
+    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+
+    object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+
+    /*
+     * CPU type is fixed and we are not supporting passing from commandline yet.
+     * So let it be in instance_init. When supported should use ms->cpu_type
+     * instead of TYPE_RISCV_CPU_SHAKTI_C
+     */
+    object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
+                            TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
+    object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+                            &error_abort);
+}
+
+static const TypeInfo shakti_c_type_info = {
+    .name = TYPE_RISCV_SHAKTI_SOC,
+    .parent = TYPE_DEVICE,
+    .class_init = shakti_c_soc_class_init,
+    .instance_init = shakti_c_soc_instance_init,
+    .instance_size = sizeof(ShaktiCSoCState),
+};
+
+static void shakti_c_type_info_register(void)
+{
+    type_register_static(&shakti_c_type_info);
+}
+type_init(shakti_c_type_info_register)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_dmc.h
 F: include/hw/misc/mchp_pfsoc_ioscb.h
 F: include/hw/misc/mchp_pfsoc_sysreg.h
 
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
 SiFive Machines
 M: Alistair Francis <Alistair.Francis@wdc.com>
 M: Bin Meng <bin.meng@windriver.com>
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
     select IBEX
     select UNIMP
 
+config SHAKTI
+    bool
+
+config SHAKTI_C
+    bool
+    select UNIMP
+    select SHAKTI
+    select SIFIVE_CLINT
+    select SIFIVE_PLIC
+
 config RISCV_VIRT
     bool
     imply PCI_DEVICES
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

This is the initial implementation of Shakti UART.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-4-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/shakti_uart.h |  74 ++++++++++++++
 hw/char/shakti_uart.c         | 185 ++++++++++++++++++++++++++++++++++
 MAINTAINERS                   |   2 +
 hw/char/meson.build           |   1 +
 hw/char/trace-events          |   4 +
 5 files changed, 266 insertions(+)
 create mode 100644 include/hw/char/shakti_uart.h
 create mode 100644 hw/char/shakti_uart.c

diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/char/shakti_uart.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SHAKTI_UART_H
+#define HW_SHAKTI_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define SHAKTI_UART_BAUD        0x00
+#define SHAKTI_UART_TX          0x04
+#define SHAKTI_UART_RX          0x08
+#define SHAKTI_UART_STATUS      0x0C
+#define SHAKTI_UART_DELAY       0x10
+#define SHAKTI_UART_CONTROL     0x14
+#define SHAKTI_UART_INT_EN      0x18
+#define SHAKTI_UART_IQ_CYCLES   0x1C
+#define SHAKTI_UART_RX_THRES    0x20
+
+#define SHAKTI_UART_STATUS_TX_EMPTY     (1 << 0)
+#define SHAKTI_UART_STATUS_TX_FULL      (1 << 1)
+#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
+#define SHAKTI_UART_STATUS_RX_FULL      (1 << 3)
+/* 9600 8N1 is the default setting */
+/* Reg value = (50000000 Hz)/(16 * 9600)*/
+#define SHAKTI_UART_BAUD_DEFAULT    0x0145
+#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
+
+#define TYPE_SHAKTI_UART "shakti-uart"
+#define SHAKTI_UART(obj) \
+    OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t uart_baud;
+    uint32_t uart_tx;
+    uint32_t uart_rx;
+    uint32_t uart_status;
+    uint32_t uart_delay;
+    uint32_t uart_control;
+    uint32_t uart_interrupt;
+    uint32_t uart_iq_cycles;
+    uint32_t uart_rx_threshold;
+
+    CharBackend chr;
+} ShaktiUartState;
+
+#endif /* HW_SHAKTI_UART_H */
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/char/shakti_uart.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/shakti_uart.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+
+static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    ShaktiUartState *s = opaque;
+
+    switch (addr) {
+    case SHAKTI_UART_BAUD:
+        return s->uart_baud;
+    case SHAKTI_UART_RX:
+        qemu_chr_fe_accept_input(&s->chr);
+        s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+        return s->uart_rx;
+    case SHAKTI_UART_STATUS:
+        return s->uart_status;
+    case SHAKTI_UART_DELAY:
+        return s->uart_delay;
+    case SHAKTI_UART_CONTROL:
+        return s->uart_control;
+    case SHAKTI_UART_INT_EN:
+        return s->uart_interrupt;
+    case SHAKTI_UART_IQ_CYCLES:
+        return s->uart_iq_cycles;
+    case SHAKTI_UART_RX_THRES:
+        return s->uart_rx_threshold;
+    default:
+        /* Also handles TX REG which is write only */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+
+    return 0;
+}
+
+static void shakti_uart_write(void *opaque, hwaddr addr,
+                              uint64_t data, unsigned size)
+{
+    ShaktiUartState *s = opaque;
+    uint32_t value = data;
+    uint8_t ch;
+
+    switch (addr) {
+    case SHAKTI_UART_BAUD:
+        s->uart_baud = value;
+        break;
+    case SHAKTI_UART_TX:
+        ch = value;
+        qemu_chr_fe_write_all(&s->chr, &ch, 1);
+        s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
+        break;
+    case SHAKTI_UART_STATUS:
+        s->uart_status = value;
+        break;
+    case SHAKTI_UART_DELAY:
+        s->uart_delay = value;
+        break;
+    case SHAKTI_UART_CONTROL:
+        s->uart_control = value;
+        break;
+    case SHAKTI_UART_INT_EN:
+        s->uart_interrupt = value;
+        break;
+    case SHAKTI_UART_IQ_CYCLES:
+        s->uart_iq_cycles = value;
+        break;
+    case SHAKTI_UART_RX_THRES:
+        s->uart_rx_threshold = value;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps shakti_uart_ops = {
+    .read = shakti_uart_read,
+    .write = shakti_uart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.min_access_size = 1, .max_access_size = 4},
+    .valid = {.min_access_size = 1, .max_access_size = 4},
+};
+
+static void shakti_uart_reset(DeviceState *dev)
+{
+    ShaktiUartState *s = SHAKTI_UART(dev);
+
+    s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
+    s->uart_tx = 0x0;
+    s->uart_rx = 0x0;
+    s->uart_status = 0x0000;
+    s->uart_delay = 0x0000;
+    s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
+    s->uart_interrupt = 0x0000;
+    s->uart_iq_cycles = 0x00;
+    s->uart_rx_threshold = 0x00;
+}
+
+static int shakti_uart_can_receive(void *opaque)
+{
+    ShaktiUartState *s = opaque;
+
+    return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
+}
+
+static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+    ShaktiUartState *s = opaque;
+
+    s->uart_rx = *buf;
+    s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+}
+
+static void shakti_uart_realize(DeviceState *dev, Error **errp)
+{
+    ShaktiUartState *sus = SHAKTI_UART(dev);
+    qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
+                             shakti_uart_receive, NULL, NULL, sus, NULL, true);
+}
+
+static void shakti_uart_instance_init(Object *obj)
+{
+    ShaktiUartState *sus = SHAKTI_UART(obj);
+    memory_region_init_io(&sus->mmio,
+                          obj,
+                          &shakti_uart_ops,
+                          sus,
+                          TYPE_SHAKTI_UART,
+                          0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
+}
+
+static Property shakti_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void shakti_uart_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->reset = shakti_uart_reset;
+    dc->realize = shakti_uart_realize;
+    device_class_set_props(dc, shakti_uart_properties);
+}
+
+static const TypeInfo shakti_uart_info = {
+    .name = TYPE_SHAKTI_UART,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(ShaktiUartState),
+    .class_init = shakti_uart_class_init,
+    .instance_init = shakti_uart_instance_init,
+};
+
+static void shakti_uart_register_types(void)
+{
+    type_register_static(&shakti_uart_info);
+}
+type_init(shakti_uart_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Vijai Kumar K <vijai@behindbytes.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/shakti_c.c
+F: hw/char/shakti_uart.c
 F: include/hw/riscv/shakti_c.h
+F: include/hw/char/shakti_uart.h
 
 SiFive Machines
 M: Alistair Francis <Alistair.Francis@wdc.com>
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
+softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
 softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
 softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
 softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
diff --git a/hw/char/trace-events b/hw/char/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
 nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 
+# shakti_uart.c
+shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
+shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+
 # exynos4210_uart.c
 exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
 exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/shakti_c.h | 2 ++
 hw/riscv/shakti_c.c         | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
 
 #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
 #define RISCV_SHAKTI_SOC(obj) \
@@ -XXX,XX +XXX,XX @@ typedef struct ShaktiCSoCState {
     /*< public >*/
     RISCVHartArrayState cpus;
     DeviceState *plic;
+    ShaktiUartState uart;
     MemoryRegion rom;
 
 } ShaktiCSoCState;
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
         SIFIVE_CLINT_TIMEBASE_FREQ, false);
 
+    qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
+    if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
+                    shakti_c_memmap[SHAKTI_C_UART].base);
+
     /* ROM */
     memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
                            shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_instance_init(Object *obj)
     ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
 
     object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+    object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
 
     /*
      * CPU type is fixed and we are not supporting passing from commandline yet.
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 44 ++++++++++++++++++++-------------------
 target/riscv/cpu.c        |  2 +-
 target/riscv/cpu_helper.c |  4 ++--
 3 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define DEFAULT_RSTVEC      0x1000
 
 /* Exception causes */
-#define EXCP_NONE                                -1 /* sentinel value */
-#define RISCV_EXCP_INST_ADDR_MIS                 0x0
-#define RISCV_EXCP_INST_ACCESS_FAULT             0x1
-#define RISCV_EXCP_ILLEGAL_INST                  0x2
-#define RISCV_EXCP_BREAKPOINT                    0x3
-#define RISCV_EXCP_LOAD_ADDR_MIS                 0x4
-#define RISCV_EXCP_LOAD_ACCESS_FAULT             0x5
-#define RISCV_EXCP_STORE_AMO_ADDR_MIS            0x6
-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT        0x7
-#define RISCV_EXCP_U_ECALL                       0x8
-#define RISCV_EXCP_S_ECALL                      0x9
-#define RISCV_EXCP_VS_ECALL                      0xa
-#define RISCV_EXCP_M_ECALL                       0xb
-#define RISCV_EXCP_INST_PAGE_FAULT               0xc /* since: priv-1.10.0 */
-#define RISCV_EXCP_LOAD_PAGE_FAULT               0xd /* since: priv-1.10.0 */
-#define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
-#define RISCV_EXCP_SEMIHOST                      0x10
-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
+typedef enum RISCVException {
+    RISCV_EXCP_NONE = -1, /* sentinel value */
+    RISCV_EXCP_INST_ADDR_MIS = 0x0,
+    RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
+    RISCV_EXCP_ILLEGAL_INST = 0x2,
+    RISCV_EXCP_BREAKPOINT = 0x3,
+    RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
+    RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
+    RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
+    RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
+    RISCV_EXCP_U_ECALL = 0x8,
+    RISCV_EXCP_S_ECALL = 0x9,
+    RISCV_EXCP_VS_ECALL = 0xa,
+    RISCV_EXCP_M_ECALL = 0xb,
+    RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+    RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+    RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+    RISCV_EXCP_SEMIHOST = 0x10,
+    RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+    RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+    RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+} RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
 #define RISCV_EXCP_INT_MASK                0x7fffffff
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
 #endif
-    cs->exception_index = EXCP_NONE;
+    cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
 }
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
     if (irqs) {
         return ctz64(irqs); /* since non-zero */
     } else {
-        return EXCP_NONE; /* indicates no pending interrupt */
+        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
     }
 }
 #endif
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
 
     env->two_stage_lookup = false;
 #endif
-    cs->exception_index = EXCP_NONE; /* mark handled to qemu */
+    cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h |  3 +-
 target/riscv/csr.c | 80 +++++++++++++++++++++++++---------------------
 2 files changed, 46 insertions(+), 37 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h |  14 +-
 target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------
 2 files changed, 382 insertions(+), 261 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 
 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
                                                  int csrno);
-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
-    target_ulong *ret_value);
-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
-    target_ulong new_value);
-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
-    target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
+typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+                                            target_ulong *ret_value);
+typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+                                             target_ulong new_value);
+typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+                                          target_ulong *ret_value,
+                                          target_ulong new_value,
+                                          target_ulong write_mask);
 
 typedef struct {
     const char *name;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 #endif
 
 /* User Floating-Point CSRs */
-static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_fflags(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = riscv_cpu_get_fflags(env);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_fflags(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_frm(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = env->frm;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_frm(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_fcsr(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
         *val |= (env->vxrm << FSR_VXRM_SHIFT)
                 | (env->vxsat << FSR_VXSAT_SHIFT);
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_fcsr(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
     }
     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vtype(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vtype;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vl(CPURISCVState *env, int csrno,
+                              target_ulong *val)
 {
     *val = env->vl;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vxrm(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->vxrm;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vxrm(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     env->vxrm = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vxsat(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vxsat;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vxsat(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vxsat = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vstart(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->vstart;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstart(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstart = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* User Timers and Counters */
-static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_instret(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 #else
     *val = cpu_get_host_ticks();
 #endif
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_instreth(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 #else
     *val = cpu_get_host_ticks() >> 32;
 #endif
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #if defined(CONFIG_USER_ONLY)
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_time(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = cpu_get_host_ticks();
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = cpu_get_host_ticks() >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #else /* CONFIG_USER_ONLY */
 
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_time(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine constants */
@@ -XXX,XX +XXX,XX @@ static const char valid_vm_1_10_64[16] = {
 };
 
 /* Machine Information Registers */
-static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_zero(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
-    return *val = 0;
+    *val = 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mhartid(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mhartid;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine Trap Setup */
-static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mstatus;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 static int validate_vm(CPURISCVState *env, target_ulong vm)
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
     }
 }
 
-static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
     env->mstatus = mstatus;
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mstatush(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->mstatus >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mstatush(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     uint64_t valh = (uint64_t)val << 32;
     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 
     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_misa(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->misa;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_misa(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
         /* drop write to misa */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* 'I' or 'E' must be present */
     if (!(val & (RVI | RVE))) {
         /* It is not, drop write to misa */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* 'E' excludes all other extensions */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
         /* when we support 'E' we can do "val = RVE;" however
          * for now we just drop writes if 'E' is present.
          */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* Mask extensions that are not supported by this hart */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 
     env->misa = val;
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_medeleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->medeleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_medeleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mideleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mideleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mideleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
     if (riscv_has_ext(env, RVH)) {
         env->mideleg |= VS_MODE_INTERRUPTS;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     *val = env->mie;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mie(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
     env->mie = (env->mie & ~all_ints) | (val & all_ints);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtvec(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->mtvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtvec(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
     if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->mcounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->mcounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine Trap Handling */
-static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mscratch(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->mscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mscratch(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mepc(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->mepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mepc(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mcause(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->mcause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mcause(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mcause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->mtval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->mtval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     RISCVCPU *cpu = env_archcpu(env);
     /* Allow software control of delegable interrupts not claimed by hardware */
@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
         *ret_value = old_mip;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Supervisor Trap Setup */
-static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
     *val = env->mstatus & mask;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsie(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     /* Shift the VS bits to their S bit location in vsie */
     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
         read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsie(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     /* Shift the S bits to their VS bit location in mie */
     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
@@ -XXX,XX +XXX,XX @@ static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
         write_mie(env, CSR_MIE, newval);
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_stvec(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->stvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_stvec(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
     if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_scounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->scounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_scounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->scounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Supervisor Trap Handling */
-static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sscratch(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->sscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sscratch(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->sscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sepc(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->sepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sepc(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     env->sepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_scause(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->scause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_scause(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->scause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_stval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->stval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_stval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->stval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value, target_ulong write_mask)
 {
     /* Shift the S bits to their VS bit location in mip */
     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
@@ -XXX,XX +XXX,XX @@ static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
@@ -XXX,XX +XXX,XX @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 }
 
 /* Supervisor Protection and Translation */
-static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_satp(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
         *val = 0;
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     } else {
         *val = env->satp;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_satp(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-        return 0;
+        return RISCV_EXCP_NONE;
     }
     if (validate_vm(env, get_field(val, SATP_MODE)) &&
         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
     {
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-            return -RISCV_EXCP_ILLEGAL_INST;
+            return RISCV_EXCP_ILLEGAL_INST;
         } else {
             if ((val ^ env->satp) & SATP_ASID) {
                 tlb_flush(env_cpu(env));
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
             env->satp = val;
         }
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Hypervisor Extensions */
-static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hstatus;
     if (!riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
     }
     /* We only support little endian */
     *val = set_field(*val, HSTATUS_VSBE, 0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hstatus = val;
     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
     if (get_field(val, HSTATUS_VSBE) != 0) {
         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hedeleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hedeleg = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hideleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hideleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hideleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hideleg = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hvip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_hip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     *val = env->mie & VS_MODE_INTERRUPTS;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hie(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
     return write_mie(env, CSR_MIE, newval);
 }
 
-static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->hcounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->hcounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->htval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->htval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htinst(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->htinst;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htinst(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgeip(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgatp(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->hgatp;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgatp(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->hgatp = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->htimedelta;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     if (riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         env->htimedelta = val;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->htimedelta >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
+                                        target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Virtual CSR Registers */
-static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->vsstatus;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     uint64_t mask = (target_ulong)-1;
     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstvec(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstvec = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->vsscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
+                                      target_ulong val)
 {
     env->vsscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsepc(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vsepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsepc(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vsepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vscause(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->vscause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vscause(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->vscause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vstval(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->vstval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstval(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsatp(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vsatp;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsatp(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vsatp = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtval2(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->mtval2;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtval2(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->mtval2 = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtinst(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->mtinst;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtinst(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->mtinst = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Physical Memory Protection */
-static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #endif
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
-        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+        if (ret != RISCV_EXCP_NONE) {
+            return -ret;
+        }
+        return 0;
     }
 
     /* if no accessor exists then return failure */
     if (!csr_ops[csrno].read) {
         return -RISCV_EXCP_ILLEGAL_INST;
     }
-
     /* read old value */
     ret = csr_ops[csrno].read(env, csrno, &old_value);
-    if (ret < 0) {
-        return ret;
+    if (ret != RISCV_EXCP_NONE) {
+        return -ret;
     }
 
     /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         new_value = (old_value & ~write_mask) | (new_value & write_mask);
         if (csr_ops[csrno].write) {
             ret = csr_ops[csrno].write(env, csrno, new_value);
-            if (ret < 0) {
-                return ret;
+            if (ret != RISCV_EXCP_NONE) {
+                return -ret;
             }
         }
     }
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h       | 11 +++++++----
 target/riscv/csr.c       | 37 ++++++++++++++++++-------------------
 target/riscv/gdbstub.c   |  8 ++++----
 target/riscv/op_helper.c | 18 +++++++++---------
 4 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pflags = flags;
 }
 
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask);
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                      target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value,
+                           target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+                                 target_ulong *ret_value,
+                                 target_ulong new_value,
+                                 target_ulong write_mask);
 
 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
                                    target_ulong val)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
  */
 
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value,
+                           target_ulong new_value, target_ulong write_mask)
 {
-    int ret;
+    RISCVException ret;
     target_ulong old_value;
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     if ((write_mask && read_only) ||
         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
 
     /* ensure the CSR extension is enabled. */
     if (!cpu->cfg.ext_icsr) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     /* check predicate */
     if (!csr_ops[csrno].predicate) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     ret = csr_ops[csrno].predicate(env, csrno);
     if (ret != RISCV_EXCP_NONE) {
-        return -ret;
+        return ret;
     }
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
-        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
-        if (ret != RISCV_EXCP_NONE) {
-            return -ret;
-        }
-        return 0;
+        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
     }
 
     /* if no accessor exists then return failure */
     if (!csr_ops[csrno].read) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     /* read old value */
     ret = csr_ops[csrno].read(env, csrno, &old_value);
     if (ret != RISCV_EXCP_NONE) {
-        return -ret;
+        return ret;
     }
 
     /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         if (csr_ops[csrno].write) {
             ret = csr_ops[csrno].write(env, csrno, new_value);
             if (ret != RISCV_EXCP_NONE) {
-                return -ret;
+                return ret;
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         *ret_value = old_value;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /*
  * Debugger support.  If not in user mode, set env->debugger before the
  * riscv_csrrw call and clear it after the call.
  */
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+                                 target_ulong *ret_value,
+                                 target_ulong new_value,
+                                 target_ulong write_mask)
 {
-    int ret;
+    RISCVException ret;
 #if !defined(CONFIG_USER_ONLY)
     env->debugger = true;
 #endif
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
          */
         result = riscv_csrrw_debug(env, n - 32, &val,
                                    0, 0);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return gdb_get_regl(buf, val);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
          */
         result = riscv_csrrw_debug(env, n - 32, NULL,
                                    val, -1);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return sizeof(target_ulong);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
         int result;
 
         result = riscv_csrrw_debug(env, n, &val, 0, 0);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return gdb_get_regl(buf, val);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
         int result;
 
         result = riscv_csrrw_debug(env, n, NULL, val, -1);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return sizeof(target_ulong);
         }
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
         target_ulong csr)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, src, -1);
+    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
-- 
2.31.1

Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.

Also add Bin who has been helping with reviews.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
---
 MAINTAINERS | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_ppc.py
 
 RISC-V TCG CPUs
 M: Palmer Dabbelt <palmer@dabbelt.com>
-M: Alistair Francis <Alistair.Francis@wdc.com>
-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+M: Alistair Francis <alistair.francis@wdc.com>
+M: Bin Meng <bin.meng@windriver.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/
-- 
2.31.1

Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h | 16 ++++++++--------
 hw/intc/ibex_plic.c          | 20 ++++++++++----------
 hw/riscv/opentitan.c         |  8 ++++----
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
-    IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
-    IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
-    IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
-    IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
-    IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
-    IBEX_UART_TX_EMPTY_IRQ = 0x23,
-    IBEX_UART_RX_WATERMARK_IRQ = 0x22,
-    IBEX_UART_TX_WATERMARK_IRQ = 0x21,
+    IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+    IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+    IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+    IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+    IBEX_UART0_RX_OVERFLOW_IRQ = 4,
+    IBEX_UART0_TX_EMPTY_IRQ = 3,
+    IBEX_UART0_RX_WATERMARK_IRQ = 2,
+    IBEX_UART0_TX_WATERMARK_IRQ = 1,
 };
 
 #endif
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
 
 static Property ibex_plic_properties[] = {
     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
 
     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
 
-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
+    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
 
-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
+    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
 
-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
+    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
 
-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
+    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
 
-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        0, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_TX_WATERMARK_IRQ));
+                       IBEX_UART0_TX_WATERMARK_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        1, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_RX_WATERMARK_IRQ));
+                       IBEX_UART0_RX_WATERMARK_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        2, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_TX_EMPTY_IRQ));
+                       IBEX_UART0_TX_EMPTY_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        3, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_RX_OVERFLOW_IRQ));
+                       IBEX_UART0_RX_OVERFLOW_IRQ));
 
     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
-- 
2.31.1

From: Jade Fink <qemu@jade.fyi>

Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.

Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
  * @first_stage: Are we in first stage translation?
  *               Second stage is used for hypervisor guest translation
  * @two_stage: Are we going to perform two stage translation
+ * @is_debug: Is this access from a debugger or the monitor?
  */
 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                                 int *prot, target_ulong addr,
                                 target_ulong *fault_pte_addr,
                                 int access_type, int mmu_idx,
-                                bool first_stage, bool two_stage)
+                                bool first_stage, bool two_stage,
+                                bool is_debug)
 {
     /* NOTE: the env->pc value visible here will not be
      * correct, but the value visible to the exception handler
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         widened = 2;
     }
     /* status.SUM will be ignored if execute on background */
-    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
+    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
     switch (vm) {
     case VM_1_10_SV32:
       levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -XXX,XX +XXX,XX @@ restart:
             /* Do the second stage translation on the base PTE address. */
             int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
                                                  base, NULL, MMU_DATA_LOAD,
-                                                 mmu_idx, false, true);
+                                                 mmu_idx, false, true,
+                                                 is_debug);
 
             if (vbase_ret != TRANSLATE_SUCCESS) {
                 if (fault_pte_addr) {
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     int mmu_idx = cpu_mmu_index(&cpu->env, false);
 
     if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
-                             true, riscv_cpu_virt_enabled(env))) {
+                             true, riscv_cpu_virt_enabled(env), true)) {
         return -1;
     }
 
     if (riscv_cpu_virt_enabled(env)) {
         if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
-                                 0, mmu_idx, false, true)) {
+                                 0, mmu_idx, false, true, true)) {
             return -1;
         }
     }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         /* Two stage lookup */
         ret = get_physical_address(env, &pa, &prot, address,
                                    &env->guest_phys_fault_addr, access_type,
-                                   mmu_idx, true, true);
+                                   mmu_idx, true, true, false);
 
         /*
          * A G-stage exception may be triggered during two state lookup.
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             im_address = pa;
 
             ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
-                                       access_type, mmu_idx, false, true);
+                                       access_type, mmu_idx, false, true,
+                                       false);
 
             qemu_log_mask(CPU_LOG_MMU,
                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     } else {
         /* Single stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, NULL,
-                                   access_type, mmu_idx, true, false);
+                                   access_type, mmu_idx, true, false, false);
 
         qemu_log_mask(CPU_LOG_MMU,
                       "%s address=%" VADDR_PRIx " ret %d physical "
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
     int8_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT8_MIN) {
-        res = a > 0 ? INT8_MAX : INT8_MIN;
+        res = a >= 0 ? INT8_MAX : INT8_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
 {
     int16_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT16_MIN) {
-        res = a > 0 ? INT16_MAX : INT16_MIN;
+        res = a >= 0 ? INT16_MAX : INT16_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
 {
     int32_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT32_MIN) {
-        res = a > 0 ? INT32_MAX : INT32_MIN;
+        res = a >= 0 ? INT32_MAX : INT32_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
 {
     int64_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT64_MIN) {
-        res = a > 0 ? INT64_MAX : INT64_MIN;
+        res = a >= 0 ? INT64_MAX : INT64_MIN;
         env->vxsat = 0x1;
     }
     return res;
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Add documentation for Shakti C reference platform.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
[ Changes from Bin Meng:
 - Add missing TOC
 Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
 docs/system/target-riscv.rst   |  1 +
 2 files changed, 83 insertions(+)
 create mode 100644 docs/system/riscv/shakti-c.rst

diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/shakti-c.rst
@@ -XXX,XX +XXX,XX @@
+Shakti C Reference Platform (``shakti_c``)
+==========================================
+
+Shakti C Reference Platform is a reference platform based on arty a7 100t
+for the Shakti SoC.
+
+Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
+is a 64bit RV64GCSUN processor core.
+
+For more details on Shakti SoC, please see:
+https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
+
+For more info on the Shakti C-class core, please see:
+https://c-class.readthedocs.io/en/latest/
+
+Supported devices
+-----------------
+
+The ``shakti_c`` machine supports the following devices:
+
+ * 1 C-class core
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * 1 UART
+
+Boot options
+------------
+
+The ``shakti_c`` machine can start using the standard -bios
+functionality for loading the baremetal application or opensbi.
+
+Boot the machine
+----------------
+
+Shakti SDK
+~~~~~~~~~~
+Shakti SDK can be used to generate the baremetal example UART applications.
+
+.. code-block:: bash
+
+   $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
+   $ cd shakti-sdk
+   $ make software PROGRAM=loopback TARGET=artix7_100t
+
+Binary would be generated in:
+  software/examples/uart_applns/loopback/output/loopback.shakti
+
+You could also download the precompiled example applicatons using below
+commands.
+
+.. code-block:: bash
+
+   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
+   $ unzip shakti_sdk_qemu.zip
+
+Then we can run the UART example using:
+
+.. code-block:: bash
+
+   $ qemu-system-riscv64 -M shakti_c -nographic \
+      -bios path/to/shakti_sdk_qemu/loopback.shakti
+
+OpenSBI
+~~~~~~~
+We can also run OpenSBI with Test Payload.
+
+.. code-block:: bash
+
+   $ git clone https://github.com/riscv/opensbi.git -b v0.9
+   $ cd opensbi
+   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
+   $ export CROSS_COMPILE=riscv64-unknown-elf-
+   $ export FW_FDT_PATH=./shakti.dtb
+   $ make PLATFORM=generic
+
+fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
+Boot it using the below qemu command.
+
+.. code-block:: bash
+
+   $ qemu-system-riscv64 -M shakti_c -nographic \
+      -bios path/to/fw_payload.elf
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    :maxdepth: 1
 
    riscv/microchip-icicle-kit
+   riscv/shakti-c
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.31.1

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
---
 target/riscv/pmp.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
         return 0;
     }
 
-    /* In TOR mode, need to check the lock bit of the next pmp
-     * (if there is a next)
-     */
-    const uint8_t a_field =
-        pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
-    if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
-         (PMP_AMATCH_TOR == a_field)) {
-        return 1;
-    }
-
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val)
 {
     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
+
     if (addr_index < MAX_RISCV_PMPS) {
+        /*
+         * In TOR mode, need to check the lock bit of the next pmp
+         * (if there is a next).
+         */
+        if (addr_index + 1 < MAX_RISCV_PMPS) {
+            uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
+
+            if (pmp_cfg & PMP_LOCK &&
+                PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "ignoring pmpaddr write - pmpcfg + 1 locked\n");
+                return;
+            }
+        }
+
         if (!pmp_is_locked(env, addr_index)) {
             env->pmp_state.pmp[addr_index].addr_reg = val;
             pmp_update_rule(env, addr_index);
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_bits.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Fix build errors
 - Fix some style issues
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu.h        |  1 +
 target/riscv/pmp.h        | 14 ++++++++++++++
 target/riscv/csr.c        | 24 ++++++++++++++++++++++++
 target/riscv/pmp.c        | 34 ++++++++++++++++++++++++++++++++++
 target/riscv/trace-events |  3 +++
 5 files changed, 76 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     /* physical memory protection */
     pmp_table_t pmp_state;
+    target_ulong mseccfg;
 
     /* machine specific rdtime callback */
     uint64_t (*rdtime_fn)(uint32_t);
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
 } pmp_am_t;
 
+typedef enum {
+    MSECCFG_MML  = 1 << 0,
+    MSECCFG_MMWP = 1 << 1,
+    MSECCFG_RLB  = 1 << 2
+} mseccfg_field_t;
+
 typedef struct {
     target_ulong addr_reg;
     uint8_t  cfg_reg;
@@ -XXX,XX +XXX,XX @@ typedef struct {
 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
     target_ulong val);
 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
+
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
+target_ulong mseccfg_csr_read(CPURISCVState *env);
+
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
 int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
+
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 
     return RISCV_EXCP_ILLEGAL_INST;
 }
+
+static RISCVException epmp(CPURISCVState *env, int csrno)
+{
+    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
 #endif
 
 /* User Floating-Point CSRs */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
 }
 
 /* Physical Memory Protection */
+static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+{
+    *val = mseccfg_csr_read(env);
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
+                         target_ulong val)
+{
+    mseccfg_csr_write(env, val);
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
     /* Physical Memory Protection */
+    [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
     return val;
 }
 
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+    int i;
+
+    trace_mseccfg_csr_write(env->mhartid, val);
+
+    /* RLB cannot be enabled if it's already 0 and if any regions are locked */
+    if (!MSECCFG_RLB_ISSET(env)) {
+        for (i = 0; i < MAX_RISCV_PMPS; i++) {
+            if (pmp_is_locked(env, i)) {
+                val &= ~MSECCFG_RLB;
+                break;
+            }
+        }
+    }
+
+    /* Sticky bits */
+    val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+    env->mseccfg = val;
+}
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+    trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+    return env->mseccfg;
+}
+
 /*
  * Calculate the TLB size if the start address or the end address of
  * PMP entry is presented in thie TLB page.
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -XXX,XX +XXX,XX @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
+
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

This commit adds support for ePMP v0.9.1.

The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Update to latest spec
 - Use a switch case to handle ePMP MML permissions
 - Fix a few bugs
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 146 insertions(+), 8 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
 static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
 {
     if (pmp_index < MAX_RISCV_PMPS) {
-        if (!pmp_is_locked(env, pmp_index)) {
-            env->pmp_state.pmp[pmp_index].cfg_reg = val;
-            pmp_update_rule(env, pmp_index);
+        bool locked = true;
+
+        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+            /* mseccfg.RLB is set */
+            if (MSECCFG_RLB_ISSET(env)) {
+                locked = false;
+            }
+
+            /* mseccfg.MML is not set */
+            if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index)) {
+                locked = false;
+            }
+
+            /* mseccfg.MML is set */
+            if (MSECCFG_MML_ISSET(env)) {
+                /* not adding execute bit */
+                if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) {
+                    locked = false;
+                }
+                /* shared region and not adding X bit */
+                if ((val & PMP_LOCK) != PMP_LOCK &&
+                    (val & 0x7) != (PMP_WRITE | PMP_EXEC)) {
+                    locked = false;
+                }
+            }
         } else {
+            if (!pmp_is_locked(env, pmp_index)) {
+                locked = false;
+            }
+        }
+
+        if (locked) {
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
+        } else {
+            env->pmp_state.pmp[pmp_index].cfg_reg = val;
+            pmp_update_rule(env, pmp_index);
         }
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 {
     bool ret;
 
+    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        if (MSECCFG_MMWP_ISSET(env)) {
+            /*
+             * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
+             * so we default to deny all, even for M-mode.
+             */
+            *allowed_privs = 0;
+            return false;
+        } else if (MSECCFG_MML_ISSET(env)) {
+            /*
+             * The Machine Mode Lockdown (mseccfg.MML) bit is set
+             * so we can only execute code in M-mode with an applicable
+             * rule. Other modes are disabled.
+             */
+            if (mode == PRV_M && !(privs & PMP_EXEC)) {
+                ret = true;
+                *allowed_privs = PMP_READ | PMP_WRITE;
+            } else {
+                ret = false;
+                *allowed_privs = 0;
+            }
+
+            return ret;
+        }
+    }
+
     if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
         /*
          * Privileged spec v1.10 states if HW doesn't implement any PMP entry
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
 
         /*
-         * If the PMP entry is not off and the address is in range, do the priv
-         * check
+         * Convert the PMP permissions to match the truth table in the
+         * ePMP spec.
          */
+        const uint8_t epmp_operation =
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
+            (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
+
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-            if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+            /*
+             * If the PMP entry is not off and the address is in range,
+             * do the priv check
+             */
+            if (!MSECCFG_MML_ISSET(env)) {
+                /*
+                 * If mseccfg.MML Bit is not set, do pmp priv check
+                 * This will always apply to regular PMP.
+                 */
+                *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+                if ((mode != PRV_M) || pmp_is_locked(env, i)) {
+                    *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                }
+            } else {
+                /*
+                 * If mseccfg.MML Bit set, do the enhanced pmp priv check
+                 */
+                if (mode == PRV_M) {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 1:
+                    case 4:
+                    case 5:
+                    case 6:
+                    case 7:
+                    case 8:
+                        *allowed_privs = 0;
+                        break;
+                    case 2:
+                    case 3:
+                    case 14:
+                        *allowed_privs = PMP_READ | PMP_WRITE;
+                        break;
+                    case 9:
+                    case 10:
+                        *allowed_privs = PMP_EXEC;
+                        break;
+                    case 11:
+                    case 13:
+                        *allowed_privs = PMP_READ | PMP_EXEC;
+                        break;
+                    case 12:
+                    case 15:
+                        *allowed_privs = PMP_READ;
+                        break;
+                    }
+                } else {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 8:
+                    case 9:
+                    case 12:
+                    case 13:
+                    case 14:
+                        *allowed_privs = 0;
+                        break;
+                    case 1:
+                    case 10:
+                    case 11:
+                        *allowed_privs = PMP_EXEC;
+                        break;
+                    case 2:
+                    case 4:
+                    case 15:
+                        *allowed_privs = PMP_READ;
+                        break;
+                    case 3:
+                    case 6:
+                        *allowed_privs = PMP_READ | PMP_WRITE;
+                        break;
+                    case 5:
+                        *allowed_privs = PMP_READ | PMP_EXEC;
+                        break;
+                    case 7:
+                        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+                        break;
+                    }
+                }
             }
 
             ret = ((privs & *allowed_privs) == privs);
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         uint16_t elen;
         bool mmu;
         bool pmp;
+        bool epmp;
         uint64_t resetvec;
     } cfg;
 };
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     if (cpu->cfg.pmp) {
         set_feature(env, RISCV_FEATURE_PMP);
+
+        /*
+         * Enhanced PMP should only be available
+         * on harts with PMP support
+         */
+        if (cpu->cfg.epmp) {
+            set_feature(env, RISCV_FEATURE_EPMP);
+        }
     }
 
     set_resetvec(env, cpu->cfg.resetvec);
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
-    uint32_t index, i;                                                    \
+    uint64_t index;                                                       \
+    uint32_t i;                                                           \
                                                                           \
     for (i = 0; i < vl; i++) {                                            \
         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
-    uint32_t index = s1, i;                                               \
+    uint64_t index = s1;                                                  \
+    uint32_t i;                                                           \
                                                                           \
     for (i = 0; i < vl; i++) {                                            \
         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
-- 
2.31.1

From: Emmanuel Blot <emmanuel.blot@sifive.com>

When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 
     if (access_type == MMU_DATA_STORE) {
         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-    } else {
+    } else if (access_type == MMU_DATA_LOAD) {
         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+    } else {
+        cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
     }
 
     env->badaddr = addr;
-- 
2.31.1

From: Alexander Wagner <alexander.wagner@ulal.de>

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 fpu/softfloat-specialize.c.inc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
     } else {
         return 1;
     }
+#elif defined(TARGET_RISCV)
+    /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
+    if (infzero) {
+        float_raise(float_flag_invalid, status);
+    }
+    return 3; /* default NaN */
 #elif defined(TARGET_XTENSA)
     /*
      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h | 6 ------
 target/riscv/cpu.c | 6 +++++-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
 
-#if defined(TARGET_RISCV32)
-#define RVXLEN RV32
-#elif defined(TARGET_RISCV64)
-#define RVXLEN RV64
-#endif
-
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 #define RVI RV('I')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#if defined(TARGET_RISCV32)
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#elif defined(TARGET_RISCV64)
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#endif
     set_priv_version(env, PRIV_VERSION_1_11_0);
 }
 
-- 
2.31.1

This also ensures that the SD bit is not writable.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h | 6 ------
 target/riscv/csr.c      | 9 ++++++++-
 2 files changed, 8 insertions(+), 7 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 11 -----------
 target/riscv/cpu_helper.c | 24 +++++++++++++++---------
 2 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_HTIMEDELTA      0x605
 #define CSR_HTIMEDELTAH     0x615
 
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE           SATP32_MODE
-#define HGATP_VMID           SATP32_ASID
-#define HGATP_PPN            SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE           SATP64_MODE
-#define HGATP_VMID           SATP64_ASID
-#define HGATP_PPN            SATP64_PPN
-#endif
-
 /* Virtual CSRs */
 #define CSR_VSSTATUS        0x200
 #define CSR_VSIE            0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         }
         widened = 0;
     } else {
-        base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
-        vm = get_field(env->hgatp, HGATP_MODE);
+        if (riscv_cpu_is_32bit(env)) {
+            base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+            vm = get_field(env->hgatp, SATP32_MODE);
+        } else {
+            base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+            vm = get_field(env->hgatp, SATP64_MODE);
+        }
         widened = 2;
     }
     /* status.SUM will be ignored if execute on background */
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
                                 bool first_stage, bool two_stage)
 {
     CPUState *cs = env_cpu(env);
-    int page_fault_exceptions;
+    int page_fault_exceptions, vm;
+
     if (first_stage) {
-        page_fault_exceptions =
-            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
-            !pmp_violation;
+        vm = get_field(env->satp, SATP_MODE);
+    } else if (riscv_cpu_is_32bit(env)) {
+        vm = get_field(env->hgatp, SATP32_MODE);
     } else {
-        page_fault_exceptions =
-            get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
-            !pmp_violation;
+        vm = get_field(env->hgatp, SATP64_MODE);
     }
+    page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
     switch (access_type) {
     case MMU_INST_FETCH:
         if (riscv_cpu_virt_enabled(env) && !first_stage) {
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h  | 10 ----------
 target/riscv/csr.c       | 12 ++++++++++--
 target/riscv/translate.c | 19 +++++++++++++++++--
 3 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define MXL_RV64            2
 #define MXL_RV128           3
 
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+    if (riscv_cpu_is_32bit(env)) {
+        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+    } else {
+        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+    }
     env->mstatus = mstatus;
 
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     }
 
     /* misa.MXL writes are not supported by QEMU */
-    val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+    if (riscv_cpu_is_32bit(env)) {
+        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+    } else {
+        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+    }
 
     /* flush translation cache */
     if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
     return ctx->misa & ext;
 }
 
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx)  true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx)  false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+    return (ctx->misa & RV32) == RV32;
+}
+#endif
+
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
+    target_ulong sd;
+
     if (ctx->mstatus_fs == MSTATUS_FS) {
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
     ctx->mstatus_fs = MSTATUS_FS;
 
     tmp = tcg_temp_new();
+    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 
     if (ctx->virt_enabled) {
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
     }
     tcg_temp_free(tmp);
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 11 -----------
 target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
 target/riscv/csr.c        | 19 +++++++++++++++----
 target/riscv/monitor.c    | 22 +++++++++++++++++-----
 4 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define SATP64_ASID         0x0FFFF00000000000ULL
 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
 
-#if defined(TARGET_RISCV32)
-#define SATP_MODE           SATP32_MODE
-#define SATP_ASID           SATP32_ASID
-#define SATP_PPN            SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE           SATP64_MODE
-#define SATP_ASID           SATP64_ASID
-#define SATP_PPN            SATP64_PPN
-#endif
-
 /* VM modes (mstatus.vm) privileged ISA 1.9.1 */
 #define VM_1_09_MBARE       0
 #define VM_1_09_MBB         1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 
     if (first_stage == true) {
         if (use_background) {
-            base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
-            vm = get_field(env->vsatp, SATP_MODE);
+            if (riscv_cpu_is_32bit(env)) {
+                base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+                vm = get_field(env->vsatp, SATP32_MODE);
+            } else {
+                base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+                vm = get_field(env->vsatp, SATP64_MODE);
+            }
         } else {
-            base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
-            vm = get_field(env->satp, SATP_MODE);
+            if (riscv_cpu_is_32bit(env)) {
+                base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+                vm = get_field(env->satp, SATP32_MODE);
+            } else {
+                base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+                vm = get_field(env->satp, SATP64_MODE);
+            }
         }
         widened = 0;
     } else {
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 {
     CPUState *cs = env_cpu(env);
     int page_fault_exceptions, vm;
+    uint64_t stap_mode;
+
+    if (riscv_cpu_is_32bit(env)) {
+        stap_mode = SATP32_MODE;
+    } else {
+        stap_mode = SATP64_MODE;
+    }
 
     if (first_stage) {
-        vm = get_field(env->satp, SATP_MODE);
-    } else if (riscv_cpu_is_32bit(env)) {
-        vm = get_field(env->hgatp, SATP32_MODE);
+        vm = get_field(env->satp, stap_mode);
     } else {
-        vm = get_field(env->hgatp, SATP64_MODE);
+        vm = get_field(env->hgatp, stap_mode);
     }
+
     page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
 
     switch (access_type) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
 static RISCVException write_satp(CPURISCVState *env, int csrno,
                                  target_ulong val)
 {
+    int vm, mask, asid;
+
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
         return RISCV_EXCP_NONE;
     }
-    if (validate_vm(env, get_field(val, SATP_MODE)) &&
-        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
-    {
+
+    if (riscv_cpu_is_32bit(env)) {
+        vm = validate_vm(env, get_field(val, SATP32_MODE));
+        mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+        asid = (val ^ env->satp) & SATP32_ASID;
+    } else {
+        vm = validate_vm(env, get_field(val, SATP64_MODE));
+        mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+        asid = (val ^ env->satp) & SATP64_ASID;
+    }
+
+    if (vm && mask) {
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return RISCV_EXCP_ILLEGAL_INST;
         } else {
-            if ((val ^ env->satp) & SATP_ASID) {
+            if (asid) {
                 tlb_flush(env_cpu(env));
             }
             env->satp = val;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
     target_ulong last_size;
     int last_attr;
 
-    base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+    if (riscv_cpu_is_32bit(env)) {
+        base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+        vm = get_field(env->satp, SATP32_MODE);
+    } else {
+        base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+        vm = get_field(env->satp, SATP64_MODE);
+    }
 
-    vm = get_field(env->satp, SATP_MODE);
     switch (vm) {
     case VM_1_10_SV32:
         levels = 2;
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
         return;
     }
 
-    if (!(env->satp & SATP_MODE)) {
-        monitor_printf(mon, "No translation or protection\n");
-        return;
+    if (riscv_cpu_is_32bit(env)) {
+        if (!(env->satp & SATP32_MODE)) {
+            monitor_printf(mon, "No translation or protection\n");
+            return;
+        }
+    } else {
+        if (!(env->satp & SATP64_MODE)) {
+            monitor_printf(mon, "No translation or protection\n");
+            return;
+        }
     }
 
     mem_info_svxx(mon, env);
-- 
2.31.1

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/helper.h                   | 18 +++--
 target/riscv/insn32-64.decode           | 88 -------------------------
 target/riscv/insn32.decode              | 67 ++++++++++++++++++-
 target/riscv/fpu_helper.c               | 16 ++---
 target/riscv/translate.c                |  9 ++-
 target/riscv/vector_helper.c            |  4 --
 target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
 target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
 target/riscv/insn_trans/trans_rvf.c.inc |  6 +-
 target/riscv/insn_trans/trans_rvh.c.inc |  8 ++-
 target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
 target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
 target/riscv/meson.build                |  2 +-
 14 files changed, 166 insertions(+), 150 deletions(-)
 delete mode 100644 target/riscv/insn32-64.decode

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Floating Point - Double Precision */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Special functions */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
-#ifdef TARGET_RISCV64
 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoaddw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-#endif
 DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoaddw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoxorw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn32-64.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RV Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# This is concatenated with insn32.decode for risc64 targets.
-# Most of the fields and formats are there.
-
-%sh5    20:5
-
-@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
-
-# *** RV64I Base Instruction Set (in addition to RV32I) ***
-lwu      ............   ..... 110 ..... 0000011 @i
-ld       ............   ..... 011 ..... 0000011 @i
-sd       ....... .....  ..... 011 ..... 0100011 @s
-addiw    ............   ..... 000 ..... 0011011 @i
-slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
-srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
-sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
-addw     0000000 .....  ..... 000 ..... 0111011 @r
-subw     0100000 .....  ..... 000 ..... 0111011 @r
-sllw     0000000 .....  ..... 001 ..... 0111011 @r
-srlw     0000000 .....  ..... 101 ..... 0111011 @r
-sraw     0100000 .....  ..... 101 ..... 0111011 @r
-
-# *** RV64M Standard Extension (in addition to RV32M) ***
-mulw     0000001 .....  ..... 000 ..... 0111011 @r
-divw     0000001 .....  ..... 100 ..... 0111011 @r
-divuw    0000001 .....  ..... 101 ..... 0111011 @r
-remw     0000001 .....  ..... 110 ..... 0111011 @r
-remuw    0000001 .....  ..... 111 ..... 0111011 @r
-
-# *** RV64A Standard Extension (in addition to RV32A) ***
-lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
-sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
-amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
-amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
-amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
-amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
-
-#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-
-# *** RV64F Standard Extension (in addition to RV32F) ***
-fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
-fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
-
-# *** RV64D Standard Extension (in addition to RV32D) ***
-fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
-fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
-fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
-fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
-
-# *** RV32H Base Instruction Set ***
-hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
-hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
-hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %rs2       20:5
 %rs1       15:5
 %rd        7:5
+%sh5       20:5
 
 %sh10    20:10
 %csr    20:12
@@ -XXX,XX +XXX,XX @@
 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 
+# Formats 64:
+@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
 
 # *** Privileged Instructions ***
 ecall       000000000000     00000 000 00000 1110011
@@ -XXX,XX +XXX,XX @@ csrrwi   ............     ..... 101 ..... 1110011 @csr
 csrrsi   ............     ..... 110 ..... 1110011 @csr
 csrrci   ............     ..... 111 ..... 1110011 @csr
 
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu      ............   ..... 110 ..... 0000011 @i
+ld       ............   ..... 011 ..... 0000011 @i
+sd       ....... .....  ..... 011 ..... 0100011 @s
+addiw    ............   ..... 000 ..... 0011011 @i
+slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
+srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
+sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
+addw     0000000 .....  ..... 000 ..... 0111011 @r
+subw     0100000 .....  ..... 000 ..... 0111011 @r
+sllw     0000000 .....  ..... 001 ..... 0111011 @r
+srlw     0000000 .....  ..... 101 ..... 0111011 @r
+sraw     0100000 .....  ..... 101 ..... 0111011 @r
+
 # *** RV32M Standard Extension ***
 mul      0000001 .....  ..... 000 ..... 0110011 @r
 mulh     0000001 .....  ..... 001 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ divu     0000001 .....  ..... 101 ..... 0110011 @r
 rem      0000001 .....  ..... 110 ..... 0110011 @r
 remu     0000001 .....  ..... 111 ..... 0110011 @r
 
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw     0000001 .....  ..... 000 ..... 0111011 @r
+divw     0000001 .....  ..... 100 ..... 0111011 @r
+divuw    0000001 .....  ..... 101 ..... 0111011 @r
+remw     0000001 .....  ..... 110 ..... 0111011 @r
+remuw    0000001 .....  ..... 111 ..... 0111011 @r
+
 # *** RV32A Standard Extension ***
 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
@@ -XXX,XX +XXX,XX @@ amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
 # *** RV32F Standard Extension ***
 flw        ............   ..... 010 ..... 0000111 @i
 fsw        .......  ..... ..... 010 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
+
 # *** RV32D Standard Extension ***
 fld        ............   ..... 011 ..... 0000111 @i
 fsd        ....... .....  ..... 011 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
+
 # *** RV32H Base Instruction Set ***
 hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 
-# *** RV32V Extension ***
+# *** RV32H Base Instruction Set ***
+hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 
 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
@@ -XXX,XX +XXX,XX @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
+
+#*** Vector AMO operations (in addition to Zvamo) ***
+vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
     return (int32_t)float32_to_uint32(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_uint64(frs1, &env->fp_status);
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
     return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
     return (int32_t)float64_to_uint32(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_uint64(frs1, &env->fp_status);
 }
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
     return uint32_to_float64((uint32_t)rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
 {
     return int64_to_float64(rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
 {
     return uint64_to_float64(rs1, &env->fp_status);
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
+#define REQUIRE_64BIT(ctx) do { \
+    if (is_32bit(ctx)) {        \
+        return false;           \
+    }                           \
+} while (0)
+
 static int ex_rvc_register(DisasContext *ctx, int reg)
 {
     return 8 + reg;
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
     return true;
 }
 
-#ifdef TARGET_RISCV64
 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_add_tl(ret, arg1, arg2);
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
     return true;
 }
 
-#endif
-
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w,  32, 32, H4, DO_MIN,  l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w,  32, 32, H4, DO_MAX,  l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
-#ifdef TARGET_RISCV64
 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d,  64, 32, H8, DO_ADD,  l)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
-#endif
 
 static inline void
 vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base,       \
                       GETPC());                                 \
 }
 
-#ifdef TARGET_RISCV64
 GEN_VEXT_AMO(vamoswapw_v_d, int32_t,  int64_t,  idx_d, clearq)
 GEN_VEXT_AMO(vamoswapd_v_d, int64_t,  int64_t,  idx_d, clearq)
 GEN_VEXT_AMO(vamoaddw_v_d,  int32_t,  int64_t,  idx_d, clearq)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
-#endif
 GEN_VEXT_AMO(vamoswapw_v_w, int32_t,  int32_t,  idx_w, clearl)
 GEN_VEXT_AMO(vamoaddw_v_w,  int32_t,  int32_t,  idx_w, clearl)
 GEN_VEXT_AMO(vamoxorw_v_w,  int32_t,  int32_t,  idx_w, clearl)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
 }
 
-#ifdef TARGET_RISCV64
-
 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
 }
 
 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
     return true;
 }
 
-#ifdef TARGET_RISCV64
-
 static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
 
 static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
 
 static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+#ifdef TARGET_RISCV64
     gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
     return true;
+#else
+    qemu_build_not_reached();
+#endif
 }
 
 static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
 
 static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
 
 static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+#ifdef TARGET_RISCV64
     TCGv t0 = tcg_temp_new();
     gen_get_gpr(t0, a->rs1);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
     tcg_temp_free(t0);
     mark_fs_dirty(ctx);
     return true;
-}
+#else
+    qemu_build_not_reached();
 #endif
+}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
     return true;
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
 
 static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
 
 static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
 
 static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
     tcg_temp_free(t0);
     return true;
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
 #endif
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 
 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 
 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv dat = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
     return false;
 #endif
 }
-#endif
 
 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
 {
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
     return gen_store(ctx, a, MO_TESL);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_load(ctx, a, MO_TEUL);
 }
 
 static bool trans_ld(DisasContext *ctx, arg_ld *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_load(ctx, a, MO_TEQ);
 }
 
 static bool trans_sd(DisasContext *ctx, arg_sd *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_store(ctx, a, MO_TEQ);
 }
-#endif
 
 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 {
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
     return gen_arith(ctx, a, &tcg_gen_and_tl);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith_imm_tl(ctx, a, &gen_addw);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1;
     source1 = tcg_temp_new();
     gen_get_gpr(source1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
     gen_get_gpr(t, a->rs1);
     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
     gen_get_gpr(t, a->rs1);
     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith(ctx, a, &gen_addw);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith(ctx, a, &gen_subw);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 
     return true;
 }
-#endif
 
 static bool trans_fence(DisasContext *ctx, arg_fence *a)
 {
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
     return gen_arith(ctx, a, &gen_remu);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith(ctx, a, &gen_mulw);
 }
 
 static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_w(ctx, a, &gen_div);
 }
 
 static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_uw(ctx, a, &gen_divu);
 }
 
 static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_w(ctx, a, &gen_rem);
 }
 
 static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_uw(ctx, a, &gen_remu);
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         gen_helper_vamominuw_v_w,
         gen_helper_vamomaxuw_v_w
     };
-#ifdef TARGET_RISCV64
     static gen_helper_amo *const fnsd[18] = {
         gen_helper_vamoswapw_v_d,
         gen_helper_vamoaddw_v_d,
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         gen_helper_vamominud_v_d,
         gen_helper_vamomaxud_v_d
     };
-#endif
 
     if (tb_cflags(s->base.tb) & CF_PARALLEL) {
         gen_helper_exit_atomic(cpu_env);
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         return true;
     } else {
         if (s->sew == 3) {
-#ifdef TARGET_RISCV64
-            fn = fnsd[seq];
-#else
-            /* Check done in amo_check(). */
-            g_assert_not_reached();
-#endif
+            if (!is_32bit(s)) {
+                fn = fnsd[seq];
+            } else {
+                /* Check done in amo_check(). */
+                g_assert_not_reached();
+            }
         } else {
             assert(seq < ARRAY_SIZE(fnsw));
             fn = fnsw[seq];
@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
             ((1 << s->sew) >= 4));
 }
 
+static bool amo_check64(DisasContext *s, arg_rwdvm* a)
+{
+    return !is_32bit(s) && amo_check(s, a);
+}
+
 GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
-#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
-#endif
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
 
 /*
  *** Vector Integer Arithmetic Instructions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ gen32 = [
 
 gen64 = [
   decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
-  decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
+  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
 ]
 
 riscv_ss = ss.source_set()
-- 
2.31.1

This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/insn16-32.decode           | 28 -------------------
 target/riscv/insn16-64.decode           | 36 -------------------------
 target/riscv/insn16.decode              | 30 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc |  6 +++++
 target/riscv/meson.build                | 11 +++-----
 5 files changed, 39 insertions(+), 72 deletions(-)
 delete mode 100644 target/riscv/insn16-32.decode
 delete mode 100644 target/riscv/insn16-64.decode

diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn16-32.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV32C Standard Extension (Quadrant 0) ***
-flw               011  ... ... .. ... 00 @cl_w
-fsw               111  ... ... .. ... 00 @cs_w
-
-# *** RV32C Standard Extension (Quadrant 1) ***
-jal               001     ........... 01 @cj    rd=1  # C.JAL
-
-# *** RV32C Standard Extension (Quadrant 2) ***
-flw               011 .  .....  ..... 10 @c_lwsp
-fsw               111 .  .....  ..... 10 @c_swsp
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn16-64.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV64C Standard Extension (Quadrant 0) ***
-ld                011  ... ... .. ... 00 @cl_d
-sd                111  ... ... .. ... 00 @cs_d
-
-# *** RV64C Standard Extension (Quadrant 1) ***
-{
-  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
-  addiw           001 .  .....  ..... 01 @ci
-}
-subw              100 1 11 ... 00 ... 01 @cs_2
-addw              100 1 11 ... 01 ... 01 @cs_2
-
-# *** RV64C Standard Extension (Quadrant 2) ***
-{
-  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
-  ld              011 .  .....  ..... 10 @c_ldsp
-}
-sd                111 .  .....  ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -XXX,XX +XXX,XX @@ lw                010  ... ... .. ... 00 @cl_w
 fsd               101  ... ... .. ... 00 @cs_d
 sw                110  ... ... .. ... 00 @cs_w
 
+# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
+{
+  ld              011  ... ... .. ... 00 @cl_d
+  flw             011  ... ... .. ... 00 @cl_w
+}
+{
+  sd              111  ... ... .. ... 00 @cs_d
+  fsw             111  ... ... .. ... 00 @cs_w
+}
+
 # *** RV32/64C Standard Extension (Quadrant 1) ***
 addi              000 .  .....  ..... 01 @ci
 addi              010 .  .....  ..... 01 @c_li
@@ -XXX,XX +XXX,XX @@ jal               101     ........... 01 @cj    rd=0  # C.J
 beq               110  ... ...  ..... 01 @cb_z
 bne               111  ... ...  ..... 01 @cb_z
 
+# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
+{
+  c64_illegal     001 -  00000  ----- 01 # c.addiw, RES rd=0
+  addiw           001 .  .....  ..... 01 @ci
+  jal             001     ........... 01 @cj    rd=1  # C.JAL
+}
+subw              100 1 11 ... 00 ... 01 @cs_2
+addw              100 1 11 ... 01 ... 01 @cs_2
+
 # *** RV32/64C Standard Extension (Quadrant 2) ***
 slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
@@ -XXX,XX +XXX,XX @@ fld               001 .  .....  ..... 10 @c_ldsp
 }
 fsd               101   ......  ..... 10 @c_sdsp
 sw                110 .  .....  ..... 10 @c_swsp
+
+# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
+{
+  c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
+  ld              011 .  .....  ..... 10 @c_ldsp
+  flw             011 .  .....  ..... 10 @c_lwsp
+}
+{
+  sd              111 .  .....  ..... 10 @c_sdsp
+  fsw             111 .  .....  ..... 10 @c_swsp
+}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
     return true;
 }
 
+static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
+{
+     REQUIRE_64BIT(ctx);
+     return trans_illegal(ctx, a);
+}
+
 static bool trans_lui(DisasContext *ctx, arg_lui *a)
 {
     if (a->rd != 0) {
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 # FIXME extra_args should accept files()
 dir = meson.current_source_dir()
-gen32 = [
-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
-  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
-]
 
-gen64 = [
-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+gen = [
+  decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
 ]
 
 riscv_ss = ss.source_set()
-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
+riscv_ss.add(gen)
 riscv_ss.add(files(
   'cpu.c',
   'cpu_helper.c',
-- 
2.31.1