| 1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: | 3 | Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03 12:47:58 +0000) |
| 4 | |||
| 5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | ||
| 6 | 4 | ||
| 7 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 8 | 6 | ||
| 9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 | 7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103 |
| 10 | 8 | ||
| 11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: | 9 | for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870: |
| 12 | 10 | ||
| 13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) | 11 | target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03 07:17:23 -0800) |
| 14 | 12 | ||
| 15 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 16 | Seventh RISC-V PR for QEMU 6.2 | 14 | This series adds support for migration to RISC-V QEMU and expands the |
| 17 | 15 | Microchip PFSoC to allow unmodified HSS and Linux boots. | |
| 18 | - Deprecate IF_NONE for SiFive OTP | ||
| 19 | - Don't reset SiFive OTP content | ||
| 20 | 16 | ||
| 21 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 22 | Philippe Mathieu-Daudé (1): | 18 | Anup Patel (2): |
| 23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset | 19 | hw/riscv: sifive_u: Allow passing custom DTB |
| 20 | hw/riscv: virt: Allow passing custom DTB | ||
| 24 | 21 | ||
| 25 | Thomas Huth (1): | 22 | Bin Meng (10): |
| 26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE | 23 | hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps |
| 24 | hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support | ||
| 25 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | ||
| 26 | hw/misc: Add Microchip PolarFire SoC IOSCB module support | ||
| 27 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | ||
| 28 | hw/misc: Add Microchip PolarFire SoC SYSREG module support | ||
| 29 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | ||
| 30 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | ||
| 31 | hw/riscv: microchip_pfsoc: Correct DDR memory map | ||
| 32 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | ||
| 27 | 33 | ||
| 28 | docs/about/deprecated.rst | 6 ++++++ | 34 | Xinhao Zhang (1): |
| 29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- | 35 | target/riscv/csr.c : add space before the open parenthesis '(' |
| 30 | 2 files changed, 19 insertions(+), 9 deletions(-) | ||
| 31 | 36 | ||
| 37 | Yifei Jiang (6): | ||
| 38 | target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit | ||
| 39 | target/riscv: Add basic vmstate description of CPU | ||
| 40 | target/riscv: Add PMP state description | ||
| 41 | target/riscv: Add H extension state description | ||
| 42 | target/riscv: Add V extension state description | ||
| 43 | target/riscv: Add sifive_plic vmstate | ||
| 44 | |||
| 45 | include/hw/intc/sifive_plic.h | 1 + | ||
| 46 | include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ | ||
| 47 | include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ | ||
| 48 | include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ | ||
| 49 | include/hw/riscv/microchip_pfsoc.h | 18 ++- | ||
| 50 | target/riscv/cpu.h | 24 ++-- | ||
| 51 | target/riscv/cpu_bits.h | 19 +-- | ||
| 52 | target/riscv/internals.h | 4 + | ||
| 53 | target/riscv/pmp.h | 2 + | ||
| 54 | hw/intc/sifive_plic.c | 26 +++- | ||
| 55 | hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ | ||
| 56 | hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ | ||
| 57 | hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ | ||
| 58 | hw/riscv/microchip_pfsoc.c | 125 ++++++++++++++++--- | ||
| 59 | hw/riscv/sifive_u.c | 28 +++-- | ||
| 60 | hw/riscv/virt.c | 27 ++-- | ||
| 61 | target/riscv/cpu.c | 16 +-- | ||
| 62 | target/riscv/cpu_helper.c | 35 ++---- | ||
| 63 | target/riscv/csr.c | 20 +-- | ||
| 64 | target/riscv/machine.c | 196 +++++++++++++++++++++++++++++ | ||
| 65 | target/riscv/op_helper.c | 11 +- | ||
| 66 | target/riscv/pmp.c | 29 +++-- | ||
| 67 | MAINTAINERS | 6 + | ||
| 68 | hw/misc/Kconfig | 9 ++ | ||
| 69 | hw/misc/meson.build | 3 + | ||
| 70 | hw/riscv/Kconfig | 3 + | ||
| 71 | target/riscv/meson.build | 3 +- | ||
| 72 | 27 files changed, 1180 insertions(+), 127 deletions(-) | ||
| 73 | create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h | ||
| 74 | create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 75 | create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h | ||
| 76 | create mode 100644 hw/misc/mchp_pfsoc_dmc.c | ||
| 77 | create mode 100644 hw/misc/mchp_pfsoc_ioscb.c | ||
| 78 | create mode 100644 hw/misc/mchp_pfsoc_sysreg.c | ||
| 79 | create mode 100644 target/riscv/machine.c | ||
| 80 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Anup Patel <anup.patel@wdc.com> | ||
| 1 | 2 | ||
| 3 | Extend sifive_u machine to allow passing custom DTB using "-dtb" | ||
| 4 | command-line parameter. This will help users pass modified DTB | ||
| 5 | or Linux SiFive DTB to sifive_u machine. | ||
| 6 | |||
| 7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20201022053225.2596110-1-anup.patel@wdc.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | hw/riscv/sifive_u.c | 28 ++++++++++++++++++++-------- | ||
| 13 | 1 file changed, 20 insertions(+), 8 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/riscv/sifive_u.c | ||
| 18 | +++ b/hw/riscv/sifive_u.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, | ||
| 20 | int cpu; | ||
| 21 | uint32_t *cells; | ||
| 22 | char *nodename; | ||
| 23 | + const char *dtb_filename; | ||
| 24 | char ethclk_names[] = "pclk\0hclk"; | ||
| 25 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; | ||
| 26 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; | ||
| 27 | |||
| 28 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
| 29 | - if (!fdt) { | ||
| 30 | - error_report("create_device_tree() failed"); | ||
| 31 | - exit(1); | ||
| 32 | + dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | ||
| 33 | + if (dtb_filename) { | ||
| 34 | + fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); | ||
| 35 | + if (!fdt) { | ||
| 36 | + error_report("load_device_tree() failed"); | ||
| 37 | + exit(1); | ||
| 38 | + } | ||
| 39 | + goto update_bootargs; | ||
| 40 | + } else { | ||
| 41 | + fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
| 42 | + if (!fdt) { | ||
| 43 | + error_report("create_device_tree() failed"); | ||
| 44 | + exit(1); | ||
| 45 | + } | ||
| 46 | } | ||
| 47 | |||
| 48 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); | ||
| 49 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, | ||
| 50 | |||
| 51 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
| 52 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | ||
| 53 | - if (cmdline) { | ||
| 54 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
| 55 | - } | ||
| 56 | - | ||
| 57 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | ||
| 58 | |||
| 59 | g_free(nodename); | ||
| 60 | + | ||
| 61 | +update_bootargs: | ||
| 62 | + if (cmdline) { | ||
| 63 | + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
| 64 | + } | ||
| 65 | } | ||
| 66 | |||
| 67 | static void sifive_u_machine_reset(void *opaque, int n, int level) | ||
| 68 | -- | ||
| 69 | 2.28.0 | ||
| 70 | |||
| 71 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Anup Patel <anup.patel@wdc.com> | ||
| 1 | 2 | ||
| 3 | Extend virt machine to allow passing custom DTB using "-dtb" | ||
| 4 | command-line parameter. This will help users pass modified DTB | ||
| 5 | to virt machine. | ||
| 6 | |||
| 7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20201022053225.2596110-2-anup.patel@wdc.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | hw/riscv/virt.c | 27 ++++++++++++++++++++------- | ||
| 13 | 1 file changed, 20 insertions(+), 7 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/riscv/virt.c | ||
| 18 | +++ b/hw/riscv/virt.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
| 20 | { | ||
| 21 | void *fdt; | ||
| 22 | int i, cpu, socket; | ||
| 23 | + const char *dtb_filename; | ||
| 24 | MachineState *mc = MACHINE(s); | ||
| 25 | uint64_t addr, size; | ||
| 26 | uint32_t *clint_cells, *plic_cells; | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
| 28 | hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; | ||
| 29 | hwaddr flashbase = virt_memmap[VIRT_FLASH].base; | ||
| 30 | |||
| 31 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
| 32 | - if (!fdt) { | ||
| 33 | - error_report("create_device_tree() failed"); | ||
| 34 | - exit(1); | ||
| 35 | + dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | ||
| 36 | + if (dtb_filename) { | ||
| 37 | + fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); | ||
| 38 | + if (!fdt) { | ||
| 39 | + error_report("load_device_tree() failed"); | ||
| 40 | + exit(1); | ||
| 41 | + } | ||
| 42 | + goto update_bootargs; | ||
| 43 | + } else { | ||
| 44 | + fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
| 45 | + if (!fdt) { | ||
| 46 | + error_report("create_device_tree() failed"); | ||
| 47 | + exit(1); | ||
| 48 | + } | ||
| 49 | } | ||
| 50 | |||
| 51 | qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
| 53 | |||
| 54 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
| 55 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); | ||
| 56 | - if (cmdline) { | ||
| 57 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
| 58 | - } | ||
| 59 | g_free(name); | ||
| 60 | |||
| 61 | name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
| 63 | 2, flashbase + flashsize, 2, flashsize); | ||
| 64 | qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); | ||
| 65 | g_free(name); | ||
| 66 | + | ||
| 67 | +update_bootargs: | ||
| 68 | + if (cmdline) { | ||
| 69 | + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
| 70 | + } | ||
| 71 | } | ||
| 72 | |||
| 73 | static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, | ||
| 74 | -- | ||
| 75 | 2.28.0 | ||
| 76 | |||
| 77 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Yifei Jiang <jiangyifei@huawei.com> | |
| 2 | |||
| 3 | mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. | ||
| 4 | This patch expands mstatus and vsstatus to uint64_t instead of | ||
| 5 | target_ulong so that it can be saved as one unit and reduce some | ||
| 6 | ifdefs in the code. | ||
| 7 | |||
| 8 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 9 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | Message-id: 20201026115530.304-2-jiangyifei@huawei.com | ||
| 13 | --- | ||
| 14 | target/riscv/cpu.h | 24 +++++++++++------------- | ||
| 15 | target/riscv/cpu_bits.h | 19 ++++--------------- | ||
| 16 | target/riscv/cpu.c | 8 +++++--- | ||
| 17 | target/riscv/cpu_helper.c | 35 +++++++---------------------------- | ||
| 18 | target/riscv/csr.c | 18 ++++++++++-------- | ||
| 19 | target/riscv/op_helper.c | 11 ++++------- | ||
| 20 | 6 files changed, 41 insertions(+), 74 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/riscv/cpu.h | ||
| 25 | +++ b/target/riscv/cpu.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
| 27 | target_ulong resetvec; | ||
| 28 | |||
| 29 | target_ulong mhartid; | ||
| 30 | - target_ulong mstatus; | ||
| 31 | + /* | ||
| 32 | + * For RV32 this is 32-bit mstatus and 32-bit mstatush. | ||
| 33 | + * For RV64 this is a 64-bit mstatus. | ||
| 34 | + */ | ||
| 35 | + uint64_t mstatus; | ||
| 36 | |||
| 37 | target_ulong mip; | ||
| 38 | |||
| 39 | -#ifdef TARGET_RISCV32 | ||
| 40 | - target_ulong mstatush; | ||
| 41 | -#endif | ||
| 42 | - | ||
| 43 | uint32_t miclaim; | ||
| 44 | |||
| 45 | target_ulong mie; | ||
| 46 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
| 47 | uint64_t htimedelta; | ||
| 48 | |||
| 49 | /* Virtual CSRs */ | ||
| 50 | - target_ulong vsstatus; | ||
| 51 | + /* | ||
| 52 | + * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | ||
| 53 | + * For RV64 this is a 64-bit vsstatus. | ||
| 54 | + */ | ||
| 55 | + uint64_t vsstatus; | ||
| 56 | target_ulong vstvec; | ||
| 57 | target_ulong vsscratch; | ||
| 58 | target_ulong vsepc; | ||
| 59 | target_ulong vscause; | ||
| 60 | target_ulong vstval; | ||
| 61 | target_ulong vsatp; | ||
| 62 | -#ifdef TARGET_RISCV32 | ||
| 63 | - target_ulong vsstatush; | ||
| 64 | -#endif | ||
| 65 | |||
| 66 | target_ulong mtval2; | ||
| 67 | target_ulong mtinst; | ||
| 68 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
| 69 | target_ulong scause_hs; | ||
| 70 | target_ulong stval_hs; | ||
| 71 | target_ulong satp_hs; | ||
| 72 | - target_ulong mstatus_hs; | ||
| 73 | -#ifdef TARGET_RISCV32 | ||
| 74 | - target_ulong mstatush_hs; | ||
| 75 | -#endif | ||
| 76 | + uint64_t mstatus_hs; | ||
| 77 | |||
| 78 | target_ulong scounteren; | ||
| 79 | target_ulong mcounteren; | ||
| 80 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h | ||
| 81 | index XXXXXXX..XXXXXXX 100644 | ||
| 82 | --- a/target/riscv/cpu_bits.h | ||
| 83 | +++ b/target/riscv/cpu_bits.h | ||
| 84 | @@ -XXX,XX +XXX,XX @@ | ||
| 85 | #define TARGET_RISCV_CPU_BITS_H | ||
| 86 | |||
| 87 | #define get_field(reg, mask) (((reg) & \ | ||
| 88 | - (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) | ||
| 89 | -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ | ||
| 90 | - (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ | ||
| 91 | - (target_ulong)(mask))) | ||
| 92 | + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) | ||
| 93 | +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ | ||
| 94 | + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ | ||
| 95 | + (uint64_t)(mask))) | ||
| 96 | |||
| 97 | /* Floating point round mode */ | ||
| 98 | #define FSR_RD_SHIFT 5 | ||
| 99 | @@ -XXX,XX +XXX,XX @@ | ||
| 100 | #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ | ||
| 101 | #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ | ||
| 102 | #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ | ||
| 103 | -#if defined(TARGET_RISCV64) | ||
| 104 | #define MSTATUS_GVA 0x4000000000ULL | ||
| 105 | #define MSTATUS_MPV 0x8000000000ULL | ||
| 106 | -#elif defined(TARGET_RISCV32) | ||
| 107 | -#define MSTATUS_GVA 0x00000040 | ||
| 108 | -#define MSTATUS_MPV 0x00000080 | ||
| 109 | -#endif | ||
| 110 | - | ||
| 111 | -#ifdef TARGET_RISCV32 | ||
| 112 | -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) | ||
| 113 | -#else | ||
| 114 | -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) | ||
| 115 | -#endif | ||
| 116 | |||
| 117 | #define MSTATUS64_UXL 0x0000000300000000ULL | ||
| 118 | #define MSTATUS64_SXL 0x0000000C00000000ULL | ||
| 119 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 120 | index XXXXXXX..XXXXXXX 100644 | ||
| 121 | --- a/target/riscv/cpu.c | ||
| 122 | +++ b/target/riscv/cpu.c | ||
| 123 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) | ||
| 124 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); | ||
| 125 | #ifndef CONFIG_USER_ONLY | ||
| 126 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); | ||
| 127 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); | ||
| 128 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); | ||
| 129 | #ifdef TARGET_RISCV32 | ||
| 130 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); | ||
| 131 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", | ||
| 132 | + (target_ulong)(env->mstatus >> 32)); | ||
| 133 | #endif | ||
| 134 | if (riscv_has_ext(env, RVH)) { | ||
| 135 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); | ||
| 136 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); | ||
| 137 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", | ||
| 138 | + (target_ulong)env->vsstatus); | ||
| 139 | } | ||
| 140 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); | ||
| 141 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); | ||
| 142 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | ||
| 143 | index XXXXXXX..XXXXXXX 100644 | ||
| 144 | --- a/target/riscv/cpu_helper.c | ||
| 145 | +++ b/target/riscv/cpu_helper.c | ||
| 146 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) | ||
| 147 | |||
| 148 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) | ||
| 149 | { | ||
| 150 | - target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | | ||
| 151 | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; | ||
| 152 | + uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | | ||
| 153 | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | | ||
| 154 | + MSTATUS64_UXL; | ||
| 155 | bool current_virt = riscv_cpu_virt_enabled(env); | ||
| 156 | |||
| 157 | g_assert(riscv_has_ext(env, RVH)); | ||
| 158 | |||
| 159 | -#if defined(TARGET_RISCV64) | ||
| 160 | - mstatus_mask |= MSTATUS64_UXL; | ||
| 161 | -#endif | ||
| 162 | - | ||
| 163 | if (current_virt) { | ||
| 164 | /* Current V=1 and we are about to change to V=0 */ | ||
| 165 | env->vsstatus = env->mstatus & mstatus_mask; | ||
| 166 | env->mstatus &= ~mstatus_mask; | ||
| 167 | env->mstatus |= env->mstatus_hs; | ||
| 168 | |||
| 169 | -#if defined(TARGET_RISCV32) | ||
| 170 | - env->vsstatush = env->mstatush; | ||
| 171 | - env->mstatush |= env->mstatush_hs; | ||
| 172 | -#endif | ||
| 173 | - | ||
| 174 | env->vstvec = env->stvec; | ||
| 175 | env->stvec = env->stvec_hs; | ||
| 176 | |||
| 177 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) | ||
| 178 | env->mstatus &= ~mstatus_mask; | ||
| 179 | env->mstatus |= env->vsstatus; | ||
| 180 | |||
| 181 | -#if defined(TARGET_RISCV32) | ||
| 182 | - env->mstatush_hs = env->mstatush; | ||
| 183 | - env->mstatush |= env->vsstatush; | ||
| 184 | -#endif | ||
| 185 | - | ||
| 186 | env->stvec_hs = env->stvec; | ||
| 187 | env->stvec = env->vstvec; | ||
| 188 | |||
| 189 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 190 | if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
| 191 | access_type != MMU_INST_FETCH && | ||
| 192 | get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 193 | - MSTATUS_MPV_ISSET(env)) { | ||
| 194 | + get_field(env->mstatus, MSTATUS_MPV)) { | ||
| 195 | riscv_cpu_set_two_stage_lookup(env, true); | ||
| 196 | } | ||
| 197 | |||
| 198 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 199 | if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
| 200 | access_type != MMU_INST_FETCH && | ||
| 201 | get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 202 | - MSTATUS_MPV_ISSET(env)) { | ||
| 203 | + get_field(env->mstatus, MSTATUS_MPV)) { | ||
| 204 | riscv_cpu_set_two_stage_lookup(env, false); | ||
| 205 | } | ||
| 206 | |||
| 207 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | ||
| 208 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 209 | CPURISCVState *env = &cpu->env; | ||
| 210 | bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); | ||
| 211 | - target_ulong s; | ||
| 212 | + uint64_t s; | ||
| 213 | |||
| 214 | /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide | ||
| 215 | * so we mask off the MSB and separate into trap type and cause. | ||
| 216 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | ||
| 217 | if (riscv_cpu_virt_enabled(env)) { | ||
| 218 | riscv_cpu_swap_hypervisor_regs(env); | ||
| 219 | } | ||
| 220 | -#ifdef TARGET_RISCV32 | ||
| 221 | - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, | ||
| 222 | - riscv_cpu_virt_enabled(env)); | ||
| 223 | - if (riscv_cpu_virt_enabled(env) && tval) { | ||
| 224 | - env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); | ||
| 225 | - } | ||
| 226 | -#else | ||
| 227 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | ||
| 228 | - riscv_cpu_virt_enabled(env)); | ||
| 229 | + riscv_cpu_virt_enabled(env)); | ||
| 230 | if (riscv_cpu_virt_enabled(env) && tval) { | ||
| 231 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | ||
| 232 | } | ||
| 233 | -#endif | ||
| 234 | |||
| 235 | mtval2 = env->guest_phys_fault_addr; | ||
| 236 | |||
| 237 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
| 238 | index XXXXXXX..XXXXXXX 100644 | ||
| 239 | --- a/target/riscv/csr.c | ||
| 240 | +++ b/target/riscv/csr.c | ||
| 241 | @@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm) | ||
| 242 | |||
| 243 | static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 244 | { | ||
| 245 | - target_ulong mstatus = env->mstatus; | ||
| 246 | - target_ulong mask = 0; | ||
| 247 | + uint64_t mstatus = env->mstatus; | ||
| 248 | + uint64_t mask = 0; | ||
| 249 | int dirty; | ||
| 250 | |||
| 251 | /* flush tlb on mstatus fields that affect VM */ | ||
| 252 | @@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 253 | #ifdef TARGET_RISCV32 | ||
| 254 | static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 255 | { | ||
| 256 | - *val = env->mstatush; | ||
| 257 | + *val = env->mstatus >> 32; | ||
| 258 | return 0; | ||
| 259 | } | ||
| 260 | |||
| 261 | static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) | ||
| 262 | { | ||
| 263 | - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { | ||
| 264 | + uint64_t valh = (uint64_t)val << 32; | ||
| 265 | + uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | ||
| 266 | + | ||
| 267 | + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | ||
| 268 | tlb_flush(env_cpu(env)); | ||
| 269 | } | ||
| 270 | |||
| 271 | - val &= MSTATUS_MPV | MSTATUS_GVA; | ||
| 272 | - | ||
| 273 | - env->mstatush = val; | ||
| 274 | + env->mstatus = (env->mstatus & ~mask) | (valh & mask); | ||
| 275 | |||
| 276 | return 0; | ||
| 277 | } | ||
| 278 | @@ -XXX,XX +XXX,XX @@ static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 279 | |||
| 280 | static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 281 | { | ||
| 282 | - env->vsstatus = val; | ||
| 283 | + uint64_t mask = (target_ulong)-1; | ||
| 284 | + env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | ||
| 285 | return 0; | ||
| 286 | } | ||
| 287 | |||
| 288 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 289 | index XXXXXXX..XXXXXXX 100644 | ||
| 290 | --- a/target/riscv/op_helper.c | ||
| 291 | +++ b/target/riscv/op_helper.c | ||
| 292 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, | ||
| 293 | |||
| 294 | target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
| 295 | { | ||
| 296 | - target_ulong prev_priv, prev_virt, mstatus; | ||
| 297 | + uint64_t mstatus; | ||
| 298 | + target_ulong prev_priv, prev_virt; | ||
| 299 | |||
| 300 | if (!(env->priv >= PRV_S)) { | ||
| 301 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 302 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
| 303 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); | ||
| 304 | } | ||
| 305 | |||
| 306 | - target_ulong mstatus = env->mstatus; | ||
| 307 | + uint64_t mstatus = env->mstatus; | ||
| 308 | target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); | ||
| 309 | - target_ulong prev_virt = MSTATUS_MPV_ISSET(env); | ||
| 310 | + target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); | ||
| 311 | mstatus = set_field(mstatus, MSTATUS_MIE, | ||
| 312 | get_field(mstatus, MSTATUS_MPIE)); | ||
| 313 | mstatus = set_field(mstatus, MSTATUS_MPIE, 1); | ||
| 314 | mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); | ||
| 315 | -#ifdef TARGET_RISCV32 | ||
| 316 | - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0); | ||
| 317 | -#else | ||
| 318 | mstatus = set_field(mstatus, MSTATUS_MPV, 0); | ||
| 319 | -#endif | ||
| 320 | env->mstatus = mstatus; | ||
| 321 | riscv_cpu_set_mode(env, prev_priv); | ||
| 322 | |||
| 323 | -- | ||
| 324 | 2.28.0 | ||
| 325 | |||
| 326 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yifei Jiang <jiangyifei@huawei.com> | ||
| 1 | 2 | ||
| 3 | Add basic CPU state description to the newly created machine.c | ||
| 4 | |||
| 5 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 6 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 20201026115530.304-3-jiangyifei@huawei.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/internals.h | 4 +++ | ||
| 12 | target/riscv/cpu.c | 8 +---- | ||
| 13 | target/riscv/machine.c | 74 ++++++++++++++++++++++++++++++++++++++++ | ||
| 14 | target/riscv/meson.build | 3 +- | ||
| 15 | 4 files changed, 81 insertions(+), 8 deletions(-) | ||
| 16 | create mode 100644 target/riscv/machine.c | ||
| 17 | |||
| 18 | diff --git a/target/riscv/internals.h b/target/riscv/internals.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/riscv/internals.h | ||
| 21 | +++ b/target/riscv/internals.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1); | ||
| 23 | #define SEW32 2 | ||
| 24 | #define SEW64 3 | ||
| 25 | |||
| 26 | +#ifndef CONFIG_USER_ONLY | ||
| 27 | +extern const VMStateDescription vmstate_riscv_cpu; | ||
| 28 | +#endif | ||
| 29 | + | ||
| 30 | static inline uint64_t nanbox_s(float32 f) | ||
| 31 | { | ||
| 32 | return f | MAKE_64BIT_MASK(32, 32); | ||
| 33 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/riscv/cpu.c | ||
| 36 | +++ b/target/riscv/cpu.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ | ||
| 38 | #include "qemu/ctype.h" | ||
| 39 | #include "qemu/log.h" | ||
| 40 | #include "cpu.h" | ||
| 41 | +#include "internals.h" | ||
| 42 | #include "exec/exec-all.h" | ||
| 43 | #include "qapi/error.h" | ||
| 44 | #include "qemu/error-report.h" | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj) | ||
| 46 | cpu_set_cpustate_pointers(cpu); | ||
| 47 | } | ||
| 48 | |||
| 49 | -#ifndef CONFIG_USER_ONLY | ||
| 50 | -static const VMStateDescription vmstate_riscv_cpu = { | ||
| 51 | - .name = "cpu", | ||
| 52 | - .unmigratable = 1, | ||
| 53 | -}; | ||
| 54 | -#endif | ||
| 55 | - | ||
| 56 | static Property riscv_cpu_properties[] = { | ||
| 57 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), | ||
| 58 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | ||
| 59 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | ||
| 60 | new file mode 100644 | ||
| 61 | index XXXXXXX..XXXXXXX | ||
| 62 | --- /dev/null | ||
| 63 | +++ b/target/riscv/machine.c | ||
| 64 | @@ -XXX,XX +XXX,XX @@ | ||
| 65 | +/* | ||
| 66 | + * RISC-V VMState Description | ||
| 67 | + * | ||
| 68 | + * Copyright (c) 2020 Huawei Technologies Co., Ltd | ||
| 69 | + * | ||
| 70 | + * This program is free software; you can redistribute it and/or modify it | ||
| 71 | + * under the terms and conditions of the GNU General Public License, | ||
| 72 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 73 | + * | ||
| 74 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 75 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 76 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 77 | + * more details. | ||
| 78 | + * | ||
| 79 | + * You should have received a copy of the GNU General Public License along with | ||
| 80 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 81 | + */ | ||
| 82 | + | ||
| 83 | +#include "qemu/osdep.h" | ||
| 84 | +#include "cpu.h" | ||
| 85 | +#include "qemu/error-report.h" | ||
| 86 | +#include "sysemu/kvm.h" | ||
| 87 | +#include "migration/cpu.h" | ||
| 88 | + | ||
| 89 | +const VMStateDescription vmstate_riscv_cpu = { | ||
| 90 | + .name = "cpu", | ||
| 91 | + .version_id = 1, | ||
| 92 | + .minimum_version_id = 1, | ||
| 93 | + .fields = (VMStateField[]) { | ||
| 94 | + VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), | ||
| 95 | + VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), | ||
| 96 | + VMSTATE_UINTTL(env.pc, RISCVCPU), | ||
| 97 | + VMSTATE_UINTTL(env.load_res, RISCVCPU), | ||
| 98 | + VMSTATE_UINTTL(env.load_val, RISCVCPU), | ||
| 99 | + VMSTATE_UINTTL(env.frm, RISCVCPU), | ||
| 100 | + VMSTATE_UINTTL(env.badaddr, RISCVCPU), | ||
| 101 | + VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), | ||
| 102 | + VMSTATE_UINTTL(env.priv_ver, RISCVCPU), | ||
| 103 | + VMSTATE_UINTTL(env.vext_ver, RISCVCPU), | ||
| 104 | + VMSTATE_UINTTL(env.misa, RISCVCPU), | ||
| 105 | + VMSTATE_UINTTL(env.misa_mask, RISCVCPU), | ||
| 106 | + VMSTATE_UINT32(env.features, RISCVCPU), | ||
| 107 | + VMSTATE_UINTTL(env.priv, RISCVCPU), | ||
| 108 | + VMSTATE_UINTTL(env.virt, RISCVCPU), | ||
| 109 | + VMSTATE_UINTTL(env.resetvec, RISCVCPU), | ||
| 110 | + VMSTATE_UINTTL(env.mhartid, RISCVCPU), | ||
| 111 | + VMSTATE_UINT64(env.mstatus, RISCVCPU), | ||
| 112 | + VMSTATE_UINTTL(env.mip, RISCVCPU), | ||
| 113 | + VMSTATE_UINT32(env.miclaim, RISCVCPU), | ||
| 114 | + VMSTATE_UINTTL(env.mie, RISCVCPU), | ||
| 115 | + VMSTATE_UINTTL(env.mideleg, RISCVCPU), | ||
| 116 | + VMSTATE_UINTTL(env.sptbr, RISCVCPU), | ||
| 117 | + VMSTATE_UINTTL(env.satp, RISCVCPU), | ||
| 118 | + VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), | ||
| 119 | + VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), | ||
| 120 | + VMSTATE_UINTTL(env.medeleg, RISCVCPU), | ||
| 121 | + VMSTATE_UINTTL(env.stvec, RISCVCPU), | ||
| 122 | + VMSTATE_UINTTL(env.sepc, RISCVCPU), | ||
| 123 | + VMSTATE_UINTTL(env.scause, RISCVCPU), | ||
| 124 | + VMSTATE_UINTTL(env.mtvec, RISCVCPU), | ||
| 125 | + VMSTATE_UINTTL(env.mepc, RISCVCPU), | ||
| 126 | + VMSTATE_UINTTL(env.mcause, RISCVCPU), | ||
| 127 | + VMSTATE_UINTTL(env.mtval, RISCVCPU), | ||
| 128 | + VMSTATE_UINTTL(env.scounteren, RISCVCPU), | ||
| 129 | + VMSTATE_UINTTL(env.mcounteren, RISCVCPU), | ||
| 130 | + VMSTATE_UINTTL(env.sscratch, RISCVCPU), | ||
| 131 | + VMSTATE_UINTTL(env.mscratch, RISCVCPU), | ||
| 132 | + VMSTATE_UINT64(env.mfromhost, RISCVCPU), | ||
| 133 | + VMSTATE_UINT64(env.mtohost, RISCVCPU), | ||
| 134 | + VMSTATE_UINT64(env.timecmp, RISCVCPU), | ||
| 135 | + | ||
| 136 | + VMSTATE_END_OF_LIST() | ||
| 137 | + } | ||
| 138 | +}; | ||
| 139 | diff --git a/target/riscv/meson.build b/target/riscv/meson.build | ||
| 140 | index XXXXXXX..XXXXXXX 100644 | ||
| 141 | --- a/target/riscv/meson.build | ||
| 142 | +++ b/target/riscv/meson.build | ||
| 143 | @@ -XXX,XX +XXX,XX @@ riscv_ss.add(files( | ||
| 144 | riscv_softmmu_ss = ss.source_set() | ||
| 145 | riscv_softmmu_ss.add(files( | ||
| 146 | 'pmp.c', | ||
| 147 | - 'monitor.c' | ||
| 148 | + 'monitor.c', | ||
| 149 | + 'machine.c' | ||
| 150 | )) | ||
| 151 | |||
| 152 | target_arch += {'riscv': riscv_ss} | ||
| 153 | -- | ||
| 154 | 2.28.0 | ||
| 155 | |||
| 156 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yifei Jiang <jiangyifei@huawei.com> | ||
| 1 | 2 | ||
| 3 | In the case of supporting PMP feature, add PMP state description | ||
| 4 | to vmstate_riscv_cpu. | ||
| 5 | |||
| 6 | 'vmstate_pmp_addr' and 'num_rules' could be regenerated by | ||
| 7 | pmp_update_rule(). But there exists the problem of updating | ||
| 8 | num_rules repeatedly in pmp_update_rule(). So here extracts | ||
| 9 | pmp_update_rule_addr() and pmp_update_rule_nums() to update | ||
| 10 | 'vmstate_pmp_addr' and 'num_rules' respectively. | ||
| 11 | |||
| 12 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 13 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Message-id: 20201026115530.304-4-jiangyifei@huawei.com | ||
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | --- | ||
| 18 | target/riscv/pmp.h | 2 ++ | ||
| 19 | target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ | ||
| 20 | target/riscv/pmp.c | 29 ++++++++++++++---------- | ||
| 21 | 3 files changed, 70 insertions(+), 11 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/target/riscv/pmp.h | ||
| 26 | +++ b/target/riscv/pmp.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 28 | target_ulong size, pmp_priv_t priv, target_ulong mode); | ||
| 29 | bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 30 | target_ulong *tlb_size); | ||
| 31 | +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); | ||
| 32 | +void pmp_update_rule_nums(CPURISCVState *env); | ||
| 33 | |||
| 34 | #endif | ||
| 35 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/riscv/machine.c | ||
| 38 | +++ b/target/riscv/machine.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | ||
| 40 | #include "sysemu/kvm.h" | ||
| 41 | #include "migration/cpu.h" | ||
| 42 | |||
| 43 | +static bool pmp_needed(void *opaque) | ||
| 44 | +{ | ||
| 45 | + RISCVCPU *cpu = opaque; | ||
| 46 | + CPURISCVState *env = &cpu->env; | ||
| 47 | + | ||
| 48 | + return riscv_feature(env, RISCV_FEATURE_PMP); | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | +static int pmp_post_load(void *opaque, int version_id) | ||
| 52 | +{ | ||
| 53 | + RISCVCPU *cpu = opaque; | ||
| 54 | + CPURISCVState *env = &cpu->env; | ||
| 55 | + int i; | ||
| 56 | + | ||
| 57 | + for (i = 0; i < MAX_RISCV_PMPS; i++) { | ||
| 58 | + pmp_update_rule_addr(env, i); | ||
| 59 | + } | ||
| 60 | + pmp_update_rule_nums(env); | ||
| 61 | + | ||
| 62 | + return 0; | ||
| 63 | +} | ||
| 64 | + | ||
| 65 | +static const VMStateDescription vmstate_pmp_entry = { | ||
| 66 | + .name = "cpu/pmp/entry", | ||
| 67 | + .version_id = 1, | ||
| 68 | + .minimum_version_id = 1, | ||
| 69 | + .fields = (VMStateField[]) { | ||
| 70 | + VMSTATE_UINTTL(addr_reg, pmp_entry_t), | ||
| 71 | + VMSTATE_UINT8(cfg_reg, pmp_entry_t), | ||
| 72 | + VMSTATE_END_OF_LIST() | ||
| 73 | + } | ||
| 74 | +}; | ||
| 75 | + | ||
| 76 | +static const VMStateDescription vmstate_pmp = { | ||
| 77 | + .name = "cpu/pmp", | ||
| 78 | + .version_id = 1, | ||
| 79 | + .minimum_version_id = 1, | ||
| 80 | + .needed = pmp_needed, | ||
| 81 | + .post_load = pmp_post_load, | ||
| 82 | + .fields = (VMStateField[]) { | ||
| 83 | + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, | ||
| 84 | + 0, vmstate_pmp_entry, pmp_entry_t), | ||
| 85 | + VMSTATE_END_OF_LIST() | ||
| 86 | + } | ||
| 87 | +}; | ||
| 88 | + | ||
| 89 | const VMStateDescription vmstate_riscv_cpu = { | ||
| 90 | .name = "cpu", | ||
| 91 | .version_id = 1, | ||
| 92 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
| 93 | VMSTATE_UINT64(env.timecmp, RISCVCPU), | ||
| 94 | |||
| 95 | VMSTATE_END_OF_LIST() | ||
| 96 | + }, | ||
| 97 | + .subsections = (const VMStateDescription * []) { | ||
| 98 | + &vmstate_pmp, | ||
| 99 | + NULL | ||
| 100 | } | ||
| 101 | }; | ||
| 102 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 103 | index XXXXXXX..XXXXXXX 100644 | ||
| 104 | --- a/target/riscv/pmp.c | ||
| 105 | +++ b/target/riscv/pmp.c | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) | ||
| 107 | } | ||
| 108 | } | ||
| 109 | |||
| 110 | - | ||
| 111 | -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' | ||
| 112 | - * end address values. | ||
| 113 | - * This function is called relatively infrequently whereas the check that | ||
| 114 | - * an address is within a pmp rule is called often, so optimise that one | ||
| 115 | - */ | ||
| 116 | -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
| 117 | +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) | ||
| 118 | { | ||
| 119 | - int i; | ||
| 120 | - | ||
| 121 | - env->pmp_state.num_rules = 0; | ||
| 122 | - | ||
| 123 | uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; | ||
| 124 | target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; | ||
| 125 | target_ulong prev_addr = 0u; | ||
| 126 | @@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
| 127 | |||
| 128 | env->pmp_state.addr[pmp_index].sa = sa; | ||
| 129 | env->pmp_state.addr[pmp_index].ea = ea; | ||
| 130 | +} | ||
| 131 | |||
| 132 | +void pmp_update_rule_nums(CPURISCVState *env) | ||
| 133 | +{ | ||
| 134 | + int i; | ||
| 135 | + | ||
| 136 | + env->pmp_state.num_rules = 0; | ||
| 137 | for (i = 0; i < MAX_RISCV_PMPS; i++) { | ||
| 138 | const uint8_t a_field = | ||
| 139 | pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
| 141 | } | ||
| 142 | } | ||
| 143 | |||
| 144 | +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' | ||
| 145 | + * end address values. | ||
| 146 | + * This function is called relatively infrequently whereas the check that | ||
| 147 | + * an address is within a pmp rule is called often, so optimise that one | ||
| 148 | + */ | ||
| 149 | +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
| 150 | +{ | ||
| 151 | + pmp_update_rule_addr(env, pmp_index); | ||
| 152 | + pmp_update_rule_nums(env); | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
| 156 | { | ||
| 157 | int result = 0; | ||
| 158 | -- | ||
| 159 | 2.28.0 | ||
| 160 | |||
| 161 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yifei Jiang <jiangyifei@huawei.com> | ||
| 1 | 2 | ||
| 3 | In the case of supporting H extension, add H extension description | ||
| 4 | to vmstate_riscv_cpu. | ||
| 5 | |||
| 6 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 7 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20201026115530.304-5-jiangyifei@huawei.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++ | ||
| 13 | 1 file changed, 47 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/riscv/machine.c | ||
| 18 | +++ b/target/riscv/machine.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmp = { | ||
| 20 | } | ||
| 21 | }; | ||
| 22 | |||
| 23 | +static bool hyper_needed(void *opaque) | ||
| 24 | +{ | ||
| 25 | + RISCVCPU *cpu = opaque; | ||
| 26 | + CPURISCVState *env = &cpu->env; | ||
| 27 | + | ||
| 28 | + return riscv_has_ext(env, RVH); | ||
| 29 | +} | ||
| 30 | + | ||
| 31 | +static const VMStateDescription vmstate_hyper = { | ||
| 32 | + .name = "cpu/hyper", | ||
| 33 | + .version_id = 1, | ||
| 34 | + .minimum_version_id = 1, | ||
| 35 | + .needed = hyper_needed, | ||
| 36 | + .fields = (VMStateField[]) { | ||
| 37 | + VMSTATE_UINTTL(env.hstatus, RISCVCPU), | ||
| 38 | + VMSTATE_UINTTL(env.hedeleg, RISCVCPU), | ||
| 39 | + VMSTATE_UINTTL(env.hideleg, RISCVCPU), | ||
| 40 | + VMSTATE_UINTTL(env.hcounteren, RISCVCPU), | ||
| 41 | + VMSTATE_UINTTL(env.htval, RISCVCPU), | ||
| 42 | + VMSTATE_UINTTL(env.htinst, RISCVCPU), | ||
| 43 | + VMSTATE_UINTTL(env.hgatp, RISCVCPU), | ||
| 44 | + VMSTATE_UINT64(env.htimedelta, RISCVCPU), | ||
| 45 | + | ||
| 46 | + VMSTATE_UINT64(env.vsstatus, RISCVCPU), | ||
| 47 | + VMSTATE_UINTTL(env.vstvec, RISCVCPU), | ||
| 48 | + VMSTATE_UINTTL(env.vsscratch, RISCVCPU), | ||
| 49 | + VMSTATE_UINTTL(env.vsepc, RISCVCPU), | ||
| 50 | + VMSTATE_UINTTL(env.vscause, RISCVCPU), | ||
| 51 | + VMSTATE_UINTTL(env.vstval, RISCVCPU), | ||
| 52 | + VMSTATE_UINTTL(env.vsatp, RISCVCPU), | ||
| 53 | + | ||
| 54 | + VMSTATE_UINTTL(env.mtval2, RISCVCPU), | ||
| 55 | + VMSTATE_UINTTL(env.mtinst, RISCVCPU), | ||
| 56 | + | ||
| 57 | + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), | ||
| 58 | + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), | ||
| 59 | + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), | ||
| 60 | + VMSTATE_UINTTL(env.scause_hs, RISCVCPU), | ||
| 61 | + VMSTATE_UINTTL(env.stval_hs, RISCVCPU), | ||
| 62 | + VMSTATE_UINTTL(env.satp_hs, RISCVCPU), | ||
| 63 | + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), | ||
| 64 | + | ||
| 65 | + VMSTATE_END_OF_LIST() | ||
| 66 | + } | ||
| 67 | +}; | ||
| 68 | + | ||
| 69 | const VMStateDescription vmstate_riscv_cpu = { | ||
| 70 | .name = "cpu", | ||
| 71 | .version_id = 1, | ||
| 72 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
| 73 | }, | ||
| 74 | .subsections = (const VMStateDescription * []) { | ||
| 75 | &vmstate_pmp, | ||
| 76 | + &vmstate_hyper, | ||
| 77 | NULL | ||
| 78 | } | ||
| 79 | }; | ||
| 80 | -- | ||
| 81 | 2.28.0 | ||
| 82 | |||
| 83 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yifei Jiang <jiangyifei@huawei.com> | ||
| 1 | 2 | ||
| 3 | In the case of supporting V extension, add V extension description | ||
| 4 | to vmstate_riscv_cpu. | ||
| 5 | |||
| 6 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 7 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-id: 20201026115530.304-6-jiangyifei@huawei.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | target/riscv/machine.c | 25 +++++++++++++++++++++++++ | ||
| 14 | 1 file changed, 25 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/riscv/machine.c | ||
| 19 | +++ b/target/riscv/machine.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque) | ||
| 21 | return riscv_has_ext(env, RVH); | ||
| 22 | } | ||
| 23 | |||
| 24 | +static bool vector_needed(void *opaque) | ||
| 25 | +{ | ||
| 26 | + RISCVCPU *cpu = opaque; | ||
| 27 | + CPURISCVState *env = &cpu->env; | ||
| 28 | + | ||
| 29 | + return riscv_has_ext(env, RVV); | ||
| 30 | +} | ||
| 31 | + | ||
| 32 | +static const VMStateDescription vmstate_vector = { | ||
| 33 | + .name = "cpu/vector", | ||
| 34 | + .version_id = 1, | ||
| 35 | + .minimum_version_id = 1, | ||
| 36 | + .needed = vector_needed, | ||
| 37 | + .fields = (VMStateField[]) { | ||
| 38 | + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), | ||
| 39 | + VMSTATE_UINTTL(env.vxrm, RISCVCPU), | ||
| 40 | + VMSTATE_UINTTL(env.vxsat, RISCVCPU), | ||
| 41 | + VMSTATE_UINTTL(env.vl, RISCVCPU), | ||
| 42 | + VMSTATE_UINTTL(env.vstart, RISCVCPU), | ||
| 43 | + VMSTATE_UINTTL(env.vtype, RISCVCPU), | ||
| 44 | + VMSTATE_END_OF_LIST() | ||
| 45 | + } | ||
| 46 | +}; | ||
| 47 | + | ||
| 48 | static const VMStateDescription vmstate_hyper = { | ||
| 49 | .name = "cpu/hyper", | ||
| 50 | .version_id = 1, | ||
| 51 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
| 52 | .subsections = (const VMStateDescription * []) { | ||
| 53 | &vmstate_pmp, | ||
| 54 | &vmstate_hyper, | ||
| 55 | + &vmstate_vector, | ||
| 56 | NULL | ||
| 57 | } | ||
| 58 | }; | ||
| 59 | -- | ||
| 60 | 2.28.0 | ||
| 61 | |||
| 62 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yifei Jiang <jiangyifei@huawei.com> | ||
| 1 | 2 | ||
| 3 | Add sifive_plic vmstate for supporting sifive_plic migration. | ||
| 4 | Current vmstate framework only supports one structure parameter | ||
| 5 | as num field to describe variable length arrays, so introduce | ||
| 6 | num_enables. | ||
| 7 | |||
| 8 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | ||
| 9 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | Message-id: 20201026115530.304-7-jiangyifei@huawei.com | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | include/hw/intc/sifive_plic.h | 1 + | ||
| 15 | hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++- | ||
| 16 | 2 files changed, 26 insertions(+), 1 deletion(-) | ||
| 17 | |||
| 18 | diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/include/hw/intc/sifive_plic.h | ||
| 21 | +++ b/include/hw/intc/sifive_plic.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ struct SiFivePLICState { | ||
| 23 | uint32_t num_addrs; | ||
| 24 | uint32_t num_harts; | ||
| 25 | uint32_t bitfield_words; | ||
| 26 | + uint32_t num_enables; | ||
| 27 | PLICAddr *addr_config; | ||
| 28 | uint32_t *source_priority; | ||
| 29 | uint32_t *target_priority; | ||
| 30 | diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/hw/intc/sifive_plic.c | ||
| 33 | +++ b/hw/intc/sifive_plic.c | ||
| 34 | @@ -XXX,XX +XXX,XX @@ | ||
| 35 | #include "hw/intc/sifive_plic.h" | ||
| 36 | #include "target/riscv/cpu.h" | ||
| 37 | #include "sysemu/sysemu.h" | ||
| 38 | +#include "migration/vmstate.h" | ||
| 39 | |||
| 40 | #define RISCV_DEBUG_PLIC 0 | ||
| 41 | |||
| 42 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) | ||
| 43 | TYPE_SIFIVE_PLIC, plic->aperture_size); | ||
| 44 | parse_hart_config(plic); | ||
| 45 | plic->bitfield_words = (plic->num_sources + 31) >> 5; | ||
| 46 | + plic->num_enables = plic->bitfield_words * plic->num_addrs; | ||
| 47 | plic->source_priority = g_new0(uint32_t, plic->num_sources); | ||
| 48 | plic->target_priority = g_new(uint32_t, plic->num_addrs); | ||
| 49 | plic->pending = g_new0(uint32_t, plic->bitfield_words); | ||
| 50 | plic->claimed = g_new0(uint32_t, plic->bitfield_words); | ||
| 51 | - plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs); | ||
| 52 | + plic->enable = g_new0(uint32_t, plic->num_enables); | ||
| 53 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio); | ||
| 54 | qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources); | ||
| 55 | |||
| 56 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) | ||
| 57 | msi_nonbroken = true; | ||
| 58 | } | ||
| 59 | |||
| 60 | +static const VMStateDescription vmstate_sifive_plic = { | ||
| 61 | + .name = "riscv_sifive_plic", | ||
| 62 | + .version_id = 1, | ||
| 63 | + .minimum_version_id = 1, | ||
| 64 | + .fields = (VMStateField[]) { | ||
| 65 | + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, | ||
| 66 | + num_sources, 0, | ||
| 67 | + vmstate_info_uint32, uint32_t), | ||
| 68 | + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, | ||
| 69 | + num_addrs, 0, | ||
| 70 | + vmstate_info_uint32, uint32_t), | ||
| 71 | + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0, | ||
| 72 | + vmstate_info_uint32, uint32_t), | ||
| 73 | + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0, | ||
| 74 | + vmstate_info_uint32, uint32_t), | ||
| 75 | + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, | ||
| 76 | + vmstate_info_uint32, uint32_t), | ||
| 77 | + VMSTATE_END_OF_LIST() | ||
| 78 | + } | ||
| 79 | +}; | ||
| 80 | + | ||
| 81 | static void sifive_plic_class_init(ObjectClass *klass, void *data) | ||
| 82 | { | ||
| 83 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 84 | |||
| 85 | device_class_set_props(dc, sifive_plic_properties); | ||
| 86 | dc->realize = sifive_plic_realize; | ||
| 87 | + dc->vmsd = &vmstate_sifive_plic; | ||
| 88 | } | ||
| 89 | |||
| 90 | static const TypeInfo sifive_plic_info = { | ||
| 91 | -- | ||
| 92 | 2.28.0 | ||
| 93 | |||
| 94 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | It is not easy to find out the memory map for a specific component | ||
| 4 | in the PolarFire SoC as the information is scattered in different | ||
| 5 | documents. Add some comments so that people can know where to get | ||
| 6 | such information from the Microchip website. | ||
| 7 | |||
| 8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ | ||
| 14 | 1 file changed, 18 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 19 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | /* GEM version */ | ||
| 22 | #define GEM_REVISION 0x0107010c | ||
| 23 | |||
| 24 | +/* | ||
| 25 | + * The complete description of the whole PolarFire SoC memory map is scattered | ||
| 26 | + * in different documents. There are several places to look at for memory maps: | ||
| 27 | + * | ||
| 28 | + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA | ||
| 29 | + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from | ||
| 30 | + * https://www.microsemi.com/document-portal/doc_download/ | ||
| 31 | + * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, | ||
| 32 | + * describes the whole picture of the PolarFire SoC memory map. | ||
| 33 | + * | ||
| 34 | + * 2 A zip file for PolarFire soC memory map, which can be downloaded from | ||
| 35 | + * https://www.microsemi.com/document-portal/doc_download/ | ||
| 36 | + * 1244581-polarfire-soc-register-map, contains the following 2 major parts: | ||
| 37 | + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm | ||
| 38 | + * describes the complete integrated peripherals memory map | ||
| 39 | + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm | ||
| 40 | + * describes the complete IOSCB modules memory maps | ||
| 41 | + */ | ||
| 42 | static const struct MemmapEntry { | ||
| 43 | hwaddr base; | ||
| 44 | hwaddr size; | ||
| 45 | -- | ||
| 46 | 2.28.0 | ||
| 47 | |||
| 48 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Bin Meng <bin.meng@windriver.com> | |
| 2 | |||
| 3 | The PolarFire SoC DDR Memory Controller mainly includes 2 modules, | ||
| 4 | called SGMII PHY module and the CFG module, as documented in the | ||
| 5 | chipset datasheet. | ||
| 6 | |||
| 7 | This creates a single file that groups these 2 modules, providing | ||
| 8 | the minimum functionalities that make the HSS DDR initialization | ||
| 9 | codes happy. | ||
| 10 | |||
| 11 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com | ||
| 14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | --- | ||
| 16 | include/hw/misc/mchp_pfsoc_dmc.h | 56 ++++++++ | ||
| 17 | hw/misc/mchp_pfsoc_dmc.c | 216 +++++++++++++++++++++++++++++++ | ||
| 18 | MAINTAINERS | 2 + | ||
| 19 | hw/misc/Kconfig | 3 + | ||
| 20 | hw/misc/meson.build | 1 + | ||
| 21 | 5 files changed, 278 insertions(+) | ||
| 22 | create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h | ||
| 23 | create mode 100644 hw/misc/mchp_pfsoc_dmc.c | ||
| 24 | |||
| 25 | diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h | ||
| 26 | new file mode 100644 | ||
| 27 | index XXXXXXX..XXXXXXX | ||
| 28 | --- /dev/null | ||
| 29 | +++ b/include/hw/misc/mchp_pfsoc_dmc.h | ||
| 30 | @@ -XXX,XX +XXX,XX @@ | ||
| 31 | +/* | ||
| 32 | + * Microchip PolarFire SoC DDR Memory Controller module emulation | ||
| 33 | + * | ||
| 34 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 35 | + * | ||
| 36 | + * Author: | ||
| 37 | + * Bin Meng <bin.meng@windriver.com> | ||
| 38 | + * | ||
| 39 | + * This program is free software; you can redistribute it and/or | ||
| 40 | + * modify it under the terms of the GNU General Public License as | ||
| 41 | + * published by the Free Software Foundation; either version 2 or | ||
| 42 | + * (at your option) version 3 of the License. | ||
| 43 | + * | ||
| 44 | + * This program is distributed in the hope that it will be useful, | ||
| 45 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 46 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 47 | + * GNU General Public License for more details. | ||
| 48 | + * | ||
| 49 | + * You should have received a copy of the GNU General Public License along | ||
| 50 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 51 | + */ | ||
| 52 | + | ||
| 53 | +#ifndef MCHP_PFSOC_DMC_H | ||
| 54 | +#define MCHP_PFSOC_DMC_H | ||
| 55 | + | ||
| 56 | +/* DDR SGMII PHY module */ | ||
| 57 | + | ||
| 58 | +#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 | ||
| 59 | + | ||
| 60 | +typedef struct MchpPfSoCDdrSgmiiPhyState { | ||
| 61 | + SysBusDevice parent; | ||
| 62 | + MemoryRegion sgmii_phy; | ||
| 63 | +} MchpPfSoCDdrSgmiiPhyState; | ||
| 64 | + | ||
| 65 | +#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy" | ||
| 66 | + | ||
| 67 | +#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \ | ||
| 68 | + OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \ | ||
| 69 | + TYPE_MCHP_PFSOC_DDR_SGMII_PHY) | ||
| 70 | + | ||
| 71 | +/* DDR CFG module */ | ||
| 72 | + | ||
| 73 | +#define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000 | ||
| 74 | + | ||
| 75 | +typedef struct MchpPfSoCDdrCfgState { | ||
| 76 | + SysBusDevice parent; | ||
| 77 | + MemoryRegion cfg; | ||
| 78 | +} MchpPfSoCDdrCfgState; | ||
| 79 | + | ||
| 80 | +#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg" | ||
| 81 | + | ||
| 82 | +#define MCHP_PFSOC_DDR_CFG(obj) \ | ||
| 83 | + OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \ | ||
| 84 | + TYPE_MCHP_PFSOC_DDR_CFG) | ||
| 85 | + | ||
| 86 | +#endif /* MCHP_PFSOC_DMC_H */ | ||
| 87 | diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c | ||
| 88 | new file mode 100644 | ||
| 89 | index XXXXXXX..XXXXXXX | ||
| 90 | --- /dev/null | ||
| 91 | +++ b/hw/misc/mchp_pfsoc_dmc.c | ||
| 92 | @@ -XXX,XX +XXX,XX @@ | ||
| 93 | +/* | ||
| 94 | + * Microchip PolarFire SoC DDR Memory Controller module emulation | ||
| 95 | + * | ||
| 96 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 97 | + * | ||
| 98 | + * Author: | ||
| 99 | + * Bin Meng <bin.meng@windriver.com> | ||
| 100 | + * | ||
| 101 | + * This program is free software; you can redistribute it and/or | ||
| 102 | + * modify it under the terms of the GNU General Public License as | ||
| 103 | + * published by the Free Software Foundation; either version 2 or | ||
| 104 | + * (at your option) version 3 of the License. | ||
| 105 | + * | ||
| 106 | + * This program is distributed in the hope that it will be useful, | ||
| 107 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 108 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 109 | + * GNU General Public License for more details. | ||
| 110 | + * | ||
| 111 | + * You should have received a copy of the GNU General Public License along | ||
| 112 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 113 | + */ | ||
| 114 | + | ||
| 115 | +#include "qemu/osdep.h" | ||
| 116 | +#include "qemu/bitops.h" | ||
| 117 | +#include "qemu/log.h" | ||
| 118 | +#include "qapi/error.h" | ||
| 119 | +#include "hw/hw.h" | ||
| 120 | +#include "hw/sysbus.h" | ||
| 121 | +#include "hw/misc/mchp_pfsoc_dmc.h" | ||
| 122 | + | ||
| 123 | +/* DDR SGMII PHY module */ | ||
| 124 | + | ||
| 125 | +#define SGMII_PHY_IOC_REG1 0x208 | ||
| 126 | +#define SGMII_PHY_TRAINING_STATUS 0x814 | ||
| 127 | +#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834 | ||
| 128 | +#define SGMII_PHY_DQDQS_STATUS1 0x84c | ||
| 129 | +#define SGMII_PHY_PVT_STAT 0xc20 | ||
| 130 | + | ||
| 131 | +static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset, | ||
| 132 | + unsigned size) | ||
| 133 | +{ | ||
| 134 | + uint32_t val = 0; | ||
| 135 | + static int training_status_bit; | ||
| 136 | + | ||
| 137 | + switch (offset) { | ||
| 138 | + case SGMII_PHY_IOC_REG1: | ||
| 139 | + /* See ddr_pvt_calibration() in HSS */ | ||
| 140 | + val = BIT(4) | BIT(2); | ||
| 141 | + break; | ||
| 142 | + case SGMII_PHY_TRAINING_STATUS: | ||
| 143 | + /* | ||
| 144 | + * The codes logic emulates the training status change from | ||
| 145 | + * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS. | ||
| 146 | + * | ||
| 147 | + * See ddr_setup() in mss_ddr.c in the HSS source codes. | ||
| 148 | + */ | ||
| 149 | + val = 1 << training_status_bit; | ||
| 150 | + training_status_bit = (training_status_bit + 1) % 5; | ||
| 151 | + break; | ||
| 152 | + case SGMII_PHY_DQ_DQS_ERR_DONE: | ||
| 153 | + /* | ||
| 154 | + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(), | ||
| 155 | + * check that DQ/DQS training passed without error. | ||
| 156 | + */ | ||
| 157 | + val = 8; | ||
| 158 | + break; | ||
| 159 | + case SGMII_PHY_DQDQS_STATUS1: | ||
| 160 | + /* | ||
| 161 | + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(), | ||
| 162 | + * check that DQ/DQS calculated window is above 5 taps. | ||
| 163 | + */ | ||
| 164 | + val = 0xff; | ||
| 165 | + break; | ||
| 166 | + case SGMII_PHY_PVT_STAT: | ||
| 167 | + /* See sgmii_channel_setup() in HSS */ | ||
| 168 | + val = BIT(14) | BIT(6); | ||
| 169 | + break; | ||
| 170 | + default: | ||
| 171 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 172 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 173 | + __func__, size, offset); | ||
| 174 | + break; | ||
| 175 | + } | ||
| 176 | + | ||
| 177 | + return val; | ||
| 178 | +} | ||
| 179 | + | ||
| 180 | +static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset, | ||
| 181 | + uint64_t value, unsigned size) | ||
| 182 | +{ | ||
| 183 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | ||
| 184 | + "(size %d, value 0x%" PRIx64 | ||
| 185 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
| 186 | + __func__, size, value, offset); | ||
| 187 | +} | ||
| 188 | + | ||
| 189 | +static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = { | ||
| 190 | + .read = mchp_pfsoc_ddr_sgmii_phy_read, | ||
| 191 | + .write = mchp_pfsoc_ddr_sgmii_phy_write, | ||
| 192 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 193 | +}; | ||
| 194 | + | ||
| 195 | +static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp) | ||
| 196 | +{ | ||
| 197 | + MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev); | ||
| 198 | + | ||
| 199 | + memory_region_init_io(&s->sgmii_phy, OBJECT(dev), | ||
| 200 | + &mchp_pfsoc_ddr_sgmii_phy_ops, s, | ||
| 201 | + "mchp.pfsoc.ddr_sgmii_phy", | ||
| 202 | + MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE); | ||
| 203 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy); | ||
| 204 | +} | ||
| 205 | + | ||
| 206 | +static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data) | ||
| 207 | +{ | ||
| 208 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 209 | + | ||
| 210 | + dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module"; | ||
| 211 | + dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize; | ||
| 212 | +} | ||
| 213 | + | ||
| 214 | +static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = { | ||
| 215 | + .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY, | ||
| 216 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 217 | + .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState), | ||
| 218 | + .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init, | ||
| 219 | +}; | ||
| 220 | + | ||
| 221 | +static void mchp_pfsoc_ddr_sgmii_phy_register_types(void) | ||
| 222 | +{ | ||
| 223 | + type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info); | ||
| 224 | +} | ||
| 225 | + | ||
| 226 | +type_init(mchp_pfsoc_ddr_sgmii_phy_register_types) | ||
| 227 | + | ||
| 228 | +/* DDR CFG module */ | ||
| 229 | + | ||
| 230 | +#define CFG_MT_DONE_ACK 0x4428 | ||
| 231 | +#define CFG_STAT_DFI_INIT_COMPLETE 0x10034 | ||
| 232 | +#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038 | ||
| 233 | + | ||
| 234 | +static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset, | ||
| 235 | + unsigned size) | ||
| 236 | +{ | ||
| 237 | + uint32_t val = 0; | ||
| 238 | + | ||
| 239 | + switch (offset) { | ||
| 240 | + case CFG_MT_DONE_ACK: | ||
| 241 | + /* memory test in MTC_test() */ | ||
| 242 | + val = BIT(0); | ||
| 243 | + break; | ||
| 244 | + case CFG_STAT_DFI_INIT_COMPLETE: | ||
| 245 | + /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */ | ||
| 246 | + val = BIT(0); | ||
| 247 | + break; | ||
| 248 | + case CFG_STAT_DFI_TRAINING_COMPLETE: | ||
| 249 | + /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */ | ||
| 250 | + val = BIT(0); | ||
| 251 | + break; | ||
| 252 | + default: | ||
| 253 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 254 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 255 | + __func__, size, offset); | ||
| 256 | + break; | ||
| 257 | + } | ||
| 258 | + | ||
| 259 | + return val; | ||
| 260 | +} | ||
| 261 | + | ||
| 262 | +static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset, | ||
| 263 | + uint64_t value, unsigned size) | ||
| 264 | +{ | ||
| 265 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | ||
| 266 | + "(size %d, value 0x%" PRIx64 | ||
| 267 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
| 268 | + __func__, size, value, offset); | ||
| 269 | +} | ||
| 270 | + | ||
| 271 | +static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = { | ||
| 272 | + .read = mchp_pfsoc_ddr_cfg_read, | ||
| 273 | + .write = mchp_pfsoc_ddr_cfg_write, | ||
| 274 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 275 | +}; | ||
| 276 | + | ||
| 277 | +static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp) | ||
| 278 | +{ | ||
| 279 | + MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev); | ||
| 280 | + | ||
| 281 | + memory_region_init_io(&s->cfg, OBJECT(dev), | ||
| 282 | + &mchp_pfsoc_ddr_cfg_ops, s, | ||
| 283 | + "mchp.pfsoc.ddr_cfg", | ||
| 284 | + MCHP_PFSOC_DDR_CFG_REG_SIZE); | ||
| 285 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg); | ||
| 286 | +} | ||
| 287 | + | ||
| 288 | +static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data) | ||
| 289 | +{ | ||
| 290 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 291 | + | ||
| 292 | + dc->desc = "Microchip PolarFire SoC DDR CFG module"; | ||
| 293 | + dc->realize = mchp_pfsoc_ddr_cfg_realize; | ||
| 294 | +} | ||
| 295 | + | ||
| 296 | +static const TypeInfo mchp_pfsoc_ddr_cfg_info = { | ||
| 297 | + .name = TYPE_MCHP_PFSOC_DDR_CFG, | ||
| 298 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 299 | + .instance_size = sizeof(MchpPfSoCDdrCfgState), | ||
| 300 | + .class_init = mchp_pfsoc_ddr_cfg_class_init, | ||
| 301 | +}; | ||
| 302 | + | ||
| 303 | +static void mchp_pfsoc_ddr_cfg_register_types(void) | ||
| 304 | +{ | ||
| 305 | + type_register_static(&mchp_pfsoc_ddr_cfg_info); | ||
| 306 | +} | ||
| 307 | + | ||
| 308 | +type_init(mchp_pfsoc_ddr_cfg_register_types) | ||
| 309 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 310 | index XXXXXXX..XXXXXXX 100644 | ||
| 311 | --- a/MAINTAINERS | ||
| 312 | +++ b/MAINTAINERS | ||
| 313 | @@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org | ||
| 314 | S: Supported | ||
| 315 | F: hw/riscv/microchip_pfsoc.c | ||
| 316 | F: hw/char/mchp_pfsoc_mmuart.c | ||
| 317 | +F: hw/misc/mchp_pfsoc_dmc.c | ||
| 318 | F: include/hw/riscv/microchip_pfsoc.h | ||
| 319 | F: include/hw/char/mchp_pfsoc_mmuart.h | ||
| 320 | +F: include/hw/misc/mchp_pfsoc_dmc.h | ||
| 321 | |||
| 322 | RX Machines | ||
| 323 | ----------- | ||
| 324 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
| 325 | index XXXXXXX..XXXXXXX 100644 | ||
| 326 | --- a/hw/misc/Kconfig | ||
| 327 | +++ b/hw/misc/Kconfig | ||
| 328 | @@ -XXX,XX +XXX,XX @@ config MAC_VIA | ||
| 329 | config AVR_POWER | ||
| 330 | bool | ||
| 331 | |||
| 332 | +config MCHP_PFSOC_DMC | ||
| 333 | + bool | ||
| 334 | + | ||
| 335 | config SIFIVE_TEST | ||
| 336 | bool | ||
| 337 | |||
| 338 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
| 339 | index XXXXXXX..XXXXXXX 100644 | ||
| 340 | --- a/hw/misc/meson.build | ||
| 341 | +++ b/hw/misc/meson.build | ||
| 342 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) | ||
| 343 | softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
| 344 | |||
| 345 | # RISC-V devices | ||
| 346 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
| 347 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
| 348 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
| 349 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
| 350 | -- | ||
| 351 | 2.28.0 | ||
| 352 | |||
| 353 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. | ||
| 4 | |||
| 5 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 7 | Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com | ||
| 8 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | --- | ||
| 10 | include/hw/riscv/microchip_pfsoc.h | 5 +++++ | ||
| 11 | hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ | ||
| 12 | hw/riscv/Kconfig | 1 + | ||
| 13 | 3 files changed, 24 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/include/hw/riscv/microchip_pfsoc.h | ||
| 18 | +++ b/include/hw/riscv/microchip_pfsoc.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | |||
| 21 | #include "hw/char/mchp_pfsoc_mmuart.h" | ||
| 22 | #include "hw/dma/sifive_pdma.h" | ||
| 23 | +#include "hw/misc/mchp_pfsoc_dmc.h" | ||
| 24 | #include "hw/net/cadence_gem.h" | ||
| 25 | #include "hw/sd/cadence_sdhci.h" | ||
| 26 | |||
| 27 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | ||
| 28 | RISCVHartArrayState e_cpus; | ||
| 29 | RISCVHartArrayState u_cpus; | ||
| 30 | DeviceState *plic; | ||
| 31 | + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; | ||
| 32 | + MchpPfSoCDdrCfgState ddr_cfg; | ||
| 33 | MchpPfSoCMMUartState *serial0; | ||
| 34 | MchpPfSoCMMUartState *serial1; | ||
| 35 | MchpPfSoCMMUartState *serial2; | ||
| 36 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 37 | MICROCHIP_PFSOC_MMUART0, | ||
| 38 | MICROCHIP_PFSOC_SYSREG, | ||
| 39 | MICROCHIP_PFSOC_MPUCFG, | ||
| 40 | + MICROCHIP_PFSOC_DDR_SGMII_PHY, | ||
| 41 | MICROCHIP_PFSOC_EMMC_SD, | ||
| 42 | + MICROCHIP_PFSOC_DDR_CFG, | ||
| 43 | MICROCHIP_PFSOC_MMUART1, | ||
| 44 | MICROCHIP_PFSOC_MMUART2, | ||
| 45 | MICROCHIP_PFSOC_MMUART3, | ||
| 46 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 49 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | ||
| 51 | * 4) Cadence eMMC/SDHC controller and an SD card connected to it | ||
| 52 | * 5) SiFive Platform DMA (Direct Memory Access Controller) | ||
| 53 | * 6) GEM (Gigabit Ethernet MAC Controller) | ||
| 54 | + * 7) DMC (DDR Memory Controller) | ||
| 55 | * | ||
| 56 | * This board currently generates devicetree dynamically that indicates at least | ||
| 57 | * two harts and up to five harts. | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
| 59 | [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, | ||
| 60 | [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, | ||
| 61 | [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, | ||
| 62 | + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, | ||
| 63 | [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, | ||
| 64 | + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, | ||
| 65 | [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, | ||
| 66 | [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, | ||
| 67 | [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
| 69 | object_initialize_child(obj, "dma-controller", &s->dma, | ||
| 70 | TYPE_SIFIVE_PDMA); | ||
| 71 | |||
| 72 | + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, | ||
| 73 | + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); | ||
| 74 | + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, | ||
| 75 | + TYPE_MCHP_PFSOC_DDR_CFG); | ||
| 76 | + | ||
| 77 | object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); | ||
| 78 | object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); | ||
| 79 | |||
| 80 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 81 | memmap[MICROCHIP_PFSOC_MPUCFG].base, | ||
| 82 | memmap[MICROCHIP_PFSOC_MPUCFG].size); | ||
| 83 | |||
| 84 | + /* DDR SGMII PHY */ | ||
| 85 | + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); | ||
| 86 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, | ||
| 87 | + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); | ||
| 88 | + | ||
| 89 | + /* DDR CFG */ | ||
| 90 | + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); | ||
| 91 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, | ||
| 92 | + memmap[MICROCHIP_PFSOC_DDR_CFG].base); | ||
| 93 | + | ||
| 94 | /* SDHCI */ | ||
| 95 | sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); | ||
| 96 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 97 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | ||
| 98 | index XXXXXXX..XXXXXXX 100644 | ||
| 99 | --- a/hw/riscv/Kconfig | ||
| 100 | +++ b/hw/riscv/Kconfig | ||
| 101 | @@ -XXX,XX +XXX,XX @@ config IBEX | ||
| 102 | config MICROCHIP_PFSOC | ||
| 103 | bool | ||
| 104 | select CADENCE_SDHCI | ||
| 105 | + select MCHP_PFSOC_DMC | ||
| 106 | select MCHP_PFSOC_MMUART | ||
| 107 | select MSI_NONBROKEN | ||
| 108 | select SIFIVE_CLINT | ||
| 109 | -- | ||
| 110 | 2.28.0 | ||
| 111 | |||
| 112 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Bin Meng <bin.meng@windriver.com> | |
| 2 | |||
| 3 | This creates a model for PolarFire SoC IOSCB [1] module. It actually | ||
| 4 | contains lots of sub-modules like various PLLs to control different | ||
| 5 | peripherals. Only the mininum capabilities are emulated to make the | ||
| 6 | HSS DDR memory initialization codes happy. Lots of sub-modules are | ||
| 7 | created as an unimplemented devices. | ||
| 8 | |||
| 9 | [1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in | ||
| 10 | https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map | ||
| 11 | |||
| 12 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 14 | Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com | ||
| 15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | --- | ||
| 17 | include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++ | ||
| 18 | hw/misc/mchp_pfsoc_ioscb.c | 242 +++++++++++++++++++++++++++++ | ||
| 19 | MAINTAINERS | 2 + | ||
| 20 | hw/misc/Kconfig | 3 + | ||
| 21 | hw/misc/meson.build | 1 + | ||
| 22 | 5 files changed, 298 insertions(+) | ||
| 23 | create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 24 | create mode 100644 hw/misc/mchp_pfsoc_ioscb.c | ||
| 25 | |||
| 26 | diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 27 | new file mode 100644 | ||
| 28 | index XXXXXXX..XXXXXXX | ||
| 29 | --- /dev/null | ||
| 30 | +++ b/include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 31 | @@ -XXX,XX +XXX,XX @@ | ||
| 32 | +/* | ||
| 33 | + * Microchip PolarFire SoC IOSCB module emulation | ||
| 34 | + * | ||
| 35 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 36 | + * | ||
| 37 | + * Author: | ||
| 38 | + * Bin Meng <bin.meng@windriver.com> | ||
| 39 | + * | ||
| 40 | + * This program is free software; you can redistribute it and/or | ||
| 41 | + * modify it under the terms of the GNU General Public License as | ||
| 42 | + * published by the Free Software Foundation; either version 2 or | ||
| 43 | + * (at your option) version 3 of the License. | ||
| 44 | + * | ||
| 45 | + * This program is distributed in the hope that it will be useful, | ||
| 46 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 47 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 48 | + * GNU General Public License for more details. | ||
| 49 | + * | ||
| 50 | + * You should have received a copy of the GNU General Public License along | ||
| 51 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 52 | + */ | ||
| 53 | + | ||
| 54 | +#ifndef MCHP_PFSOC_IOSCB_H | ||
| 55 | +#define MCHP_PFSOC_IOSCB_H | ||
| 56 | + | ||
| 57 | +typedef struct MchpPfSoCIoscbState { | ||
| 58 | + SysBusDevice parent; | ||
| 59 | + MemoryRegion container; | ||
| 60 | + MemoryRegion lane01; | ||
| 61 | + MemoryRegion lane23; | ||
| 62 | + MemoryRegion ctrl; | ||
| 63 | + MemoryRegion cfg; | ||
| 64 | + MemoryRegion pll_mss; | ||
| 65 | + MemoryRegion cfm_mss; | ||
| 66 | + MemoryRegion pll_ddr; | ||
| 67 | + MemoryRegion bc_ddr; | ||
| 68 | + MemoryRegion io_calib_ddr; | ||
| 69 | + MemoryRegion pll_sgmii; | ||
| 70 | + MemoryRegion dll_sgmii; | ||
| 71 | + MemoryRegion cfm_sgmii; | ||
| 72 | + MemoryRegion bc_sgmii; | ||
| 73 | + MemoryRegion io_calib_sgmii; | ||
| 74 | +} MchpPfSoCIoscbState; | ||
| 75 | + | ||
| 76 | +#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb" | ||
| 77 | + | ||
| 78 | +#define MCHP_PFSOC_IOSCB(obj) \ | ||
| 79 | + OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB) | ||
| 80 | + | ||
| 81 | +#endif /* MCHP_PFSOC_IOSCB_H */ | ||
| 82 | diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c | ||
| 83 | new file mode 100644 | ||
| 84 | index XXXXXXX..XXXXXXX | ||
| 85 | --- /dev/null | ||
| 86 | +++ b/hw/misc/mchp_pfsoc_ioscb.c | ||
| 87 | @@ -XXX,XX +XXX,XX @@ | ||
| 88 | +/* | ||
| 89 | + * Microchip PolarFire SoC IOSCB module emulation | ||
| 90 | + * | ||
| 91 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 92 | + * | ||
| 93 | + * Author: | ||
| 94 | + * Bin Meng <bin.meng@windriver.com> | ||
| 95 | + * | ||
| 96 | + * This program is free software; you can redistribute it and/or | ||
| 97 | + * modify it under the terms of the GNU General Public License as | ||
| 98 | + * published by the Free Software Foundation; either version 2 or | ||
| 99 | + * (at your option) version 3 of the License. | ||
| 100 | + * | ||
| 101 | + * This program is distributed in the hope that it will be useful, | ||
| 102 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 103 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 104 | + * GNU General Public License for more details. | ||
| 105 | + * | ||
| 106 | + * You should have received a copy of the GNU General Public License along | ||
| 107 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 108 | + */ | ||
| 109 | + | ||
| 110 | +#include "qemu/osdep.h" | ||
| 111 | +#include "qemu/bitops.h" | ||
| 112 | +#include "qemu/log.h" | ||
| 113 | +#include "qapi/error.h" | ||
| 114 | +#include "hw/hw.h" | ||
| 115 | +#include "hw/sysbus.h" | ||
| 116 | +#include "hw/misc/mchp_pfsoc_ioscb.h" | ||
| 117 | + | ||
| 118 | +/* | ||
| 119 | + * The whole IOSCB module registers map into the system address at 0x3000_0000, | ||
| 120 | + * named as "System Port 0 (AXI-D0)". | ||
| 121 | + */ | ||
| 122 | +#define IOSCB_WHOLE_REG_SIZE 0x10000000 | ||
| 123 | +#define IOSCB_SUBMOD_REG_SIZE 0x1000 | ||
| 124 | + | ||
| 125 | +/* | ||
| 126 | + * There are many sub-modules in the IOSCB module. | ||
| 127 | + * See Microchip PolarFire SoC documentation (Register_Map.zip), | ||
| 128 | + * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm | ||
| 129 | + * | ||
| 130 | + * The following are sub-modules offsets that are of concern. | ||
| 131 | + */ | ||
| 132 | +#define IOSCB_LANE01_BASE 0x06500000 | ||
| 133 | +#define IOSCB_LANE23_BASE 0x06510000 | ||
| 134 | +#define IOSCB_CTRL_BASE 0x07020000 | ||
| 135 | +#define IOSCB_CFG_BASE 0x07080000 | ||
| 136 | +#define IOSCB_PLL_MSS_BASE 0x0E001000 | ||
| 137 | +#define IOSCB_CFM_MSS_BASE 0x0E002000 | ||
| 138 | +#define IOSCB_PLL_DDR_BASE 0x0E010000 | ||
| 139 | +#define IOSCB_BC_DDR_BASE 0x0E020000 | ||
| 140 | +#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000 | ||
| 141 | +#define IOSCB_PLL_SGMII_BASE 0x0E080000 | ||
| 142 | +#define IOSCB_DLL_SGMII_BASE 0x0E100000 | ||
| 143 | +#define IOSCB_CFM_SGMII_BASE 0x0E200000 | ||
| 144 | +#define IOSCB_BC_SGMII_BASE 0x0E400000 | ||
| 145 | +#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000 | ||
| 146 | + | ||
| 147 | +static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset, | ||
| 148 | + unsigned size) | ||
| 149 | +{ | ||
| 150 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 151 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 152 | + __func__, size, offset); | ||
| 153 | + | ||
| 154 | + return 0; | ||
| 155 | +} | ||
| 156 | + | ||
| 157 | +static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset, | ||
| 158 | + uint64_t value, unsigned size) | ||
| 159 | +{ | ||
| 160 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | ||
| 161 | + "(size %d, value 0x%" PRIx64 | ||
| 162 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
| 163 | + __func__, size, value, offset); | ||
| 164 | +} | ||
| 165 | + | ||
| 166 | +static const MemoryRegionOps mchp_pfsoc_dummy_ops = { | ||
| 167 | + .read = mchp_pfsoc_dummy_read, | ||
| 168 | + .write = mchp_pfsoc_dummy_write, | ||
| 169 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 170 | +}; | ||
| 171 | + | ||
| 172 | +/* All PLL modules in IOSCB have the same register layout */ | ||
| 173 | + | ||
| 174 | +#define PLL_CTRL 0x04 | ||
| 175 | + | ||
| 176 | +static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset, | ||
| 177 | + unsigned size) | ||
| 178 | +{ | ||
| 179 | + uint32_t val = 0; | ||
| 180 | + | ||
| 181 | + switch (offset) { | ||
| 182 | + case PLL_CTRL: | ||
| 183 | + /* PLL is locked */ | ||
| 184 | + val = BIT(25); | ||
| 185 | + break; | ||
| 186 | + default: | ||
| 187 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 188 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 189 | + __func__, size, offset); | ||
| 190 | + break; | ||
| 191 | + } | ||
| 192 | + | ||
| 193 | + return val; | ||
| 194 | +} | ||
| 195 | + | ||
| 196 | +static const MemoryRegionOps mchp_pfsoc_pll_ops = { | ||
| 197 | + .read = mchp_pfsoc_pll_read, | ||
| 198 | + .write = mchp_pfsoc_dummy_write, | ||
| 199 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 200 | +}; | ||
| 201 | + | ||
| 202 | +/* IO_CALIB_DDR submodule */ | ||
| 203 | + | ||
| 204 | +#define IO_CALIB_DDR_IOC_REG1 0x08 | ||
| 205 | + | ||
| 206 | +static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset, | ||
| 207 | + unsigned size) | ||
| 208 | +{ | ||
| 209 | + uint32_t val = 0; | ||
| 210 | + | ||
| 211 | + switch (offset) { | ||
| 212 | + case IO_CALIB_DDR_IOC_REG1: | ||
| 213 | + /* calibration completed */ | ||
| 214 | + val = BIT(2); | ||
| 215 | + break; | ||
| 216 | + default: | ||
| 217 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 218 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 219 | + __func__, size, offset); | ||
| 220 | + break; | ||
| 221 | + } | ||
| 222 | + | ||
| 223 | + return val; | ||
| 224 | +} | ||
| 225 | + | ||
| 226 | +static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { | ||
| 227 | + .read = mchp_pfsoc_io_calib_ddr_read, | ||
| 228 | + .write = mchp_pfsoc_dummy_write, | ||
| 229 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 230 | +}; | ||
| 231 | + | ||
| 232 | +static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) | ||
| 233 | +{ | ||
| 234 | + MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); | ||
| 235 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 236 | + | ||
| 237 | + memory_region_init(&s->container, OBJECT(s), | ||
| 238 | + "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE); | ||
| 239 | + sysbus_init_mmio(sbd, &s->container); | ||
| 240 | + | ||
| 241 | + /* add subregions for all sub-modules in IOSCB */ | ||
| 242 | + | ||
| 243 | + memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 244 | + "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE); | ||
| 245 | + memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01); | ||
| 246 | + | ||
| 247 | + memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 248 | + "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE); | ||
| 249 | + memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23); | ||
| 250 | + | ||
| 251 | + memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 252 | + "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE); | ||
| 253 | + memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl); | ||
| 254 | + | ||
| 255 | + memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 256 | + "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); | ||
| 257 | + memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); | ||
| 258 | + | ||
| 259 | + memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
| 260 | + "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE); | ||
| 261 | + memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss); | ||
| 262 | + | ||
| 263 | + memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 264 | + "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE); | ||
| 265 | + memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss); | ||
| 266 | + | ||
| 267 | + memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
| 268 | + "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE); | ||
| 269 | + memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr); | ||
| 270 | + | ||
| 271 | + memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 272 | + "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE); | ||
| 273 | + memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr); | ||
| 274 | + | ||
| 275 | + memory_region_init_io(&s->io_calib_ddr, OBJECT(s), | ||
| 276 | + &mchp_pfsoc_io_calib_ddr_ops, s, | ||
| 277 | + "mchp.pfsoc.ioscb.io_calib_ddr", | ||
| 278 | + IOSCB_SUBMOD_REG_SIZE); | ||
| 279 | + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE, | ||
| 280 | + &s->io_calib_ddr); | ||
| 281 | + | ||
| 282 | + memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
| 283 | + "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
| 284 | + memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE, | ||
| 285 | + &s->pll_sgmii); | ||
| 286 | + | ||
| 287 | + memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 288 | + "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
| 289 | + memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE, | ||
| 290 | + &s->dll_sgmii); | ||
| 291 | + | ||
| 292 | + memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 293 | + "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
| 294 | + memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE, | ||
| 295 | + &s->cfm_sgmii); | ||
| 296 | + | ||
| 297 | + memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
| 298 | + "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
| 299 | + memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE, | ||
| 300 | + &s->bc_sgmii); | ||
| 301 | + | ||
| 302 | + memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, | ||
| 303 | + s, "mchp.pfsoc.ioscb.io_calib_sgmii", | ||
| 304 | + IOSCB_SUBMOD_REG_SIZE); | ||
| 305 | + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE, | ||
| 306 | + &s->io_calib_sgmii); | ||
| 307 | +} | ||
| 308 | + | ||
| 309 | +static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data) | ||
| 310 | +{ | ||
| 311 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 312 | + | ||
| 313 | + dc->desc = "Microchip PolarFire SoC IOSCB modules"; | ||
| 314 | + dc->realize = mchp_pfsoc_ioscb_realize; | ||
| 315 | +} | ||
| 316 | + | ||
| 317 | +static const TypeInfo mchp_pfsoc_ioscb_info = { | ||
| 318 | + .name = TYPE_MCHP_PFSOC_IOSCB, | ||
| 319 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 320 | + .instance_size = sizeof(MchpPfSoCIoscbState), | ||
| 321 | + .class_init = mchp_pfsoc_ioscb_class_init, | ||
| 322 | +}; | ||
| 323 | + | ||
| 324 | +static void mchp_pfsoc_ioscb_register_types(void) | ||
| 325 | +{ | ||
| 326 | + type_register_static(&mchp_pfsoc_ioscb_info); | ||
| 327 | +} | ||
| 328 | + | ||
| 329 | +type_init(mchp_pfsoc_ioscb_register_types) | ||
| 330 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 331 | index XXXXXXX..XXXXXXX 100644 | ||
| 332 | --- a/MAINTAINERS | ||
| 333 | +++ b/MAINTAINERS | ||
| 334 | @@ -XXX,XX +XXX,XX @@ S: Supported | ||
| 335 | F: hw/riscv/microchip_pfsoc.c | ||
| 336 | F: hw/char/mchp_pfsoc_mmuart.c | ||
| 337 | F: hw/misc/mchp_pfsoc_dmc.c | ||
| 338 | +F: hw/misc/mchp_pfsoc_ioscb.c | ||
| 339 | F: include/hw/riscv/microchip_pfsoc.h | ||
| 340 | F: include/hw/char/mchp_pfsoc_mmuart.h | ||
| 341 | F: include/hw/misc/mchp_pfsoc_dmc.h | ||
| 342 | +F: include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 343 | |||
| 344 | RX Machines | ||
| 345 | ----------- | ||
| 346 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
| 347 | index XXXXXXX..XXXXXXX 100644 | ||
| 348 | --- a/hw/misc/Kconfig | ||
| 349 | +++ b/hw/misc/Kconfig | ||
| 350 | @@ -XXX,XX +XXX,XX @@ config AVR_POWER | ||
| 351 | config MCHP_PFSOC_DMC | ||
| 352 | bool | ||
| 353 | |||
| 354 | +config MCHP_PFSOC_IOSCB | ||
| 355 | + bool | ||
| 356 | + | ||
| 357 | config SIFIVE_TEST | ||
| 358 | bool | ||
| 359 | |||
| 360 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
| 361 | index XXXXXXX..XXXXXXX 100644 | ||
| 362 | --- a/hw/misc/meson.build | ||
| 363 | +++ b/hw/misc/meson.build | ||
| 364 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
| 365 | |||
| 366 | # RISC-V devices | ||
| 367 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
| 368 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) | ||
| 369 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
| 370 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
| 371 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
| 372 | -- | ||
| 373 | 2.28.0 | ||
| 374 | |||
| 375 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | Previously IOSCB_CFG was created as an unimplemented device. With | ||
| 4 | the new IOSCB model, its memory range is already covered by the | ||
| 5 | IOSCB hence remove the previous unimplemented device creation in | ||
| 6 | the SoC codes. | ||
| 7 | |||
| 8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | include/hw/riscv/microchip_pfsoc.h | 4 +++- | ||
| 14 | hw/riscv/microchip_pfsoc.c | 13 ++++++++----- | ||
| 15 | hw/riscv/Kconfig | 1 + | ||
| 16 | 3 files changed, 12 insertions(+), 6 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/include/hw/riscv/microchip_pfsoc.h | ||
| 21 | +++ b/include/hw/riscv/microchip_pfsoc.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ | ||
| 23 | #include "hw/char/mchp_pfsoc_mmuart.h" | ||
| 24 | #include "hw/dma/sifive_pdma.h" | ||
| 25 | #include "hw/misc/mchp_pfsoc_dmc.h" | ||
| 26 | +#include "hw/misc/mchp_pfsoc_ioscb.h" | ||
| 27 | #include "hw/net/cadence_gem.h" | ||
| 28 | #include "hw/sd/cadence_sdhci.h" | ||
| 29 | |||
| 30 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | ||
| 31 | DeviceState *plic; | ||
| 32 | MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; | ||
| 33 | MchpPfSoCDdrCfgState ddr_cfg; | ||
| 34 | + MchpPfSoCIoscbState ioscb; | ||
| 35 | MchpPfSoCMMUartState *serial0; | ||
| 36 | MchpPfSoCMMUartState *serial1; | ||
| 37 | MchpPfSoCMMUartState *serial2; | ||
| 38 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 39 | MICROCHIP_PFSOC_GPIO2, | ||
| 40 | MICROCHIP_PFSOC_ENVM_CFG, | ||
| 41 | MICROCHIP_PFSOC_ENVM_DATA, | ||
| 42 | - MICROCHIP_PFSOC_IOSCB_CFG, | ||
| 43 | + MICROCHIP_PFSOC_IOSCB, | ||
| 44 | MICROCHIP_PFSOC_DRAM, | ||
| 45 | }; | ||
| 46 | |||
| 47 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | ||
| 49 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 50 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 51 | @@ -XXX,XX +XXX,XX @@ | ||
| 52 | * 5) SiFive Platform DMA (Direct Memory Access Controller) | ||
| 53 | * 6) GEM (Gigabit Ethernet MAC Controller) | ||
| 54 | * 7) DMC (DDR Memory Controller) | ||
| 55 | + * 8) IOSCB modules | ||
| 56 | * | ||
| 57 | * This board currently generates devicetree dynamically that indicates at least | ||
| 58 | * two harts and up to five harts. | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
| 60 | [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, | ||
| 61 | [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, | ||
| 62 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, | ||
| 63 | - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, | ||
| 64 | + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, | ||
| 65 | [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, | ||
| 66 | }; | ||
| 67 | |||
| 68 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
| 69 | |||
| 70 | object_initialize_child(obj, "sd-controller", &s->sdhci, | ||
| 71 | TYPE_CADENCE_SDHCI); | ||
| 72 | + | ||
| 73 | + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); | ||
| 74 | } | ||
| 75 | |||
| 76 | static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 78 | memmap[MICROCHIP_PFSOC_ENVM_DATA].base, | ||
| 79 | envm_data); | ||
| 80 | |||
| 81 | - /* IOSCBCFG */ | ||
| 82 | - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", | ||
| 83 | - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, | ||
| 84 | - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); | ||
| 85 | + /* IOSCB */ | ||
| 86 | + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); | ||
| 87 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, | ||
| 88 | + memmap[MICROCHIP_PFSOC_IOSCB].base); | ||
| 89 | } | ||
| 90 | |||
| 91 | static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) | ||
| 92 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | ||
| 93 | index XXXXXXX..XXXXXXX 100644 | ||
| 94 | --- a/hw/riscv/Kconfig | ||
| 95 | +++ b/hw/riscv/Kconfig | ||
| 96 | @@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC | ||
| 97 | bool | ||
| 98 | select CADENCE_SDHCI | ||
| 99 | select MCHP_PFSOC_DMC | ||
| 100 | + select MCHP_PFSOC_IOSCB | ||
| 101 | select MCHP_PFSOC_MMUART | ||
| 102 | select MSI_NONBROKEN | ||
| 103 | select SIFIVE_CLINT | ||
| 104 | -- | ||
| 105 | 2.28.0 | ||
| 106 | |||
| 107 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Bin Meng <bin.meng@windriver.com> | |
| 2 | |||
| 3 | This creates a minimum model for Microchip PolarFire SoC SYSREG | ||
| 4 | module. It only implements the ENVM_CR register to tell guest | ||
| 5 | software that eNVM is running at the configured divider rate. | ||
| 6 | |||
| 7 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++ | ||
| 13 | hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++++++++++++++++ | ||
| 14 | MAINTAINERS | 2 + | ||
| 15 | hw/misc/Kconfig | 3 + | ||
| 16 | hw/misc/meson.build | 1 + | ||
| 17 | 5 files changed, 144 insertions(+) | ||
| 18 | create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h | ||
| 19 | create mode 100644 hw/misc/mchp_pfsoc_sysreg.c | ||
| 20 | |||
| 21 | diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h | ||
| 22 | new file mode 100644 | ||
| 23 | index XXXXXXX..XXXXXXX | ||
| 24 | --- /dev/null | ||
| 25 | +++ b/include/hw/misc/mchp_pfsoc_sysreg.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ | ||
| 27 | +/* | ||
| 28 | + * Microchip PolarFire SoC SYSREG module emulation | ||
| 29 | + * | ||
| 30 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 31 | + * | ||
| 32 | + * Author: | ||
| 33 | + * Bin Meng <bin.meng@windriver.com> | ||
| 34 | + * | ||
| 35 | + * This program is free software; you can redistribute it and/or | ||
| 36 | + * modify it under the terms of the GNU General Public License as | ||
| 37 | + * published by the Free Software Foundation; either version 2 or | ||
| 38 | + * (at your option) version 3 of the License. | ||
| 39 | + * | ||
| 40 | + * This program is distributed in the hope that it will be useful, | ||
| 41 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 42 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 43 | + * GNU General Public License for more details. | ||
| 44 | + * | ||
| 45 | + * You should have received a copy of the GNU General Public License along | ||
| 46 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 47 | + */ | ||
| 48 | + | ||
| 49 | +#ifndef MCHP_PFSOC_SYSREG_H | ||
| 50 | +#define MCHP_PFSOC_SYSREG_H | ||
| 51 | + | ||
| 52 | +#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000 | ||
| 53 | + | ||
| 54 | +typedef struct MchpPfSoCSysregState { | ||
| 55 | + SysBusDevice parent; | ||
| 56 | + MemoryRegion sysreg; | ||
| 57 | +} MchpPfSoCSysregState; | ||
| 58 | + | ||
| 59 | +#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg" | ||
| 60 | + | ||
| 61 | +#define MCHP_PFSOC_SYSREG(obj) \ | ||
| 62 | + OBJECT_CHECK(MchpPfSoCSysregState, (obj), \ | ||
| 63 | + TYPE_MCHP_PFSOC_SYSREG) | ||
| 64 | + | ||
| 65 | +#endif /* MCHP_PFSOC_SYSREG_H */ | ||
| 66 | diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c | ||
| 67 | new file mode 100644 | ||
| 68 | index XXXXXXX..XXXXXXX | ||
| 69 | --- /dev/null | ||
| 70 | +++ b/hw/misc/mchp_pfsoc_sysreg.c | ||
| 71 | @@ -XXX,XX +XXX,XX @@ | ||
| 72 | +/* | ||
| 73 | + * Microchip PolarFire SoC SYSREG module emulation | ||
| 74 | + * | ||
| 75 | + * Copyright (c) 2020 Wind River Systems, Inc. | ||
| 76 | + * | ||
| 77 | + * Author: | ||
| 78 | + * Bin Meng <bin.meng@windriver.com> | ||
| 79 | + * | ||
| 80 | + * This program is free software; you can redistribute it and/or | ||
| 81 | + * modify it under the terms of the GNU General Public License as | ||
| 82 | + * published by the Free Software Foundation; either version 2 or | ||
| 83 | + * (at your option) version 3 of the License. | ||
| 84 | + * | ||
| 85 | + * This program is distributed in the hope that it will be useful, | ||
| 86 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 87 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 88 | + * GNU General Public License for more details. | ||
| 89 | + * | ||
| 90 | + * You should have received a copy of the GNU General Public License along | ||
| 91 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 92 | + */ | ||
| 93 | + | ||
| 94 | +#include "qemu/osdep.h" | ||
| 95 | +#include "qemu/bitops.h" | ||
| 96 | +#include "qemu/log.h" | ||
| 97 | +#include "qapi/error.h" | ||
| 98 | +#include "hw/hw.h" | ||
| 99 | +#include "hw/sysbus.h" | ||
| 100 | +#include "hw/misc/mchp_pfsoc_sysreg.h" | ||
| 101 | + | ||
| 102 | +#define ENVM_CR 0xb8 | ||
| 103 | + | ||
| 104 | +static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, | ||
| 105 | + unsigned size) | ||
| 106 | +{ | ||
| 107 | + uint32_t val = 0; | ||
| 108 | + | ||
| 109 | + switch (offset) { | ||
| 110 | + case ENVM_CR: | ||
| 111 | + /* Indicate the eNVM is running at the configured divider rate */ | ||
| 112 | + val = BIT(6); | ||
| 113 | + break; | ||
| 114 | + default: | ||
| 115 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
| 116 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
| 117 | + __func__, size, offset); | ||
| 118 | + break; | ||
| 119 | + } | ||
| 120 | + | ||
| 121 | + return val; | ||
| 122 | +} | ||
| 123 | + | ||
| 124 | +static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, | ||
| 125 | + uint64_t value, unsigned size) | ||
| 126 | +{ | ||
| 127 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | ||
| 128 | + "(size %d, value 0x%" PRIx64 | ||
| 129 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
| 130 | + __func__, size, value, offset); | ||
| 131 | +} | ||
| 132 | + | ||
| 133 | +static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { | ||
| 134 | + .read = mchp_pfsoc_sysreg_read, | ||
| 135 | + .write = mchp_pfsoc_sysreg_write, | ||
| 136 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 137 | +}; | ||
| 138 | + | ||
| 139 | +static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) | ||
| 140 | +{ | ||
| 141 | + MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev); | ||
| 142 | + | ||
| 143 | + memory_region_init_io(&s->sysreg, OBJECT(dev), | ||
| 144 | + &mchp_pfsoc_sysreg_ops, s, | ||
| 145 | + "mchp.pfsoc.sysreg", | ||
| 146 | + MCHP_PFSOC_SYSREG_REG_SIZE); | ||
| 147 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); | ||
| 148 | +} | ||
| 149 | + | ||
| 150 | +static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) | ||
| 151 | +{ | ||
| 152 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 153 | + | ||
| 154 | + dc->desc = "Microchip PolarFire SoC SYSREG module"; | ||
| 155 | + dc->realize = mchp_pfsoc_sysreg_realize; | ||
| 156 | +} | ||
| 157 | + | ||
| 158 | +static const TypeInfo mchp_pfsoc_sysreg_info = { | ||
| 159 | + .name = TYPE_MCHP_PFSOC_SYSREG, | ||
| 160 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 161 | + .instance_size = sizeof(MchpPfSoCSysregState), | ||
| 162 | + .class_init = mchp_pfsoc_sysreg_class_init, | ||
| 163 | +}; | ||
| 164 | + | ||
| 165 | +static void mchp_pfsoc_sysreg_register_types(void) | ||
| 166 | +{ | ||
| 167 | + type_register_static(&mchp_pfsoc_sysreg_info); | ||
| 168 | +} | ||
| 169 | + | ||
| 170 | +type_init(mchp_pfsoc_sysreg_register_types) | ||
| 171 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 172 | index XXXXXXX..XXXXXXX 100644 | ||
| 173 | --- a/MAINTAINERS | ||
| 174 | +++ b/MAINTAINERS | ||
| 175 | @@ -XXX,XX +XXX,XX @@ F: hw/riscv/microchip_pfsoc.c | ||
| 176 | F: hw/char/mchp_pfsoc_mmuart.c | ||
| 177 | F: hw/misc/mchp_pfsoc_dmc.c | ||
| 178 | F: hw/misc/mchp_pfsoc_ioscb.c | ||
| 179 | +F: hw/misc/mchp_pfsoc_sysreg.c | ||
| 180 | F: include/hw/riscv/microchip_pfsoc.h | ||
| 181 | F: include/hw/char/mchp_pfsoc_mmuart.h | ||
| 182 | F: include/hw/misc/mchp_pfsoc_dmc.h | ||
| 183 | F: include/hw/misc/mchp_pfsoc_ioscb.h | ||
| 184 | +F: include/hw/misc/mchp_pfsoc_sysreg.h | ||
| 185 | |||
| 186 | RX Machines | ||
| 187 | ----------- | ||
| 188 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
| 189 | index XXXXXXX..XXXXXXX 100644 | ||
| 190 | --- a/hw/misc/Kconfig | ||
| 191 | +++ b/hw/misc/Kconfig | ||
| 192 | @@ -XXX,XX +XXX,XX @@ config MCHP_PFSOC_DMC | ||
| 193 | config MCHP_PFSOC_IOSCB | ||
| 194 | bool | ||
| 195 | |||
| 196 | +config MCHP_PFSOC_SYSREG | ||
| 197 | + bool | ||
| 198 | + | ||
| 199 | config SIFIVE_TEST | ||
| 200 | bool | ||
| 201 | |||
| 202 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
| 203 | index XXXXXXX..XXXXXXX 100644 | ||
| 204 | --- a/hw/misc/meson.build | ||
| 205 | +++ b/hw/misc/meson.build | ||
| 206 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
| 207 | # RISC-V devices | ||
| 208 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
| 209 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) | ||
| 210 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) | ||
| 211 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
| 212 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
| 213 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
| 214 | -- | ||
| 215 | 2.28.0 | ||
| 216 | |||
| 217 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | Previously SYSREG was created as an unimplemented device. Now that | ||
| 4 | we have a simple SYSREG module, connect it. | ||
| 5 | |||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | include/hw/riscv/microchip_pfsoc.h | 2 ++ | ||
| 12 | hw/riscv/microchip_pfsoc.c | 9 ++++++--- | ||
| 13 | hw/riscv/Kconfig | 1 + | ||
| 14 | 3 files changed, 9 insertions(+), 3 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/riscv/microchip_pfsoc.h | ||
| 19 | +++ b/include/hw/riscv/microchip_pfsoc.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | #include "hw/dma/sifive_pdma.h" | ||
| 22 | #include "hw/misc/mchp_pfsoc_dmc.h" | ||
| 23 | #include "hw/misc/mchp_pfsoc_ioscb.h" | ||
| 24 | +#include "hw/misc/mchp_pfsoc_sysreg.h" | ||
| 25 | #include "hw/net/cadence_gem.h" | ||
| 26 | #include "hw/sd/cadence_sdhci.h" | ||
| 27 | |||
| 28 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | ||
| 29 | MchpPfSoCMMUartState *serial2; | ||
| 30 | MchpPfSoCMMUartState *serial3; | ||
| 31 | MchpPfSoCMMUartState *serial4; | ||
| 32 | + MchpPfSoCSysregState sysreg; | ||
| 33 | SiFivePDMAState dma; | ||
| 34 | CadenceGEMState gem0; | ||
| 35 | CadenceGEMState gem1; | ||
| 36 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 39 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
| 41 | object_initialize_child(obj, "dma-controller", &s->dma, | ||
| 42 | TYPE_SIFIVE_PDMA); | ||
| 43 | |||
| 44 | + object_initialize_child(obj, "sysreg", &s->sysreg, | ||
| 45 | + TYPE_MCHP_PFSOC_SYSREG); | ||
| 46 | + | ||
| 47 | object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, | ||
| 48 | TYPE_MCHP_PFSOC_DDR_SGMII_PHY); | ||
| 49 | object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 51 | } | ||
| 52 | |||
| 53 | /* SYSREG */ | ||
| 54 | - create_unimplemented_device("microchip.pfsoc.sysreg", | ||
| 55 | - memmap[MICROCHIP_PFSOC_SYSREG].base, | ||
| 56 | - memmap[MICROCHIP_PFSOC_SYSREG].size); | ||
| 57 | + sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); | ||
| 58 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, | ||
| 59 | + memmap[MICROCHIP_PFSOC_SYSREG].base); | ||
| 60 | |||
| 61 | /* MPUCFG */ | ||
| 62 | create_unimplemented_device("microchip.pfsoc.mpucfg", | ||
| 63 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/hw/riscv/Kconfig | ||
| 66 | +++ b/hw/riscv/Kconfig | ||
| 67 | @@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC | ||
| 68 | select MCHP_PFSOC_DMC | ||
| 69 | select MCHP_PFSOC_IOSCB | ||
| 70 | select MCHP_PFSOC_MMUART | ||
| 71 | + select MCHP_PFSOC_SYSREG | ||
| 72 | select MSI_NONBROKEN | ||
| 73 | select SIFIVE_CLINT | ||
| 74 | select SIFIVE_PDMA | ||
| 75 | -- | ||
| 76 | 2.28.0 | ||
| 77 | |||
| 78 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | Somehow HSS needs to access address 0 [1] for the DDR calibration data | ||
| 4 | which is in the chipset's reserved memory. Let's map it. | ||
| 5 | |||
| 6 | [1] See the config_copy() calls in various places in ddr_setup() in | ||
| 7 | the HSS source codes. | ||
| 8 | |||
| 9 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | include/hw/riscv/microchip_pfsoc.h | 1 + | ||
| 15 | hw/riscv/microchip_pfsoc.c | 11 ++++++++++- | ||
| 16 | 2 files changed, 11 insertions(+), 1 deletion(-) | ||
| 17 | |||
| 18 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/include/hw/riscv/microchip_pfsoc.h | ||
| 21 | +++ b/include/hw/riscv/microchip_pfsoc.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipIcicleKitState { | ||
| 23 | TYPE_MICROCHIP_ICICLE_KIT_MACHINE) | ||
| 24 | |||
| 25 | enum { | ||
| 26 | + MICROCHIP_PFSOC_RSVD0, | ||
| 27 | MICROCHIP_PFSOC_DEBUG, | ||
| 28 | MICROCHIP_PFSOC_E51_DTIM, | ||
| 29 | MICROCHIP_PFSOC_BUSERR_UNIT0, | ||
| 30 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 33 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 34 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
| 35 | hwaddr base; | ||
| 36 | hwaddr size; | ||
| 37 | } microchip_pfsoc_memmap[] = { | ||
| 38 | - [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, | ||
| 39 | + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, | ||
| 40 | + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, | ||
| 41 | [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, | ||
| 42 | [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, | ||
| 43 | [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 45 | MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); | ||
| 46 | const struct MemmapEntry *memmap = microchip_pfsoc_memmap; | ||
| 47 | MemoryRegion *system_memory = get_system_memory(); | ||
| 48 | + MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); | ||
| 49 | MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); | ||
| 50 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); | ||
| 51 | MemoryRegion *envm_data = g_new(MemoryRegion, 1); | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 53 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); | ||
| 54 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | ||
| 55 | |||
| 56 | + /* Reserved Memory at address 0 */ | ||
| 57 | + memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", | ||
| 58 | + memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); | ||
| 59 | + memory_region_add_subregion(system_memory, | ||
| 60 | + memmap[MICROCHIP_PFSOC_RSVD0].base, | ||
| 61 | + rsvd0_mem); | ||
| 62 | + | ||
| 63 | /* E51 DTIM */ | ||
| 64 | memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", | ||
| 65 | memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); | ||
| 66 | -- | ||
| 67 | 2.28.0 | ||
| 68 | |||
| 69 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Bin Meng <bin.meng@windriver.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. | 3 | When system memory is larger than 1 GiB (high memory), PolarFire SoC |
| 4 | maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is | ||
| 5 | aliased to the same 1 GiB low memory with different cache attributes. | ||
| 4 | 6 | ||
| 5 | Do not re-initialize the OTP content in the DeviceReset handler, | 7 | At present QEMU maps the system memory contiguously from 0x8000_0000. |
| 6 | initialize it once in the DeviceRealize one. | 8 | This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is |
| 9 | the alias to the high memory, and even physical memory is only 1 GiB, | ||
| 10 | the HSS codes still tries to probe the high memory alias address. | ||
| 11 | It seems there is no issue on the real hardware, so we will have to | ||
| 12 | take that into the consideration in our emulation. Due to this, we | ||
| 13 | we increase the default system memory size to 1537 MiB (the minimum | ||
| 14 | required high memory size by HSS) so that user gets notified an error | ||
| 15 | when less than 1537 MiB is specified. | ||
| 7 | 16 | ||
| 8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") | 17 | Signed-off-by: Bin Meng <bin.meng@windriver.com> |
| 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 18 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> | 19 | Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com |
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | --- | 21 | --- |
| 14 | hw/misc/sifive_u_otp.c | 13 +++++-------- | 22 | include/hw/riscv/microchip_pfsoc.h | 5 ++- |
| 15 | 1 file changed, 5 insertions(+), 8 deletions(-) | 23 | hw/riscv/microchip_pfsoc.c | 50 ++++++++++++++++++++++++++---- |
| 24 | 2 files changed, 48 insertions(+), 7 deletions(-) | ||
| 16 | 25 | ||
| 17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 26 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h |
| 18 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/misc/sifive_u_otp.c | 28 | --- a/include/hw/riscv/microchip_pfsoc.h |
| 20 | +++ b/hw/misc/sifive_u_otp.c | 29 | +++ b/include/hw/riscv/microchip_pfsoc.h |
| 21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 30 | @@ -XXX,XX +XXX,XX @@ enum { |
| 22 | 31 | MICROCHIP_PFSOC_ENVM_CFG, | |
| 23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { | 32 | MICROCHIP_PFSOC_ENVM_DATA, |
| 24 | error_setg(errp, "failed to read the initial flash content"); | 33 | MICROCHIP_PFSOC_IOSCB, |
| 25 | + return; | 34 | - MICROCHIP_PFSOC_DRAM, |
| 26 | } | 35 | + MICROCHIP_PFSOC_DRAM_LO, |
| 27 | } | 36 | + MICROCHIP_PFSOC_DRAM_LO_ALIAS, |
| 28 | } | 37 | + MICROCHIP_PFSOC_DRAM_HI, |
| 29 | -} | 38 | + MICROCHIP_PFSOC_DRAM_HI_ALIAS |
| 30 | - | 39 | }; |
| 31 | -static void sifive_u_otp_reset(DeviceState *dev) | 40 | |
| 32 | -{ | 41 | enum { |
| 33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); | 42 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c |
| 34 | 43 | index XXXXXXX..XXXXXXX 100644 | |
| 35 | /* Initialize all fuses' initial value to 0xFFs */ | 44 | --- a/hw/riscv/microchip_pfsoc.c |
| 36 | memset(s->fuse, 0xff, sizeof(s->fuse)); | 45 | +++ b/hw/riscv/microchip_pfsoc.c |
| 37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | 46 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { |
| 38 | serial_data = s->serial; | 47 | [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, |
| 39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | 48 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, |
| 40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 49 | [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, |
| 41 | - error_report("write error index<%d>", index); | 50 | - [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, |
| 42 | + error_setg(errp, "failed to write index<%d>", index); | 51 | + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, |
| 43 | + return; | 52 | + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, |
| 44 | } | 53 | + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, |
| 45 | 54 | + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, | |
| 46 | serial_data = ~(s->serial); | 55 | }; |
| 47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | 56 | |
| 48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 57 | static void microchip_pfsoc_soc_instance_init(Object *obj) |
| 49 | - error_report("write error index<%d>", index + 1); | 58 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) |
| 50 | + error_setg(errp, "failed to write index<%d>", index + 1); | 59 | const struct MemmapEntry *memmap = microchip_pfsoc_memmap; |
| 51 | + return; | 60 | MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); |
| 52 | } | 61 | MemoryRegion *system_memory = get_system_memory(); |
| 53 | } | 62 | - MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
| 54 | 63 | + MemoryRegion *mem_low = g_new(MemoryRegion, 1); | |
| 55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) | 64 | + MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); |
| 56 | 65 | + MemoryRegion *mem_high = g_new(MemoryRegion, 1); | |
| 57 | device_class_set_props(dc, sifive_u_otp_properties); | 66 | + MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); |
| 58 | dc->realize = sifive_u_otp_realize; | 67 | + uint64_t mem_high_size; |
| 59 | - dc->reset = sifive_u_otp_reset; | 68 | DriveInfo *dinfo = drive_get_next(IF_SD); |
| 69 | |||
| 70 | /* Sanity check on RAM size */ | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
| 72 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); | ||
| 73 | |||
| 74 | /* Register RAM */ | ||
| 75 | - memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", | ||
| 76 | - machine->ram_size, &error_fatal); | ||
| 77 | + memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low", | ||
| 78 | + memmap[MICROCHIP_PFSOC_DRAM_LO].size, | ||
| 79 | + &error_fatal); | ||
| 80 | + memory_region_init_alias(mem_low_alias, NULL, | ||
| 81 | + "microchip.icicle.kit.ram_low.alias", | ||
| 82 | + mem_low, 0, | ||
| 83 | + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size); | ||
| 84 | + memory_region_add_subregion(system_memory, | ||
| 85 | + memmap[MICROCHIP_PFSOC_DRAM_LO].base, | ||
| 86 | + mem_low); | ||
| 87 | memory_region_add_subregion(system_memory, | ||
| 88 | - memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); | ||
| 89 | + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, | ||
| 90 | + mem_low_alias); | ||
| 91 | + | ||
| 92 | + mem_high_size = machine->ram_size - 1 * GiB; | ||
| 93 | + | ||
| 94 | + memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high", | ||
| 95 | + mem_high_size, &error_fatal); | ||
| 96 | + memory_region_init_alias(mem_high_alias, NULL, | ||
| 97 | + "microchip.icicle.kit.ram_high.alias", | ||
| 98 | + mem_high, 0, mem_high_size); | ||
| 99 | + memory_region_add_subregion(system_memory, | ||
| 100 | + memmap[MICROCHIP_PFSOC_DRAM_HI].base, | ||
| 101 | + mem_high); | ||
| 102 | + memory_region_add_subregion(system_memory, | ||
| 103 | + memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, | ||
| 104 | + mem_high_alias); | ||
| 105 | |||
| 106 | /* Load the firmware */ | ||
| 107 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) | ||
| 109 | MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; | ||
| 110 | mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; | ||
| 111 | mc->default_cpus = mc->min_cpus; | ||
| 112 | - mc->default_ram_size = 1 * GiB; | ||
| 113 | + | ||
| 114 | + /* | ||
| 115 | + * Map 513 MiB high memory, the mimimum required high memory size, because | ||
| 116 | + * HSS will do memory test against the high memory address range regardless | ||
| 117 | + * of physical memory installed. | ||
| 118 | + * | ||
| 119 | + * See memory_tests() in mss_ddr.c in the HSS source code. | ||
| 120 | + */ | ||
| 121 | + mc->default_ram_size = 1537 * MiB; | ||
| 60 | } | 122 | } |
| 61 | 123 | ||
| 62 | static const TypeInfo sifive_u_otp_info = { | 124 | static const TypeInfo microchip_icicle_kit_machine_typeinfo = { |
| 63 | -- | 125 | -- |
| 64 | 2.31.1 | 126 | 2.28.0 |
| 65 | 127 | ||
| 66 | 128 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 1 | 2 | ||
| 3 | The latest SD card image [1] released by Microchip ships a Linux | ||
| 4 | kernel with built-in PolarFire SoC I2C driver support. The device | ||
| 5 | tree file includes the description for the I2C1 node hence kernel | ||
| 6 | tries to probe the I2C1 device during boot. | ||
| 7 | |||
| 8 | It is enough to create an unimplemented device for I2C1 to allow | ||
| 9 | the kernel to continue booting to the shell. | ||
| 10 | |||
| 11 | [1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | ||
| 12 | |||
| 13 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com | ||
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | --- | ||
| 18 | include/hw/riscv/microchip_pfsoc.h | 1 + | ||
| 19 | hw/riscv/microchip_pfsoc.c | 6 ++++++ | ||
| 20 | 2 files changed, 7 insertions(+) | ||
| 21 | |||
| 22 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/include/hw/riscv/microchip_pfsoc.h | ||
| 25 | +++ b/include/hw/riscv/microchip_pfsoc.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 27 | MICROCHIP_PFSOC_MMUART2, | ||
| 28 | MICROCHIP_PFSOC_MMUART3, | ||
| 29 | MICROCHIP_PFSOC_MMUART4, | ||
| 30 | + MICROCHIP_PFSOC_I2C1, | ||
| 31 | MICROCHIP_PFSOC_GEM0, | ||
| 32 | MICROCHIP_PFSOC_GEM1, | ||
| 33 | MICROCHIP_PFSOC_GPIO0, | ||
| 34 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/hw/riscv/microchip_pfsoc.c | ||
| 37 | +++ b/hw/riscv/microchip_pfsoc.c | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
| 39 | [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, | ||
| 40 | [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, | ||
| 41 | [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, | ||
| 42 | + [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, | ||
| 43 | [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, | ||
| 44 | [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, | ||
| 45 | [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 47 | qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), | ||
| 48 | serial_hd(4)); | ||
| 49 | |||
| 50 | + /* I2C1 */ | ||
| 51 | + create_unimplemented_device("microchip.pfsoc.i2c1", | ||
| 52 | + memmap[MICROCHIP_PFSOC_I2C1].base, | ||
| 53 | + memmap[MICROCHIP_PFSOC_I2C1].size); | ||
| 54 | + | ||
| 55 | /* GEMs */ | ||
| 56 | |||
| 57 | nd = &nd_table[0]; | ||
| 58 | -- | ||
| 59 | 2.28.0 | ||
| 60 | |||
| 61 | diff view generated by jsdifflib |
| 1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Configuring a drive with "if=none" is meant for creation of a backend | 3 | Fix code style. Space required before the open parenthesis '('. |
| 4 | only, it should not get automatically assigned to a device frontend. | ||
| 5 | Use "if=pflash" for the One-Time-Programmable device instead (like | ||
| 6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | ||
| 7 | 4 | ||
| 8 | Since the old way of configuring the device has already been published | 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
| 9 | with the previous QEMU versions, we cannot remove this immediately, but | 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
| 10 | have to deprecate it and support it for at least two more releases. | 7 | Reported-by: Euler Robot <euler.robot@huawei.com> |
| 11 | 8 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | |
| 12 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
| 13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 16 | Message-id: 20211119102549.217755-1-thuth@redhat.com | 10 | Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com |
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 18 | --- | 12 | --- |
| 19 | docs/about/deprecated.rst | 6 ++++++ | 13 | target/riscv/csr.c | 2 +- |
| 20 | hw/misc/sifive_u_otp.c | 9 ++++++++- | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 21 | 2 files changed, 14 insertions(+), 1 deletion(-) | ||
| 22 | 15 | ||
| 23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst | 16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 24 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/docs/about/deprecated.rst | 18 | --- a/target/riscv/csr.c |
| 26 | +++ b/docs/about/deprecated.rst | 19 | +++ b/target/riscv/csr.c |
| 27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. | 20 | @@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) |
| 28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` | 21 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
| 29 | form is preferred. | 22 | return -RISCV_EXCP_ILLEGAL_INST; |
| 30 | 23 | } else { | |
| 31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) | 24 | - if((val ^ env->satp) & SATP_ASID) { |
| 32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | 25 | + if ((val ^ env->satp) & SATP_ASID) { |
| 33 | + | 26 | tlb_flush(env_cpu(env)); |
| 34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u | 27 | } |
| 35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. | 28 | env->satp = val; |
| 36 | + | ||
| 37 | |||
| 38 | QEMU Machine Protocol (QMP) commands | ||
| 39 | ------------------------------------ | ||
| 40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/hw/misc/sifive_u_otp.c | ||
| 43 | +++ b/hw/misc/sifive_u_otp.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | ||
| 45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); | ||
| 46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); | ||
| 47 | |||
| 48 | - dinfo = drive_get_next(IF_NONE); | ||
| 49 | + dinfo = drive_get_next(IF_PFLASH); | ||
| 50 | + if (!dinfo) { | ||
| 51 | + dinfo = drive_get_next(IF_NONE); | ||
| 52 | + if (dinfo) { | ||
| 53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " | ||
| 54 | + "use \"-drive if=pflash\" instead."); | ||
| 55 | + } | ||
| 56 | + } | ||
| 57 | if (dinfo) { | ||
| 58 | int ret; | ||
| 59 | uint64_t perm; | ||
| 60 | -- | 29 | -- |
| 61 | 2.31.1 | 30 | 2.28.0 |
| 62 | 31 | ||
| 63 | 32 | diff view generated by jsdifflib |