Series comparison

-[PULL 0/4] target-arm queue
+[PULL 00/21] target-arm queue
-Hi; some minor changes for 6.2, which I think can be classified
+The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
 as bug fixes and are OK for this point in the release cycle.
 (Wouldn't be the end of the world if they slipped to 7.0.)
--- PMM
+  Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
 The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d:
   Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
-for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5:
+for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
-  hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000)
+  hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Support multiple redistributor regions for TCG GICv3
+ * allwinner-h3: Fix I2C controller model for Sun6i SoCs
- * Send RTC_CHANGE QMP event from pl031
+ * allwinner-h3: Add missing i2c controllers
  * Expose M-profile system registers to gdbstub
  * Expose pauth information to gdbstub
  * Support direct boot for Linux/arm64 EFI zboot images
  * Fix incorrect stage 2 MMU setup validation
 ----------------------------------------------------------------
-Eric Auger (1):
+Ard Biesheuvel (1):
-      hw/rtc/pl031: Send RTC_CHANGE QMP event
+      hw: arm: Support direct boot for Linux/arm64 EFI zboot images
-Peter Maydell (3):
+David Reiss (2):
-      hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
+      target/arm: Export arm_v7m_mrs_control
-      hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
+      target/arm: Export arm_v7m_get_sp_ptr
       hw/intc/arm_gicv3: Support multiple redistributor regions
- include/hw/intc/arm_gicv3_common.h | 14 ++++++++--
+Richard Henderson (16):
- hw/intc/arm_gicv3.c                | 12 +-------
+      target/arm: Normalize aarch64 gdbstub get/set function names
- hw/intc/arm_gicv3_common.c         | 56 ++++++++++++++++++++++++--------------
+      target/arm: Unexport arm_gen_dynamic_sysreg_xml
- hw/intc/arm_gicv3_kvm.c            | 10 ++-----
+      target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
- hw/intc/arm_gicv3_redist.c         | 40 +++++++++++++++------------
+      target/arm: Split out output_vector_union_type
- hw/rtc/pl031.c                     | 10 ++++++-
+      target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
- hw/rtc/meson.build                 |  2 +-
+      target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
-files changed, 83 insertions(+), 61 deletions(-)
+      target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
       target/arm: Add name argument to output_vector_union_type
       target/arm: Simplify iteration over bit widths
       target/arm: Create pauth_ptr_mask
       target/arm: Implement gdbstub pauth extension
       target/arm: Implement gdbstub m-profile systemreg and secext
       target/arm: Handle m-profile in arm_is_secure
       target/arm: Stub arm_hcr_el2_eff for m-profile
       target/arm: Diagnose incorrect usage of arm_is_secure subroutines
       target/arm: Rewrite check_s2_mmu_setup
+qianfan Zhao (2):
+      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
+      hw: arm: allwinner-h3: Fix and complete H3 i2c devices
+ configs/targets/aarch64-linux-user.mak    |   2 +-
+ configs/targets/aarch64-softmmu.mak       |   2 +-
+ configs/targets/aarch64_be-linux-user.mak |   2 +-
+ include/hw/arm/allwinner-h3.h             |   6 +
+ include/hw/i2c/allwinner-i2c.h            |   6 +
+ include/hw/loader.h                       |  19 ++
+ target/arm/cpu.h                          |  17 +-
+ target/arm/internals.h                    |  34 +++-
+ hw/arm/allwinner-h3.c                     |  29 +++-
+ hw/arm/boot.c                             |   6 +
+ hw/core/loader.c                          |  91 ++++++++++
+ hw/i2c/allwinner-i2c.c                    |  26 ++-
+ target/arm/gdbstub.c                      | 278 ++++++++++++++++++------------
+ target/arm/gdbstub64.c                    | 175 ++++++++++++++++++-
+ target/arm/helper.c                       |   3 +
+ target/arm/ptw.c                          | 173 +++++++++++--------
+ target/arm/tcg/m_helper.c                 |  90 +++++-----
+ target/arm/tcg/pauth_helper.c             |  26 ++-
+ gdb-xml/aarch64-pauth.xml                 |  15 ++
+files changed, 742 insertions(+), 258 deletions(-)
+ create mode 100644 gdb-xml/aarch64-pauth.xml

-[PULL 3/4] hw/intc/arm_gicv3: Support multiple redistributor regions
+[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
-Our GICv3 QOM interface includes an array property
+From: Richard Henderson <richard.henderson@linaro.org>
 redist-region-count which allows board models to specify that the
 registributor registers are not in a single contiguous range, but
 split into multiple pieces.  We implemented this for KVM, but
 currently the TCG GICv3 model insists that there is only one region.
 You can see the limit being hit with a setup like:
   qemu-system-aarch64 -machine virt,gic-version=3 -smp 124
-Add support for split regions to the TCG GICv3.  To do this we switch
+Make the form of the function names between fp and sve the same:
-from allocating a simple array of MemoryRegions to an array of
+  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
-GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
+  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
 the opaque pointer in the MemoryRegion read/write callbacks.  Each
 GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
 the read/write callback to get hold of the GICv3State, and an index
 which allows us to calculate which CPU's redistributor is being
 accessed.
-Note that arm_gicv3_kvm always passes in NULL as the ops argument
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
-to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-callbacks we need to update to handle this new scheme are the
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-gicv3_redist_read/write functions used by the emulated GICv3.
+Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/internals.h | 8 ++++----
  target/arm/gdbstub.c   | 9 +++++----
  target/arm/gdbstub64.c | 8 ++++----
 files changed, 13 insertions(+), 12 deletions(-)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
  include/hw/intc/arm_gicv3_common.h | 12 ++++++++-
  hw/intc/arm_gicv3.c                |  6 -----
  hw/intc/arm_gicv3_common.c         | 15 ++++++++---
  hw/intc/arm_gicv3_kvm.c            |  4 +--
  hw/intc/arm_gicv3_redist.c         | 40 ++++++++++++++++--------------
 files changed, 46 insertions(+), 31 deletions(-)
 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/arm_gicv3_common.h
+--- a/target/arm/internals.h
-+++ b/include/hw/intc/arm_gicv3_common.h
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
-     bool seenbetter;
+ }
- };
+ #ifdef TARGET_AARCH64
-+/*
+-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-+ * The redistributor pages might be split into more than one region
+-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-+ * on some machine types if there are many CPUs.
+-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-+ */
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
-+typedef struct GICv3RedistRegion {
++int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
-+    GICv3State *gic;
++int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
-+    MemoryRegion iomem;
++int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
-+    uint32_t cpuidx; /* index of first CPU this region covers */
++int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
-+} GICv3RedistRegion;
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
-+
+ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
- struct GICv3State {
+ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
-     /*< private >*/
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
      SysBusDevice parent_obj;
      /*< public >*/
      MemoryRegion iomem_dist; /* Distributor */
 -    MemoryRegion *iomem_redist; /* Redistributor Regions */
 +    GICv3RedistRegion *redist_regions; /* Redistributor Regions */
      uint32_t *redist_region_count; /* redistributor count within each region */
      uint32_t nb_redist_regions; /* number of redist regions */
 diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3.c
+--- a/target/arm/gdbstub.c
-+++ b/hw/intc/arm_gicv3.c
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-         return;
+          */
-     }
+ #ifdef TARGET_AARCH64
+         if (isar_feature_aa64_sve(&cpu->isar)) {
--    if (s->nb_redist_regions != 1) {
+-            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
--        error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
+-                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
--                   s->nb_redist_regions);
++            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
--        return;
++            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
--    }
++                                     aarch64_gdb_set_sve_reg, nreg,
--
+                                      "sve-registers.xml", 0);
-     gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
+         } else {
+-            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
-     gicv3_init_cpuif(s);
+-                                     aarch64_fpu_gdb_set_reg,
-diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
++            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
 +                                     aarch64_gdb_set_fpu_reg,
 , "aarch64-fpu.xml", 0);
          }
  #endif
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_common.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/intc/arm_gicv3_common.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
+@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
      return 0;
  }
 -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
 +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
  {
-     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+     switch (reg) {
-     int i;
+     case 0 ... 31:
-+    int cpuidx;
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
      /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
       * GPIO array layout is thus:
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
                            "gicv3_dist", 0x10000);
      sysbus_init_mmio(sbd, &s->iomem_dist);
 -    s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
 +    s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
 +    cpuidx = 0;
      for (i = 0; i < s->nb_redist_regions; i++) {
          char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
 +        GICv3RedistRegion *region = &s->redist_regions[i];
 -        memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
 -                              ops ? &ops[1] : NULL, s, name,
 +        region->gic = s;
 +        region->cpuidx = cpuidx;
 +        cpuidx += s->redist_region_count[i];
 +
 +        memory_region_init_io(&region->iomem, OBJECT(s),
 +                              ops ? &ops[1] : NULL, region, name,
                                s->redist_region_count[i] * GICV3_REDIST_SIZE);
 -        sysbus_init_mmio(sbd, &s->iomem_redist[i]);
 +        sysbus_init_mmio(sbd, &region->iomem);
          g_free(name);
      }
  }
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
-index XXXXXXX..XXXXXXX 100644
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
---- a/hw/intc/arm_gicv3_kvm.c
++int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
 +++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
                              KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
      if (!multiple_redist_region_allowed) {
 -        kvm_arm_register_device(&s->iomem_redist[0], -1,
 +        kvm_arm_register_device(&s->redist_regions[0].iomem, -1,
                                  KVM_DEV_ARM_VGIC_GRP_ADDR,
                                  KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
      } else {
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
              uint64_t addr_ormask =
                          i | ((uint64_t)s->redist_region_count[i] << 52);
 -            kvm_arm_register_device(&s->iomem_redist[i], -1,
 +            kvm_arm_register_device(&s->redist_regions[i].iomem, -1,
                                      KVM_DEV_ARM_VGIC_GRP_ADDR,
                                      KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
                                      s->dev_fd, addr_ormask);
 diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_redist.c
 +++ b/hw/intc/arm_gicv3_redist.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
  MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
                                unsigned size, MemTxAttrs attrs)
  {
--    GICv3State *s = opaque;
+     switch (reg) {
-+    GICv3RedistRegion *region = opaque;
+     case 0 ... 31:
-+    GICv3State *s = region->gic;
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
-     GICv3CPUState *cs;
+     }
-     MemTxResult r;
+ }
-     int cpuidx;
+-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
-     assert((offset & (size - 1)) == 0);
++int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
 -    /* This region covers all the redistributor pages; there are
 -     * (for GICv3) two 64K pages per CPU. At the moment they are
 -     * all contiguous (ie in this one region), though we might later
 -     * want to allow splitting of redistributor pages into several
 -     * blocks so we can support more CPUs.
 +    /*
 +     * There are (for GICv3) two 64K redistributor pages per CPU.
 +     * In some cases the redistributor pages for all CPUs are not
 +     * contiguous (eg on the virt board they are split into two
 +     * parts if there are too many CPUs to all fit in the same place
 +     * in the memory map); if so then the GIC has multiple MemoryRegions
 +     * for the redistributors.
       */
 -    cpuidx = offset / 0x20000;
 -    offset %= 0x20000;
 -    assert(cpuidx < s->num_cpu);
 +    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
 +    offset %= GICV3_REDIST_SIZE;
      cs = &s->cpu[cpuidx];
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
  MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
                                 unsigned size, MemTxAttrs attrs)
  {
--    GICv3State *s = opaque;
+     ARMCPU *cpu = env_archcpu(env);
-+    GICv3RedistRegion *region = opaque;
-+    GICv3State *s = region->gic;
+@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
-     GICv3CPUState *cs;
+     return 0;
-     MemTxResult r;
+ }
-     int cpuidx;
+-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
-     assert((offset & (size - 1)) == 0);
++int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+ {
--    /* This region covers all the redistributor pages; there are
+     ARMCPU *cpu = env_archcpu(env);
 -     * (for GICv3) two 64K pages per CPU. At the moment they are
 -     * all contiguous (ie in this one region), though we might later
 -     * want to allow splitting of redistributor pages into several
 -     * blocks so we can support more CPUs.
 +    /*
 +     * There are (for GICv3) two 64K redistributor pages per CPU.
 +     * In some cases the redistributor pages for all CPUs are not
 +     * contiguous (eg on the virt board they are split into two
 +     * parts if there are too many CPUs to all fit in the same place
 +     * in the memory map); if so then the GIC has multiple MemoryRegions
 +     * for the redistributors.
       */
 -    cpuidx = offset / 0x20000;
 -    offset %= 0x20000;
 -    assert(cpuidx < s->num_cpu);
 +    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
 +    offset %= GICV3_REDIST_SIZE;
      cs = &s->cpu[cpuidx];
 --
-.25.1
+.34.1

-New patch
+[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+This function is not used outside gdbstub.c.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h     | 1 -
+ target/arm/gdbstub.c | 2 +-
+files changed, 1 insertion(+), 2 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+  * Helpers to dynamically generates XML descriptions of the sysregs
+  * and SVE registers. Returns the number of registers in each set.
+  */
+-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
+ int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
+ /* Returns the dynamically generated XML for the gdb stub.
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub.c
++++ b/target/arm/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
+     }
+ }
+-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
++static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+     GString *s = g_string_new(NULL);
+--
+.34.1

-New patch
+[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
+From: Richard Henderson <richard.henderson@linaro.org>
 The function is only used for aarch64, so move it to the
 file that has the other aarch64 gdbstub stuff.  Move the
 declaration to internals.h.
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h       |   6 ---
  target/arm/internals.h |   1 +
  target/arm/gdbstub.c   | 120 -----------------------------------------
  target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 files changed, 119 insertions(+), 126 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
  int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 -/*
 - * Helpers to dynamically generates XML descriptions of the sysregs
 - * and SVE registers. Returns the number of registers in each set.
 - */
 -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 -
  /* Returns the dynamically generated XML for the gdb stub.
   * Returns a pointer to the XML contents for the specified XML file or NULL
   * if the XML name doesn't match the predefined one.
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
  }
  #ifdef TARGET_AARCH64
 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
  int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
  int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
  int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 -struct TypeSize {
 -    const char *gdb_type;
 -    int  size;
 -    const char sz, suffix;
 -};
 -
 -static const struct TypeSize vec_lanes[] = {
 -    /* quads */
 -    { "uint128", 128, 'q', 'u' },
 -    { "int128", 128, 'q', 's' },
 -    /* 64 bit */
 -    { "ieee_double", 64, 'd', 'f' },
 -    { "uint64", 64, 'd', 'u' },
 -    { "int64", 64, 'd', 's' },
 -    /* 32 bit */
 -    { "ieee_single", 32, 's', 'f' },
 -    { "uint32", 32, 's', 'u' },
 -    { "int32", 32, 's', 's' },
 -    /* 16 bit */
 -    { "ieee_half", 16, 'h', 'f' },
 -    { "uint16", 16, 'h', 'u' },
 -    { "int16", 16, 'h', 's' },
 -    /* bytes */
 -    { "uint8", 8, 'b', 'u' },
 -    { "int8", 8, 'b', 's' },
 -};
 -
 -
 -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 -{
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    GString *s = g_string_new(NULL);
 -    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 -    g_autoptr(GString) ts = g_string_new("");
 -    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 -    g_string_printf(s, "<?xml version=\"1.0\"?>");
 -    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 -    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 -
 -    /* First define types and totals in a whole VL */
 -    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 -        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 -        g_string_append_printf(s,
 -                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 -                               ts->str, vec_lanes[i].gdb_type, count);
 -    }
 -    /*
 -     * Now define a union for each size group containing unsigned and
 -     * signed and potentially float versions of each size from 128 to
 -     * 8 bits.
 -     */
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 -        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 -            if (vec_lanes[j].size == bits) {
 -                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 -                                       vec_lanes[j].suffix,
 -                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 -            }
 -        }
 -        g_string_append(s, "</union>");
 -    }
 -    /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 -    }
 -    g_string_append(s, "</union>");
 -
 -    /* Finally the sve prefix type */
 -    g_string_append_printf(s,
 -                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 -                           reg_width / 8);
 -
 -    /* Then define each register in parts for each vq */
 -    for (i = 0; i < 32; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"z%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svev\"/>",
 -                               i, reg_width, base_reg++);
 -        info->num++;
 -    }
 -    /* fpscr & status registers */
 -    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    info->num += 2;
 -
 -    for (i = 0; i < 16; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"p%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svep\"/>",
 -                               i, cpu->sve_max_vq * 16, base_reg++);
 -        info->num++;
 -    }
 -    g_string_append_printf(s,
 -                           "<reg name=\"ffr\" bitsize=\"%d\""
 -                           " regnum=\"%d\" group=\"vector\""
 -                           " type=\"svep\"/>",
 -                           cpu->sve_max_vq * 16, base_reg++);
 -    g_string_append_printf(s,
 -                           "<reg name=\"vg\" bitsize=\"64\""
 -                           " regnum=\"%d\" type=\"int\"/>",
 -                           base_reg++);
 -    info->num += 2;
 -    g_string_append_printf(s, "</feature>");
 -    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
 -
 -    return cpu->dyn_svereg_xml.num;
 -}
 -
 -
  const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
  {
      ARMCPU *cpu = ARM_CPU(cs);
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
      return 0;
  }
 +
 +struct TypeSize {
 +    const char *gdb_type;
 +    short size;
 +    char sz, suffix;
 +};
 +
 +static const struct TypeSize vec_lanes[] = {
 +    /* quads */
 +    { "uint128", 128, 'q', 'u' },
 +    { "int128", 128, 'q', 's' },
 +    /* 64 bit */
 +    { "ieee_double", 64, 'd', 'f' },
 +    { "uint64", 64, 'd', 'u' },
 +    { "int64", 64, 'd', 's' },
 +    /* 32 bit */
 +    { "ieee_single", 32, 's', 'f' },
 +    { "uint32", 32, 's', 'u' },
 +    { "int32", 32, 's', 's' },
 +    /* 16 bit */
 +    { "ieee_half", 16, 'h', 'f' },
 +    { "uint16", 16, 'h', 'u' },
 +    { "int16", 16, 'h', 's' },
 +    /* bytes */
 +    { "uint8", 8, 'b', 'u' },
 +    { "int8", 8, 'b', 's' },
 +};
 +
 +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 +    g_autoptr(GString) ts = g_string_new("");
 +    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 +    info->num = 0;
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +
 +    /* First define types and totals in a whole VL */
 +    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 +        int count = reg_width / vec_lanes[i].size;
 +        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 +        g_string_append_printf(s,
 +                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 +                               ts->str, vec_lanes[i].gdb_type, count);
 +    }
 +    /*
 +     * Now define a union for each size group containing unsigned and
 +     * signed and potentially float versions of each size from 128 to
 +     * 8 bits.
 +     */
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 +        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 +            if (vec_lanes[j].size == bits) {
 +                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 +                                       vec_lanes[j].suffix,
 +                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 +            }
 +        }
 +        g_string_append(s, "</union>");
 +    }
 +    /* And now the final union of unions */
 +    g_string_append(s, "<union id=\"svev\">");
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 +                               suf[i], suf[i]);
 +    }
 +    g_string_append(s, "</union>");
 +
 +    /* Finally the sve prefix type */
 +    g_string_append_printf(s,
 +                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 +                           reg_width / 8);
 +
 +    /* Then define each register in parts for each vq */
 +    for (i = 0; i < 32; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"z%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svev\"/>",
 +                               i, reg_width, base_reg++);
 +        info->num++;
 +    }
 +    /* fpscr & status registers */
 +    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    info->num += 2;
 +
 +    for (i = 0; i < 16; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"p%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svep\"/>",
 +                               i, cpu->sve_max_vq * 16, base_reg++);
 +        info->num++;
 +    }
 +    g_string_append_printf(s,
 +                           "<reg name=\"ffr\" bitsize=\"%d\""
 +                           " regnum=\"%d\" group=\"vector\""
 +                           " type=\"svep\"/>",
 +                           cpu->sve_max_vq * 16, base_reg++);
 +    g_string_append_printf(s,
 +                           "<reg name=\"vg\" bitsize=\"64\""
 +                           " regnum=\"%d\" type=\"int\"/>",
 +                           base_reg++);
 +    info->num += 2;
 +    g_string_append_printf(s, "</feature>");
 +    info->desc = g_string_free(s, false);
 +
 +    return info->num;
 +}
 --
 .34.1

-New patch
+[PULL 04/21] target/arm: Split out output_vector_union_type
+From: Richard Henderson <richard.henderson@linaro.org>
+Create a subroutine for creating the union of unions
+of the various type sizes that a vector may contain.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
+file changed, 45 insertions(+), 38 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+     return 0;
+ }
+-struct TypeSize {
+-    const char *gdb_type;
+-    short size;
+-    char sz, suffix;
+-};
+-
+-static const struct TypeSize vec_lanes[] = {
+-    /* quads */
+-    { "uint128", 128, 'q', 'u' },
+-    { "int128", 128, 'q', 's' },
+-    /* 64 bit */
+-    { "ieee_double", 64, 'd', 'f' },
+-    { "uint64", 64, 'd', 'u' },
+-    { "int64", 64, 'd', 's' },
+-    /* 32 bit */
+-    { "ieee_single", 32, 's', 'f' },
+-    { "uint32", 32, 's', 'u' },
+-    { "int32", 32, 's', 's' },
+-    /* 16 bit */
+-    { "ieee_half", 16, 'h', 'f' },
+-    { "uint16", 16, 'h', 'u' },
+-    { "int16", 16, 'h', 's' },
+-    /* bytes */
+-    { "uint8", 8, 'b', 'u' },
+-    { "int8", 8, 'b', 's' },
+-};
+-
+-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++static void output_vector_union_type(GString *s, int reg_width)
+ {
+-    ARMCPU *cpu = ARM_CPU(cs);
+-    GString *s = g_string_new(NULL);
+-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
++    struct TypeSize {
++        const char *gdb_type;
++        short size;
++        char sz, suffix;
++    };
++
++    static const struct TypeSize vec_lanes[] = {
++        /* quads */
++        { "uint128", 128, 'q', 'u' },
++        { "int128", 128, 'q', 's' },
++        /* 64 bit */
++        { "ieee_double", 64, 'd', 'f' },
++        { "uint64", 64, 'd', 'u' },
++        { "int64", 64, 'd', 's' },
++        /* 32 bit */
++        { "ieee_single", 32, 's', 'f' },
++        { "uint32", 32, 's', 'u' },
++        { "int32", 32, 's', 's' },
++        /* 16 bit */
++        { "ieee_half", 16, 'h', 'f' },
++        { "uint16", 16, 'h', 'u' },
++        { "int16", 16, 'h', 's' },
++        /* bytes */
++        { "uint8", 8, 'b', 'u' },
++        { "int8", 8, 'b', 's' },
++    };
++
++    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
++
+     g_autoptr(GString) ts = g_string_new("");
+-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
+-    info->num = 0;
+-    g_string_printf(s, "<?xml version=\"1.0\"?>");
+-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
++    int i, j, bits;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+      * 8 bits.
+      */
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+         g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+             if (vec_lanes[j].size == bits) {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+     /* And now the final union of unions */
+     g_string_append(s, "<union id=\"svev\">");
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+         g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
+                                suf[i], suf[i]);
+     }
+     g_string_append(s, "</union>");
++}
++
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++{
++    ARMCPU *cpu = ARM_CPU(cs);
++    GString *s = g_string_new(NULL);
++    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
++    int i, reg_width = (cpu->sve_max_vq * 128);
++    info->num = 0;
++    g_string_printf(s, "<?xml version=\"1.0\"?>");
++    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
++    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
++
++    output_vector_union_type(s, reg_width);
+     /* Finally the sve prefix type */
+     g_string_append_printf(s,
+--
+.34.1

-New patch
+[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+Rather than increment base_reg and num, compute num from the change
+to base_reg at the end.  Clean up some nearby comments.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
+file changed, 16 insertions(+), 11 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
+     g_string_append(s, "</union>");
+ }
+-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+     GString *s = g_string_new(NULL);
+     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+-    int i, reg_width = (cpu->sve_max_vq * 128);
+-    info->num = 0;
++    int reg_width = cpu->sve_max_vq * 128;
++    int base_reg = orig_base_reg;
++    int i;
++
+     g_string_printf(s, "<?xml version=\"1.0\"?>");
+     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
++    /* Create the vector union type. */
+     output_vector_union_type(s, reg_width);
+-    /* Finally the sve prefix type */
++    /* Create the predicate vector type. */
+     g_string_append_printf(s,
+                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+                            reg_width / 8);
+-    /* Then define each register in parts for each vq */
++    /* Define the vector registers. */
+     for (i = 0; i < 32; i++) {
+         g_string_append_printf(s,
+                                "<reg name=\"z%d\" bitsize=\"%d\""
+                                " regnum=\"%d\" type=\"svev\"/>",
+                                i, reg_width, base_reg++);
+-        info->num++;
+     }
++
+     /* fpscr & status registers */
+     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
+                            " regnum=\"%d\" group=\"float\""
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
+                            " regnum=\"%d\" group=\"float\""
+                            " type=\"int\"/>", base_reg++);
+-    info->num += 2;
++    /* Define the predicate registers. */
+     for (i = 0; i < 16; i++) {
+         g_string_append_printf(s,
+                                "<reg name=\"p%d\" bitsize=\"%d\""
+                                " regnum=\"%d\" type=\"svep\"/>",
+                                i, cpu->sve_max_vq * 16, base_reg++);
+-        info->num++;
+     }
+     g_string_append_printf(s,
+                            "<reg name=\"ffr\" bitsize=\"%d\""
+                            " regnum=\"%d\" group=\"vector\""
+                            " type=\"svep\"/>",
+                            cpu->sve_max_vq * 16, base_reg++);
++
++    /* Define the vector length pseudo-register. */
+     g_string_append_printf(s,
+                            "<reg name=\"vg\" bitsize=\"64\""
+                            " regnum=\"%d\" type=\"int\"/>",
+                            base_reg++);
+-    info->num += 2;
+-    g_string_append_printf(s, "</feature>");
+-    info->desc = g_string_free(s, false);
++    g_string_append_printf(s, "</feature>");
++
++    info->desc = g_string_free(s, false);
++    info->num = base_reg - orig_base_reg;
+     return info->num;
+ }
+--
+.34.1

-New patch
+[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 5 +++--
+file changed, 3 insertions(+), 2 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+     GString *s = g_string_new(NULL);
+     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+     int reg_width = cpu->sve_max_vq * 128;
++    int pred_width = cpu->sve_max_vq * 16;
+     int base_reg = orig_base_reg;
+     int i;
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+         g_string_append_printf(s,
+                                "<reg name=\"p%d\" bitsize=\"%d\""
+                                " regnum=\"%d\" type=\"svep\"/>",
+-                               i, cpu->sve_max_vq * 16, base_reg++);
++                               i, pred_width, base_reg++);
+     }
+     g_string_append_printf(s,
+                            "<reg name=\"ffr\" bitsize=\"%d\""
+                            " regnum=\"%d\" group=\"vector\""
+                            " type=\"svep\"/>",
+-                           cpu->sve_max_vq * 16, base_reg++);
++                           pred_width, base_reg++);
+     /* Define the vector length pseudo-register. */
+     g_string_append_printf(s,
+--
+.34.1

-New patch
+[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+Define svep based on the size of the predicates,
+not the primary vector registers.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+     /* Create the predicate vector type. */
+     g_string_append_printf(s,
+                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+-                           reg_width / 8);
++                           pred_width / 8);
+     /* Define the vector registers. */
+     for (i = 0; i < 32; i++) {
+--
+.34.1

-[PULL 2/4] hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
+[PULL 08/21] target/arm: Add name argument to output_vector_union_type
-The 'Last' bit in the GICR_TYPER GICv3 redistributor register is
+From: Richard Henderson <richard.henderson@linaro.org>
 supposed to be set to 1 if this is the last redistributor in a series
 of contiguous redistributor pages.  Currently we set Last only for
 the redistributor for CPU (num_cpu - 1).  This only works if there is
 a single redistributor region; if there are multiple redistributor
 regions then we need to set the Last bit for the last redistributor
 in each region.
-This doesn't cause any problems currently because only the KVM GICv3
+This will make the function usable between SVE and SME.
 supports multiple redistributor regions, and it ignores the value in
 GICv3State::gicr_typer.  But we need to fix this before we can enable
 support for multiple regions in the emulated GICv3.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/intc/arm_gicv3_common.c | 17 ++++++++++++-----
+ target/arm/gdbstub64.c | 28 ++++++++++++++--------------
-file changed, 12 insertions(+), 5 deletions(-)
+file changed, 14 insertions(+), 14 deletions(-)
-diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_common.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/intc/arm_gicv3_common.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
- static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
+     return 0;
  }
 -static void output_vector_union_type(GString *s, int reg_width)
 +static void output_vector_union_type(GString *s, int reg_width,
 +                                     const char *name)
  {
-     GICv3State *s = ARM_GICV3_COMMON(dev);
+     struct TypeSize {
--    int i, rdist_capacity;
+         const char *gdb_type;
-+    int i, rdist_capacity, cpuidx;
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
+     };
-     /* revision property is actually reserved and currently used only in order
-      * to keep the interface compatible with GICv2 code, avoiding extra
+     static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
+-
-     for (i = 0; i < s->num_cpu; i++) {
+-    g_autoptr(GString) ts = g_string_new("");
-         CPUState *cpu = qemu_get_cpu(i);
+     int i, j, bits;
-         uint64_t cpu_affid;
--        int last;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-         s->cpu[i].cpu = cpu;
+-        int count = reg_width / vec_lanes[i].size;
-         s->cpu[i].gic = s;
+-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
-@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
+         g_string_append_printf(s,
-          *  PLPIS == 0 (physical LPIs not supported)
+-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-          */
+-                               ts->str, vec_lanes[i].gdb_type, count);
-         cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
++                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
--        last = (i == s->num_cpu - 1);
++                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
++                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
          /* The CPU mp-affinity property is in MPIDR register format; squash
           * the affinity bytes into 32 bits as the GICR_TYPER has them.
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
                       (cpu_affid & 0xFFFFFF);
          s->cpu[i].gicr_typer = (cpu_affid << 32) |
              (1 << 24) |
 -            (i << 8) |
 -            (last << 4);
 +            (i << 8);
          if (s->lpi_enable) {
              s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
          }
      }
 +
-+    /*
+     /*
-+     * Now go through and set GICR_TYPER.Last for the final
+      * Now define a union for each size group containing unsigned and
-+     * redistributor in each region.
+      * signed and potentially float versions of each size from 128 to
-+     */
+      * 8 bits.
-+    cpuidx = 0;
+      */
-+    for (i = 0; i < s->nb_redist_regions; i++) {
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-+        cpuidx += s->redist_region_count[i];
+-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
-+        s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST;
++        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
-+    }
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
              if (vec_lanes[j].size == bits) {
 -                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 -                                       vec_lanes[j].suffix,
 +                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
 +                                       vec_lanes[j].suffix, name,
                                         vec_lanes[j].sz, vec_lanes[j].suffix);
              }
          }
          g_string_append(s, "</union>");
      }
 +
      /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 +    g_string_append_printf(s, "<union id=\"%s\">", name);
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
 +                               suf[i], name, suf[i]);
      }
      g_string_append(s, "</union>");
  }
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
- static void arm_gicv3_finalize(Object *obj)
+     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
      /* Create the vector union type. */
 -    output_vector_union_type(s, reg_width);
 +    output_vector_union_type(s, reg_width, "svev");
      /* Create the predicate vector type. */
      g_string_append_printf(s,
 --
-.25.1
+.34.1

-New patch
+[PULL 09/21] target/arm: Simplify iteration over bit widths
+From: Richard Henderson <richard.henderson@linaro.org>
+Order suf[] by the log8 of the width.
+Use ARRAY_SIZE instead of hard-coding 128.
+This changes the order of the union definitions,
+but retains the order of the union-of-union members.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 10 ++++++----
+file changed, 6 insertions(+), 4 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+         { "int8", 8, 'b', 's' },
+     };
+-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+-    int i, j, bits;
++    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
++    int i, j;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+      * signed and potentially float versions of each size from 128 to
+      * 8 bits.
+      */
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = 0; i < ARRAY_SIZE(suf); i++) {
++        int bits = 8 << i;
++
+         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+             if (vec_lanes[j].size == bits) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+     /* And now the final union of unions */
+     g_string_append_printf(s, "<union id=\"%s\">", name);
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
+         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                                suf[i], name, suf[i]);
+     }
+--
+.34.1

-New patch
+[PULL 10/21] target/arm: Create pauth_ptr_mask
+From: Richard Henderson <richard.henderson@linaro.org>
+Keep the logic for pauth within pauth_helper.c, and expose
+a helper function for use with the gdbstub pac extension.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h        | 10 ++++++++++
+ target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
+files changed, 32 insertions(+), 4 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
+ bool arm_singlestep_active(CPUARMState *env);
+ bool arm_generate_debug_exceptions(CPUARMState *env);
++/**
++ * pauth_ptr_mask:
++ * @env: cpu context
++ * @ptr: selects between TTBR0 and TTBR1
++ * @data: selects between TBI and TBID
++ *
++ * Return a mask of the bits of @ptr that contain the authentication code.
++ */
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
++
+ /* Add the cpreg definitions for debug related system registers */
+ void define_debug_regs(ARMCPU *cpu);
+diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/pauth_helper.c
++++ b/target/arm/tcg/pauth_helper.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+     return pac | ext | ptr;
+ }
+-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
+ {
+-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+-    uint64_t extfield = sextract64(ptr, 55, 1);
+     int bot_pac_bit = 64 - param.tsz;
+     int top_pac_bit = 64 - 8 * param.tbi;
+-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
++    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
++}
++
++static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++{
++    uint64_t mask = pauth_ptr_mask_internal(param);
++
++    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
++    if (extract64(ptr, 55, 1)) {
++        return ptr | mask;
++    } else {
++        return ptr & ~mask;
++    }
++}
++
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
++{
++    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
++    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
++
++    return pauth_ptr_mask_internal(param);
+ }
+ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+--
+.34.1

-New patch
+[PULL 11/21] target/arm: Implement gdbstub pauth extension
+From: Richard Henderson <richard.henderson@linaro.org>
+The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
+ptrace register set.
+The original gdb feature consists of two masks, data and code, which are
+used to mask out the authentication code within a pointer.  Following
+discussion with Luis Machado, add two more masks in order to support
+pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ configs/targets/aarch64-linux-user.mak    |  2 +-
+ configs/targets/aarch64-softmmu.mak       |  2 +-
+ configs/targets/aarch64_be-linux-user.mak |  2 +-
+ target/arm/internals.h                    |  2 ++
+ target/arm/gdbstub.c                      |  5 ++++
+ target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
+ gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
+files changed, 59 insertions(+), 3 deletions(-)
+ create mode 100644 gdb-xml/aarch64-pauth.xml
+diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64-linux-user.mak
++++ b/configs/targets/aarch64-linux-user.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
+ TARGET_HAS_BFLT=y
+ CONFIG_SEMIHOSTING=y
+ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64-softmmu.mak
++++ b/configs/targets/aarch64-softmmu.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+ TARGET_SUPPORTS_MTTCG=y
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
+ TARGET_NEED_FDT=y
+diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64_be-linux-user.mak
++++ b/configs/targets/aarch64_be-linux-user.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+ TARGET_BIG_ENDIAN=y
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
+ TARGET_HAS_BFLT=y
+ CONFIG_SEMIHOSTING=y
+ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
+ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
+ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
+ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
++int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
++int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub.c
++++ b/target/arm/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
+                                      aarch64_gdb_set_fpu_reg,
+, "aarch64-fpu.xml", 0);
+         }
++        if (isar_feature_aa64_pauth(&cpu->isar)) {
++            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
++                                     aarch64_gdb_set_pauth_reg,
++                                     4, "aarch64-pauth.xml", 0);
++        }
+ #endif
+     } else {
+         if (arm_feature(env, ARM_FEATURE_NEON)) {
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+     return 0;
+ }
++int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
++{
++    switch (reg) {
++    case 0: /* pauth_dmask */
++    case 1: /* pauth_cmask */
++    case 2: /* pauth_dmask_high */
++    case 3: /* pauth_cmask_high */
++        /*
++         * Note that older versions of this feature only contained
++         * pauth_{d,c}mask, for use with Linux user processes, and
++         * thus exclusively in the low half of the address space.
++         *
++         * To support system mode, and to debug kernels, two new regs
++         * were added to cover the high half of the address space.
++         * For the purpose of pauth_ptr_mask, we can use any well-formed
++         * address within the address space half -- here, 0 and -1.
++         */
++        {
++            bool is_data = !(reg & 1);
++            bool is_high = reg & 2;
++            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
++            return gdb_get_reg64(buf, mask);
++        }
++    default:
++        return 0;
++    }
++}
++
++int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
++{
++    /* All pseudo registers are read-only. */
++    return 0;
++}
++
+ static void output_vector_union_type(GString *s, int reg_width,
+                                      const char *name)
+ {
+diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/gdb-xml/aarch64-pauth.xml
+@@ -XXX,XX +XXX,XX @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.aarch64.pauth">
++  <reg name="pauth_dmask" bitsize="64"/>
++  <reg name="pauth_cmask" bitsize="64"/>
++  <reg name="pauth_dmask_high" bitsize="64"/>
++  <reg name="pauth_cmask_high" bitsize="64"/>
++</feature>
++
+--
+.34.1

-New patch
+[PULL 12/21] target/arm: Export arm_v7m_mrs_control
+From: David Reiss <dreiss@meta.com>
+Allow the function to be used outside of m_helper.c.
+Rename with an "arm_" prefix.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: David Reiss <dreiss@meta.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
+[rth: Split out of a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h    | 3 +++
+ target/arm/tcg/m_helper.c | 6 +++---
+files changed, 6 insertions(+), 3 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+ #endif
++/* Read the CONTROL register as the MRS instruction would. */
++uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
++
+ #ifdef CONFIG_USER_ONLY
+ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ #else
+diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/m_helper.c
++++ b/target/arm/tcg/m_helper.c
+@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
+     return xpsr_read(env) & mask;
+ }
+-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
++uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
+ {
+     uint32_t value = env->v7m.control[secure];
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+     case 0 ... 7: /* xPSR sub-fields */
+         return v7m_mrs_xpsr(env, reg, 0);
+     case 20: /* CONTROL */
+-        return v7m_mrs_control(env, 0);
++        return arm_v7m_mrs_control(env, 0);
+     default:
+         /* Unprivileged reads others as zero.  */
+         return 0;
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+     case 0 ... 7: /* xPSR sub-fields */
+         return v7m_mrs_xpsr(env, reg, el);
+     case 20: /* CONTROL */
+-        return v7m_mrs_control(env, env->v7m.secure);
++        return arm_v7m_mrs_control(env, env->v7m.secure);
+     case 0x94: /* CONTROL_NS */
+         /*
+          * We have to handle this here because unprivileged Secure code
+--
+.34.1

-New patch
+[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
+From: David Reiss <dreiss@meta.com>
+Allow the function to be used outside of m_helper.c.
+Move to be outside of ifndef CONFIG_USER_ONLY block.
+Rename from get_v7m_sp_ptr.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: David Reiss <dreiss@meta.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
+[rth: Split out of a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h    | 10 +++++
+ target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
+files changed, 51 insertions(+), 43 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+ /* Read the CONTROL register as the MRS instruction would. */
+ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
++/*
++ * Return a pointer to the location where we currently store the
++ * stack pointer for the requested security state and thread mode.
++ * This pointer will become invalid if the CPU state is updated
++ * such that the stack pointers are switched around (eg changing
++ * the SPSEL control bit).
++ */
++uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
++                             bool threadmode, bool spsel);
++
+ #ifdef CONFIG_USER_ONLY
+ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ #else
+diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/m_helper.c
++++ b/target/arm/tcg/m_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+     arm_rebuild_hflags(env);
+ }
+-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+-                                bool spsel)
+-{
+-    /*
+-     * Return a pointer to the location where we currently store the
+-     * stack pointer for the requested security state and thread mode.
+-     * This pointer will become invalid if the CPU state is updated
+-     * such that the stack pointers are switched around (eg changing
+-     * the SPSEL control bit).
+-     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
+-     * Unlike that pseudocode, we require the caller to pass us in the
+-     * SPSEL control bit value; this is because we also use this
+-     * function in handling of pushing of the callee-saves registers
+-     * part of the v8M stack frame (pseudocode PushCalleeStack()),
+-     * and in the tailchain codepath the SPSEL bit comes from the exception
+-     * return magic LR value from the previous exception. The pseudocode
+-     * opencodes the stack-selection in PushCalleeStack(), but we prefer
+-     * to make this utility function generic enough to do the job.
+-     */
+-    bool want_psp = threadmode && spsel;
+-
+-    if (secure == env->v7m.secure) {
+-        if (want_psp == v7m_using_psp(env)) {
+-            return &env->regs[13];
+-        } else {
+-            return &env->v7m.other_sp;
+-        }
+-    } else {
+-        if (want_psp) {
+-            return &env->v7m.other_ss_psp;
+-        } else {
+-            return &env->v7m.other_ss_msp;
+-        }
+-    }
+-}
+-
+ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
+                                 uint32_t *pvec)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
+             !mode;
+         mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
+-        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
+-                                    lr & R_V7M_EXCRET_SPSEL_MASK);
++        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
++                                        lr & R_V7M_EXCRET_SPSEL_MASK);
+         want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
+         if (want_psp) {
+             limit = env->v7m.psplim[M_REG_S];
+@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
+          * use 'frame_sp_p' after we do something that makes it invalid.
+          */
+         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
+-        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
+-                                              return_to_secure,
+-                                              !return_to_handler,
+-                                              spsel);
++        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
++                                                  !return_to_handler, spsel);
+         uint32_t frameptr = *frame_sp_p;
+         bool pop_ok = true;
+         ARMMMUIdx mmu_idx;
+@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
+         threadmode = !arm_v7m_is_handler_mode(env);
+         spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
+-        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
++        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
+         frameptr = *frame_sp_p;
+         /*
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+ }
+ #endif /* !CONFIG_USER_ONLY */
++
++uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
++                             bool spsel)
++{
++    /*
++     * Return a pointer to the location where we currently store the
++     * stack pointer for the requested security state and thread mode.
++     * This pointer will become invalid if the CPU state is updated
++     * such that the stack pointers are switched around (eg changing
++     * the SPSEL control bit).
++     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
++     * Unlike that pseudocode, we require the caller to pass us in the
++     * SPSEL control bit value; this is because we also use this
++     * function in handling of pushing of the callee-saves registers
++     * part of the v8M stack frame (pseudocode PushCalleeStack()),
++     * and in the tailchain codepath the SPSEL bit comes from the exception
++     * return magic LR value from the previous exception. The pseudocode
++     * opencodes the stack-selection in PushCalleeStack(), but we prefer
++     * to make this utility function generic enough to do the job.
++     */
++    bool want_psp = threadmode && spsel;
++
++    if (secure == env->v7m.secure) {
++        if (want_psp == v7m_using_psp(env)) {
++            return &env->regs[13];
++        } else {
++            return &env->v7m.other_sp;
++        }
++    } else {
++        if (want_psp) {
++            return &env->v7m.other_ss_psp;
++        } else {
++            return &env->v7m.other_ss_msp;
++        }
++    }
++}
+--
+.34.1

-New patch
+[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
+From: Richard Henderson <richard.henderson@linaro.org>
 The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
 go ahead and implement the other system registers as well.
 Since there is significant overlap between the two, implement
 them with common code.  The only exception is the systemreg
 view of CONTROL, which merges the banked bits as per MRS.
 Signed-off-by: David Reiss <dreiss@meta.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
 [rth: Substatial rewrite using enumerator and shared code.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h     |   2 +
  target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 files changed, 180 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      DynamicGDBXMLInfo dyn_sysreg_xml;
      DynamicGDBXMLInfo dyn_svereg_xml;
 +    DynamicGDBXMLInfo dyn_m_systemreg_xml;
 +    DynamicGDBXMLInfo dyn_m_secextreg_xml;
      /* Timers used by the generic (architected) timer */
      QEMUTimer *gt_timer[NUM_GTIMERS];
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 +typedef enum {
 +    M_SYSREG_MSP,
 +    M_SYSREG_PSP,
 +    M_SYSREG_PRIMASK,
 +    M_SYSREG_CONTROL,
 +    M_SYSREG_BASEPRI,
 +    M_SYSREG_FAULTMASK,
 +    M_SYSREG_MSPLIM,
 +    M_SYSREG_PSPLIM,
 +} MProfileSysreg;
 +
 +static const struct {
 +    const char *name;
 +    int feature;
 +} m_sysreg_def[] = {
 +    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
 +    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
 +    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
 +    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
 +    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
 +    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
 +};
 +
 +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
 +{
 +    uint32_t *ptr;
 +
 +    switch (reg) {
 +    case M_SYSREG_MSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
 +        break;
 +    case M_SYSREG_PSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
 +        break;
 +    case M_SYSREG_MSPLIM:
 +        ptr = &env->v7m.msplim[sec];
 +        break;
 +    case M_SYSREG_PSPLIM:
 +        ptr = &env->v7m.psplim[sec];
 +        break;
 +    case M_SYSREG_PRIMASK:
 +        ptr = &env->v7m.primask[sec];
 +        break;
 +    case M_SYSREG_BASEPRI:
 +        ptr = &env->v7m.basepri[sec];
 +        break;
 +    case M_SYSREG_FAULTMASK:
 +        ptr = &env->v7m.faultmask[sec];
 +        break;
 +    case M_SYSREG_CONTROL:
 +        ptr = &env->v7m.control[sec];
 +        break;
 +    default:
 +        return NULL;
 +    }
 +    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
 +}
 +
 +static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
 +                        MProfileSysreg reg, bool secure)
 +{
 +    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
 +
 +    if (ptr == NULL) {
 +        return 0;
 +    }
 +    return gdb_get_reg32(buf, *ptr);
 +}
 +
 +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    /*
 +     * Here, we emulate MRS instruction, where CONTROL has a mix of
 +     * banked and non-banked bits.
 +     */
 +    if (reg == M_SYSREG_CONTROL) {
 +        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
 +    }
 +    return m_sysreg_get(env, buf, reg, env->v7m.secure);
 +}
 +
 +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        if (arm_feature(env, m_sysreg_def[i].feature)) {
 +            g_string_append_printf(s,
 +                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +                m_sysreg_def[i].name, base_reg++);
 +        }
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_systemreg_xml.num;
 +}
 +
 +#ifndef CONFIG_USER_ONLY
 +/*
 + * For user-only, we see the non-secure registers via m_systemreg above.
 + * For secext, encode the non-secure view as even and secure view as odd.
 + */
 +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
 +}
 +
 +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_secextreg_xml.num;
 +}
 +#endif
 +
  const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
  {
      ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
          return cpu->dyn_sysreg_xml.desc;
      } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
          return cpu->dyn_svereg_xml.desc;
 +    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
 +        return cpu->dyn_m_systemreg_xml.desc;
 +#ifndef CONFIG_USER_ONLY
 +    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
 +        return cpu->dyn_m_secextreg_xml.desc;
 +#endif
      }
      return NULL;
  }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                               arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                               "system-registers.xml", 0);
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        gdb_register_coprocessor(cs,
 +            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
 +            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
 +            "arm-m-system.xml", 0);
 +#ifndef CONFIG_USER_ONLY
 +        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 +            gdb_register_coprocessor(cs,
 +                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
 +                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
 +                "arm-m-secext.xml", 0);
 +        }
 +#endif
 +    }
  }
 --
 .34.1

-New patch
+[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
+From: Richard Henderson <richard.henderson@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
+ /* Return true if the processor is in secure state */
+ static inline bool arm_is_secure(CPUARMState *env)
+ {
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return env->v7m.secure;
++    }
+     if (arm_is_el3_or_mon(env)) {
+         return true;
+     }
+--
+.34.1

-New patch
+[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
+From: Richard Henderson <richard.henderson@linaro.org>
+M-profile doesn't have HCR_EL2.  While we could test features
+before each call, zero is a generally safe return value to
+disable the code in the caller.  This test is required to
+avoid an assert in arm_is_secure_below_el3.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
+ uint64_t arm_hcr_el2_eff(CPUARMState *env)
+ {
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return 0;
++    }
+     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
+ }
+--
+.34.1

-[PULL 4/4] hw/rtc/pl031: Send RTC_CHANGE QMP event
+[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
-From: Eric Auger <eric.auger@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The PL031 currently is not able to report guest RTC change to the QMP
+In several places we use arm_is_secure_below_el3 and
-monitor as opposed to mc146818 or spapr RTCs. This patch adds the call
+arm_is_el3_or_mon separately from arm_is_secure.
-to qapi_event_send_rtc_change() when the Load Register is written. The
+These functions make no sense for m-profile, and
-value which is reported corresponds to the difference between the guest
+would indicate prior incorrect feature testing.
 reference time and the reference time kept in softmmu/rtc.c.
-For instance adding 20s to the guest RTC value will report 20. Adding
-an extra 20s to the guest RTC value will report 20 + 20 = 40.
-The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c
-require to compile the PL031 with specific_ss.add() to avoid
-./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned
-"TARGET_<ARCH>".
-Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210920122535.269988-1-eric.auger@redhat.com
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/rtc/pl031.c     | 10 +++++++++-
+ target/arm/cpu.h | 5 ++++-
- hw/rtc/meson.build |  2 +-
+file changed, 4 insertions(+), 1 deletion(-)
 files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/rtc/pl031.c
+--- a/target/arm/cpu.h
-+++ b/hw/rtc/pl031.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
- #include "qemu/log.h"
+ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
- #include "qemu/module.h"
- #include "trace.h"
+ #if !defined(CONFIG_USER_ONLY)
-+#include "qapi/qapi-events-misc-target.h"
+-/* Return true if exception levels below EL3 are in secure state,
++/*
- #define RTC_DR      0x00    /* Data read register */
++ * Return true if exception levels below EL3 are in secure state,
- #define RTC_MR      0x04    /* Match register */
+  * or would be following an exception return to that level.
-@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
+  * Unlike arm_is_secure() (which is always a question about the
-     trace_pl031_write(offset, value);
+  * _current_ state of the CPU) this doesn't care about the current
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
-     switch (offset) {
+  */
--    case RTC_LR:
+ static inline bool arm_is_secure_below_el3(CPUARMState *env)
-+    case RTC_LR: {
+ {
-+        struct tm tm;
++    assert(!arm_feature(env, ARM_FEATURE_M));
-+
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
-         s->tick_offset += value - pl031_get_count(s);
+         return !(env->cp15.scr_el3 & SCR_NS);
-+
+     } else {
-+        qemu_get_timedate(&tm, s->tick_offset);
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
-+        qapi_event_send_rtc_change(qemu_timedate_diff(&tm));
+ /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
-+
+ static inline bool arm_is_el3_or_mon(CPUARMState *env)
-         pl031_set_alarm(s);
+ {
-         break;
++    assert(!arm_feature(env, ARM_FEATURE_M));
-+    }
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
-     case RTC_MR:
+         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
-         s->mr = value;
+             /* CPU currently in AArch64 state and EL3 */
          pl031_set_alarm(s);
 diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/rtc/meson.build
 +++ b/hw/rtc/meson.build
@@ -XXX,XX +XXX,XX @@
  softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c'))
  softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c'))
  softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c'))
 -softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
 +specific_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
  softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c'))
  softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c'))
  softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c'))
 --
-.25.1
+.34.1

-New patch
+[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
+From: Richard Henderson <richard.henderson@linaro.org>
 Integrate neighboring code from get_phys_addr_lpae which computed
 starting level, as it is easier to validate when doing both at the
 same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
 especially S2InvalidSL and S2InconsistentSL.
 This reverts 49ba115bb74, which was incorrect -- there is nothing
 in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
 pseudocode is consistent in referencing PAMax.
 Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
 file changed, 97 insertions(+), 76 deletions(-)
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
   * check_s2_mmu_setup
   * @cpu:        ARMCPU
   * @is_aa64:    True if the translation regime is in AArch64 state
 - * @startlevel: Suggested starting level
 - * @inputsize:  Bitsize of IPAs
 + * @tcr:        VTCR_EL2 or VSTCR_EL2
 + * @ds:         Effective value of TCR.DS.
 + * @iasize:     Bitsize of IPAs
   * @stride:     Page-table stride (See the ARM ARM)
   *
 - * Returns true if the suggested S2 translation parameters are OK and
 - * false otherwise.
 + * Decode the starting level of the S2 lookup, returning INT_MIN if
 + * the configuration is invalid.
   */
 -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
 -                               int inputsize, int stride, int outputsize)
 +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
 +                              bool ds, int iasize, int stride)
  {
 -    const int grainsize = stride + 3;
 -    int startsizecheck;
 -
 -    /*
 -     * Negative levels are usually not allowed...
 -     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
 -     * begins with level -1.  Note that previous feature tests will have
 -     * eliminated this combination if it is not enabled.
 -     */
 -    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
 -        return false;
 -    }
 -
 -    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
 -    if (startsizecheck < 1 || startsizecheck > stride + 4) {
 -        return false;
 -    }
 +    int sl0, sl2, startlevel, granulebits, levels;
 +    int s1_min_iasize, s1_max_iasize;
 +    sl0 = extract32(tcr, 6, 2);
      if (is_aa64) {
 +        /*
 +         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
 +         * get_phys_addr_lpae, that used aa64_va_parameters which apply
 +         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
 +         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
 +         * inputsize is 64 - 24 = 40.
 +         */
 +        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
 +            goto fail;
 +        }
 +
 +        /*
 +         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
 +         * so interleave AArch64.S2StartLevel.
 +         */
          switch (stride) {
 -        case 13: /* 64KB Pages.  */
 -            if (level == 0 || (level == 1 && outputsize <= 42)) {
 -                return false;
 +        case 9: /* 4KB */
 +            /* SL2 is RES0 unless DS=1 & 4KB granule. */
 +            sl2 = extract64(tcr, 33, 1);
 +            if (ds && sl2) {
 +                if (sl0 != 0) {
 +                    goto fail;
 +                }
 +                startlevel = -1;
 +            } else {
 +                startlevel = 2 - sl0;
 +                switch (sl0) {
 +                case 2:
 +                    if (arm_pamax(cpu) < 44) {
 +                        goto fail;
 +                    }
 +                    break;
 +                case 3:
 +                    if (!cpu_isar_feature(aa64_st, cpu)) {
 +                        goto fail;
 +                    }
 +                    startlevel = 3;
 +                    break;
 +                }
              }
              break;
 -        case 11: /* 16KB Pages.  */
 -            if (level == 0 || (level == 1 && outputsize <= 40)) {
 -                return false;
 +        case 11: /* 16KB */
 +            switch (sl0) {
 +            case 2:
 +                if (arm_pamax(cpu) < 42) {
 +                    goto fail;
 +                }
 +                break;
 +            case 3:
 +                if (!ds) {
 +                    goto fail;
 +                }
 +                break;
              }
 +            startlevel = 3 - sl0;
              break;
 -        case 9: /* 4KB Pages.  */
 -            if (level == 0 && outputsize <= 42) {
 -                return false;
 +        case 13: /* 64KB */
 +            switch (sl0) {
 +            case 2:
 +                if (arm_pamax(cpu) < 44) {
 +                    goto fail;
 +                }
 +                break;
 +            case 3:
 +                goto fail;
              }
 +            startlevel = 3 - sl0;
              break;
          default:
              g_assert_not_reached();
          }
 -
 -        /* Inputsize checks.  */
 -        if (inputsize > outputsize &&
 -            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
 -            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
 -            return false;
 -        }
      } else {
 -        /* AArch32 only supports 4KB pages. Assert on that.  */
 +        /*
 +         * Things are simpler for AArch32 EL2, with only 4k pages.
 +         * There is no separate S2InvalidSL function, but AArch32.S2Walk
 +         * begins with walkparms.sl0 in {'1x'}.
 +         */
          assert(stride == 9);
 -
 -        if (level == 0) {
 -            return false;
 +        if (sl0 >= 2) {
 +            goto fail;
          }
 +        startlevel = 2 - sl0;
      }
 -    return true;
 +
 +    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
 +    levels = 3 - startlevel;
 +    granulebits = stride + 3;
 +
 +    s1_min_iasize = levels * stride + granulebits + 1;
 +    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
 +
 +    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
 +        return startlevel;
 +    }
 +
 + fail:
 +    return INT_MIN;
  }
  /**
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
           */
          level = 4 - (inputsize - 4) / stride;
      } else {
 -        /*
 -         * For stage 2 translations the starting level is specified by the
 -         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
 -         */
 -        uint32_t sl0 = extract32(tcr, 6, 2);
 -        uint32_t sl2 = extract64(tcr, 33, 1);
 -        int32_t startlevel;
 -        bool ok;
 -
 -        /* SL2 is RES0 unless DS=1 & 4kb granule. */
 -        if (param.ds && stride == 9 && sl2) {
 -            if (sl0 != 0) {
 -                level = 0;
 -                goto do_translation_fault;
 -            }
 -            startlevel = -1;
 -        } else if (!aarch64 || stride == 9) {
 -            /* AArch32 or 4KB pages */
 -            startlevel = 2 - sl0;
 -
 -            if (cpu_isar_feature(aa64_st, cpu)) {
 -                startlevel &= 3;
 -            }
 -        } else {
 -            /* 16KB or 64KB pages */
 -            startlevel = 3 - sl0;
 -        }
 -
 -        /* Check that the starting level is valid. */
 -        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
 -                                inputsize, stride, outputsize);
 -        if (!ok) {
 +        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
 +                                            inputsize, stride);
 +        if (startlevel == INT_MIN) {
 +            level = 0;
              goto do_translation_fault;
          }
          level = startlevel;
 --
 .34.1

-[PULL 1/4] hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
+[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
-The GICv3 devices have an array property redist-region-count.
+From: Ard Biesheuvel <ardb@kernel.org>
 Currently we check this for errors (bad values) in
 gicv3_init_irqs_and_mmio(), just before we use it.  Move this error
 checking to the arm_gicv3_common_realize() function, where we
 sanity-check all of the other base-class properties. (This will
 always be before gicv3_init_irqs_and_mmio() is called, because
 that function is called in the subclass realize methods, after
 they have called the parent-class realize.)
-The motivation for this refactor is:
+Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
- * we would like to use the redist_region_count[] values in
+format, using gzip compression for the payload.
    arm_gicv3_common_realize() in a subsequent patch, so we need
    to have already done the sanity-checking first
  * this removes the only use of the Error** argument to
    gicv3_init_irqs_and_mmio(), so we can remove some error-handling
    boilerplate
+For doing EFI boot in QEMU, this is completely transparent, as the
+firmware or bootloader will take care of this. However, for direct
+kernel boot without firmware, we will lose the ability to boot such
+distro kernels unless we deal with the new format directly.
+EFI zboot images contain metadata in the header regarding the placement
+of the compressed payload inside the image, and the type of compression
+used. This means we can wire up the existing gzip support without too
+much hassle, by parsing the header and grabbing the payload from inside
+the loaded zboot image.
+Cc: Peter Maydell <peter.maydell@linaro.org>
+Cc: Alex Bennée <alex.bennee@linaro.org>
+Cc: Richard Henderson <richard.henderson@linaro.org>
+Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Message-id: 20230303160109.3626966-1-ardb@kernel.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: tweaked comment formatting, fixed checkpatch nits]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/hw/intc/arm_gicv3_common.h |  2 +-
+ include/hw/loader.h | 19 ++++++++++
- hw/intc/arm_gicv3.c                |  6 +-----
+ hw/arm/boot.c       |  6 +++
- hw/intc/arm_gicv3_common.c         | 26 +++++++++++++-------------
+ hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
- hw/intc/arm_gicv3_kvm.c            |  6 +-----
+files changed, 116 insertions(+)
 files changed, 16 insertions(+), 24 deletions(-)
-diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
+diff --git a/include/hw/loader.h b/include/hw/loader.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/arm_gicv3_common.h
+--- a/include/hw/loader.h
-+++ b/include/hw/intc/arm_gicv3_common.h
++++ b/include/hw/loader.h
-@@ -XXX,XX +XXX,XX @@ struct ARMGICv3CommonClass {
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
- };
+                                   uint8_t **buffer);
+ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
- void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
--                              const MemoryRegionOps *ops, Error **errp);
++/**
-+                              const MemoryRegionOps *ops);
++ * unpack_efi_zboot_image:
++ * @buffer: pointer to a variable holding the address of a buffer containing the
- #endif
++ *          image
-diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
++ * @size: pointer to a variable holding the size of the buffer
 + *
 + * Check whether the buffer contains a EFI zboot image, and if it does, extract
 + * the compressed payload and decompress it into a new buffer. If successful,
 + * the old buffer is freed, and the *buffer and size variables pointed to by the
 + * function arguments are updated to refer to the newly populated buffer.
 + *
 + * Returns 0 if the image could not be identified as a EFI zboot image.
 + * Returns -1 if the buffer contents were identified as a EFI zboot image, but
 + * unpacking failed for any reason.
 + * Returns the size of the decompressed payload if decompression was performed
 + * successfully.
 + */
 +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
 +
  #define ELF_LOAD_FAILED       -1
  #define ELF_LOAD_NOT_ELF      -2
  #define ELF_LOAD_WRONG_ARCH   -3
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3.c
+--- a/hw/arm/boot.c
-+++ b/hw/intc/arm_gicv3.c
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
-         return;
+             return -1;
          }
          size = len;
 +
 +        /* Unpack the image if it is a EFI zboot image */
 +        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
 +            g_free(buffer);
 +            return -1;
 +        }
      }
--    gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
+     /* check the arm64 magic header value -- very old kernels may not have it */
--    if (local_err) {
+diff --git a/hw/core/loader.c b/hw/core/loader.c
--        error_propagate(errp, local_err);
+index XXXXXXX..XXXXXXX 100644
--        return;
+--- a/hw/core/loader.c
--    }
++++ b/hw/core/loader.c
-+    gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
+     return bytes;
      gicv3_init_cpuif(s);
  }
-diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
-index XXXXXXX..XXXXXXX 100644
++/* The PE/COFF MS-DOS stub magic number */
---- a/hw/intc/arm_gicv3_common.c
++#define EFI_PE_MSDOS_MAGIC        "MZ"
-+++ b/hw/intc/arm_gicv3_common.c
++
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
++/*
- };
++ * The Linux header magic number for a EFI PE/COFF
++ * image targetting an unspecified architecture.
- void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
++ */
--                              const MemoryRegionOps *ops, Error **errp)
++#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
-+                              const MemoryRegionOps *ops)
++
- {
++/*
-     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
++ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
--    int rdist_capacity = 0;
++ * self-decompressing executables when loaded via EFI. The compressed payload
-     int i;
++ * can also be extracted from the image and decompressed by a non-EFI loader.
++ *
--    for (i = 0; i < s->nb_redist_regions; i++) {
++ * The de facto specification for this format is at the following URL:
--        rdist_capacity += s->redist_region_count[i];
++ *
--    }
++ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
--    if (rdist_capacity < s->num_cpu) {
++ *
--        error_setg(errp, "Capacity of the redist regions(%d) "
++ * This definition is based on Linux upstream commit 29636a5ce87beba.
--                   "is less than number of vcpus(%d)",
++ */
--                   rdist_capacity, s->num_cpu);
++struct linux_efi_zboot_header {
--        return;
++    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
--    }
++    uint8_t     reserved0[2];
--
++    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
-     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
++    uint32_t    payload_offset;         /* LE offset to compressed payload */
-      * GPIO array layout is thus:
++    uint32_t    payload_size;           /* LE size of the compressed payload */
-      *  [0..N-1] spi
++    uint8_t     reserved1[8];
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
++    char        compression_type[32];   /* Compression type, NUL terminated */
- static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
++    uint8_t     linux_magic[4];         /* Linux header magic */
- {
++    uint32_t    pe_header_offset;       /* LE offset to the PE header */
-     GICv3State *s = ARM_GICV3_COMMON(dev);
++};
--    int i;
++
-+    int i, rdist_capacity;
++/*
++ * Check whether *buffer points to a Linux EFI zboot image in memory.
-     /* revision property is actually reserved and currently used only in order
++ *
-      * to keep the interface compatible with GICv2 code, avoiding extra
++ * If it does, attempt to decompress it to a new buffer, and free the old one.
-@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
++ * If any of this fails, return an error to the caller.
-         return;
++ *
-     }
++ * If the image is not a Linux EFI zboot image, do nothing and return success.
++ */
-+    rdist_capacity = 0;
++ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
-+    for (i = 0; i < s->nb_redist_regions; i++) {
++{
-+        rdist_capacity += s->redist_region_count[i];
++    const struct linux_efi_zboot_header *header;
-+    }
++    uint8_t *data = NULL;
-+    if (rdist_capacity < s->num_cpu) {
++    int ploff, plsize;
-+        error_setg(errp, "Capacity of the redist regions(%d) "
++    ssize_t bytes;
-+                   "is less than number of vcpus(%d)",
++
-+                   rdist_capacity, s->num_cpu);
++    /* ignore if this is too small to be a EFI zboot image */
-+        return;
++    if (*size < sizeof(*header)) {
 +        return 0;
 +    }
 +
-     s->cpu = g_new0(GICv3CPUState, s->num_cpu);
++    header = (struct linux_efi_zboot_header *)*buffer;
++
-     for (i = 0; i < s->num_cpu; i++) {
++    /* ignore if this is not a Linux EFI zboot image */
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
++    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
-index XXXXXXX..XXXXXXX 100644
++        memcmp(&header->zimg, "zimg", 4) != 0 ||
---- a/hw/intc/arm_gicv3_kvm.c
++        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
-+++ b/hw/intc/arm_gicv3_kvm.c
++        return 0;
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
++    }
-         return;
++
-     }
++    if (strcmp(header->compression_type, "gzip") != 0) {
++        fprintf(stderr,
--    gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
++                "unable to handle EFI zboot image with \"%.*s\" compression\n",
--    if (local_err) {
++                (int)sizeof(header->compression_type) - 1,
--        error_propagate(errp, local_err);
++                header->compression_type);
--        return;
++        return -1;
--    }
++    }
-+    gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
++
++    ploff = ldl_le_p(&header->payload_offset);
-     for (i = 0; i < s->num_cpu; i++) {
++    plsize = ldl_le_p(&header->payload_size);
-         ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
++
 +    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
 +        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
 +        return -1;
 +    }
 +
 +    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
 +    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
 +    if (bytes < 0) {
 +        fprintf(stderr, "failed to decompress EFI zboot image\n");
 +        g_free(data);
 +        return -1;
 +    }
 +
 +    g_free(*buffer);
 +    *buffer = g_realloc(data, bytes);
 +    *size = bytes;
 +    return bytes;
 +}
 +
  /*
   * Functions for reboot-persistent memory regions.
   *  - used for vga bios and option roms.
 --
-.25.1
+.34.1

-New patch
+[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
+From: qianfan Zhao <qianfanguijin@163.com>
+TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
+register on SUN6i based SoCs, we should lower interrupt when the guest
+set this bit.
+The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
+device connected on the i2c bus, next is the trace log:
+allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
+allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+...
+Fix it.
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/i2c/allwinner-i2c.h |  6 ++++++
+ hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
+files changed, 30 insertions(+), 2 deletions(-)
+diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/i2c/allwinner-i2c.h
++++ b/include/hw/i2c/allwinner-i2c.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
+ #define TYPE_AW_I2C "allwinner.i2c"
++
++/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
++#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
++
+ OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
+ #define AW_I2C_MEM_SIZE         0x24
+@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
+     uint8_t srst;
+     uint8_t efr;
+     uint8_t lcr;
++
++    bool irq_clear_inverted;
+ };
+ #endif /* ALLWINNER_I2C_H */
+diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/i2c/allwinner-i2c.c
++++ b/hw/i2c/allwinner-i2c.c
+@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
+                 s->stat = STAT_FROM_STA(STAT_IDLE);
+                 s->cntr &= ~TWI_CNTR_M_STP;
+             }
+-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
+-                /* Interrupt flag cleared */
++
++            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
++                /* Write 0 to clear this flag */
++                qemu_irq_lower(s->irq);
++            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
++                /* Write 1 to clear this flag */
++                s->cntr &= ~TWI_CNTR_INT_FLAG;
+                 qemu_irq_lower(s->irq);
+             }
++
+             if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
+                 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
+                     s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
+     .class_init = allwinner_i2c_class_init,
+ };
++static void allwinner_i2c_sun6i_init(Object *obj)
++{
++    AWI2CState *s = AW_I2C(obj);
++
++    s->irq_clear_inverted = true;
++}
++
++static const TypeInfo allwinner_i2c_sun6i_type_info = {
++    .name = TYPE_AW_I2C_SUN6I,
++    .parent = TYPE_SYS_BUS_DEVICE,
++    .instance_size = sizeof(AWI2CState),
++    .instance_init = allwinner_i2c_sun6i_init,
++    .class_init = allwinner_i2c_class_init,
++};
++
+ static void allwinner_i2c_register_types(void)
+ {
+     type_register_static(&allwinner_i2c_type_info);
++    type_register_static(&allwinner_i2c_sun6i_type_info);
+ }
+ type_init(allwinner_i2c_register_types)
+--
+.34.1

-New patch
+[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
+From: qianfan Zhao <qianfanguijin@163.com>
+Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
+The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
+control register's INT_FLAG bit.
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/allwinner-h3.h |  6 ++++++
+ hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
+files changed, 31 insertions(+), 4 deletions(-)
+diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/allwinner-h3.h
++++ b/include/hw/arm/allwinner-h3.h
+@@ -XXX,XX +XXX,XX @@ enum {
+     AW_H3_DEV_UART3,
+     AW_H3_DEV_EMAC,
+     AW_H3_DEV_TWI0,
++    AW_H3_DEV_TWI1,
++    AW_H3_DEV_TWI2,
+     AW_H3_DEV_DRAMCOM,
+     AW_H3_DEV_DRAMCTL,
+     AW_H3_DEV_DRAMPHY,
+@@ -XXX,XX +XXX,XX @@ enum {
+     AW_H3_DEV_GIC_VCPU,
+     AW_H3_DEV_RTC,
+     AW_H3_DEV_CPUCFG,
++    AW_H3_DEV_R_TWI,
+     AW_H3_DEV_SDRAM
+ };
+@@ -XXX,XX +XXX,XX @@ struct AwH3State {
+     AwSidState sid;
+     AwSdHostState mmc0;
+     AWI2CState i2c0;
++    AWI2CState i2c1;
++    AWI2CState i2c2;
++    AWI2CState r_twi;
+     AwSun8iEmacState emac;
+     AwRtcState rtc;
+     GICState gic;
+diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/allwinner-h3.c
++++ b/hw/arm/allwinner-h3.c
+@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
+     [AW_H3_DEV_UART2]      = 0x01c28800,
+     [AW_H3_DEV_UART3]      = 0x01c28c00,
+     [AW_H3_DEV_TWI0]       = 0x01c2ac00,
++    [AW_H3_DEV_TWI1]       = 0x01c2b000,
++    [AW_H3_DEV_TWI2]       = 0x01c2b400,
+     [AW_H3_DEV_EMAC]       = 0x01c30000,
+     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
+     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
+@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
+     [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
+     [AW_H3_DEV_RTC]        = 0x01f00000,
+     [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
++    [AW_H3_DEV_R_TWI]      = 0x01f02400,
+     [AW_H3_DEV_SDRAM]      = 0x40000000
+ };
+@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
+     { "uart1",     0x01c28400, 1 * KiB },
+     { "uart2",     0x01c28800, 1 * KiB },
+     { "uart3",     0x01c28c00, 1 * KiB },
+-    { "twi1",      0x01c2b000, 1 * KiB },
+-    { "twi2",      0x01c2b400, 1 * KiB },
+     { "scr",       0x01c2c400, 1 * KiB },
+     { "gpu",       0x01c40000, 64 * KiB },
+     { "hstmr",     0x01c60000, 4 * KiB },
+@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
+     { "r_prcm",    0x01f01400, 1 * KiB },
+     { "r_twd",     0x01f01800, 1 * KiB },
+     { "r_cir-rx",  0x01f02000, 1 * KiB },
+-    { "r_twi",     0x01f02400, 1 * KiB },
+     { "r_uart",    0x01f02800, 1 * KiB },
+     { "r_pio",     0x01f02c00, 1 * KiB },
+     { "r_pwm",     0x01f03800, 1 * KiB },
+@@ -XXX,XX +XXX,XX @@ enum {
+     AW_H3_GIC_SPI_UART2     =  2,
+     AW_H3_GIC_SPI_UART3     =  3,
+     AW_H3_GIC_SPI_TWI0      =  6,
++    AW_H3_GIC_SPI_TWI1      =  7,
++    AW_H3_GIC_SPI_TWI2      =  8,
+     AW_H3_GIC_SPI_TIMER0    = 18,
+     AW_H3_GIC_SPI_TIMER1    = 19,
++    AW_H3_GIC_SPI_R_TWI     = 44,
+     AW_H3_GIC_SPI_MMC0      = 60,
+     AW_H3_GIC_SPI_EHCI0     = 72,
+     AW_H3_GIC_SPI_OHCI0     = 73,
+@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
+     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
+-    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
++    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
++    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
++    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
++    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
+ }
+ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
+                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
++    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
++                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
++
++    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
++                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
++
++    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
++                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
++
+     /* Unimplemented devices */
+     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
+         create_unimplemented_device(unimplemented[i].device_name,
+--
+.34.1

Hi; some minor changes for 6.2, which I think can be classified
as bug fixes and are OK for this point in the release cycle.
(Wouldn't be the end of the world if they slipped to 7.0.)

-- PMM

The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d:

Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1

for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5:

hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000)

----------------------------------------------------------------
target-arm queue:
 * Support multiple redistributor regions for TCG GICv3
 * Send RTC_CHANGE QMP event from pl031

----------------------------------------------------------------
Eric Auger (1):
      hw/rtc/pl031: Send RTC_CHANGE QMP event

Peter Maydell (3):
      hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
      hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
      hw/intc/arm_gicv3: Support multiple redistributor regions

include/hw/intc/arm_gicv3_common.h | 14 ++++++++--
 hw/intc/arm_gicv3.c                | 12 +-------
 hw/intc/arm_gicv3_common.c         | 56 ++++++++++++++++++++++++--------------
 hw/intc/arm_gicv3_kvm.c            | 10 ++-----
 hw/intc/arm_gicv3_redist.c         | 40 +++++++++++++++------------
 hw/rtc/pl031.c                     | 10 ++++++-
 hw/rtc/meson.build                 |  2 +-
 7 files changed, 83 insertions(+), 61 deletions(-)

The GICv3 devices have an array property redist-region-count.
Currently we check this for errors (bad values) in
gicv3_init_irqs_and_mmio(), just before we use it.  Move this error
checking to the arm_gicv3_common_realize() function, where we
sanity-check all of the other base-class properties. (This will
always be before gicv3_init_irqs_and_mmio() is called, because
that function is called in the subclass realize methods, after
they have called the parent-class realize.)

The motivation for this refactor is:
 * we would like to use the redist_region_count[] values in
   arm_gicv3_common_realize() in a subsequent patch, so we need
   to have already done the sanity-checking first
 * this removes the only use of the Error** argument to
   gicv3_init_irqs_and_mmio(), so we can remove some error-handling
   boilerplate

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/intc/arm_gicv3_common.h |  2 +-
 hw/intc/arm_gicv3.c                |  6 +-----
 hw/intc/arm_gicv3_common.c         | 26 +++++++++++++-------------
 hw/intc/arm_gicv3_kvm.c            |  6 +-----
 4 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -XXX,XX +XXX,XX @@ struct ARMGICv3CommonClass {
 };
 
 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
-                              const MemoryRegionOps *ops, Error **errp);
+                              const MemoryRegionOps *ops);
 
 #endif
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
-    if (local_err) {
-        error_propagate(errp, local_err);
-        return;
-    }
+    gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
 
     gicv3_init_cpuif(s);
 }
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
 };
 
 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
-                              const MemoryRegionOps *ops, Error **errp)
+                              const MemoryRegionOps *ops)
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
-    int rdist_capacity = 0;
     int i;
 
-    for (i = 0; i < s->nb_redist_regions; i++) {
-        rdist_capacity += s->redist_region_count[i];
-    }
-    if (rdist_capacity < s->num_cpu) {
-        error_setg(errp, "Capacity of the redist regions(%d) "
-                   "is less than number of vcpus(%d)",
-                   rdist_capacity, s->num_cpu);
-        return;
-    }
-
     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
      * GPIO array layout is thus:
      *  [0..N-1] spi
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
 {
     GICv3State *s = ARM_GICV3_COMMON(dev);
-    int i;
+    int i, rdist_capacity;
 
     /* revision property is actually reserved and currently used only in order
      * to keep the interface compatible with GICv2 code, avoiding extra
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    rdist_capacity = 0;
+    for (i = 0; i < s->nb_redist_regions; i++) {
+        rdist_capacity += s->redist_region_count[i];
+    }
+    if (rdist_capacity < s->num_cpu) {
+        error_setg(errp, "Capacity of the redist regions(%d) "
+                   "is less than number of vcpus(%d)",
+                   rdist_capacity, s->num_cpu);
+        return;
+    }
+
     s->cpu = g_new0(GICv3CPUState, s->num_cpu);
 
     for (i = 0; i < s->num_cpu; i++) {
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
-    if (local_err) {
-        error_propagate(errp, local_err);
-        return;
-    }
+    gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
 
     for (i = 0; i < s->num_cpu; i++) {
         ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
-- 
2.25.1

The 'Last' bit in the GICR_TYPER GICv3 redistributor register is
supposed to be set to 1 if this is the last redistributor in a series
of contiguous redistributor pages.  Currently we set Last only for
the redistributor for CPU (num_cpu - 1).  This only works if there is
a single redistributor region; if there are multiple redistributor
regions then we need to set the Last bit for the last redistributor
in each region.

This doesn't cause any problems currently because only the KVM GICv3
supports multiple redistributor regions, and it ignores the value in
GICv3State::gicr_typer.  But we need to fix this before we can enable
support for multiple regions in the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/intc/arm_gicv3_common.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
 {
     GICv3State *s = ARM_GICV3_COMMON(dev);
-    int i, rdist_capacity;
+    int i, rdist_capacity, cpuidx;
 
     /* revision property is actually reserved and currently used only in order
      * to keep the interface compatible with GICv2 code, avoiding extra
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < s->num_cpu; i++) {
         CPUState *cpu = qemu_get_cpu(i);
         uint64_t cpu_affid;
-        int last;
 
         s->cpu[i].cpu = cpu;
         s->cpu[i].gic = s;
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
          *  PLPIS == 0 (physical LPIs not supported)
          */
         cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
-        last = (i == s->num_cpu - 1);
 
         /* The CPU mp-affinity property is in MPIDR register format; squash
          * the affinity bytes into 32 bits as the GICR_TYPER has them.
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
                      (cpu_affid & 0xFFFFFF);
         s->cpu[i].gicr_typer = (cpu_affid << 32) |
             (1 << 24) |
-            (i << 8) |
-            (last << 4);
+            (i << 8);
 
         if (s->lpi_enable) {
             s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
         }
     }
+
+    /*
+     * Now go through and set GICR_TYPER.Last for the final
+     * redistributor in each region.
+     */
+    cpuidx = 0;
+    for (i = 0; i < s->nb_redist_regions; i++) {
+        cpuidx += s->redist_region_count[i];
+        s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST;
+    }
 }
 
 static void arm_gicv3_finalize(Object *obj)
-- 
2.25.1

Our GICv3 QOM interface includes an array property
redist-region-count which allows board models to specify that the
registributor registers are not in a single contiguous range, but
split into multiple pieces.  We implemented this for KVM, but
currently the TCG GICv3 model insists that there is only one region.
You can see the limit being hit with a setup like:
  qemu-system-aarch64 -machine virt,gic-version=3 -smp 124

Add support for split regions to the TCG GICv3.  To do this we switch
from allocating a simple array of MemoryRegions to an array of
GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
the opaque pointer in the MemoryRegion read/write callbacks.  Each
GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
the read/write callback to get hold of the GICv3State, and an index
which allows us to calculate which CPU's redistributor is being
accessed.

Note that arm_gicv3_kvm always passes in NULL as the ops argument
to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
callbacks we need to update to handle this new scheme are the
gicv3_redist_read/write functions used by the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/intc/arm_gicv3_common.h | 12 ++++++++-
 hw/intc/arm_gicv3.c                |  6 -----
 hw/intc/arm_gicv3_common.c         | 15 ++++++++---
 hw/intc/arm_gicv3_kvm.c            |  4 +--
 hw/intc/arm_gicv3_redist.c         | 40 ++++++++++++++++--------------
 5 files changed, 46 insertions(+), 31 deletions(-)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
     bool seenbetter;
 };
 
+/*
+ * The redistributor pages might be split into more than one region
+ * on some machine types if there are many CPUs.
+ */
+typedef struct GICv3RedistRegion {
+    GICv3State *gic;
+    MemoryRegion iomem;
+    uint32_t cpuidx; /* index of first CPU this region covers */
+} GICv3RedistRegion;
+
 struct GICv3State {
     /*< private >*/
     SysBusDevice parent_obj;
     /*< public >*/
 
     MemoryRegion iomem_dist; /* Distributor */
-    MemoryRegion *iomem_redist; /* Redistributor Regions */
+    GICv3RedistRegion *redist_regions; /* Redistributor Regions */
     uint32_t *redist_region_count; /* redistributor count within each region */
     uint32_t nb_redist_regions; /* number of redist regions */
 
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (s->nb_redist_regions != 1) {
-        error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
-                   s->nb_redist_regions);
-        return;
-    }
-
     gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
 
     gicv3_init_cpuif(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
     int i;
+    int cpuidx;
 
     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
      * GPIO array layout is thus:
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
                           "gicv3_dist", 0x10000);
     sysbus_init_mmio(sbd, &s->iomem_dist);
 
-    s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
+    s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
+    cpuidx = 0;
     for (i = 0; i < s->nb_redist_regions; i++) {
         char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
+        GICv3RedistRegion *region = &s->redist_regions[i];
 
-        memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
-                              ops ? &ops[1] : NULL, s, name,
+        region->gic = s;
+        region->cpuidx = cpuidx;
+        cpuidx += s->redist_region_count[i];
+
+        memory_region_init_io(&region->iomem, OBJECT(s),
+                              ops ? &ops[1] : NULL, region, name,
                               s->redist_region_count[i] * GICV3_REDIST_SIZE);
-        sysbus_init_mmio(sbd, &s->iomem_redist[i]);
+        sysbus_init_mmio(sbd, &region->iomem);
         g_free(name);
     }
 }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
                             KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
 
     if (!multiple_redist_region_allowed) {
-        kvm_arm_register_device(&s->iomem_redist[0], -1,
+        kvm_arm_register_device(&s->redist_regions[0].iomem, -1,
                                 KVM_DEV_ARM_VGIC_GRP_ADDR,
                                 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
     } else {
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
             uint64_t addr_ormask =
                         i | ((uint64_t)s->redist_region_count[i] << 52);
 
-            kvm_arm_register_device(&s->iomem_redist[i], -1,
+            kvm_arm_register_device(&s->redist_regions[i].iomem, -1,
                                     KVM_DEV_ARM_VGIC_GRP_ADDR,
                                     KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
                                     s->dev_fd, addr_ormask);
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
                               unsigned size, MemTxAttrs attrs)
 {
-    GICv3State *s = opaque;
+    GICv3RedistRegion *region = opaque;
+    GICv3State *s = region->gic;
     GICv3CPUState *cs;
     MemTxResult r;
     int cpuidx;
 
     assert((offset & (size - 1)) == 0);
 
-    /* This region covers all the redistributor pages; there are
-     * (for GICv3) two 64K pages per CPU. At the moment they are
-     * all contiguous (ie in this one region), though we might later
-     * want to allow splitting of redistributor pages into several
-     * blocks so we can support more CPUs.
+    /*
+     * There are (for GICv3) two 64K redistributor pages per CPU.
+     * In some cases the redistributor pages for all CPUs are not
+     * contiguous (eg on the virt board they are split into two
+     * parts if there are too many CPUs to all fit in the same place
+     * in the memory map); if so then the GIC has multiple MemoryRegions
+     * for the redistributors.
      */
-    cpuidx = offset / 0x20000;
-    offset %= 0x20000;
-    assert(cpuidx < s->num_cpu);
+    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
+    offset %= GICV3_REDIST_SIZE;
 
     cs = &s->cpu[cpuidx];
 
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
                                unsigned size, MemTxAttrs attrs)
 {
-    GICv3State *s = opaque;
+    GICv3RedistRegion *region = opaque;
+    GICv3State *s = region->gic;
     GICv3CPUState *cs;
     MemTxResult r;
     int cpuidx;
 
     assert((offset & (size - 1)) == 0);
 
-    /* This region covers all the redistributor pages; there are
-     * (for GICv3) two 64K pages per CPU. At the moment they are
-     * all contiguous (ie in this one region), though we might later
-     * want to allow splitting of redistributor pages into several
-     * blocks so we can support more CPUs.
+    /*
+     * There are (for GICv3) two 64K redistributor pages per CPU.
+     * In some cases the redistributor pages for all CPUs are not
+     * contiguous (eg on the virt board they are split into two
+     * parts if there are too many CPUs to all fit in the same place
+     * in the memory map); if so then the GIC has multiple MemoryRegions
+     * for the redistributors.
      */
-    cpuidx = offset / 0x20000;
-    offset %= 0x20000;
-    assert(cpuidx < s->num_cpu);
+    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
+    offset %= GICV3_REDIST_SIZE;
 
     cs = &s->cpu[cpuidx];
 
-- 
2.25.1

From: Eric Auger <eric.auger@redhat.com>

The PL031 currently is not able to report guest RTC change to the QMP
monitor as opposed to mc146818 or spapr RTCs. This patch adds the call
to qapi_event_send_rtc_change() when the Load Register is written. The
value which is reported corresponds to the difference between the guest
reference time and the reference time kept in softmmu/rtc.c.

For instance adding 20s to the guest RTC value will report 20. Adding
an extra 20s to the guest RTC value will report 20 + 20 = 40.

The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c
require to compile the PL031 with specific_ss.add() to avoid
./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned
"TARGET_<ARCH>".

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210920122535.269988-1-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/rtc/pl031.c     | 10 +++++++++-
 hw/rtc/meson.build |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/pl031.c
+++ b/hw/rtc/pl031.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "trace.h"
+#include "qapi/qapi-events-misc-target.h"
 
 #define RTC_DR      0x00    /* Data read register */
 #define RTC_MR      0x04    /* Match register */
@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
     trace_pl031_write(offset, value);
 
     switch (offset) {
-    case RTC_LR:
+    case RTC_LR: {
+        struct tm tm;
+
         s->tick_offset += value - pl031_get_count(s);
+
+        qemu_get_timedate(&tm, s->tick_offset);
+        qapi_event_send_rtc_change(qemu_timedate_diff(&tm));
+
         pl031_set_alarm(s);
         break;
+    }
     case RTC_MR:
         s->mr = value;
         pl031_set_alarm(s);
diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/meson.build
+++ b/hw/rtc/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c'))
 softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c'))
 softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c'))
-softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
+specific_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
 softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c'))
 softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c'))
 softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c'))
-- 
2.25.1

The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:

Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306

for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:

hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * allwinner-h3: Fix I2C controller model for Sun6i SoCs
 * allwinner-h3: Add missing i2c controllers
 * Expose M-profile system registers to gdbstub
 * Expose pauth information to gdbstub
 * Support direct boot for Linux/arm64 EFI zboot images
 * Fix incorrect stage 2 MMU setup validation

----------------------------------------------------------------
Ard Biesheuvel (1):
      hw: arm: Support direct boot for Linux/arm64 EFI zboot images

David Reiss (2):
      target/arm: Export arm_v7m_mrs_control
      target/arm: Export arm_v7m_get_sp_ptr

Richard Henderson (16):
      target/arm: Normalize aarch64 gdbstub get/set function names
      target/arm: Unexport arm_gen_dynamic_sysreg_xml
      target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
      target/arm: Split out output_vector_union_type
      target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
      target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
      target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
      target/arm: Add name argument to output_vector_union_type
      target/arm: Simplify iteration over bit widths
      target/arm: Create pauth_ptr_mask
      target/arm: Implement gdbstub pauth extension
      target/arm: Implement gdbstub m-profile systemreg and secext
      target/arm: Handle m-profile in arm_is_secure
      target/arm: Stub arm_hcr_el2_eff for m-profile
      target/arm: Diagnose incorrect usage of arm_is_secure subroutines
      target/arm: Rewrite check_s2_mmu_setup

qianfan Zhao (2):
      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
      hw: arm: allwinner-h3: Fix and complete H3 i2c devices

From: Richard Henderson <richard.henderson@linaro.org>

Make the form of the function names between fp and sve the same:
  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 8 ++++----
 target/arm/gdbstub.c   | 9 +++++----
 target/arm/gdbstub64.c | 8 ++++----
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
          */
 #ifdef TARGET_AARCH64
         if (isar_feature_aa64_sve(&cpu->isar)) {
-            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
-                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
+            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
+            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
+                                     aarch64_gdb_set_sve_reg, nreg,
                                      "sve-registers.xml", 0);
         } else {
-            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
-                                     aarch64_fpu_gdb_set_reg,
+            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
+                                     aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
 #endif
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     return 0;
 }
 
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
     }
 }
 
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
     }
 }
 
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
     return 0;
 }
 
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is not used outside gdbstub.c.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     | 1 -
 target/arm/gdbstub.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  * Helpers to dynamically generates XML descriptions of the sysregs
  * and SVE registers. Returns the number of registers in each set.
  */
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 
 /* Returns the dynamically generated XML for the gdb stub.
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
     }
 }
 
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The function is only used for aarch64, so move it to the
file that has the other aarch64 gdbstub stuff.  Move the
declaration to internals.h.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |   6 ---
 target/arm/internals.h |   1 +
 target/arm/gdbstub.c   | 120 -----------------------------------------
 target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 119 insertions(+), 126 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
-/*
- * Helpers to dynamically generates XML descriptions of the sysregs
- * and SVE registers. Returns the number of registers in each set.
- */
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
-
 /* Returns the dynamically generated XML for the gdb stub.
  * Returns a pointer to the XML contents for the specified XML file or NULL
  * if the XML name doesn't match the predefined one.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    int  size;
-    const char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
-
-    /* First define types and totals in a whole VL */
-    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
-        g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
-    }
-    /*
-     * Now define a union for each size group containing unsigned and
-     * signed and potentially float versions of each size from 128 to
-     * 8 bits.
-     */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
-        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
-            if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
-                                       vec_lanes[j].sz, vec_lanes[j].suffix);
-            }
-        }
-        g_string_append(s, "</union>");
-    }
-    /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
-    }
-    g_string_append(s, "</union>");
-
-    /* Finally the sve prefix type */
-    g_string_append_printf(s,
-                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
-
-    /* Then define each register in parts for each vq */
-    for (i = 0; i < 32; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"z%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svev\"/>",
-                               i, reg_width, base_reg++);
-        info->num++;
-    }
-    /* fpscr & status registers */
-    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    info->num += 2;
-
-    for (i = 0; i < 16; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"p%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
-    }
-    g_string_append_printf(s,
-                           "<reg name=\"ffr\" bitsize=\"%d\""
-                           " regnum=\"%d\" group=\"vector\""
-                           " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
-    g_string_append_printf(s,
-                           "<reg name=\"vg\" bitsize=\"64\""
-                           " regnum=\"%d\" type=\"int\"/>",
-                           base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
-
-    return cpu->dyn_svereg_xml.num;
-}
-
-
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 
     return 0;
 }
+
+struct TypeSize {
+    const char *gdb_type;
+    short size;
+    char sz, suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+    /* quads */
+    { "uint128", 128, 'q', 'u' },
+    { "int128", 128, 'q', 's' },
+    /* 64 bit */
+    { "ieee_double", 64, 'd', 'f' },
+    { "uint64", 64, 'd', 'u' },
+    { "int64", 64, 'd', 's' },
+    /* 32 bit */
+    { "ieee_single", 32, 's', 'f' },
+    { "uint32", 32, 's', 'u' },
+    { "int32", 32, 's', 's' },
+    /* 16 bit */
+    { "ieee_half", 16, 'h', 'f' },
+    { "uint16", 16, 'h', 'u' },
+    { "int16", 16, 'h', 's' },
+    /* bytes */
+    { "uint8", 8, 'b', 'u' },
+    { "int8", 8, 'b', 's' },
+};
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    g_autoptr(GString) ts = g_string_new("");
+    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    /* First define types and totals in a whole VL */
+    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+        int count = reg_width / vec_lanes[i].size;
+        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
+        g_string_append_printf(s,
+                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+                               ts->str, vec_lanes[i].gdb_type, count);
+    }
+    /*
+     * Now define a union for each size group containing unsigned and
+     * signed and potentially float versions of each size from 128 to
+     * 8 bits.
+     */
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+            if (vec_lanes[j].size == bits) {
+                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
+                                       vec_lanes[j].suffix,
+                                       vec_lanes[j].sz, vec_lanes[j].suffix);
+            }
+        }
+        g_string_append(s, "</union>");
+    }
+    /* And now the final union of unions */
+    g_string_append(s, "<union id=\"svev\">");
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
+                               suf[i], suf[i]);
+    }
+    g_string_append(s, "</union>");
+
+    /* Finally the sve prefix type */
+    g_string_append_printf(s,
+                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+                           reg_width / 8);
+
+    /* Then define each register in parts for each vq */
+    for (i = 0; i < 32; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"z%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svev\"/>",
+                               i, reg_width, base_reg++);
+        info->num++;
+    }
+    /* fpscr & status registers */
+    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    info->num += 2;
+
+    for (i = 0; i < 16; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"p%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svep\"/>",
+                               i, cpu->sve_max_vq * 16, base_reg++);
+        info->num++;
+    }
+    g_string_append_printf(s,
+                           "<reg name=\"ffr\" bitsize=\"%d\""
+                           " regnum=\"%d\" group=\"vector\""
+                           " type=\"svep\"/>",
+                           cpu->sve_max_vq * 16, base_reg++);
+    g_string_append_printf(s,
+                           "<reg name=\"vg\" bitsize=\"64\""
+                           " regnum=\"%d\" type=\"int\"/>",
+                           base_reg++);
+    info->num += 2;
+    g_string_append_printf(s, "</feature>");
+    info->desc = g_string_free(s, false);
+
+    return info->num;
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a subroutine for creating the union of unions
of the various type sizes that a vector may contain.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 38 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    short size;
-    char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+static void output_vector_union_type(GString *s, int reg_width)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    struct TypeSize {
+        const char *gdb_type;
+        short size;
+        char sz, suffix;
+    };
+
+    static const struct TypeSize vec_lanes[] = {
+        /* quads */
+        { "uint128", 128, 'q', 'u' },
+        { "int128", 128, 'q', 's' },
+        /* 64 bit */
+        { "ieee_double", 64, 'd', 'f' },
+        { "uint64", 64, 'd', 'u' },
+        { "int64", 64, 'd', 's' },
+        /* 32 bit */
+        { "ieee_single", 32, 's', 'f' },
+        { "uint32", 32, 's', 'u' },
+        { "int32", 32, 's', 's' },
+        /* 16 bit */
+        { "ieee_half", 16, 'h', 'f' },
+        { "uint16", 16, 'h', 'u' },
+        { "int16", 16, 'h', 's' },
+        /* bytes */
+        { "uint8", 8, 'b', 'u' },
+        { "int8", 8, 'b', 's' },
+    };
+
+    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+
     g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+    int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     /* And now the final union of unions */
     g_string_append(s, "<union id=\"svev\">");
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
                                suf[i], suf[i]);
     }
     g_string_append(s, "</union>");
+}
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    int i, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    output_vector_union_type(s, reg_width);
 
     /* Finally the sve prefix type */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Rather than increment base_reg and num, compute num from the change
to base_reg at the end.  Clean up some nearby comments.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     g_string_append(s, "</union>");
 }
 
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    int i, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
+    int reg_width = cpu->sve_max_vq * 128;
+    int base_reg = orig_base_reg;
+    int i;
+
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
+    /* Create the vector union type. */
     output_vector_union_type(s, reg_width);
 
-    /* Finally the sve prefix type */
+    /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
                            reg_width / 8);
 
-    /* Then define each register in parts for each vq */
+    /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
         g_string_append_printf(s,
                                "<reg name=\"z%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svev\"/>",
                                i, reg_width, base_reg++);
-        info->num++;
     }
+
     /* fpscr & status registers */
     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
                            " type=\"int\"/>", base_reg++);
-    info->num += 2;
 
+    /* Define the predicate registers. */
     for (i = 0; i < 16; i++) {
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
                                i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
                            cpu->sve_max_vq * 16, base_reg++);
+
+    /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
                            "<reg name=\"vg\" bitsize=\"64\""
                            " regnum=\"%d\" type=\"int\"/>",
                            base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    info->desc = g_string_free(s, false);
 
+    g_string_append_printf(s, "</feature>");
+
+    info->desc = g_string_free(s, false);
+    info->num = base_reg - orig_base_reg;
     return info->num;
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
     int reg_width = cpu->sve_max_vq * 128;
+    int pred_width = cpu->sve_max_vq * 16;
     int base_reg = orig_base_reg;
     int i;
 
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
+                               i, pred_width, base_reg++);
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
+                           pred_width, base_reg++);
 
     /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Define svep based on the size of the predicates,
not the primary vector registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
+                           pred_width / 8);
 
     /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This will make the function usable between SVE and SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-static void output_vector_union_type(GString *s, int reg_width)
+static void output_vector_union_type(GString *s, int reg_width,
+                                     const char *name)
 {
     struct TypeSize {
         const char *gdb_type;
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     };
 
     static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-
-    g_autoptr(GString) ts = g_string_new("");
     int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
         g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
+                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
+                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
+                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
     }
+
     /*
      * Now define a union for each size group containing unsigned and
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
+                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
+                                       vec_lanes[j].suffix, name,
                                        vec_lanes[j].sz, vec_lanes[j].suffix);
             }
         }
         g_string_append(s, "</union>");
     }
+
     /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
+    g_string_append_printf(s, "<union id=\"%s\">", name);
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
+        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                               suf[i], name, suf[i]);
     }
     g_string_append(s, "</union>");
 }
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
     /* Create the vector union type. */
-    output_vector_union_type(s, reg_width);
+    output_vector_union_type(s, reg_width, "svev");
 
     /* Create the predicate vector type. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Order suf[] by the log8 of the width.
Use ARRAY_SIZE instead of hard-coding 128.

This changes the order of the union definitions,
but retains the order of the union-of-union members.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
         { "int8", 8, 'b', 's' },
     };
 
-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-    int i, j, bits;
+    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
+    int i, j;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = 0; i < ARRAY_SIZE(suf); i++) {
+        int bits = 8 << i;
+
         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
 
     /* And now the final union of unions */
     g_string_append_printf(s, "<union id=\"%s\">", name);
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
                                suf[i], name, suf[i]);
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Keep the logic for pauth within pauth_helper.c, and expose
a helper function for use with the gdbstub pac extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h        | 10 ++++++++++
 target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
 bool arm_singlestep_active(CPUARMState *env);
 bool arm_generate_debug_exceptions(CPUARMState *env);
 
+/**
+ * pauth_ptr_mask:
+ * @env: cpu context
+ * @ptr: selects between TTBR0 and TTBR1
+ * @data: selects between TBI and TBID
+ *
+ * Return a mask of the bits of @ptr that contain the authentication code.
+ */
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
+
 /* Add the cpreg definitions for debug related system registers */
 void define_debug_regs(ARMCPU *cpu);
 
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
     return pac | ext | ptr;
 }
 
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
 {
-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
-    uint64_t extfield = sextract64(ptr, 55, 1);
     int bot_pac_bit = 64 - param.tsz;
     int top_pac_bit = 64 - 8 * param.tbi;
 
-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
+    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
+}
+
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+{
+    uint64_t mask = pauth_ptr_mask_internal(param);
+
+    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+    if (extract64(ptr, 55, 1)) {
+        return ptr | mask;
+    } else {
+        return ptr & ~mask;
+    }
+}
+
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
+{
+    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
+    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
+
+    return pauth_ptr_mask_internal(param);
 }
 
 static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
ptrace register set.

The original gdb feature consists of two masks, data and code, which are
used to mask out the authentication code within a pointer.  Following
discussion with Luis Machado, add two more masks in order to support
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 configs/targets/aarch64-linux-user.mak    |  2 +-
 configs/targets/aarch64-softmmu.mak       |  2 +-
 configs/targets/aarch64_be-linux-user.mak |  2 +-
 target/arm/internals.h                    |  2 ++
 target/arm/gdbstub.c                      |  5 ++++
 target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
 gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
 7 files changed, 59 insertions(+), 3 deletions(-)
 create mode 100644 gdb-xml/aarch64-pauth.xml

diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-linux-user.mak
+++ b/configs/targets/aarch64-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
 TARGET_NEED_FDT=y
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64_be-linux-user.mak
+++ b/configs/targets/aarch64_be-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                      aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
+        if (isar_feature_aa64_pauth(&cpu->isar)) {
+            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
+                                     aarch64_gdb_set_pauth_reg,
+                                     4, "aarch64-pauth.xml", 0);
+        }
 #endif
     } else {
         if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    switch (reg) {
+    case 0: /* pauth_dmask */
+    case 1: /* pauth_cmask */
+    case 2: /* pauth_dmask_high */
+    case 3: /* pauth_cmask_high */
+        /*
+         * Note that older versions of this feature only contained
+         * pauth_{d,c}mask, for use with Linux user processes, and
+         * thus exclusively in the low half of the address space.
+         *
+         * To support system mode, and to debug kernels, two new regs
+         * were added to cover the high half of the address space.
+         * For the purpose of pauth_ptr_mask, we can use any well-formed
+         * address within the address space half -- here, 0 and -1.
+         */
+        {
+            bool is_data = !(reg & 1);
+            bool is_high = reg & 2;
+            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
+            return gdb_get_reg64(buf, mask);
+        }
+    default:
+        return 0;
+    }
+}
+
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    /* All pseudo registers are read-only. */
+    return 0;
+}
+
 static void output_vector_union_type(GString *s, int reg_width,
                                      const char *name)
 {
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/gdb-xml/aarch64-pauth.xml
@@ -XXX,XX +XXX,XX @@
+<?xml version="1.0"?>
+
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.pauth">
+  <reg name="pauth_dmask" bitsize="64"/>
+  <reg name="pauth_cmask" bitsize="64"/>
+  <reg name="pauth_dmask_high" bitsize="64"/>
+  <reg name="pauth_cmask_high" bitsize="64"/>
+</feature>
+
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Rename with an "arm_" prefix.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 3 +++
 target/arm/tcg/m_helper.c | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 #endif
 
+/* Read the CONTROL register as the MRS instruction would. */
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
     return xpsr_read(env) & mask;
 }
 
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
 {
     uint32_t value = env->v7m.control[secure];
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, 0);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, 0);
+        return arm_v7m_mrs_control(env, 0);
     default:
         /* Unprivileged reads others as zero.  */
         return 0;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, el);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, env->v7m.secure);
+        return arm_v7m_mrs_control(env, env->v7m.secure);
     case 0x94: /* CONTROL_NS */
         /*
          * We have to handle this here because unprivileged Secure code
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Move to be outside of ifndef CONFIG_USER_ONLY block.
Rename from get_v7m_sp_ptr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 10 +++++
 target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
 2 files changed, 51 insertions(+), 43 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 /* Read the CONTROL register as the MRS instruction would. */
 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
 
+/*
+ * Return a pointer to the location where we currently store the
+ * stack pointer for the requested security state and thread mode.
+ * This pointer will become invalid if the CPU state is updated
+ * such that the stack pointers are switched around (eg changing
+ * the SPSEL control bit).
+ */
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
+                             bool threadmode, bool spsel);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
     arm_rebuild_hflags(env);
 }
 
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
-                                bool spsel)
-{
-    /*
-     * Return a pointer to the location where we currently store the
-     * stack pointer for the requested security state and thread mode.
-     * This pointer will become invalid if the CPU state is updated
-     * such that the stack pointers are switched around (eg changing
-     * the SPSEL control bit).
-     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
-     * Unlike that pseudocode, we require the caller to pass us in the
-     * SPSEL control bit value; this is because we also use this
-     * function in handling of pushing of the callee-saves registers
-     * part of the v8M stack frame (pseudocode PushCalleeStack()),
-     * and in the tailchain codepath the SPSEL bit comes from the exception
-     * return magic LR value from the previous exception. The pseudocode
-     * opencodes the stack-selection in PushCalleeStack(), but we prefer
-     * to make this utility function generic enough to do the job.
-     */
-    bool want_psp = threadmode && spsel;
-
-    if (secure == env->v7m.secure) {
-        if (want_psp == v7m_using_psp(env)) {
-            return &env->regs[13];
-        } else {
-            return &env->v7m.other_sp;
-        }
-    } else {
-        if (want_psp) {
-            return &env->v7m.other_ss_psp;
-        } else {
-            return &env->v7m.other_ss_msp;
-        }
-    }
-}
-
 static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
                                 uint32_t *pvec)
 {
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
             !mode;
 
         mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
-        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
-                                    lr & R_V7M_EXCRET_SPSEL_MASK);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
+                                        lr & R_V7M_EXCRET_SPSEL_MASK);
         want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
         if (want_psp) {
             limit = env->v7m.psplim[M_REG_S];
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
          * use 'frame_sp_p' after we do something that makes it invalid.
          */
         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
-        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
-                                              return_to_secure,
-                                              !return_to_handler,
-                                              spsel);
+        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
+                                                  !return_to_handler, spsel);
         uint32_t frameptr = *frame_sp_p;
         bool pop_ok = true;
         ARMMMUIdx mmu_idx;
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
         threadmode = !arm_v7m_is_handler_mode(env);
         spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 
-        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
         frameptr = *frame_sp_p;
 
         /*
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
 }
 
 #endif /* !CONFIG_USER_ONLY */
+
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+                             bool spsel)
+{
+    /*
+     * Return a pointer to the location where we currently store the
+     * stack pointer for the requested security state and thread mode.
+     * This pointer will become invalid if the CPU state is updated
+     * such that the stack pointers are switched around (eg changing
+     * the SPSEL control bit).
+     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
+     * Unlike that pseudocode, we require the caller to pass us in the
+     * SPSEL control bit value; this is because we also use this
+     * function in handling of pushing of the callee-saves registers
+     * part of the v8M stack frame (pseudocode PushCalleeStack()),
+     * and in the tailchain codepath the SPSEL bit comes from the exception
+     * return magic LR value from the previous exception. The pseudocode
+     * opencodes the stack-selection in PushCalleeStack(), but we prefer
+     * to make this utility function generic enough to do the job.
+     */
+    bool want_psp = threadmode && spsel;
+
+    if (secure == env->v7m.secure) {
+        if (want_psp == v7m_using_psp(env)) {
+            return &env->regs[13];
+        } else {
+            return &env->v7m.other_sp;
+        }
+    } else {
+        if (want_psp) {
+            return &env->v7m.other_ss_psp;
+        } else {
+            return &env->v7m.other_ss_msp;
+        }
+    }
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
go ahead and implement the other system registers as well.

Since there is significant overlap between the two, implement
them with common code.  The only exception is the systemreg
view of CONTROL, which merges the banked bits as per MRS.

Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
[rth: Substatial rewrite using enumerator and shared code.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |   2 +
 target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     DynamicGDBXMLInfo dyn_sysreg_xml;
     DynamicGDBXMLInfo dyn_svereg_xml;
+    DynamicGDBXMLInfo dyn_m_systemreg_xml;
+    DynamicGDBXMLInfo dyn_m_secextreg_xml;
 
     /* Timers used by the generic (architected) timer */
     QEMUTimer *gt_timer[NUM_GTIMERS];
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
+typedef enum {
+    M_SYSREG_MSP,
+    M_SYSREG_PSP,
+    M_SYSREG_PRIMASK,
+    M_SYSREG_CONTROL,
+    M_SYSREG_BASEPRI,
+    M_SYSREG_FAULTMASK,
+    M_SYSREG_MSPLIM,
+    M_SYSREG_PSPLIM,
+} MProfileSysreg;
+
+static const struct {
+    const char *name;
+    int feature;
+} m_sysreg_def[] = {
+    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
+    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
+    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
+    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
+    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
+    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
+};
+
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
+{
+    uint32_t *ptr;
+
+    switch (reg) {
+    case M_SYSREG_MSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
+        break;
+    case M_SYSREG_PSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
+        break;
+    case M_SYSREG_MSPLIM:
+        ptr = &env->v7m.msplim[sec];
+        break;
+    case M_SYSREG_PSPLIM:
+        ptr = &env->v7m.psplim[sec];
+        break;
+    case M_SYSREG_PRIMASK:
+        ptr = &env->v7m.primask[sec];
+        break;
+    case M_SYSREG_BASEPRI:
+        ptr = &env->v7m.basepri[sec];
+        break;
+    case M_SYSREG_FAULTMASK:
+        ptr = &env->v7m.faultmask[sec];
+        break;
+    case M_SYSREG_CONTROL:
+        ptr = &env->v7m.control[sec];
+        break;
+    default:
+        return NULL;
+    }
+    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
+}
+
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
+                        MProfileSysreg reg, bool secure)
+{
+    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
+
+    if (ptr == NULL) {
+        return 0;
+    }
+    return gdb_get_reg32(buf, *ptr);
+}
+
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    /*
+     * Here, we emulate MRS instruction, where CONTROL has a mix of
+     * banked and non-banked bits.
+     */
+    if (reg == M_SYSREG_CONTROL) {
+        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
+    }
+    return m_sysreg_get(env, buf, reg, env->v7m.secure);
+}
+
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        if (arm_feature(env, m_sysreg_def[i].feature)) {
+            g_string_append_printf(s,
+                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+                m_sysreg_def[i].name, base_reg++);
+        }
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_systemreg_xml.num;
+}
+
+#ifndef CONFIG_USER_ONLY
+/*
+ * For user-only, we see the non-secure registers via m_systemreg above.
+ * For secext, encode the non-secure view as even and secure view as odd.
+ */
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
+}
+
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        g_string_append_printf(s,
+            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+        g_string_append_printf(s,
+            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_secextreg_xml.num;
+}
+#endif
+
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
         return cpu->dyn_sysreg_xml.desc;
     } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
         return cpu->dyn_svereg_xml.desc;
+    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
+        return cpu->dyn_m_systemreg_xml.desc;
+#ifndef CONFIG_USER_ONLY
+    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
+        return cpu->dyn_m_secextreg_xml.desc;
+#endif
     }
     return NULL;
 }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                              "system-registers.xml", 0);
 
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        gdb_register_coprocessor(cs,
+            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
+            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
+            "arm-m-system.xml", 0);
+#ifndef CONFIG_USER_ONLY
+        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+            gdb_register_coprocessor(cs,
+                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
+                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
+                "arm-m-secext.xml", 0);
+        }
+#endif
+    }
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

M-profile doesn't have HCR_EL2.  While we could test features
before each call, zero is a generally safe return value to
disable the code in the caller.  This test is required to
avoid an assert in arm_is_secure_below_el3.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
 
 uint64_t arm_hcr_el2_eff(CPUARMState *env)
 {
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return 0;
+    }
     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
 }
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

In several places we use arm_is_secure_below_el3 and
arm_is_el3_or_mon separately from arm_is_secure.
These functions make no sense for m-profile, and
would indicate prior incorrect feature testing.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
 
 #if !defined(CONFIG_USER_ONLY)
-/* Return true if exception levels below EL3 are in secure state,
+/*
+ * Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
  * Unlike arm_is_secure() (which is always a question about the
  * _current_ state of the CPU) this doesn't care about the current
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
  */
 static inline bool arm_is_secure_below_el3(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         return !(env->cp15.scr_el3 & SCR_NS);
     } else {
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
 static inline bool arm_is_el3_or_mon(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
             /* CPU currently in AArch64 state and EL3 */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Integrate neighboring code from get_phys_addr_lpae which computed
starting level, as it is easier to validate when doing both at the
same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
especially S2InvalidSL and S2InconsistentSL.

This reverts 49ba115bb74, which was incorrect -- there is nothing
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
pseudocode is consistent in referencing PAMax.

Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
 1 file changed, 97 insertions(+), 76 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
  * check_s2_mmu_setup
  * @cpu:        ARMCPU
  * @is_aa64:    True if the translation regime is in AArch64 state
- * @startlevel: Suggested starting level
- * @inputsize:  Bitsize of IPAs
+ * @tcr:        VTCR_EL2 or VSTCR_EL2
+ * @ds:         Effective value of TCR.DS.
+ * @iasize:     Bitsize of IPAs
  * @stride:     Page-table stride (See the ARM ARM)
  *
- * Returns true if the suggested S2 translation parameters are OK and
- * false otherwise.
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
+ * the configuration is invalid.
  */
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
-                               int inputsize, int stride, int outputsize)
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
+                              bool ds, int iasize, int stride)
 {
-    const int grainsize = stride + 3;
-    int startsizecheck;
-
-    /*
-     * Negative levels are usually not allowed...
-     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
-     * begins with level -1.  Note that previous feature tests will have
-     * eliminated this combination if it is not enabled.
-     */
-    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
-        return false;
-    }
-
-    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
-    if (startsizecheck < 1 || startsizecheck > stride + 4) {
-        return false;
-    }
+    int sl0, sl2, startlevel, granulebits, levels;
+    int s1_min_iasize, s1_max_iasize;
 
+    sl0 = extract32(tcr, 6, 2);
     if (is_aa64) {
+        /*
+         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
+         * get_phys_addr_lpae, that used aa64_va_parameters which apply
+         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
+         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
+         * inputsize is 64 - 24 = 40.
+         */
+        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
+            goto fail;
+        }
+
+        /*
+         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
+         * so interleave AArch64.S2StartLevel.
+         */
         switch (stride) {
-        case 13: /* 64KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 42)) {
-                return false;
+        case 9: /* 4KB */
+            /* SL2 is RES0 unless DS=1 & 4KB granule. */
+            sl2 = extract64(tcr, 33, 1);
+            if (ds && sl2) {
+                if (sl0 != 0) {
+                    goto fail;
+                }
+                startlevel = -1;
+            } else {
+                startlevel = 2 - sl0;
+                switch (sl0) {
+                case 2:
+                    if (arm_pamax(cpu) < 44) {
+                        goto fail;
+                    }
+                    break;
+                case 3:
+                    if (!cpu_isar_feature(aa64_st, cpu)) {
+                        goto fail;
+                    }
+                    startlevel = 3;
+                    break;
+                }
             }
             break;
-        case 11: /* 16KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 40)) {
-                return false;
+        case 11: /* 16KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 42) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                if (!ds) {
+                    goto fail;
+                }
+                break;
             }
+            startlevel = 3 - sl0;
             break;
-        case 9: /* 4KB Pages.  */
-            if (level == 0 && outputsize <= 42) {
-                return false;
+        case 13: /* 64KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 44) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                goto fail;
             }
+            startlevel = 3 - sl0;
             break;
         default:
             g_assert_not_reached();
         }
-
-        /* Inputsize checks.  */
-        if (inputsize > outputsize &&
-            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
-            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
-            return false;
-        }
     } else {
-        /* AArch32 only supports 4KB pages. Assert on that.  */
+        /*
+         * Things are simpler for AArch32 EL2, with only 4k pages.
+         * There is no separate S2InvalidSL function, but AArch32.S2Walk
+         * begins with walkparms.sl0 in {'1x'}.
+         */
         assert(stride == 9);
-
-        if (level == 0) {
-            return false;
+        if (sl0 >= 2) {
+            goto fail;
         }
+        startlevel = 2 - sl0;
     }
-    return true;
+
+    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
+    levels = 3 - startlevel;
+    granulebits = stride + 3;
+
+    s1_min_iasize = levels * stride + granulebits + 1;
+    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
+
+    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
+        return startlevel;
+    }
+
+ fail:
+    return INT_MIN;
 }
 
 /**
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
          */
         level = 4 - (inputsize - 4) / stride;
     } else {
-        /*
-         * For stage 2 translations the starting level is specified by the
-         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
-         */
-        uint32_t sl0 = extract32(tcr, 6, 2);
-        uint32_t sl2 = extract64(tcr, 33, 1);
-        int32_t startlevel;
-        bool ok;
-
-        /* SL2 is RES0 unless DS=1 & 4kb granule. */
-        if (param.ds && stride == 9 && sl2) {
-            if (sl0 != 0) {
-                level = 0;
-                goto do_translation_fault;
-            }
-            startlevel = -1;
-        } else if (!aarch64 || stride == 9) {
-            /* AArch32 or 4KB pages */
-            startlevel = 2 - sl0;
-
-            if (cpu_isar_feature(aa64_st, cpu)) {
-                startlevel &= 3;
-            }
-        } else {
-            /* 16KB or 64KB pages */
-            startlevel = 3 - sl0;
-        }
-
-        /* Check that the starting level is valid. */
-        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
-                                inputsize, stride, outputsize);
-        if (!ok) {
+        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
+                                            inputsize, stride);
+        if (startlevel == INT_MIN) {
+            level = 0;
             goto do_translation_fault;
         }
         level = startlevel;
-- 
2.34.1

From: Ard Biesheuvel <ardb@kernel.org>

Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
format, using gzip compression for the payload.

For doing EFI boot in QEMU, this is completely transparent, as the
firmware or bootloader will take care of this. However, for direct
kernel boot without firmware, we will lose the ability to boot such
distro kernels unless we deal with the new format directly.

EFI zboot images contain metadata in the header regarding the placement
of the compressed payload inside the image, and the type of compression
used. This means we can wire up the existing gzip support without too
much hassle, by parsing the header and grabbing the payload from inside
the loaded zboot image.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20230303160109.3626966-1-ardb@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked comment formatting, fixed checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/loader.h | 19 ++++++++++
 hw/arm/boot.c       |  6 +++
 hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
                                   uint8_t **buffer);
 ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
 
+/**
+ * unpack_efi_zboot_image:
+ * @buffer: pointer to a variable holding the address of a buffer containing the
+ *          image
+ * @size: pointer to a variable holding the size of the buffer
+ *
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
+ * the compressed payload and decompress it into a new buffer. If successful,
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
+ * function arguments are updated to refer to the newly populated buffer.
+ *
+ * Returns 0 if the image could not be identified as a EFI zboot image.
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
+ * unpacking failed for any reason.
+ * Returns the size of the decompressed payload if decompression was performed
+ * successfully.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
+
 #define ELF_LOAD_FAILED       -1
 #define ELF_LOAD_NOT_ELF      -2
 #define ELF_LOAD_WRONG_ARCH   -3
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
             return -1;
         }
         size = len;
+
+        /* Unpack the image if it is a EFI zboot image */
+        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
+            g_free(buffer);
+            return -1;
+        }
     }
 
     /* check the arm64 magic header value -- very old kernels may not have it */
diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
     return bytes;
 }
 
+/* The PE/COFF MS-DOS stub magic number */
+#define EFI_PE_MSDOS_MAGIC        "MZ"
+
+/*
+ * The Linux header magic number for a EFI PE/COFF
+ * image targetting an unspecified architecture.
+ */
+#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
+
+/*
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
+ * self-decompressing executables when loaded via EFI. The compressed payload
+ * can also be extracted from the image and decompressed by a non-EFI loader.
+ *
+ * The de facto specification for this format is at the following URL:
+ *
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
+ *
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
+ */
+struct linux_efi_zboot_header {
+    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
+    uint8_t     reserved0[2];
+    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
+    uint32_t    payload_offset;         /* LE offset to compressed payload */
+    uint32_t    payload_size;           /* LE size of the compressed payload */
+    uint8_t     reserved1[8];
+    char        compression_type[32];   /* Compression type, NUL terminated */
+    uint8_t     linux_magic[4];         /* Linux header magic */
+    uint32_t    pe_header_offset;       /* LE offset to the PE header */
+};
+
+/*
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
+ *
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
+ * If any of this fails, return an error to the caller.
+ *
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
+{
+    const struct linux_efi_zboot_header *header;
+    uint8_t *data = NULL;
+    int ploff, plsize;
+    ssize_t bytes;
+
+    /* ignore if this is too small to be a EFI zboot image */
+    if (*size < sizeof(*header)) {
+        return 0;
+    }
+
+    header = (struct linux_efi_zboot_header *)*buffer;
+
+    /* ignore if this is not a Linux EFI zboot image */
+    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
+        memcmp(&header->zimg, "zimg", 4) != 0 ||
+        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
+        return 0;
+    }
+
+    if (strcmp(header->compression_type, "gzip") != 0) {
+        fprintf(stderr,
+                "unable to handle EFI zboot image with \"%.*s\" compression\n",
+                (int)sizeof(header->compression_type) - 1,
+                header->compression_type);
+        return -1;
+    }
+
+    ploff = ldl_le_p(&header->payload_offset);
+    plsize = ldl_le_p(&header->payload_size);
+
+    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
+        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
+        return -1;
+    }
+
+    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
+    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
+    if (bytes < 0) {
+        fprintf(stderr, "failed to decompress EFI zboot image\n");
+        g_free(data);
+        return -1;
+    }
+
+    g_free(*buffer);
+    *buffer = g_realloc(data, bytes);
+    *size = bytes;
+    return bytes;
+}
+
 /*
  * Functions for reboot-persistent memory regions.
  *  - used for vga bios and option roms.
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.

The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:

allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
...

Fix it.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/allwinner-i2c.h |  6 ++++++
 hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/allwinner-i2c.h
+++ b/include/hw/i2c/allwinner-i2c.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_AW_I2C "allwinner.i2c"
+
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
+
 OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
 
 #define AW_I2C_MEM_SIZE         0x24
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
     uint8_t srst;
     uint8_t efr;
     uint8_t lcr;
+
+    bool irq_clear_inverted;
 };
 
 #endif /* ALLWINNER_I2C_H */
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/allwinner-i2c.c
+++ b/hw/i2c/allwinner-i2c.c
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
                 s->stat = STAT_FROM_STA(STAT_IDLE);
                 s->cntr &= ~TWI_CNTR_M_STP;
             }
-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
-                /* Interrupt flag cleared */
+
+            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 0 to clear this flag */
+                qemu_irq_lower(s->irq);
+            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 1 to clear this flag */
+                s->cntr &= ~TWI_CNTR_INT_FLAG;
                 qemu_irq_lower(s->irq);
             }
+
             if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
                 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
                     s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
     .class_init = allwinner_i2c_class_init,
 };
 
+static void allwinner_i2c_sun6i_init(Object *obj)
+{
+    AWI2CState *s = AW_I2C(obj);
+
+    s->irq_clear_inverted = true;
+}
+
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
+    .name = TYPE_AW_I2C_SUN6I,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AWI2CState),
+    .instance_init = allwinner_i2c_sun6i_init,
+    .class_init = allwinner_i2c_class_init,
+};
+
 static void allwinner_i2c_register_types(void)
 {
     type_register_static(&allwinner_i2c_type_info);
+    type_register_static(&allwinner_i2c_sun6i_type_info);
 }
 
 type_init(allwinner_i2c_register_types)
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
control register's INT_FLAG bit.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-h3.h |  6 ++++++
 hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_UART3,
     AW_H3_DEV_EMAC,
     AW_H3_DEV_TWI0,
+    AW_H3_DEV_TWI1,
+    AW_H3_DEV_TWI2,
     AW_H3_DEV_DRAMCOM,
     AW_H3_DEV_DRAMCTL,
     AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_GIC_VCPU,
     AW_H3_DEV_RTC,
     AW_H3_DEV_CPUCFG,
+    AW_H3_DEV_R_TWI,
     AW_H3_DEV_SDRAM
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
     AwSidState sid;
     AwSdHostState mmc0;
     AWI2CState i2c0;
+    AWI2CState i2c1;
+    AWI2CState i2c2;
+    AWI2CState r_twi;
     AwSun8iEmacState emac;
     AwRtcState rtc;
     GICState gic;
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_UART2]      = 0x01c28800,
     [AW_H3_DEV_UART3]      = 0x01c28c00,
     [AW_H3_DEV_TWI0]       = 0x01c2ac00,
+    [AW_H3_DEV_TWI1]       = 0x01c2b000,
+    [AW_H3_DEV_TWI2]       = 0x01c2b400,
     [AW_H3_DEV_EMAC]       = 0x01c30000,
     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
     [AW_H3_DEV_RTC]        = 0x01f00000,
     [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
+    [AW_H3_DEV_R_TWI]      = 0x01f02400,
     [AW_H3_DEV_SDRAM]      = 0x40000000
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "uart1",     0x01c28400, 1 * KiB },
     { "uart2",     0x01c28800, 1 * KiB },
     { "uart3",     0x01c28c00, 1 * KiB },
-    { "twi1",      0x01c2b000, 1 * KiB },
-    { "twi2",      0x01c2b400, 1 * KiB },
     { "scr",       0x01c2c400, 1 * KiB },
     { "gpu",       0x01c40000, 64 * KiB },
     { "hstmr",     0x01c60000, 4 * KiB },
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "r_prcm",    0x01f01400, 1 * KiB },
     { "r_twd",     0x01f01800, 1 * KiB },
     { "r_cir-rx",  0x01f02000, 1 * KiB },
-    { "r_twi",     0x01f02400, 1 * KiB },
     { "r_uart",    0x01f02800, 1 * KiB },
     { "r_pio",     0x01f02c00, 1 * KiB },
     { "r_pwm",     0x01f03800, 1 * KiB },
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_GIC_SPI_UART2     =  2,
     AW_H3_GIC_SPI_UART3     =  3,
     AW_H3_GIC_SPI_TWI0      =  6,
+    AW_H3_GIC_SPI_TWI1      =  7,
+    AW_H3_GIC_SPI_TWI2      =  8,
     AW_H3_GIC_SPI_TIMER0    = 18,
     AW_H3_GIC_SPI_TIMER1    = 19,
+    AW_H3_GIC_SPI_R_TWI     = 44,
     AW_H3_GIC_SPI_MMC0      = 60,
     AW_H3_GIC_SPI_EHCI0     = 72,
     AW_H3_GIC_SPI_OHCI0     = 73,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 
-    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
+    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
 }
 
 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
+
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
         create_unimplemented_device(unimplemented[i].device_name,
-- 
2.34.1