On 2021/11/19 下午8:57, Alistair Francis wrote:
> On Fri, Nov 12, 2021 at 1:52 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> In this patch set, we process the pc reigsters writes,
>> gdb reads and writes, and address calculation under
>> different UXLEN settings.
> Awesome!
>
> Do you have steps on how to test this?
I have some little of weird tests. Compile 32 bit baremetal benchmarks,
such as dhrystone and coremark, and run them on qemu-system-riscv64.
These tests can pass.
These tests cases cover the most of instruction translation.
I think some assembling test cases covering XLEN change are also
needed. Not yet.
Thanks,
Zhiwei
>
> Alistair
>
>> The patch set v4 mainly address Richard comments on v3.
>> Patch 8, 18, 19, 20 have not been reviewed. Others have been reviewed or acked.
>>
>> v4:
>> Support SSTATUS64_UXL write
>> Bump vmstate version for vill split
>>
>> v3:
>> Merge gen_pm_adjust_address into a canonical address function
>> Adjust address for RVA with XLEN
>> Split pm_enabled into pm_mask_enabled and pm_base_enabled
>> Replace array of pm tcg globals with one scalar tcg global
>> Split and change patch sequence
>>
>> v2:
>> Split out vill from vtype
>> Remove context switch when xlen changes at exception
>> Use XL instead of OL in many places
>> Use pointer masking and XLEN for vector address
>> Define an common fuction to calculate address for ldst
>>
>>
>> LIU Zhiwei (20):
>> target/riscv: Don't save pc when exception return
>> target/riscv: Sign extend pc for different XLEN
>> target/riscv: Ignore the pc bits above XLEN
>> target/riscv: Extend pc for runtime pc write
>> target/riscv: Use gdb xml according to max mxlen
>> target/riscv: Relax debug check for pm write
>> target/riscv: Adjust csr write mask with XLEN
>> target/riscv: Create current pm fields in env
>> target/riscv: Alloc tcg global for cur_pm[mask|base]
>> target/riscv: Calculate address according to XLEN
>> target/riscv: Split pm_enabled into mask and base
>> target/riscv: Split out the vill from vtype
>> target/riscv: Fix RESERVED field length in VTYPE
>> target/riscv: Adjust vsetvl according to XLEN
>> target/riscv: Remove VILL field in VTYPE
>> target/riscv: Ajdust vector atomic check with XLEN
>> target/riscv: Fix check range for first fault only
>> target/riscv: Adjust vector address with mask
>> target/riscv: Adjust scalar reg in vector with XLEN
>> target/riscv: Enable uxl field write
>>
>> target/riscv/cpu.c | 23 +++++-
>> target/riscv/cpu.h | 13 +++-
>> target/riscv/cpu_bits.h | 2 +
>> target/riscv/cpu_helper.c | 66 ++++++++++++----
>> target/riscv/csr.c | 43 ++++++++++-
>> target/riscv/gdbstub.c | 71 ++++++++++++-----
>> target/riscv/helper.h | 6 +-
>> .../riscv/insn_trans/trans_privileged.c.inc | 7 +-
>> target/riscv/insn_trans/trans_rva.c.inc | 9 +--
>> target/riscv/insn_trans/trans_rvd.c.inc | 19 +----
>> target/riscv/insn_trans/trans_rvf.c.inc | 19 +----
>> target/riscv/insn_trans/trans_rvi.c.inc | 22 +-----
>> target/riscv/insn_trans/trans_rvv.c.inc | 51 ++++++++----
>> target/riscv/machine.c | 15 +++-
>> target/riscv/op_helper.c | 7 +-
>> target/riscv/translate.c | 77 +++++++++----------
>> target/riscv/vector_helper.c | 38 +++++----
>> 17 files changed, 300 insertions(+), 188 deletions(-)
>>
>> --
>> 2.25.1
>>
>>