[PATCH v3 06/20] target/riscv: Relax debug check for pm write

LIU Zhiwei posted 20 patches 4 years, 3 months ago
Maintainers: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>
There is a newer version of this series
[PATCH v3 06/20] target/riscv: Relax debug check for pm write
Posted by LIU Zhiwei 4 years, 3 months ago
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/csr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
     int csr_priv = get_field(csrno, 0x300);
     int pm_current;
 
+    if (env->debugger) {
+        return false;
+    }
     /*
      * If priv lvls differ that means we're accessing csr from higher priv lvl,
      * so allow the access
-- 
2.25.1