[v3] Support UXL filed in xstatus

[PATCH v3 20/20] target/riscv: Enable uxl field write

Posted by LIU Zhiwei 4 years, 3 months ago

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/csr.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f8f170768..43eaa6c710 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
          */
-        mask |= MSTATUS_MPV | MSTATUS_GVA;
+        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
     }
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
     if (riscv_cpu_mxl(env) == MXL_RV64) {
-        /* SXL and UXL fields are for now read only */
+        /* SXL fields are for now read only */
         mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
-        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
     }
     env->mstatus = mstatus;
 
-- 
2.25.1

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

Posted by Richard Henderson 4 years, 3 months ago

On 11/11/21 6:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>   target/riscv/csr.c | 5 ++---
>   1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8f8f170768..43eaa6c710 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>            * RV32: MPV and GVA are not in mstatus. The current plan is to
>            * add them to mstatush. For now, we just don't support it.
>            */
> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
> +        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>       }
>   
>       mstatus = (mstatus & ~mask) | (val & mask);
>   
>       if (riscv_cpu_mxl(env) == MXL_RV64) {
> -        /* SXL and UXL fields are for now read only */
> +        /* SXL fields are for now read only */
>           mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> -        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>       }
>       env->mstatus = mstatus;

Still missing the update for write_sstatus, which I think is simply an update to 
sstatus_v1_10_mask.


r~

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

Posted by Frédéric Pétrot 4 years, 3 months ago

On 11/11/2021 12:49, Richard Henderson wrote:
> On 11/11/21 6:58 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>   target/riscv/csr.c | 5 ++---
>>   1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 8f8f170768..43eaa6c710 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, 
>> int csrno,
>>            * RV32: MPV and GVA are not in mstatus. The current plan is to
>>            * add them to mstatush. For now, we just don't support it.
>>            */
>> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
>> +        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>>       }
>>       mstatus = (mstatus & ~mask) | (val & mask);
>>       if (riscv_cpu_mxl(env) == MXL_RV64) {
>> -        /* SXL and UXL fields are for now read only */
>> +        /* SXL fields are for now read only */
>>           mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
>> -        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>>       }
>>       env->mstatus = mstatus;
> 
> Still missing the update for write_sstatus, which I think is simply an update to 
> sstatus_v1_10_mask.

   I take the liberty to jump in as I face the issue of updating that mask in the
   128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
   32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
   32-bit limits.
   I am currently oring in write_sstatus using a uint64_t mask, but this is not
   so nice.

   What solution would be best in your opinion ?
   Thanks,
   Frédéric
> 
> 
> r~
> 
> 

-- 
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70      Ad augusta  per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

Posted by Richard Henderson 4 years, 3 months ago

On 11/11/21 4:18 PM, Frédéric Pétrot wrote:
>> Still missing the update for write_sstatus, which I think is simply an update to 
>> sstatus_v1_10_mask.
> 
>    I take the liberty to jump in as I face the issue of updating that mask in the
>    128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
>    32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
>    32-bit limits.

Surely (target_ulong)MSTATUS64_UXL will properly produce 0 when oring into 
sstatus_v1_10_mask?  Which is correct for an RV32-only build.


r~